atsam4e8c_pac/spi/
idr.rs

1#[doc = "Register `IDR` writer"]
2pub struct W(crate::W<IDR_SPEC>);
3impl core::ops::Deref for W {
4    type Target = crate::W<IDR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl core::ops::DerefMut for W {
11    #[inline(always)]
12    fn deref_mut(&mut self) -> &mut Self::Target {
13        &mut self.0
14    }
15}
16impl From<crate::W<IDR_SPEC>> for W {
17    #[inline(always)]
18    fn from(writer: crate::W<IDR_SPEC>) -> Self {
19        W(writer)
20    }
21}
22#[doc = "Field `RDRF` writer - Receive Data Register Full Interrupt Disable"]
23pub type RDRF_W<'a, const O: u8> = crate::BitWriter<'a, u32, IDR_SPEC, bool, O>;
24#[doc = "Field `TDRE` writer - SPI Transmit Data Register Empty Interrupt Disable"]
25pub type TDRE_W<'a, const O: u8> = crate::BitWriter<'a, u32, IDR_SPEC, bool, O>;
26#[doc = "Field `MODF` writer - Mode Fault Error Interrupt Disable"]
27pub type MODF_W<'a, const O: u8> = crate::BitWriter<'a, u32, IDR_SPEC, bool, O>;
28#[doc = "Field `OVRES` writer - Overrun Error Interrupt Disable"]
29pub type OVRES_W<'a, const O: u8> = crate::BitWriter<'a, u32, IDR_SPEC, bool, O>;
30#[doc = "Field `ENDRX` writer - End of Receive Buffer Interrupt Disable"]
31pub type ENDRX_W<'a, const O: u8> = crate::BitWriter<'a, u32, IDR_SPEC, bool, O>;
32#[doc = "Field `ENDTX` writer - End of Transmit Buffer Interrupt Disable"]
33pub type ENDTX_W<'a, const O: u8> = crate::BitWriter<'a, u32, IDR_SPEC, bool, O>;
34#[doc = "Field `RXBUFF` writer - Receive Buffer Full Interrupt Disable"]
35pub type RXBUFF_W<'a, const O: u8> = crate::BitWriter<'a, u32, IDR_SPEC, bool, O>;
36#[doc = "Field `TXBUFE` writer - Transmit Buffer Empty Interrupt Disable"]
37pub type TXBUFE_W<'a, const O: u8> = crate::BitWriter<'a, u32, IDR_SPEC, bool, O>;
38#[doc = "Field `NSSR` writer - NSS Rising Interrupt Disable"]
39pub type NSSR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IDR_SPEC, bool, O>;
40#[doc = "Field `TXEMPTY` writer - Transmission Registers Empty Disable"]
41pub type TXEMPTY_W<'a, const O: u8> = crate::BitWriter<'a, u32, IDR_SPEC, bool, O>;
42#[doc = "Field `UNDES` writer - Underrun Error Interrupt Disable"]
43pub type UNDES_W<'a, const O: u8> = crate::BitWriter<'a, u32, IDR_SPEC, bool, O>;
44impl W {
45    #[doc = "Bit 0 - Receive Data Register Full Interrupt Disable"]
46    #[inline(always)]
47    #[must_use]
48    pub fn rdrf(&mut self) -> RDRF_W<0> {
49        RDRF_W::new(self)
50    }
51    #[doc = "Bit 1 - SPI Transmit Data Register Empty Interrupt Disable"]
52    #[inline(always)]
53    #[must_use]
54    pub fn tdre(&mut self) -> TDRE_W<1> {
55        TDRE_W::new(self)
56    }
57    #[doc = "Bit 2 - Mode Fault Error Interrupt Disable"]
58    #[inline(always)]
59    #[must_use]
60    pub fn modf(&mut self) -> MODF_W<2> {
61        MODF_W::new(self)
62    }
63    #[doc = "Bit 3 - Overrun Error Interrupt Disable"]
64    #[inline(always)]
65    #[must_use]
66    pub fn ovres(&mut self) -> OVRES_W<3> {
67        OVRES_W::new(self)
68    }
69    #[doc = "Bit 4 - End of Receive Buffer Interrupt Disable"]
70    #[inline(always)]
71    #[must_use]
72    pub fn endrx(&mut self) -> ENDRX_W<4> {
73        ENDRX_W::new(self)
74    }
75    #[doc = "Bit 5 - End of Transmit Buffer Interrupt Disable"]
76    #[inline(always)]
77    #[must_use]
78    pub fn endtx(&mut self) -> ENDTX_W<5> {
79        ENDTX_W::new(self)
80    }
81    #[doc = "Bit 6 - Receive Buffer Full Interrupt Disable"]
82    #[inline(always)]
83    #[must_use]
84    pub fn rxbuff(&mut self) -> RXBUFF_W<6> {
85        RXBUFF_W::new(self)
86    }
87    #[doc = "Bit 7 - Transmit Buffer Empty Interrupt Disable"]
88    #[inline(always)]
89    #[must_use]
90    pub fn txbufe(&mut self) -> TXBUFE_W<7> {
91        TXBUFE_W::new(self)
92    }
93    #[doc = "Bit 8 - NSS Rising Interrupt Disable"]
94    #[inline(always)]
95    #[must_use]
96    pub fn nssr(&mut self) -> NSSR_W<8> {
97        NSSR_W::new(self)
98    }
99    #[doc = "Bit 9 - Transmission Registers Empty Disable"]
100    #[inline(always)]
101    #[must_use]
102    pub fn txempty(&mut self) -> TXEMPTY_W<9> {
103        TXEMPTY_W::new(self)
104    }
105    #[doc = "Bit 10 - Underrun Error Interrupt Disable"]
106    #[inline(always)]
107    #[must_use]
108    pub fn undes(&mut self) -> UNDES_W<10> {
109        UNDES_W::new(self)
110    }
111    #[doc = "Writes raw bits to the register."]
112    #[inline(always)]
113    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
114        self.0.bits(bits);
115        self
116    }
117}
118#[doc = "Interrupt Disable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [idr](index.html) module"]
119pub struct IDR_SPEC;
120impl crate::RegisterSpec for IDR_SPEC {
121    type Ux = u32;
122}
123#[doc = "`write(|w| ..)` method takes [idr::W](W) writer structure"]
124impl crate::Writable for IDR_SPEC {
125    type Writer = W;
126    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
127    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
128}
atsam4e8c_pac/spi/idr.rs

atsam4e8c_pac/spi/
idr.rs
