1#[doc = r"Register block"]
2#[repr(C)]
3pub struct RegisterBlock {
4 #[doc = "0x00 - Channel Control Register (channel = 0)"]
5 pub ccr0: CCR0,
6 _reserved_1_cmr0: [u8; 0x04],
7 #[doc = "0x08 - Stepper Motor Mode Register (channel = 0)"]
8 pub smmr0: SMMR0,
9 #[doc = "0x0c - Register AB (channel = 0)"]
10 pub rab0: RAB0,
11 #[doc = "0x10 - Counter Value (channel = 0)"]
12 pub cv0: CV0,
13 #[doc = "0x14 - Register A (channel = 0)"]
14 pub ra0: RA0,
15 #[doc = "0x18 - Register B (channel = 0)"]
16 pub rb0: RB0,
17 #[doc = "0x1c - Register C (channel = 0)"]
18 pub rc0: RC0,
19 #[doc = "0x20 - Status Register (channel = 0)"]
20 pub sr0: SR0,
21 #[doc = "0x24 - Interrupt Enable Register (channel = 0)"]
22 pub ier0: IER0,
23 #[doc = "0x28 - Interrupt Disable Register (channel = 0)"]
24 pub idr0: IDR0,
25 #[doc = "0x2c - Interrupt Mask Register (channel = 0)"]
26 pub imr0: IMR0,
27 #[doc = "0x30 - Extended Mode Register (channel = 0)"]
28 pub emr0: EMR0,
29 _reserved13: [u8; 0x0c],
30 #[doc = "0x40 - Channel Control Register (channel = 1)"]
31 pub ccr1: CCR1,
32 _reserved_14_cmr1: [u8; 0x04],
33 #[doc = "0x48 - Stepper Motor Mode Register (channel = 1)"]
34 pub smmr1: SMMR1,
35 #[doc = "0x4c - Register AB (channel = 1)"]
36 pub rab1: RAB1,
37 #[doc = "0x50 - Counter Value (channel = 1)"]
38 pub cv1: CV1,
39 #[doc = "0x54 - Register A (channel = 1)"]
40 pub ra1: RA1,
41 #[doc = "0x58 - Register B (channel = 1)"]
42 pub rb1: RB1,
43 #[doc = "0x5c - Register C (channel = 1)"]
44 pub rc1: RC1,
45 #[doc = "0x60 - Status Register (channel = 1)"]
46 pub sr1: SR1,
47 #[doc = "0x64 - Interrupt Enable Register (channel = 1)"]
48 pub ier1: IER1,
49 #[doc = "0x68 - Interrupt Disable Register (channel = 1)"]
50 pub idr1: IDR1,
51 #[doc = "0x6c - Interrupt Mask Register (channel = 1)"]
52 pub imr1: IMR1,
53 #[doc = "0x70 - Extended Mode Register (channel = 1)"]
54 pub emr1: EMR1,
55 _reserved26: [u8; 0x0c],
56 #[doc = "0x80 - Channel Control Register (channel = 2)"]
57 pub ccr2: CCR2,
58 _reserved_27_cmr2: [u8; 0x04],
59 #[doc = "0x88 - Stepper Motor Mode Register (channel = 2)"]
60 pub smmr2: SMMR2,
61 #[doc = "0x8c - Register AB (channel = 2)"]
62 pub rab2: RAB2,
63 #[doc = "0x90 - Counter Value (channel = 2)"]
64 pub cv2: CV2,
65 #[doc = "0x94 - Register A (channel = 2)"]
66 pub ra2: RA2,
67 #[doc = "0x98 - Register B (channel = 2)"]
68 pub rb2: RB2,
69 #[doc = "0x9c - Register C (channel = 2)"]
70 pub rc2: RC2,
71 #[doc = "0xa0 - Status Register (channel = 2)"]
72 pub sr2: SR2,
73 #[doc = "0xa4 - Interrupt Enable Register (channel = 2)"]
74 pub ier2: IER2,
75 #[doc = "0xa8 - Interrupt Disable Register (channel = 2)"]
76 pub idr2: IDR2,
77 #[doc = "0xac - Interrupt Mask Register (channel = 2)"]
78 pub imr2: IMR2,
79 #[doc = "0xb0 - Extended Mode Register (channel = 2)"]
80 pub emr2: EMR2,
81 _reserved39: [u8; 0x0c],
82 #[doc = "0xc0 - Block Control Register"]
83 pub bcr: BCR,
84 #[doc = "0xc4 - Block Mode Register"]
85 pub bmr: BMR,
86 #[doc = "0xc8 - QDEC Interrupt Enable Register"]
87 pub qier: QIER,
88 #[doc = "0xcc - QDEC Interrupt Disable Register"]
89 pub qidr: QIDR,
90 #[doc = "0xd0 - QDEC Interrupt Mask Register"]
91 pub qimr: QIMR,
92 #[doc = "0xd4 - QDEC Interrupt Status Register"]
93 pub qisr: QISR,
94 #[doc = "0xd8 - Fault Mode Register"]
95 pub fmr: FMR,
96 _reserved46: [u8; 0x08],
97 #[doc = "0xe4 - Write Protection Mode Register"]
98 pub wpmr: WPMR,
99}
100impl RegisterBlock {
101 #[doc = "0x04 - Channel Mode Register (channel = 0)"]
102 #[inline(always)]
103 pub const fn wave_eq_1_cmr0_wave_eq_1(&self) -> &WAVE_EQ_1_CMR0_WAVE_EQ_1 {
104 unsafe { &*(self as *const Self).cast::<u8>().add(4usize).cast() }
105 }
106 #[doc = "0x04 - Channel Mode Register (channel = 0)"]
107 #[inline(always)]
108 pub const fn cmr0(&self) -> &CMR0 {
109 unsafe { &*(self as *const Self).cast::<u8>().add(4usize).cast() }
110 }
111 #[doc = "0x44 - Channel Mode Register (channel = 1)"]
112 #[inline(always)]
113 pub const fn wave_eq_1_cmr1_wave_eq_1(&self) -> &WAVE_EQ_1_CMR1_WAVE_EQ_1 {
114 unsafe { &*(self as *const Self).cast::<u8>().add(68usize).cast() }
115 }
116 #[doc = "0x44 - Channel Mode Register (channel = 1)"]
117 #[inline(always)]
118 pub const fn cmr1(&self) -> &CMR1 {
119 unsafe { &*(self as *const Self).cast::<u8>().add(68usize).cast() }
120 }
121 #[doc = "0x84 - Channel Mode Register (channel = 2)"]
122 #[inline(always)]
123 pub const fn wave_eq_1_cmr2_wave_eq_1(&self) -> &WAVE_EQ_1_CMR2_WAVE_EQ_1 {
124 unsafe { &*(self as *const Self).cast::<u8>().add(132usize).cast() }
125 }
126 #[doc = "0x84 - Channel Mode Register (channel = 2)"]
127 #[inline(always)]
128 pub const fn cmr2(&self) -> &CMR2 {
129 unsafe { &*(self as *const Self).cast::<u8>().add(132usize).cast() }
130 }
131}
132#[doc = "CCR0 (w) register accessor: an alias for `Reg<CCR0_SPEC>`"]
133pub type CCR0 = crate::Reg<ccr0::CCR0_SPEC>;
134#[doc = "Channel Control Register (channel = 0)"]
135pub mod ccr0;
136#[doc = "CMR0 (rw) register accessor: an alias for `Reg<CMR0_SPEC>`"]
137pub type CMR0 = crate::Reg<cmr0::CMR0_SPEC>;
138#[doc = "Channel Mode Register (channel = 0)"]
139pub mod cmr0;
140#[doc = "WAVE_EQ_1_CMR0_WAVE_EQ_1 (rw) register accessor: an alias for `Reg<WAVE_EQ_1_CMR0_WAVE_EQ_1_SPEC>`"]
141pub type WAVE_EQ_1_CMR0_WAVE_EQ_1 =
142 crate::Reg<wave_eq_1_cmr0_wave_eq_1::WAVE_EQ_1_CMR0_WAVE_EQ_1_SPEC>;
143#[doc = "Channel Mode Register (channel = 0)"]
144pub mod wave_eq_1_cmr0_wave_eq_1;
145#[doc = "SMMR0 (rw) register accessor: an alias for `Reg<SMMR0_SPEC>`"]
146pub type SMMR0 = crate::Reg<smmr0::SMMR0_SPEC>;
147#[doc = "Stepper Motor Mode Register (channel = 0)"]
148pub mod smmr0;
149#[doc = "RAB0 (r) register accessor: an alias for `Reg<RAB0_SPEC>`"]
150pub type RAB0 = crate::Reg<rab0::RAB0_SPEC>;
151#[doc = "Register AB (channel = 0)"]
152pub mod rab0;
153#[doc = "CV0 (r) register accessor: an alias for `Reg<CV0_SPEC>`"]
154pub type CV0 = crate::Reg<cv0::CV0_SPEC>;
155#[doc = "Counter Value (channel = 0)"]
156pub mod cv0;
157#[doc = "RA0 (rw) register accessor: an alias for `Reg<RA0_SPEC>`"]
158pub type RA0 = crate::Reg<ra0::RA0_SPEC>;
159#[doc = "Register A (channel = 0)"]
160pub mod ra0;
161#[doc = "RB0 (rw) register accessor: an alias for `Reg<RB0_SPEC>`"]
162pub type RB0 = crate::Reg<rb0::RB0_SPEC>;
163#[doc = "Register B (channel = 0)"]
164pub mod rb0;
165#[doc = "RC0 (rw) register accessor: an alias for `Reg<RC0_SPEC>`"]
166pub type RC0 = crate::Reg<rc0::RC0_SPEC>;
167#[doc = "Register C (channel = 0)"]
168pub mod rc0;
169#[doc = "SR0 (r) register accessor: an alias for `Reg<SR0_SPEC>`"]
170pub type SR0 = crate::Reg<sr0::SR0_SPEC>;
171#[doc = "Status Register (channel = 0)"]
172pub mod sr0;
173#[doc = "IER0 (w) register accessor: an alias for `Reg<IER0_SPEC>`"]
174pub type IER0 = crate::Reg<ier0::IER0_SPEC>;
175#[doc = "Interrupt Enable Register (channel = 0)"]
176pub mod ier0;
177#[doc = "IDR0 (w) register accessor: an alias for `Reg<IDR0_SPEC>`"]
178pub type IDR0 = crate::Reg<idr0::IDR0_SPEC>;
179#[doc = "Interrupt Disable Register (channel = 0)"]
180pub mod idr0;
181#[doc = "IMR0 (r) register accessor: an alias for `Reg<IMR0_SPEC>`"]
182pub type IMR0 = crate::Reg<imr0::IMR0_SPEC>;
183#[doc = "Interrupt Mask Register (channel = 0)"]
184pub mod imr0;
185#[doc = "EMR0 (rw) register accessor: an alias for `Reg<EMR0_SPEC>`"]
186pub type EMR0 = crate::Reg<emr0::EMR0_SPEC>;
187#[doc = "Extended Mode Register (channel = 0)"]
188pub mod emr0;
189#[doc = "CCR1 (w) register accessor: an alias for `Reg<CCR1_SPEC>`"]
190pub type CCR1 = crate::Reg<ccr1::CCR1_SPEC>;
191#[doc = "Channel Control Register (channel = 1)"]
192pub mod ccr1;
193#[doc = "CMR1 (rw) register accessor: an alias for `Reg<CMR1_SPEC>`"]
194pub type CMR1 = crate::Reg<cmr1::CMR1_SPEC>;
195#[doc = "Channel Mode Register (channel = 1)"]
196pub mod cmr1;
197#[doc = "WAVE_EQ_1_CMR1_WAVE_EQ_1 (rw) register accessor: an alias for `Reg<WAVE_EQ_1_CMR1_WAVE_EQ_1_SPEC>`"]
198pub type WAVE_EQ_1_CMR1_WAVE_EQ_1 =
199 crate::Reg<wave_eq_1_cmr1_wave_eq_1::WAVE_EQ_1_CMR1_WAVE_EQ_1_SPEC>;
200#[doc = "Channel Mode Register (channel = 1)"]
201pub mod wave_eq_1_cmr1_wave_eq_1;
202#[doc = "SMMR1 (rw) register accessor: an alias for `Reg<SMMR1_SPEC>`"]
203pub type SMMR1 = crate::Reg<smmr1::SMMR1_SPEC>;
204#[doc = "Stepper Motor Mode Register (channel = 1)"]
205pub mod smmr1;
206#[doc = "RAB1 (r) register accessor: an alias for `Reg<RAB1_SPEC>`"]
207pub type RAB1 = crate::Reg<rab1::RAB1_SPEC>;
208#[doc = "Register AB (channel = 1)"]
209pub mod rab1;
210#[doc = "CV1 (r) register accessor: an alias for `Reg<CV1_SPEC>`"]
211pub type CV1 = crate::Reg<cv1::CV1_SPEC>;
212#[doc = "Counter Value (channel = 1)"]
213pub mod cv1;
214#[doc = "RA1 (rw) register accessor: an alias for `Reg<RA1_SPEC>`"]
215pub type RA1 = crate::Reg<ra1::RA1_SPEC>;
216#[doc = "Register A (channel = 1)"]
217pub mod ra1;
218#[doc = "RB1 (rw) register accessor: an alias for `Reg<RB1_SPEC>`"]
219pub type RB1 = crate::Reg<rb1::RB1_SPEC>;
220#[doc = "Register B (channel = 1)"]
221pub mod rb1;
222#[doc = "RC1 (rw) register accessor: an alias for `Reg<RC1_SPEC>`"]
223pub type RC1 = crate::Reg<rc1::RC1_SPEC>;
224#[doc = "Register C (channel = 1)"]
225pub mod rc1;
226#[doc = "SR1 (r) register accessor: an alias for `Reg<SR1_SPEC>`"]
227pub type SR1 = crate::Reg<sr1::SR1_SPEC>;
228#[doc = "Status Register (channel = 1)"]
229pub mod sr1;
230#[doc = "IER1 (w) register accessor: an alias for `Reg<IER1_SPEC>`"]
231pub type IER1 = crate::Reg<ier1::IER1_SPEC>;
232#[doc = "Interrupt Enable Register (channel = 1)"]
233pub mod ier1;
234#[doc = "IDR1 (w) register accessor: an alias for `Reg<IDR1_SPEC>`"]
235pub type IDR1 = crate::Reg<idr1::IDR1_SPEC>;
236#[doc = "Interrupt Disable Register (channel = 1)"]
237pub mod idr1;
238#[doc = "IMR1 (r) register accessor: an alias for `Reg<IMR1_SPEC>`"]
239pub type IMR1 = crate::Reg<imr1::IMR1_SPEC>;
240#[doc = "Interrupt Mask Register (channel = 1)"]
241pub mod imr1;
242#[doc = "EMR1 (rw) register accessor: an alias for `Reg<EMR1_SPEC>`"]
243pub type EMR1 = crate::Reg<emr1::EMR1_SPEC>;
244#[doc = "Extended Mode Register (channel = 1)"]
245pub mod emr1;
246#[doc = "CCR2 (w) register accessor: an alias for `Reg<CCR2_SPEC>`"]
247pub type CCR2 = crate::Reg<ccr2::CCR2_SPEC>;
248#[doc = "Channel Control Register (channel = 2)"]
249pub mod ccr2;
250#[doc = "CMR2 (rw) register accessor: an alias for `Reg<CMR2_SPEC>`"]
251pub type CMR2 = crate::Reg<cmr2::CMR2_SPEC>;
252#[doc = "Channel Mode Register (channel = 2)"]
253pub mod cmr2;
254#[doc = "WAVE_EQ_1_CMR2_WAVE_EQ_1 (rw) register accessor: an alias for `Reg<WAVE_EQ_1_CMR2_WAVE_EQ_1_SPEC>`"]
255pub type WAVE_EQ_1_CMR2_WAVE_EQ_1 =
256 crate::Reg<wave_eq_1_cmr2_wave_eq_1::WAVE_EQ_1_CMR2_WAVE_EQ_1_SPEC>;
257#[doc = "Channel Mode Register (channel = 2)"]
258pub mod wave_eq_1_cmr2_wave_eq_1;
259#[doc = "SMMR2 (rw) register accessor: an alias for `Reg<SMMR2_SPEC>`"]
260pub type SMMR2 = crate::Reg<smmr2::SMMR2_SPEC>;
261#[doc = "Stepper Motor Mode Register (channel = 2)"]
262pub mod smmr2;
263#[doc = "RAB2 (r) register accessor: an alias for `Reg<RAB2_SPEC>`"]
264pub type RAB2 = crate::Reg<rab2::RAB2_SPEC>;
265#[doc = "Register AB (channel = 2)"]
266pub mod rab2;
267#[doc = "CV2 (r) register accessor: an alias for `Reg<CV2_SPEC>`"]
268pub type CV2 = crate::Reg<cv2::CV2_SPEC>;
269#[doc = "Counter Value (channel = 2)"]
270pub mod cv2;
271#[doc = "RA2 (rw) register accessor: an alias for `Reg<RA2_SPEC>`"]
272pub type RA2 = crate::Reg<ra2::RA2_SPEC>;
273#[doc = "Register A (channel = 2)"]
274pub mod ra2;
275#[doc = "RB2 (rw) register accessor: an alias for `Reg<RB2_SPEC>`"]
276pub type RB2 = crate::Reg<rb2::RB2_SPEC>;
277#[doc = "Register B (channel = 2)"]
278pub mod rb2;
279#[doc = "RC2 (rw) register accessor: an alias for `Reg<RC2_SPEC>`"]
280pub type RC2 = crate::Reg<rc2::RC2_SPEC>;
281#[doc = "Register C (channel = 2)"]
282pub mod rc2;
283#[doc = "SR2 (r) register accessor: an alias for `Reg<SR2_SPEC>`"]
284pub type SR2 = crate::Reg<sr2::SR2_SPEC>;
285#[doc = "Status Register (channel = 2)"]
286pub mod sr2;
287#[doc = "IER2 (w) register accessor: an alias for `Reg<IER2_SPEC>`"]
288pub type IER2 = crate::Reg<ier2::IER2_SPEC>;
289#[doc = "Interrupt Enable Register (channel = 2)"]
290pub mod ier2;
291#[doc = "IDR2 (w) register accessor: an alias for `Reg<IDR2_SPEC>`"]
292pub type IDR2 = crate::Reg<idr2::IDR2_SPEC>;
293#[doc = "Interrupt Disable Register (channel = 2)"]
294pub mod idr2;
295#[doc = "IMR2 (r) register accessor: an alias for `Reg<IMR2_SPEC>`"]
296pub type IMR2 = crate::Reg<imr2::IMR2_SPEC>;
297#[doc = "Interrupt Mask Register (channel = 2)"]
298pub mod imr2;
299#[doc = "EMR2 (rw) register accessor: an alias for `Reg<EMR2_SPEC>`"]
300pub type EMR2 = crate::Reg<emr2::EMR2_SPEC>;
301#[doc = "Extended Mode Register (channel = 2)"]
302pub mod emr2;
303#[doc = "BCR (w) register accessor: an alias for `Reg<BCR_SPEC>`"]
304pub type BCR = crate::Reg<bcr::BCR_SPEC>;
305#[doc = "Block Control Register"]
306pub mod bcr;
307#[doc = "BMR (rw) register accessor: an alias for `Reg<BMR_SPEC>`"]
308pub type BMR = crate::Reg<bmr::BMR_SPEC>;
309#[doc = "Block Mode Register"]
310pub mod bmr;
311#[doc = "QIER (w) register accessor: an alias for `Reg<QIER_SPEC>`"]
312pub type QIER = crate::Reg<qier::QIER_SPEC>;
313#[doc = "QDEC Interrupt Enable Register"]
314pub mod qier;
315#[doc = "QIDR (w) register accessor: an alias for `Reg<QIDR_SPEC>`"]
316pub type QIDR = crate::Reg<qidr::QIDR_SPEC>;
317#[doc = "QDEC Interrupt Disable Register"]
318pub mod qidr;
319#[doc = "QIMR (r) register accessor: an alias for `Reg<QIMR_SPEC>`"]
320pub type QIMR = crate::Reg<qimr::QIMR_SPEC>;
321#[doc = "QDEC Interrupt Mask Register"]
322pub mod qimr;
323#[doc = "QISR (r) register accessor: an alias for `Reg<QISR_SPEC>`"]
324pub type QISR = crate::Reg<qisr::QISR_SPEC>;
325#[doc = "QDEC Interrupt Status Register"]
326pub mod qisr;
327#[doc = "FMR (rw) register accessor: an alias for `Reg<FMR_SPEC>`"]
328pub type FMR = crate::Reg<fmr::FMR_SPEC>;
329#[doc = "Fault Mode Register"]
330pub mod fmr;
331#[doc = "WPMR (rw) register accessor: an alias for `Reg<WPMR_SPEC>`"]
332pub type WPMR = crate::Reg<wpmr::WPMR_SPEC>;
333#[doc = "Write Protection Mode Register"]
334pub mod wpmr;