atsam4e16e_pac/tc0/
ier2.rs1#[doc = "Register `IER2` writer"]
2pub struct W(crate::W<IER2_SPEC>);
3impl core::ops::Deref for W {
4 type Target = crate::W<IER2_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl core::ops::DerefMut for W {
11 #[inline(always)]
12 fn deref_mut(&mut self) -> &mut Self::Target {
13 &mut self.0
14 }
15}
16impl From<crate::W<IER2_SPEC>> for W {
17 #[inline(always)]
18 fn from(writer: crate::W<IER2_SPEC>) -> Self {
19 W(writer)
20 }
21}
22#[doc = "Field `COVFS` writer - Counter Overflow"]
23pub type COVFS_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER2_SPEC, bool, O>;
24#[doc = "Field `LOVRS` writer - Load Overrun"]
25pub type LOVRS_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER2_SPEC, bool, O>;
26#[doc = "Field `CPAS` writer - RA Compare"]
27pub type CPAS_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER2_SPEC, bool, O>;
28#[doc = "Field `CPBS` writer - RB Compare"]
29pub type CPBS_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER2_SPEC, bool, O>;
30#[doc = "Field `CPCS` writer - RC Compare"]
31pub type CPCS_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER2_SPEC, bool, O>;
32#[doc = "Field `LDRAS` writer - RA Loading"]
33pub type LDRAS_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER2_SPEC, bool, O>;
34#[doc = "Field `LDRBS` writer - RB Loading"]
35pub type LDRBS_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER2_SPEC, bool, O>;
36#[doc = "Field `ETRGS` writer - External Trigger"]
37pub type ETRGS_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER2_SPEC, bool, O>;
38#[doc = "Field `ENDRX` writer - End of Receiver Transfer"]
39pub type ENDRX_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER2_SPEC, bool, O>;
40#[doc = "Field `RXBUFF` writer - Reception Buffer Full"]
41pub type RXBUFF_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER2_SPEC, bool, O>;
42impl W {
43 #[doc = "Bit 0 - Counter Overflow"]
44 #[inline(always)]
45 #[must_use]
46 pub fn covfs(&mut self) -> COVFS_W<0> {
47 COVFS_W::new(self)
48 }
49 #[doc = "Bit 1 - Load Overrun"]
50 #[inline(always)]
51 #[must_use]
52 pub fn lovrs(&mut self) -> LOVRS_W<1> {
53 LOVRS_W::new(self)
54 }
55 #[doc = "Bit 2 - RA Compare"]
56 #[inline(always)]
57 #[must_use]
58 pub fn cpas(&mut self) -> CPAS_W<2> {
59 CPAS_W::new(self)
60 }
61 #[doc = "Bit 3 - RB Compare"]
62 #[inline(always)]
63 #[must_use]
64 pub fn cpbs(&mut self) -> CPBS_W<3> {
65 CPBS_W::new(self)
66 }
67 #[doc = "Bit 4 - RC Compare"]
68 #[inline(always)]
69 #[must_use]
70 pub fn cpcs(&mut self) -> CPCS_W<4> {
71 CPCS_W::new(self)
72 }
73 #[doc = "Bit 5 - RA Loading"]
74 #[inline(always)]
75 #[must_use]
76 pub fn ldras(&mut self) -> LDRAS_W<5> {
77 LDRAS_W::new(self)
78 }
79 #[doc = "Bit 6 - RB Loading"]
80 #[inline(always)]
81 #[must_use]
82 pub fn ldrbs(&mut self) -> LDRBS_W<6> {
83 LDRBS_W::new(self)
84 }
85 #[doc = "Bit 7 - External Trigger"]
86 #[inline(always)]
87 #[must_use]
88 pub fn etrgs(&mut self) -> ETRGS_W<7> {
89 ETRGS_W::new(self)
90 }
91 #[doc = "Bit 8 - End of Receiver Transfer"]
92 #[inline(always)]
93 #[must_use]
94 pub fn endrx(&mut self) -> ENDRX_W<8> {
95 ENDRX_W::new(self)
96 }
97 #[doc = "Bit 9 - Reception Buffer Full"]
98 #[inline(always)]
99 #[must_use]
100 pub fn rxbuff(&mut self) -> RXBUFF_W<9> {
101 RXBUFF_W::new(self)
102 }
103 #[doc = "Writes raw bits to the register."]
104 #[inline(always)]
105 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
106 self.0.bits(bits);
107 self
108 }
109}
110#[doc = "Interrupt Enable Register (channel = 2)\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ier2](index.html) module"]
111pub struct IER2_SPEC;
112impl crate::RegisterSpec for IER2_SPEC {
113 type Ux = u32;
114}
115#[doc = "`write(|w| ..)` method takes [ier2::W](W) writer structure"]
116impl crate::Writable for IER2_SPEC {
117 type Writer = W;
118 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
119 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
120}