atsam4e16c_pac/uart0/
imr.rs

1#[doc = "Register `IMR` reader"]
2pub struct R(crate::R<IMR_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<IMR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<IMR_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<IMR_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Field `RXRDY` reader - Mask RXRDY Interrupt"]
17pub type RXRDY_R = crate::BitReader<bool>;
18#[doc = "Field `TXRDY` reader - Disable TXRDY Interrupt"]
19pub type TXRDY_R = crate::BitReader<bool>;
20#[doc = "Field `ENDRX` reader - Mask End of Receive Transfer Interrupt"]
21pub type ENDRX_R = crate::BitReader<bool>;
22#[doc = "Field `ENDTX` reader - Mask End of Transmit Interrupt"]
23pub type ENDTX_R = crate::BitReader<bool>;
24#[doc = "Field `OVRE` reader - Mask Overrun Error Interrupt"]
25pub type OVRE_R = crate::BitReader<bool>;
26#[doc = "Field `FRAME` reader - Mask Framing Error Interrupt"]
27pub type FRAME_R = crate::BitReader<bool>;
28#[doc = "Field `PARE` reader - Mask Parity Error Interrupt"]
29pub type PARE_R = crate::BitReader<bool>;
30#[doc = "Field `TXEMPTY` reader - Mask TXEMPTY Interrupt"]
31pub type TXEMPTY_R = crate::BitReader<bool>;
32#[doc = "Field `TXBUFE` reader - Mask TXBUFE Interrupt"]
33pub type TXBUFE_R = crate::BitReader<bool>;
34#[doc = "Field `RXBUFF` reader - Mask RXBUFF Interrupt"]
35pub type RXBUFF_R = crate::BitReader<bool>;
36impl R {
37    #[doc = "Bit 0 - Mask RXRDY Interrupt"]
38    #[inline(always)]
39    pub fn rxrdy(&self) -> RXRDY_R {
40        RXRDY_R::new((self.bits & 1) != 0)
41    }
42    #[doc = "Bit 1 - Disable TXRDY Interrupt"]
43    #[inline(always)]
44    pub fn txrdy(&self) -> TXRDY_R {
45        TXRDY_R::new(((self.bits >> 1) & 1) != 0)
46    }
47    #[doc = "Bit 3 - Mask End of Receive Transfer Interrupt"]
48    #[inline(always)]
49    pub fn endrx(&self) -> ENDRX_R {
50        ENDRX_R::new(((self.bits >> 3) & 1) != 0)
51    }
52    #[doc = "Bit 4 - Mask End of Transmit Interrupt"]
53    #[inline(always)]
54    pub fn endtx(&self) -> ENDTX_R {
55        ENDTX_R::new(((self.bits >> 4) & 1) != 0)
56    }
57    #[doc = "Bit 5 - Mask Overrun Error Interrupt"]
58    #[inline(always)]
59    pub fn ovre(&self) -> OVRE_R {
60        OVRE_R::new(((self.bits >> 5) & 1) != 0)
61    }
62    #[doc = "Bit 6 - Mask Framing Error Interrupt"]
63    #[inline(always)]
64    pub fn frame(&self) -> FRAME_R {
65        FRAME_R::new(((self.bits >> 6) & 1) != 0)
66    }
67    #[doc = "Bit 7 - Mask Parity Error Interrupt"]
68    #[inline(always)]
69    pub fn pare(&self) -> PARE_R {
70        PARE_R::new(((self.bits >> 7) & 1) != 0)
71    }
72    #[doc = "Bit 9 - Mask TXEMPTY Interrupt"]
73    #[inline(always)]
74    pub fn txempty(&self) -> TXEMPTY_R {
75        TXEMPTY_R::new(((self.bits >> 9) & 1) != 0)
76    }
77    #[doc = "Bit 11 - Mask TXBUFE Interrupt"]
78    #[inline(always)]
79    pub fn txbufe(&self) -> TXBUFE_R {
80        TXBUFE_R::new(((self.bits >> 11) & 1) != 0)
81    }
82    #[doc = "Bit 12 - Mask RXBUFF Interrupt"]
83    #[inline(always)]
84    pub fn rxbuff(&self) -> RXBUFF_R {
85        RXBUFF_R::new(((self.bits >> 12) & 1) != 0)
86    }
87}
88#[doc = "Interrupt Mask Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [imr](index.html) module"]
89pub struct IMR_SPEC;
90impl crate::RegisterSpec for IMR_SPEC {
91    type Ux = u32;
92}
93#[doc = "`read()` method returns [imr::R](R) reader structure"]
94impl crate::Readable for IMR_SPEC {
95    type Reader = R;
96}
97#[doc = "`reset()` method sets IMR to value 0"]
98impl crate::Resettable for IMR_SPEC {
99    const RESET_VALUE: Self::Ux = 0;
100}
atsam4e16c_pac/uart0/imr.rs

atsam4e16c_pac/uart0/
imr.rs
