atsam4e16c_pac/twi0/
cwgr.rs

1#[doc = "Register `CWGR` reader"]
2pub struct R(crate::R<CWGR_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CWGR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CWGR_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CWGR_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CWGR` writer"]
17pub struct W(crate::W<CWGR_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CWGR_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CWGR_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CWGR_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `CLDIV` reader - Clock Low Divider"]
38pub type CLDIV_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `CLDIV` writer - Clock Low Divider"]
40pub type CLDIV_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CWGR_SPEC, u8, u8, 8, O>;
41#[doc = "Field `CHDIV` reader - Clock High Divider"]
42pub type CHDIV_R = crate::FieldReader<u8, u8>;
43#[doc = "Field `CHDIV` writer - Clock High Divider"]
44pub type CHDIV_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CWGR_SPEC, u8, u8, 8, O>;
45#[doc = "Field `CKDIV` reader - Clock Divider"]
46pub type CKDIV_R = crate::FieldReader<u8, u8>;
47#[doc = "Field `CKDIV` writer - Clock Divider"]
48pub type CKDIV_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CWGR_SPEC, u8, u8, 3, O>;
49impl R {
50    #[doc = "Bits 0:7 - Clock Low Divider"]
51    #[inline(always)]
52    pub fn cldiv(&self) -> CLDIV_R {
53        CLDIV_R::new((self.bits & 0xff) as u8)
54    }
55    #[doc = "Bits 8:15 - Clock High Divider"]
56    #[inline(always)]
57    pub fn chdiv(&self) -> CHDIV_R {
58        CHDIV_R::new(((self.bits >> 8) & 0xff) as u8)
59    }
60    #[doc = "Bits 16:18 - Clock Divider"]
61    #[inline(always)]
62    pub fn ckdiv(&self) -> CKDIV_R {
63        CKDIV_R::new(((self.bits >> 16) & 7) as u8)
64    }
65}
66impl W {
67    #[doc = "Bits 0:7 - Clock Low Divider"]
68    #[inline(always)]
69    #[must_use]
70    pub fn cldiv(&mut self) -> CLDIV_W<0> {
71        CLDIV_W::new(self)
72    }
73    #[doc = "Bits 8:15 - Clock High Divider"]
74    #[inline(always)]
75    #[must_use]
76    pub fn chdiv(&mut self) -> CHDIV_W<8> {
77        CHDIV_W::new(self)
78    }
79    #[doc = "Bits 16:18 - Clock Divider"]
80    #[inline(always)]
81    #[must_use]
82    pub fn ckdiv(&mut self) -> CKDIV_W<16> {
83        CKDIV_W::new(self)
84    }
85    #[doc = "Writes raw bits to the register."]
86    #[inline(always)]
87    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
88        self.0.bits(bits);
89        self
90    }
91}
92#[doc = "Clock Waveform Generator Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cwgr](index.html) module"]
93pub struct CWGR_SPEC;
94impl crate::RegisterSpec for CWGR_SPEC {
95    type Ux = u32;
96}
97#[doc = "`read()` method returns [cwgr::R](R) reader structure"]
98impl crate::Readable for CWGR_SPEC {
99    type Reader = R;
100}
101#[doc = "`write(|w| ..)` method takes [cwgr::W](W) writer structure"]
102impl crate::Writable for CWGR_SPEC {
103    type Writer = W;
104    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
105    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
106}
107#[doc = "`reset()` method sets CWGR to value 0"]
108impl crate::Resettable for CWGR_SPEC {
109    const RESET_VALUE: Self::Ux = 0;
110}
atsam4e16c_pac/twi0/cwgr.rs

atsam4e16c_pac/twi0/
cwgr.rs
