atsam3x8h/dmac/
ctrlb0.rs

1#[doc = "Register `CTRLB0` reader"]
2pub type R = crate::R<Ctrlb0Spec>;
3#[doc = "Register `CTRLB0` writer"]
4pub type W = crate::W<Ctrlb0Spec>;
5#[doc = "Source Address Descriptor\n\nValue on reset: 0"]
6#[derive(Clone, Copy, Debug, PartialEq, Eq)]
7pub enum SrcDscr {
8    #[doc = "0: Source address is updated when the descriptor is fetched from the memory."]
9    FetchFromMem = 0,
10    #[doc = "1: Buffer Descriptor Fetch operation is disabled for the source."]
11    FetchDisable = 1,
12}
13impl From<SrcDscr> for bool {
14    #[inline(always)]
15    fn from(variant: SrcDscr) -> Self {
16        variant as u8 != 0
17    }
18}
19#[doc = "Field `SRC_DSCR` reader - Source Address Descriptor"]
20pub type SrcDscrR = crate::BitReader<SrcDscr>;
21impl SrcDscrR {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> SrcDscr {
25        match self.bits {
26            false => SrcDscr::FetchFromMem,
27            true => SrcDscr::FetchDisable,
28        }
29    }
30    #[doc = "Source address is updated when the descriptor is fetched from the memory."]
31    #[inline(always)]
32    pub fn is_fetch_from_mem(&self) -> bool {
33        *self == SrcDscr::FetchFromMem
34    }
35    #[doc = "Buffer Descriptor Fetch operation is disabled for the source."]
36    #[inline(always)]
37    pub fn is_fetch_disable(&self) -> bool {
38        *self == SrcDscr::FetchDisable
39    }
40}
41#[doc = "Field `SRC_DSCR` writer - Source Address Descriptor"]
42pub type SrcDscrW<'a, REG> = crate::BitWriter<'a, REG, SrcDscr>;
43impl<'a, REG> SrcDscrW<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "Source address is updated when the descriptor is fetched from the memory."]
48    #[inline(always)]
49    pub fn fetch_from_mem(self) -> &'a mut crate::W<REG> {
50        self.variant(SrcDscr::FetchFromMem)
51    }
52    #[doc = "Buffer Descriptor Fetch operation is disabled for the source."]
53    #[inline(always)]
54    pub fn fetch_disable(self) -> &'a mut crate::W<REG> {
55        self.variant(SrcDscr::FetchDisable)
56    }
57}
58#[doc = "Destination Address Descriptor\n\nValue on reset: 0"]
59#[derive(Clone, Copy, Debug, PartialEq, Eq)]
60pub enum DstDscr {
61    #[doc = "0: Destination address is updated when the descriptor is fetched from the memory."]
62    FetchFromMem = 0,
63    #[doc = "1: Buffer Descriptor Fetch operation is disabled for the destination."]
64    FetchDisable = 1,
65}
66impl From<DstDscr> for bool {
67    #[inline(always)]
68    fn from(variant: DstDscr) -> Self {
69        variant as u8 != 0
70    }
71}
72#[doc = "Field `DST_DSCR` reader - Destination Address Descriptor"]
73pub type DstDscrR = crate::BitReader<DstDscr>;
74impl DstDscrR {
75    #[doc = "Get enumerated values variant"]
76    #[inline(always)]
77    pub const fn variant(&self) -> DstDscr {
78        match self.bits {
79            false => DstDscr::FetchFromMem,
80            true => DstDscr::FetchDisable,
81        }
82    }
83    #[doc = "Destination address is updated when the descriptor is fetched from the memory."]
84    #[inline(always)]
85    pub fn is_fetch_from_mem(&self) -> bool {
86        *self == DstDscr::FetchFromMem
87    }
88    #[doc = "Buffer Descriptor Fetch operation is disabled for the destination."]
89    #[inline(always)]
90    pub fn is_fetch_disable(&self) -> bool {
91        *self == DstDscr::FetchDisable
92    }
93}
94#[doc = "Field `DST_DSCR` writer - Destination Address Descriptor"]
95pub type DstDscrW<'a, REG> = crate::BitWriter<'a, REG, DstDscr>;
96impl<'a, REG> DstDscrW<'a, REG>
97where
98    REG: crate::Writable + crate::RegisterSpec,
99{
100    #[doc = "Destination address is updated when the descriptor is fetched from the memory."]
101    #[inline(always)]
102    pub fn fetch_from_mem(self) -> &'a mut crate::W<REG> {
103        self.variant(DstDscr::FetchFromMem)
104    }
105    #[doc = "Buffer Descriptor Fetch operation is disabled for the destination."]
106    #[inline(always)]
107    pub fn fetch_disable(self) -> &'a mut crate::W<REG> {
108        self.variant(DstDscr::FetchDisable)
109    }
110}
111#[doc = "Flow Control\n\nValue on reset: 0"]
112#[derive(Clone, Copy, Debug, PartialEq, Eq)]
113#[repr(u8)]
114pub enum Fc {
115    #[doc = "0: Memory-to-Memory Transfer DMAC is flow controller"]
116    Mem2memDmaFc = 0,
117    #[doc = "1: Memory-to-Peripheral Transfer DMAC is flow controller"]
118    Mem2perDmaFc = 1,
119    #[doc = "2: Peripheral-to-Memory Transfer DMAC is flow controller"]
120    Per2memDmaFc = 2,
121    #[doc = "3: Peripheral-to-Peripheral Transfer DMAC is flow controller"]
122    Per2perDmaFc = 3,
123}
124impl From<Fc> for u8 {
125    #[inline(always)]
126    fn from(variant: Fc) -> Self {
127        variant as _
128    }
129}
130impl crate::FieldSpec for Fc {
131    type Ux = u8;
132}
133impl crate::IsEnum for Fc {}
134#[doc = "Field `FC` reader - Flow Control"]
135pub type FcR = crate::FieldReader<Fc>;
136impl FcR {
137    #[doc = "Get enumerated values variant"]
138    #[inline(always)]
139    pub const fn variant(&self) -> Fc {
140        match self.bits {
141            0 => Fc::Mem2memDmaFc,
142            1 => Fc::Mem2perDmaFc,
143            2 => Fc::Per2memDmaFc,
144            3 => Fc::Per2perDmaFc,
145            _ => unreachable!(),
146        }
147    }
148    #[doc = "Memory-to-Memory Transfer DMAC is flow controller"]
149    #[inline(always)]
150    pub fn is_mem2mem_dma_fc(&self) -> bool {
151        *self == Fc::Mem2memDmaFc
152    }
153    #[doc = "Memory-to-Peripheral Transfer DMAC is flow controller"]
154    #[inline(always)]
155    pub fn is_mem2per_dma_fc(&self) -> bool {
156        *self == Fc::Mem2perDmaFc
157    }
158    #[doc = "Peripheral-to-Memory Transfer DMAC is flow controller"]
159    #[inline(always)]
160    pub fn is_per2mem_dma_fc(&self) -> bool {
161        *self == Fc::Per2memDmaFc
162    }
163    #[doc = "Peripheral-to-Peripheral Transfer DMAC is flow controller"]
164    #[inline(always)]
165    pub fn is_per2per_dma_fc(&self) -> bool {
166        *self == Fc::Per2perDmaFc
167    }
168}
169#[doc = "Field `FC` writer - Flow Control"]
170pub type FcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Fc, crate::Safe>;
171impl<'a, REG> FcW<'a, REG>
172where
173    REG: crate::Writable + crate::RegisterSpec,
174    REG::Ux: From<u8>,
175{
176    #[doc = "Memory-to-Memory Transfer DMAC is flow controller"]
177    #[inline(always)]
178    pub fn mem2mem_dma_fc(self) -> &'a mut crate::W<REG> {
179        self.variant(Fc::Mem2memDmaFc)
180    }
181    #[doc = "Memory-to-Peripheral Transfer DMAC is flow controller"]
182    #[inline(always)]
183    pub fn mem2per_dma_fc(self) -> &'a mut crate::W<REG> {
184        self.variant(Fc::Mem2perDmaFc)
185    }
186    #[doc = "Peripheral-to-Memory Transfer DMAC is flow controller"]
187    #[inline(always)]
188    pub fn per2mem_dma_fc(self) -> &'a mut crate::W<REG> {
189        self.variant(Fc::Per2memDmaFc)
190    }
191    #[doc = "Peripheral-to-Peripheral Transfer DMAC is flow controller"]
192    #[inline(always)]
193    pub fn per2per_dma_fc(self) -> &'a mut crate::W<REG> {
194        self.variant(Fc::Per2perDmaFc)
195    }
196}
197#[doc = "Incrementing, Decrementing or Fixed Address for the Source\n\nValue on reset: 0"]
198#[derive(Clone, Copy, Debug, PartialEq, Eq)]
199#[repr(u8)]
200pub enum SrcIncr {
201    #[doc = "0: The source address is incremented"]
202    Incrementing = 0,
203    #[doc = "1: The source address is decremented"]
204    Decrementing = 1,
205    #[doc = "2: The source address remains unchanged"]
206    Fixed = 2,
207}
208impl From<SrcIncr> for u8 {
209    #[inline(always)]
210    fn from(variant: SrcIncr) -> Self {
211        variant as _
212    }
213}
214impl crate::FieldSpec for SrcIncr {
215    type Ux = u8;
216}
217impl crate::IsEnum for SrcIncr {}
218#[doc = "Field `SRC_INCR` reader - Incrementing, Decrementing or Fixed Address for the Source"]
219pub type SrcIncrR = crate::FieldReader<SrcIncr>;
220impl SrcIncrR {
221    #[doc = "Get enumerated values variant"]
222    #[inline(always)]
223    pub const fn variant(&self) -> Option<SrcIncr> {
224        match self.bits {
225            0 => Some(SrcIncr::Incrementing),
226            1 => Some(SrcIncr::Decrementing),
227            2 => Some(SrcIncr::Fixed),
228            _ => None,
229        }
230    }
231    #[doc = "The source address is incremented"]
232    #[inline(always)]
233    pub fn is_incrementing(&self) -> bool {
234        *self == SrcIncr::Incrementing
235    }
236    #[doc = "The source address is decremented"]
237    #[inline(always)]
238    pub fn is_decrementing(&self) -> bool {
239        *self == SrcIncr::Decrementing
240    }
241    #[doc = "The source address remains unchanged"]
242    #[inline(always)]
243    pub fn is_fixed(&self) -> bool {
244        *self == SrcIncr::Fixed
245    }
246}
247#[doc = "Field `SRC_INCR` writer - Incrementing, Decrementing or Fixed Address for the Source"]
248pub type SrcIncrW<'a, REG> = crate::FieldWriter<'a, REG, 2, SrcIncr>;
249impl<'a, REG> SrcIncrW<'a, REG>
250where
251    REG: crate::Writable + crate::RegisterSpec,
252    REG::Ux: From<u8>,
253{
254    #[doc = "The source address is incremented"]
255    #[inline(always)]
256    pub fn incrementing(self) -> &'a mut crate::W<REG> {
257        self.variant(SrcIncr::Incrementing)
258    }
259    #[doc = "The source address is decremented"]
260    #[inline(always)]
261    pub fn decrementing(self) -> &'a mut crate::W<REG> {
262        self.variant(SrcIncr::Decrementing)
263    }
264    #[doc = "The source address remains unchanged"]
265    #[inline(always)]
266    pub fn fixed(self) -> &'a mut crate::W<REG> {
267        self.variant(SrcIncr::Fixed)
268    }
269}
270#[doc = "Incrementing, Decrementing or Fixed Address for the Destination\n\nValue on reset: 0"]
271#[derive(Clone, Copy, Debug, PartialEq, Eq)]
272#[repr(u8)]
273pub enum DstIncr {
274    #[doc = "0: The destination address is incremented"]
275    Incrementing = 0,
276    #[doc = "1: The destination address is decremented"]
277    Decrementing = 1,
278    #[doc = "2: The destination address remains unchanged"]
279    Fixed = 2,
280}
281impl From<DstIncr> for u8 {
282    #[inline(always)]
283    fn from(variant: DstIncr) -> Self {
284        variant as _
285    }
286}
287impl crate::FieldSpec for DstIncr {
288    type Ux = u8;
289}
290impl crate::IsEnum for DstIncr {}
291#[doc = "Field `DST_INCR` reader - Incrementing, Decrementing or Fixed Address for the Destination"]
292pub type DstIncrR = crate::FieldReader<DstIncr>;
293impl DstIncrR {
294    #[doc = "Get enumerated values variant"]
295    #[inline(always)]
296    pub const fn variant(&self) -> Option<DstIncr> {
297        match self.bits {
298            0 => Some(DstIncr::Incrementing),
299            1 => Some(DstIncr::Decrementing),
300            2 => Some(DstIncr::Fixed),
301            _ => None,
302        }
303    }
304    #[doc = "The destination address is incremented"]
305    #[inline(always)]
306    pub fn is_incrementing(&self) -> bool {
307        *self == DstIncr::Incrementing
308    }
309    #[doc = "The destination address is decremented"]
310    #[inline(always)]
311    pub fn is_decrementing(&self) -> bool {
312        *self == DstIncr::Decrementing
313    }
314    #[doc = "The destination address remains unchanged"]
315    #[inline(always)]
316    pub fn is_fixed(&self) -> bool {
317        *self == DstIncr::Fixed
318    }
319}
320#[doc = "Field `DST_INCR` writer - Incrementing, Decrementing or Fixed Address for the Destination"]
321pub type DstIncrW<'a, REG> = crate::FieldWriter<'a, REG, 2, DstIncr>;
322impl<'a, REG> DstIncrW<'a, REG>
323where
324    REG: crate::Writable + crate::RegisterSpec,
325    REG::Ux: From<u8>,
326{
327    #[doc = "The destination address is incremented"]
328    #[inline(always)]
329    pub fn incrementing(self) -> &'a mut crate::W<REG> {
330        self.variant(DstIncr::Incrementing)
331    }
332    #[doc = "The destination address is decremented"]
333    #[inline(always)]
334    pub fn decrementing(self) -> &'a mut crate::W<REG> {
335        self.variant(DstIncr::Decrementing)
336    }
337    #[doc = "The destination address remains unchanged"]
338    #[inline(always)]
339    pub fn fixed(self) -> &'a mut crate::W<REG> {
340        self.variant(DstIncr::Fixed)
341    }
342}
343#[doc = "Field `IEN` reader - Interrupt Enable Not"]
344pub type IenR = crate::BitReader;
345#[doc = "Field `IEN` writer - Interrupt Enable Not"]
346pub type IenW<'a, REG> = crate::BitWriter<'a, REG>;
347impl R {
348    #[doc = "Bit 16 - Source Address Descriptor"]
349    #[inline(always)]
350    pub fn src_dscr(&self) -> SrcDscrR {
351        SrcDscrR::new(((self.bits >> 16) & 1) != 0)
352    }
353    #[doc = "Bit 20 - Destination Address Descriptor"]
354    #[inline(always)]
355    pub fn dst_dscr(&self) -> DstDscrR {
356        DstDscrR::new(((self.bits >> 20) & 1) != 0)
357    }
358    #[doc = "Bits 21:22 - Flow Control"]
359    #[inline(always)]
360    pub fn fc(&self) -> FcR {
361        FcR::new(((self.bits >> 21) & 3) as u8)
362    }
363    #[doc = "Bits 24:25 - Incrementing, Decrementing or Fixed Address for the Source"]
364    #[inline(always)]
365    pub fn src_incr(&self) -> SrcIncrR {
366        SrcIncrR::new(((self.bits >> 24) & 3) as u8)
367    }
368    #[doc = "Bits 28:29 - Incrementing, Decrementing or Fixed Address for the Destination"]
369    #[inline(always)]
370    pub fn dst_incr(&self) -> DstIncrR {
371        DstIncrR::new(((self.bits >> 28) & 3) as u8)
372    }
373    #[doc = "Bit 30 - Interrupt Enable Not"]
374    #[inline(always)]
375    pub fn ien(&self) -> IenR {
376        IenR::new(((self.bits >> 30) & 1) != 0)
377    }
378}
379impl W {
380    #[doc = "Bit 16 - Source Address Descriptor"]
381    #[inline(always)]
382    #[must_use]
383    pub fn src_dscr(&mut self) -> SrcDscrW<Ctrlb0Spec> {
384        SrcDscrW::new(self, 16)
385    }
386    #[doc = "Bit 20 - Destination Address Descriptor"]
387    #[inline(always)]
388    #[must_use]
389    pub fn dst_dscr(&mut self) -> DstDscrW<Ctrlb0Spec> {
390        DstDscrW::new(self, 20)
391    }
392    #[doc = "Bits 21:22 - Flow Control"]
393    #[inline(always)]
394    #[must_use]
395    pub fn fc(&mut self) -> FcW<Ctrlb0Spec> {
396        FcW::new(self, 21)
397    }
398    #[doc = "Bits 24:25 - Incrementing, Decrementing or Fixed Address for the Source"]
399    #[inline(always)]
400    #[must_use]
401    pub fn src_incr(&mut self) -> SrcIncrW<Ctrlb0Spec> {
402        SrcIncrW::new(self, 24)
403    }
404    #[doc = "Bits 28:29 - Incrementing, Decrementing or Fixed Address for the Destination"]
405    #[inline(always)]
406    #[must_use]
407    pub fn dst_incr(&mut self) -> DstIncrW<Ctrlb0Spec> {
408        DstIncrW::new(self, 28)
409    }
410    #[doc = "Bit 30 - Interrupt Enable Not"]
411    #[inline(always)]
412    #[must_use]
413    pub fn ien(&mut self) -> IenW<Ctrlb0Spec> {
414        IenW::new(self, 30)
415    }
416}
417#[doc = "DMAC Channel Control B Register (ch_num = 0)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrlb0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrlb0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
418pub struct Ctrlb0Spec;
419impl crate::RegisterSpec for Ctrlb0Spec {
420    type Ux = u32;
421}
422#[doc = "`read()` method returns [`ctrlb0::R`](R) reader structure"]
423impl crate::Readable for Ctrlb0Spec {}
424#[doc = "`write(|w| ..)` method takes [`ctrlb0::W`](W) writer structure"]
425impl crate::Writable for Ctrlb0Spec {
426    type Safety = crate::Unsafe;
427    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
428    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
429}
430#[doc = "`reset()` method sets CTRLB0 to value 0"]
431impl crate::Resettable for Ctrlb0Spec {
432    const RESET_VALUE: u32 = 0;
433}
atsam3x8h/dmac/ctrlb0.rs

atsam3x8h/dmac/
ctrlb0.rs
