atsam3x4e/uotghs/
devicr.rs

1#[doc = "Register `DEVICR` writer"]
2pub type W = crate::W<DevicrSpec>;
3#[doc = "Field `SUSPC` writer - Suspend Interrupt Clear"]
4pub type SuspcW<'a, REG> = crate::BitWriter<'a, REG>;
5#[doc = "Field `MSOFC` writer - Micro Start of Frame Interrupt Clear"]
6pub type MsofcW<'a, REG> = crate::BitWriter<'a, REG>;
7#[doc = "Field `SOFC` writer - Start of Frame Interrupt Clear"]
8pub type SofcW<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `EORSTC` writer - End of Reset Interrupt Clear"]
10pub type EorstcW<'a, REG> = crate::BitWriter<'a, REG>;
11#[doc = "Field `WAKEUPC` writer - Wake-Up Interrupt Clear"]
12pub type WakeupcW<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `EORSMC` writer - End of Resume Interrupt Clear"]
14pub type EorsmcW<'a, REG> = crate::BitWriter<'a, REG>;
15#[doc = "Field `UPRSMC` writer - Upstream Resume Interrupt Clear"]
16pub type UprsmcW<'a, REG> = crate::BitWriter<'a, REG>;
17impl W {
18    #[doc = "Bit 0 - Suspend Interrupt Clear"]
19    #[inline(always)]
20    #[must_use]
21    pub fn suspc(&mut self) -> SuspcW<DevicrSpec> {
22        SuspcW::new(self, 0)
23    }
24    #[doc = "Bit 1 - Micro Start of Frame Interrupt Clear"]
25    #[inline(always)]
26    #[must_use]
27    pub fn msofc(&mut self) -> MsofcW<DevicrSpec> {
28        MsofcW::new(self, 1)
29    }
30    #[doc = "Bit 2 - Start of Frame Interrupt Clear"]
31    #[inline(always)]
32    #[must_use]
33    pub fn sofc(&mut self) -> SofcW<DevicrSpec> {
34        SofcW::new(self, 2)
35    }
36    #[doc = "Bit 3 - End of Reset Interrupt Clear"]
37    #[inline(always)]
38    #[must_use]
39    pub fn eorstc(&mut self) -> EorstcW<DevicrSpec> {
40        EorstcW::new(self, 3)
41    }
42    #[doc = "Bit 4 - Wake-Up Interrupt Clear"]
43    #[inline(always)]
44    #[must_use]
45    pub fn wakeupc(&mut self) -> WakeupcW<DevicrSpec> {
46        WakeupcW::new(self, 4)
47    }
48    #[doc = "Bit 5 - End of Resume Interrupt Clear"]
49    #[inline(always)]
50    #[must_use]
51    pub fn eorsmc(&mut self) -> EorsmcW<DevicrSpec> {
52        EorsmcW::new(self, 5)
53    }
54    #[doc = "Bit 6 - Upstream Resume Interrupt Clear"]
55    #[inline(always)]
56    #[must_use]
57    pub fn uprsmc(&mut self) -> UprsmcW<DevicrSpec> {
58        UprsmcW::new(self, 6)
59    }
60}
61#[doc = "Device Global Interrupt Clear Register\n\nYou can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`devicr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
62pub struct DevicrSpec;
63impl crate::RegisterSpec for DevicrSpec {
64    type Ux = u32;
65}
66#[doc = "`write(|w| ..)` method takes [`devicr::W`](W) writer structure"]
67impl crate::Writable for DevicrSpec {
68    type Safety = crate::Unsafe;
69    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
70    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
71}
atsam3x4e/uotghs/devicr.rs

atsam3x4e/uotghs/
devicr.rs
