atsam3x4e/dmac/
cfg2.rs

1#[doc = "Register `CFG2` reader"]
2pub type R = crate::R<Cfg2Spec>;
3#[doc = "Register `CFG2` writer"]
4pub type W = crate::W<Cfg2Spec>;
5#[doc = "Field `SRC_PER` reader - Source with Peripheral identifier"]
6pub type SrcPerR = crate::FieldReader;
7#[doc = "Field `SRC_PER` writer - Source with Peripheral identifier"]
8pub type SrcPerW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
9#[doc = "Field `DST_PER` reader - Destination with Peripheral identifier"]
10pub type DstPerR = crate::FieldReader;
11#[doc = "Field `DST_PER` writer - Destination with Peripheral identifier"]
12pub type DstPerW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
13#[doc = "Software or Hardware Selection for the Source\n\nValue on reset: 0"]
14#[derive(Clone, Copy, Debug, PartialEq, Eq)]
15pub enum SrcH2sel {
16    #[doc = "0: Software handshaking interface is used to trigger a transfer request."]
17    Sw = 0,
18    #[doc = "1: Hardware handshaking interface is used to trigger a transfer request."]
19    Hw = 1,
20}
21impl From<SrcH2sel> for bool {
22    #[inline(always)]
23    fn from(variant: SrcH2sel) -> Self {
24        variant as u8 != 0
25    }
26}
27#[doc = "Field `SRC_H2SEL` reader - Software or Hardware Selection for the Source"]
28pub type SrcH2selR = crate::BitReader<SrcH2sel>;
29impl SrcH2selR {
30    #[doc = "Get enumerated values variant"]
31    #[inline(always)]
32    pub const fn variant(&self) -> SrcH2sel {
33        match self.bits {
34            false => SrcH2sel::Sw,
35            true => SrcH2sel::Hw,
36        }
37    }
38    #[doc = "Software handshaking interface is used to trigger a transfer request."]
39    #[inline(always)]
40    pub fn is_sw(&self) -> bool {
41        *self == SrcH2sel::Sw
42    }
43    #[doc = "Hardware handshaking interface is used to trigger a transfer request."]
44    #[inline(always)]
45    pub fn is_hw(&self) -> bool {
46        *self == SrcH2sel::Hw
47    }
48}
49#[doc = "Field `SRC_H2SEL` writer - Software or Hardware Selection for the Source"]
50pub type SrcH2selW<'a, REG> = crate::BitWriter<'a, REG, SrcH2sel>;
51impl<'a, REG> SrcH2selW<'a, REG>
52where
53    REG: crate::Writable + crate::RegisterSpec,
54{
55    #[doc = "Software handshaking interface is used to trigger a transfer request."]
56    #[inline(always)]
57    pub fn sw(self) -> &'a mut crate::W<REG> {
58        self.variant(SrcH2sel::Sw)
59    }
60    #[doc = "Hardware handshaking interface is used to trigger a transfer request."]
61    #[inline(always)]
62    pub fn hw(self) -> &'a mut crate::W<REG> {
63        self.variant(SrcH2sel::Hw)
64    }
65}
66#[doc = "Software or Hardware Selection for the Destination\n\nValue on reset: 0"]
67#[derive(Clone, Copy, Debug, PartialEq, Eq)]
68pub enum DstH2sel {
69    #[doc = "0: Software handshaking interface is used to trigger a transfer request."]
70    Sw = 0,
71    #[doc = "1: Hardware handshaking interface is used to trigger a transfer request."]
72    Hw = 1,
73}
74impl From<DstH2sel> for bool {
75    #[inline(always)]
76    fn from(variant: DstH2sel) -> Self {
77        variant as u8 != 0
78    }
79}
80#[doc = "Field `DST_H2SEL` reader - Software or Hardware Selection for the Destination"]
81pub type DstH2selR = crate::BitReader<DstH2sel>;
82impl DstH2selR {
83    #[doc = "Get enumerated values variant"]
84    #[inline(always)]
85    pub const fn variant(&self) -> DstH2sel {
86        match self.bits {
87            false => DstH2sel::Sw,
88            true => DstH2sel::Hw,
89        }
90    }
91    #[doc = "Software handshaking interface is used to trigger a transfer request."]
92    #[inline(always)]
93    pub fn is_sw(&self) -> bool {
94        *self == DstH2sel::Sw
95    }
96    #[doc = "Hardware handshaking interface is used to trigger a transfer request."]
97    #[inline(always)]
98    pub fn is_hw(&self) -> bool {
99        *self == DstH2sel::Hw
100    }
101}
102#[doc = "Field `DST_H2SEL` writer - Software or Hardware Selection for the Destination"]
103pub type DstH2selW<'a, REG> = crate::BitWriter<'a, REG, DstH2sel>;
104impl<'a, REG> DstH2selW<'a, REG>
105where
106    REG: crate::Writable + crate::RegisterSpec,
107{
108    #[doc = "Software handshaking interface is used to trigger a transfer request."]
109    #[inline(always)]
110    pub fn sw(self) -> &'a mut crate::W<REG> {
111        self.variant(DstH2sel::Sw)
112    }
113    #[doc = "Hardware handshaking interface is used to trigger a transfer request."]
114    #[inline(always)]
115    pub fn hw(self) -> &'a mut crate::W<REG> {
116        self.variant(DstH2sel::Hw)
117    }
118}
119#[doc = "Stop On Done\n\nValue on reset: 0"]
120#[derive(Clone, Copy, Debug, PartialEq, Eq)]
121pub enum Sod {
122    #[doc = "0: STOP ON DONE disabled, the descriptor fetch operation ignores DONE Field of CTRLA register."]
123    Disable = 0,
124    #[doc = "1: STOP ON DONE activated, the DMAC module is automatically disabled if DONE FIELD is set to 1."]
125    Enable = 1,
126}
127impl From<Sod> for bool {
128    #[inline(always)]
129    fn from(variant: Sod) -> Self {
130        variant as u8 != 0
131    }
132}
133#[doc = "Field `SOD` reader - Stop On Done"]
134pub type SodR = crate::BitReader<Sod>;
135impl SodR {
136    #[doc = "Get enumerated values variant"]
137    #[inline(always)]
138    pub const fn variant(&self) -> Sod {
139        match self.bits {
140            false => Sod::Disable,
141            true => Sod::Enable,
142        }
143    }
144    #[doc = "STOP ON DONE disabled, the descriptor fetch operation ignores DONE Field of CTRLA register."]
145    #[inline(always)]
146    pub fn is_disable(&self) -> bool {
147        *self == Sod::Disable
148    }
149    #[doc = "STOP ON DONE activated, the DMAC module is automatically disabled if DONE FIELD is set to 1."]
150    #[inline(always)]
151    pub fn is_enable(&self) -> bool {
152        *self == Sod::Enable
153    }
154}
155#[doc = "Field `SOD` writer - Stop On Done"]
156pub type SodW<'a, REG> = crate::BitWriter<'a, REG, Sod>;
157impl<'a, REG> SodW<'a, REG>
158where
159    REG: crate::Writable + crate::RegisterSpec,
160{
161    #[doc = "STOP ON DONE disabled, the descriptor fetch operation ignores DONE Field of CTRLA register."]
162    #[inline(always)]
163    pub fn disable(self) -> &'a mut crate::W<REG> {
164        self.variant(Sod::Disable)
165    }
166    #[doc = "STOP ON DONE activated, the DMAC module is automatically disabled if DONE FIELD is set to 1."]
167    #[inline(always)]
168    pub fn enable(self) -> &'a mut crate::W<REG> {
169        self.variant(Sod::Enable)
170    }
171}
172#[doc = "Interface Lock\n\nValue on reset: 0"]
173#[derive(Clone, Copy, Debug, PartialEq, Eq)]
174pub enum LockIf {
175    #[doc = "0: Interface Lock capability is disabled"]
176    Disable = 0,
177    #[doc = "1: Interface Lock capability is enabled"]
178    Enable = 1,
179}
180impl From<LockIf> for bool {
181    #[inline(always)]
182    fn from(variant: LockIf) -> Self {
183        variant as u8 != 0
184    }
185}
186#[doc = "Field `LOCK_IF` reader - Interface Lock"]
187pub type LockIfR = crate::BitReader<LockIf>;
188impl LockIfR {
189    #[doc = "Get enumerated values variant"]
190    #[inline(always)]
191    pub const fn variant(&self) -> LockIf {
192        match self.bits {
193            false => LockIf::Disable,
194            true => LockIf::Enable,
195        }
196    }
197    #[doc = "Interface Lock capability is disabled"]
198    #[inline(always)]
199    pub fn is_disable(&self) -> bool {
200        *self == LockIf::Disable
201    }
202    #[doc = "Interface Lock capability is enabled"]
203    #[inline(always)]
204    pub fn is_enable(&self) -> bool {
205        *self == LockIf::Enable
206    }
207}
208#[doc = "Field `LOCK_IF` writer - Interface Lock"]
209pub type LockIfW<'a, REG> = crate::BitWriter<'a, REG, LockIf>;
210impl<'a, REG> LockIfW<'a, REG>
211where
212    REG: crate::Writable + crate::RegisterSpec,
213{
214    #[doc = "Interface Lock capability is disabled"]
215    #[inline(always)]
216    pub fn disable(self) -> &'a mut crate::W<REG> {
217        self.variant(LockIf::Disable)
218    }
219    #[doc = "Interface Lock capability is enabled"]
220    #[inline(always)]
221    pub fn enable(self) -> &'a mut crate::W<REG> {
222        self.variant(LockIf::Enable)
223    }
224}
225#[doc = "Bus Lock\n\nValue on reset: 0"]
226#[derive(Clone, Copy, Debug, PartialEq, Eq)]
227pub enum LockB {
228    #[doc = "0: AHB Bus Locking capability is disabled."]
229    Disable = 0,
230}
231impl From<LockB> for bool {
232    #[inline(always)]
233    fn from(variant: LockB) -> Self {
234        variant as u8 != 0
235    }
236}
237#[doc = "Field `LOCK_B` reader - Bus Lock"]
238pub type LockBR = crate::BitReader<LockB>;
239impl LockBR {
240    #[doc = "Get enumerated values variant"]
241    #[inline(always)]
242    pub const fn variant(&self) -> Option<LockB> {
243        match self.bits {
244            false => Some(LockB::Disable),
245            _ => None,
246        }
247    }
248    #[doc = "AHB Bus Locking capability is disabled."]
249    #[inline(always)]
250    pub fn is_disable(&self) -> bool {
251        *self == LockB::Disable
252    }
253}
254#[doc = "Field `LOCK_B` writer - Bus Lock"]
255pub type LockBW<'a, REG> = crate::BitWriter<'a, REG, LockB>;
256impl<'a, REG> LockBW<'a, REG>
257where
258    REG: crate::Writable + crate::RegisterSpec,
259{
260    #[doc = "AHB Bus Locking capability is disabled."]
261    #[inline(always)]
262    pub fn disable(self) -> &'a mut crate::W<REG> {
263        self.variant(LockB::Disable)
264    }
265}
266#[doc = "Master Interface Arbiter Lock\n\nValue on reset: 0"]
267#[derive(Clone, Copy, Debug, PartialEq, Eq)]
268pub enum LockIfL {
269    #[doc = "0: The Master Interface Arbiter is locked by the channel x for a chunk transfer."]
270    Chunk = 0,
271    #[doc = "1: The Master Interface Arbiter is locked by the channel x for a buffer transfer."]
272    Buffer = 1,
273}
274impl From<LockIfL> for bool {
275    #[inline(always)]
276    fn from(variant: LockIfL) -> Self {
277        variant as u8 != 0
278    }
279}
280#[doc = "Field `LOCK_IF_L` reader - Master Interface Arbiter Lock"]
281pub type LockIfLR = crate::BitReader<LockIfL>;
282impl LockIfLR {
283    #[doc = "Get enumerated values variant"]
284    #[inline(always)]
285    pub const fn variant(&self) -> LockIfL {
286        match self.bits {
287            false => LockIfL::Chunk,
288            true => LockIfL::Buffer,
289        }
290    }
291    #[doc = "The Master Interface Arbiter is locked by the channel x for a chunk transfer."]
292    #[inline(always)]
293    pub fn is_chunk(&self) -> bool {
294        *self == LockIfL::Chunk
295    }
296    #[doc = "The Master Interface Arbiter is locked by the channel x for a buffer transfer."]
297    #[inline(always)]
298    pub fn is_buffer(&self) -> bool {
299        *self == LockIfL::Buffer
300    }
301}
302#[doc = "Field `LOCK_IF_L` writer - Master Interface Arbiter Lock"]
303pub type LockIfLW<'a, REG> = crate::BitWriter<'a, REG, LockIfL>;
304impl<'a, REG> LockIfLW<'a, REG>
305where
306    REG: crate::Writable + crate::RegisterSpec,
307{
308    #[doc = "The Master Interface Arbiter is locked by the channel x for a chunk transfer."]
309    #[inline(always)]
310    pub fn chunk(self) -> &'a mut crate::W<REG> {
311        self.variant(LockIfL::Chunk)
312    }
313    #[doc = "The Master Interface Arbiter is locked by the channel x for a buffer transfer."]
314    #[inline(always)]
315    pub fn buffer(self) -> &'a mut crate::W<REG> {
316        self.variant(LockIfL::Buffer)
317    }
318}
319#[doc = "Field `AHB_PROT` reader - AHB Protection"]
320pub type AhbProtR = crate::FieldReader;
321#[doc = "Field `AHB_PROT` writer - AHB Protection"]
322pub type AhbProtW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
323#[doc = "FIFO Configuration\n\nValue on reset: 0"]
324#[derive(Clone, Copy, Debug, PartialEq, Eq)]
325#[repr(u8)]
326pub enum Fifocfg {
327    #[doc = "0: The largest defined length AHB burst is performed on the destination AHB interface."]
328    AlapCfg = 0,
329    #[doc = "1: When half FIFO size is available/filled, a source/destination request is serviced."]
330    HalfCfg = 1,
331    #[doc = "2: When there is enough space/data available to perform a single AHB access, then the request is serviced."]
332    AsapCfg = 2,
333}
334impl From<Fifocfg> for u8 {
335    #[inline(always)]
336    fn from(variant: Fifocfg) -> Self {
337        variant as _
338    }
339}
340impl crate::FieldSpec for Fifocfg {
341    type Ux = u8;
342}
343impl crate::IsEnum for Fifocfg {}
344#[doc = "Field `FIFOCFG` reader - FIFO Configuration"]
345pub type FifocfgR = crate::FieldReader<Fifocfg>;
346impl FifocfgR {
347    #[doc = "Get enumerated values variant"]
348    #[inline(always)]
349    pub const fn variant(&self) -> Option<Fifocfg> {
350        match self.bits {
351            0 => Some(Fifocfg::AlapCfg),
352            1 => Some(Fifocfg::HalfCfg),
353            2 => Some(Fifocfg::AsapCfg),
354            _ => None,
355        }
356    }
357    #[doc = "The largest defined length AHB burst is performed on the destination AHB interface."]
358    #[inline(always)]
359    pub fn is_alap_cfg(&self) -> bool {
360        *self == Fifocfg::AlapCfg
361    }
362    #[doc = "When half FIFO size is available/filled, a source/destination request is serviced."]
363    #[inline(always)]
364    pub fn is_half_cfg(&self) -> bool {
365        *self == Fifocfg::HalfCfg
366    }
367    #[doc = "When there is enough space/data available to perform a single AHB access, then the request is serviced."]
368    #[inline(always)]
369    pub fn is_asap_cfg(&self) -> bool {
370        *self == Fifocfg::AsapCfg
371    }
372}
373#[doc = "Field `FIFOCFG` writer - FIFO Configuration"]
374pub type FifocfgW<'a, REG> = crate::FieldWriter<'a, REG, 2, Fifocfg>;
375impl<'a, REG> FifocfgW<'a, REG>
376where
377    REG: crate::Writable + crate::RegisterSpec,
378    REG::Ux: From<u8>,
379{
380    #[doc = "The largest defined length AHB burst is performed on the destination AHB interface."]
381    #[inline(always)]
382    pub fn alap_cfg(self) -> &'a mut crate::W<REG> {
383        self.variant(Fifocfg::AlapCfg)
384    }
385    #[doc = "When half FIFO size is available/filled, a source/destination request is serviced."]
386    #[inline(always)]
387    pub fn half_cfg(self) -> &'a mut crate::W<REG> {
388        self.variant(Fifocfg::HalfCfg)
389    }
390    #[doc = "When there is enough space/data available to perform a single AHB access, then the request is serviced."]
391    #[inline(always)]
392    pub fn asap_cfg(self) -> &'a mut crate::W<REG> {
393        self.variant(Fifocfg::AsapCfg)
394    }
395}
396impl R {
397    #[doc = "Bits 0:3 - Source with Peripheral identifier"]
398    #[inline(always)]
399    pub fn src_per(&self) -> SrcPerR {
400        SrcPerR::new((self.bits & 0x0f) as u8)
401    }
402    #[doc = "Bits 4:7 - Destination with Peripheral identifier"]
403    #[inline(always)]
404    pub fn dst_per(&self) -> DstPerR {
405        DstPerR::new(((self.bits >> 4) & 0x0f) as u8)
406    }
407    #[doc = "Bit 9 - Software or Hardware Selection for the Source"]
408    #[inline(always)]
409    pub fn src_h2sel(&self) -> SrcH2selR {
410        SrcH2selR::new(((self.bits >> 9) & 1) != 0)
411    }
412    #[doc = "Bit 13 - Software or Hardware Selection for the Destination"]
413    #[inline(always)]
414    pub fn dst_h2sel(&self) -> DstH2selR {
415        DstH2selR::new(((self.bits >> 13) & 1) != 0)
416    }
417    #[doc = "Bit 16 - Stop On Done"]
418    #[inline(always)]
419    pub fn sod(&self) -> SodR {
420        SodR::new(((self.bits >> 16) & 1) != 0)
421    }
422    #[doc = "Bit 20 - Interface Lock"]
423    #[inline(always)]
424    pub fn lock_if(&self) -> LockIfR {
425        LockIfR::new(((self.bits >> 20) & 1) != 0)
426    }
427    #[doc = "Bit 21 - Bus Lock"]
428    #[inline(always)]
429    pub fn lock_b(&self) -> LockBR {
430        LockBR::new(((self.bits >> 21) & 1) != 0)
431    }
432    #[doc = "Bit 22 - Master Interface Arbiter Lock"]
433    #[inline(always)]
434    pub fn lock_if_l(&self) -> LockIfLR {
435        LockIfLR::new(((self.bits >> 22) & 1) != 0)
436    }
437    #[doc = "Bits 24:26 - AHB Protection"]
438    #[inline(always)]
439    pub fn ahb_prot(&self) -> AhbProtR {
440        AhbProtR::new(((self.bits >> 24) & 7) as u8)
441    }
442    #[doc = "Bits 28:29 - FIFO Configuration"]
443    #[inline(always)]
444    pub fn fifocfg(&self) -> FifocfgR {
445        FifocfgR::new(((self.bits >> 28) & 3) as u8)
446    }
447}
448impl W {
449    #[doc = "Bits 0:3 - Source with Peripheral identifier"]
450    #[inline(always)]
451    #[must_use]
452    pub fn src_per(&mut self) -> SrcPerW<Cfg2Spec> {
453        SrcPerW::new(self, 0)
454    }
455    #[doc = "Bits 4:7 - Destination with Peripheral identifier"]
456    #[inline(always)]
457    #[must_use]
458    pub fn dst_per(&mut self) -> DstPerW<Cfg2Spec> {
459        DstPerW::new(self, 4)
460    }
461    #[doc = "Bit 9 - Software or Hardware Selection for the Source"]
462    #[inline(always)]
463    #[must_use]
464    pub fn src_h2sel(&mut self) -> SrcH2selW<Cfg2Spec> {
465        SrcH2selW::new(self, 9)
466    }
467    #[doc = "Bit 13 - Software or Hardware Selection for the Destination"]
468    #[inline(always)]
469    #[must_use]
470    pub fn dst_h2sel(&mut self) -> DstH2selW<Cfg2Spec> {
471        DstH2selW::new(self, 13)
472    }
473    #[doc = "Bit 16 - Stop On Done"]
474    #[inline(always)]
475    #[must_use]
476    pub fn sod(&mut self) -> SodW<Cfg2Spec> {
477        SodW::new(self, 16)
478    }
479    #[doc = "Bit 20 - Interface Lock"]
480    #[inline(always)]
481    #[must_use]
482    pub fn lock_if(&mut self) -> LockIfW<Cfg2Spec> {
483        LockIfW::new(self, 20)
484    }
485    #[doc = "Bit 21 - Bus Lock"]
486    #[inline(always)]
487    #[must_use]
488    pub fn lock_b(&mut self) -> LockBW<Cfg2Spec> {
489        LockBW::new(self, 21)
490    }
491    #[doc = "Bit 22 - Master Interface Arbiter Lock"]
492    #[inline(always)]
493    #[must_use]
494    pub fn lock_if_l(&mut self) -> LockIfLW<Cfg2Spec> {
495        LockIfLW::new(self, 22)
496    }
497    #[doc = "Bits 24:26 - AHB Protection"]
498    #[inline(always)]
499    #[must_use]
500    pub fn ahb_prot(&mut self) -> AhbProtW<Cfg2Spec> {
501        AhbProtW::new(self, 24)
502    }
503    #[doc = "Bits 28:29 - FIFO Configuration"]
504    #[inline(always)]
505    #[must_use]
506    pub fn fifocfg(&mut self) -> FifocfgW<Cfg2Spec> {
507        FifocfgW::new(self, 28)
508    }
509}
510#[doc = "DMAC Channel Configuration Register (ch_num = 2)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfg2::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfg2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
511pub struct Cfg2Spec;
512impl crate::RegisterSpec for Cfg2Spec {
513    type Ux = u32;
514}
515#[doc = "`read()` method returns [`cfg2::R`](R) reader structure"]
516impl crate::Readable for Cfg2Spec {}
517#[doc = "`write(|w| ..)` method takes [`cfg2::W`](W) writer structure"]
518impl crate::Writable for Cfg2Spec {
519    type Safety = crate::Unsafe;
520    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
521    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
522}
523#[doc = "`reset()` method sets CFG2 to value 0x0100_0000"]
524impl crate::Resettable for Cfg2Spec {
525    const RESET_VALUE: u32 = 0x0100_0000;
526}
atsam3x4e/dmac/cfg2.rs

atsam3x4e/dmac/
cfg2.rs
