atsam3u4e/udphs/
dmacontrol2.rs

1#[doc = "Register `DMACONTROL2` reader"]
2pub type R = crate::R<Dmacontrol2Spec>;
3#[doc = "Register `DMACONTROL2` writer"]
4pub type W = crate::W<Dmacontrol2Spec>;
5#[doc = "Field `CHANN_ENB` reader - (Channel Enable Command)"]
6pub type ChannEnbR = crate::BitReader;
7#[doc = "Field `CHANN_ENB` writer - (Channel Enable Command)"]
8pub type ChannEnbW<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `LDNXT_DSC` reader - Load Next Channel Transfer Descriptor Enable (Command)"]
10pub type LdnxtDscR = crate::BitReader;
11#[doc = "Field `LDNXT_DSC` writer - Load Next Channel Transfer Descriptor Enable (Command)"]
12pub type LdnxtDscW<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `END_TR_EN` reader - End of Transfer Enable (Control)"]
14pub type EndTrEnR = crate::BitReader;
15#[doc = "Field `END_TR_EN` writer - End of Transfer Enable (Control)"]
16pub type EndTrEnW<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `END_B_EN` reader - End of Buffer Enable (Control)"]
18pub type EndBEnR = crate::BitReader;
19#[doc = "Field `END_B_EN` writer - End of Buffer Enable (Control)"]
20pub type EndBEnW<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `END_TR_IT` reader - End of Transfer Interrupt Enable"]
22pub type EndTrItR = crate::BitReader;
23#[doc = "Field `END_TR_IT` writer - End of Transfer Interrupt Enable"]
24pub type EndTrItW<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `END_BUFFIT` reader - End of Buffer Interrupt Enable"]
26pub type EndBuffitR = crate::BitReader;
27#[doc = "Field `END_BUFFIT` writer - End of Buffer Interrupt Enable"]
28pub type EndBuffitW<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `DESC_LD_IT` reader - Descriptor Loaded Interrupt Enable"]
30pub type DescLdItR = crate::BitReader;
31#[doc = "Field `DESC_LD_IT` writer - Descriptor Loaded Interrupt Enable"]
32pub type DescLdItW<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `BURST_LCK` reader - Burst Lock Enable"]
34pub type BurstLckR = crate::BitReader;
35#[doc = "Field `BURST_LCK` writer - Burst Lock Enable"]
36pub type BurstLckW<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `BUFF_LENGTH` reader - Buffer Byte Length (Write-only)"]
38pub type BuffLengthR = crate::FieldReader<u16>;
39#[doc = "Field `BUFF_LENGTH` writer - Buffer Byte Length (Write-only)"]
40pub type BuffLengthW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
41impl R {
42    #[doc = "Bit 0 - (Channel Enable Command)"]
43    #[inline(always)]
44    pub fn chann_enb(&self) -> ChannEnbR {
45        ChannEnbR::new((self.bits & 1) != 0)
46    }
47    #[doc = "Bit 1 - Load Next Channel Transfer Descriptor Enable (Command)"]
48    #[inline(always)]
49    pub fn ldnxt_dsc(&self) -> LdnxtDscR {
50        LdnxtDscR::new(((self.bits >> 1) & 1) != 0)
51    }
52    #[doc = "Bit 2 - End of Transfer Enable (Control)"]
53    #[inline(always)]
54    pub fn end_tr_en(&self) -> EndTrEnR {
55        EndTrEnR::new(((self.bits >> 2) & 1) != 0)
56    }
57    #[doc = "Bit 3 - End of Buffer Enable (Control)"]
58    #[inline(always)]
59    pub fn end_b_en(&self) -> EndBEnR {
60        EndBEnR::new(((self.bits >> 3) & 1) != 0)
61    }
62    #[doc = "Bit 4 - End of Transfer Interrupt Enable"]
63    #[inline(always)]
64    pub fn end_tr_it(&self) -> EndTrItR {
65        EndTrItR::new(((self.bits >> 4) & 1) != 0)
66    }
67    #[doc = "Bit 5 - End of Buffer Interrupt Enable"]
68    #[inline(always)]
69    pub fn end_buffit(&self) -> EndBuffitR {
70        EndBuffitR::new(((self.bits >> 5) & 1) != 0)
71    }
72    #[doc = "Bit 6 - Descriptor Loaded Interrupt Enable"]
73    #[inline(always)]
74    pub fn desc_ld_it(&self) -> DescLdItR {
75        DescLdItR::new(((self.bits >> 6) & 1) != 0)
76    }
77    #[doc = "Bit 7 - Burst Lock Enable"]
78    #[inline(always)]
79    pub fn burst_lck(&self) -> BurstLckR {
80        BurstLckR::new(((self.bits >> 7) & 1) != 0)
81    }
82    #[doc = "Bits 16:31 - Buffer Byte Length (Write-only)"]
83    #[inline(always)]
84    pub fn buff_length(&self) -> BuffLengthR {
85        BuffLengthR::new(((self.bits >> 16) & 0xffff) as u16)
86    }
87}
88impl W {
89    #[doc = "Bit 0 - (Channel Enable Command)"]
90    #[inline(always)]
91    #[must_use]
92    pub fn chann_enb(&mut self) -> ChannEnbW<Dmacontrol2Spec> {
93        ChannEnbW::new(self, 0)
94    }
95    #[doc = "Bit 1 - Load Next Channel Transfer Descriptor Enable (Command)"]
96    #[inline(always)]
97    #[must_use]
98    pub fn ldnxt_dsc(&mut self) -> LdnxtDscW<Dmacontrol2Spec> {
99        LdnxtDscW::new(self, 1)
100    }
101    #[doc = "Bit 2 - End of Transfer Enable (Control)"]
102    #[inline(always)]
103    #[must_use]
104    pub fn end_tr_en(&mut self) -> EndTrEnW<Dmacontrol2Spec> {
105        EndTrEnW::new(self, 2)
106    }
107    #[doc = "Bit 3 - End of Buffer Enable (Control)"]
108    #[inline(always)]
109    #[must_use]
110    pub fn end_b_en(&mut self) -> EndBEnW<Dmacontrol2Spec> {
111        EndBEnW::new(self, 3)
112    }
113    #[doc = "Bit 4 - End of Transfer Interrupt Enable"]
114    #[inline(always)]
115    #[must_use]
116    pub fn end_tr_it(&mut self) -> EndTrItW<Dmacontrol2Spec> {
117        EndTrItW::new(self, 4)
118    }
119    #[doc = "Bit 5 - End of Buffer Interrupt Enable"]
120    #[inline(always)]
121    #[must_use]
122    pub fn end_buffit(&mut self) -> EndBuffitW<Dmacontrol2Spec> {
123        EndBuffitW::new(self, 5)
124    }
125    #[doc = "Bit 6 - Descriptor Loaded Interrupt Enable"]
126    #[inline(always)]
127    #[must_use]
128    pub fn desc_ld_it(&mut self) -> DescLdItW<Dmacontrol2Spec> {
129        DescLdItW::new(self, 6)
130    }
131    #[doc = "Bit 7 - Burst Lock Enable"]
132    #[inline(always)]
133    #[must_use]
134    pub fn burst_lck(&mut self) -> BurstLckW<Dmacontrol2Spec> {
135        BurstLckW::new(self, 7)
136    }
137    #[doc = "Bits 16:31 - Buffer Byte Length (Write-only)"]
138    #[inline(always)]
139    #[must_use]
140    pub fn buff_length(&mut self) -> BuffLengthW<Dmacontrol2Spec> {
141        BuffLengthW::new(self, 16)
142    }
143}
144#[doc = "UDPHS DMA Channel Control Register (channel = 2)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmacontrol2::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmacontrol2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
145pub struct Dmacontrol2Spec;
146impl crate::RegisterSpec for Dmacontrol2Spec {
147    type Ux = u32;
148}
149#[doc = "`read()` method returns [`dmacontrol2::R`](R) reader structure"]
150impl crate::Readable for Dmacontrol2Spec {}
151#[doc = "`write(|w| ..)` method takes [`dmacontrol2::W`](W) writer structure"]
152impl crate::Writable for Dmacontrol2Spec {
153    type Safety = crate::Unsafe;
154    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
155    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
156}
157#[doc = "`reset()` method sets DMACONTROL2 to value 0"]
158impl crate::Resettable for Dmacontrol2Spec {
159    const RESET_VALUE: u32 = 0;
160}
atsam3u4e/udphs/dmacontrol2.rs

atsam3u4e/udphs/
dmacontrol2.rs
