atsam3u4e/spi/
mr.rs

1#[doc = "Register `MR` reader"]
2pub type R = crate::R<MrSpec>;
3#[doc = "Register `MR` writer"]
4pub type W = crate::W<MrSpec>;
5#[doc = "Field `MSTR` reader - Master/Slave Mode"]
6pub type MstrR = crate::BitReader;
7#[doc = "Field `MSTR` writer - Master/Slave Mode"]
8pub type MstrW<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `PS` reader - Peripheral Select"]
10pub type PsR = crate::BitReader;
11#[doc = "Field `PS` writer - Peripheral Select"]
12pub type PsW<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `PCSDEC` reader - Chip Select Decode"]
14pub type PcsdecR = crate::BitReader;
15#[doc = "Field `PCSDEC` writer - Chip Select Decode"]
16pub type PcsdecW<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `MODFDIS` reader - Mode Fault Detection"]
18pub type ModfdisR = crate::BitReader;
19#[doc = "Field `MODFDIS` writer - Mode Fault Detection"]
20pub type ModfdisW<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `WDRBT` reader - Wait Data Read Before Transfer"]
22pub type WdrbtR = crate::BitReader;
23#[doc = "Field `WDRBT` writer - Wait Data Read Before Transfer"]
24pub type WdrbtW<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `LLB` reader - Local Loopback Enable"]
26pub type LlbR = crate::BitReader;
27#[doc = "Field `LLB` writer - Local Loopback Enable"]
28pub type LlbW<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `PCS` reader - Peripheral Chip Select"]
30pub type PcsR = crate::FieldReader;
31#[doc = "Field `PCS` writer - Peripheral Chip Select"]
32pub type PcsW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
33#[doc = "Field `DLYBCS` reader - Delay Between Chip Selects"]
34pub type DlybcsR = crate::FieldReader;
35#[doc = "Field `DLYBCS` writer - Delay Between Chip Selects"]
36pub type DlybcsW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
37impl R {
38    #[doc = "Bit 0 - Master/Slave Mode"]
39    #[inline(always)]
40    pub fn mstr(&self) -> MstrR {
41        MstrR::new((self.bits & 1) != 0)
42    }
43    #[doc = "Bit 1 - Peripheral Select"]
44    #[inline(always)]
45    pub fn ps(&self) -> PsR {
46        PsR::new(((self.bits >> 1) & 1) != 0)
47    }
48    #[doc = "Bit 2 - Chip Select Decode"]
49    #[inline(always)]
50    pub fn pcsdec(&self) -> PcsdecR {
51        PcsdecR::new(((self.bits >> 2) & 1) != 0)
52    }
53    #[doc = "Bit 4 - Mode Fault Detection"]
54    #[inline(always)]
55    pub fn modfdis(&self) -> ModfdisR {
56        ModfdisR::new(((self.bits >> 4) & 1) != 0)
57    }
58    #[doc = "Bit 5 - Wait Data Read Before Transfer"]
59    #[inline(always)]
60    pub fn wdrbt(&self) -> WdrbtR {
61        WdrbtR::new(((self.bits >> 5) & 1) != 0)
62    }
63    #[doc = "Bit 7 - Local Loopback Enable"]
64    #[inline(always)]
65    pub fn llb(&self) -> LlbR {
66        LlbR::new(((self.bits >> 7) & 1) != 0)
67    }
68    #[doc = "Bits 16:19 - Peripheral Chip Select"]
69    #[inline(always)]
70    pub fn pcs(&self) -> PcsR {
71        PcsR::new(((self.bits >> 16) & 0x0f) as u8)
72    }
73    #[doc = "Bits 24:31 - Delay Between Chip Selects"]
74    #[inline(always)]
75    pub fn dlybcs(&self) -> DlybcsR {
76        DlybcsR::new(((self.bits >> 24) & 0xff) as u8)
77    }
78}
79impl W {
80    #[doc = "Bit 0 - Master/Slave Mode"]
81    #[inline(always)]
82    #[must_use]
83    pub fn mstr(&mut self) -> MstrW<MrSpec> {
84        MstrW::new(self, 0)
85    }
86    #[doc = "Bit 1 - Peripheral Select"]
87    #[inline(always)]
88    #[must_use]
89    pub fn ps(&mut self) -> PsW<MrSpec> {
90        PsW::new(self, 1)
91    }
92    #[doc = "Bit 2 - Chip Select Decode"]
93    #[inline(always)]
94    #[must_use]
95    pub fn pcsdec(&mut self) -> PcsdecW<MrSpec> {
96        PcsdecW::new(self, 2)
97    }
98    #[doc = "Bit 4 - Mode Fault Detection"]
99    #[inline(always)]
100    #[must_use]
101    pub fn modfdis(&mut self) -> ModfdisW<MrSpec> {
102        ModfdisW::new(self, 4)
103    }
104    #[doc = "Bit 5 - Wait Data Read Before Transfer"]
105    #[inline(always)]
106    #[must_use]
107    pub fn wdrbt(&mut self) -> WdrbtW<MrSpec> {
108        WdrbtW::new(self, 5)
109    }
110    #[doc = "Bit 7 - Local Loopback Enable"]
111    #[inline(always)]
112    #[must_use]
113    pub fn llb(&mut self) -> LlbW<MrSpec> {
114        LlbW::new(self, 7)
115    }
116    #[doc = "Bits 16:19 - Peripheral Chip Select"]
117    #[inline(always)]
118    #[must_use]
119    pub fn pcs(&mut self) -> PcsW<MrSpec> {
120        PcsW::new(self, 16)
121    }
122    #[doc = "Bits 24:31 - Delay Between Chip Selects"]
123    #[inline(always)]
124    #[must_use]
125    pub fn dlybcs(&mut self) -> DlybcsW<MrSpec> {
126        DlybcsW::new(self, 24)
127    }
128}
129#[doc = "Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
130pub struct MrSpec;
131impl crate::RegisterSpec for MrSpec {
132    type Ux = u32;
133}
134#[doc = "`read()` method returns [`mr::R`](R) reader structure"]
135impl crate::Readable for MrSpec {}
136#[doc = "`write(|w| ..)` method takes [`mr::W`](W) writer structure"]
137impl crate::Writable for MrSpec {
138    type Safety = crate::Unsafe;
139    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
140    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
141}
142#[doc = "`reset()` method sets MR to value 0"]
143impl crate::Resettable for MrSpec {
144    const RESET_VALUE: u32 = 0;
145}
atsam3u4e/spi/mr.rs

atsam3u4e/spi/
mr.rs
