1#[doc = "Register `CR` writer"]
2pub type W = crate::W<CrSpec>;
3#[doc = "Field `RSTRX` writer - Reset Receiver"]
4pub type RstrxW<'a, REG> = crate::BitWriter<'a, REG>;
5#[doc = "Field `RSTTX` writer - Reset Transmitter"]
6pub type RsttxW<'a, REG> = crate::BitWriter<'a, REG>;
7#[doc = "Field `RXEN` writer - Receiver Enable"]
8pub type RxenW<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `RXDIS` writer - Receiver Disable"]
10pub type RxdisW<'a, REG> = crate::BitWriter<'a, REG>;
11#[doc = "Field `TXEN` writer - Transmitter Enable"]
12pub type TxenW<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `TXDIS` writer - Transmitter Disable"]
14pub type TxdisW<'a, REG> = crate::BitWriter<'a, REG>;
15#[doc = "Field `RSTSTA` writer - Reset Status Bits"]
16pub type RststaW<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `STTBRK` writer - Start Break"]
18pub type SttbrkW<'a, REG> = crate::BitWriter<'a, REG>;
19#[doc = "Field `STPBRK` writer - Stop Break"]
20pub type StpbrkW<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `STTTO` writer - Start Time-out"]
22pub type StttoW<'a, REG> = crate::BitWriter<'a, REG>;
23#[doc = "Field `SENDA` writer - Send Address"]
24pub type SendaW<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `RSTIT` writer - Reset Iterations"]
26pub type RstitW<'a, REG> = crate::BitWriter<'a, REG>;
27#[doc = "Field `RSTNACK` writer - Reset Non Acknowledge"]
28pub type RstnackW<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `RETTO` writer - Rearm Time-out"]
30pub type RettoW<'a, REG> = crate::BitWriter<'a, REG>;
31#[doc = "Field `DTREN` writer - Data Terminal Ready Enable"]
32pub type DtrenW<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `DTRDIS` writer - Data Terminal Ready Disable"]
34pub type DtrdisW<'a, REG> = crate::BitWriter<'a, REG>;
35#[doc = "Field `RTSEN` writer - Request to Send Enable"]
36pub type RtsenW<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `RTSDIS` writer - Request to Send Disable"]
38pub type RtsdisW<'a, REG> = crate::BitWriter<'a, REG>;
39impl W {
40 #[doc = "Bit 2 - Reset Receiver"]
41 #[inline(always)]
42 #[must_use]
43 pub fn rstrx(&mut self) -> RstrxW<CrSpec> {
44 RstrxW::new(self, 2)
45 }
46 #[doc = "Bit 3 - Reset Transmitter"]
47 #[inline(always)]
48 #[must_use]
49 pub fn rsttx(&mut self) -> RsttxW<CrSpec> {
50 RsttxW::new(self, 3)
51 }
52 #[doc = "Bit 4 - Receiver Enable"]
53 #[inline(always)]
54 #[must_use]
55 pub fn rxen(&mut self) -> RxenW<CrSpec> {
56 RxenW::new(self, 4)
57 }
58 #[doc = "Bit 5 - Receiver Disable"]
59 #[inline(always)]
60 #[must_use]
61 pub fn rxdis(&mut self) -> RxdisW<CrSpec> {
62 RxdisW::new(self, 5)
63 }
64 #[doc = "Bit 6 - Transmitter Enable"]
65 #[inline(always)]
66 #[must_use]
67 pub fn txen(&mut self) -> TxenW<CrSpec> {
68 TxenW::new(self, 6)
69 }
70 #[doc = "Bit 7 - Transmitter Disable"]
71 #[inline(always)]
72 #[must_use]
73 pub fn txdis(&mut self) -> TxdisW<CrSpec> {
74 TxdisW::new(self, 7)
75 }
76 #[doc = "Bit 8 - Reset Status Bits"]
77 #[inline(always)]
78 #[must_use]
79 pub fn rststa(&mut self) -> RststaW<CrSpec> {
80 RststaW::new(self, 8)
81 }
82 #[doc = "Bit 9 - Start Break"]
83 #[inline(always)]
84 #[must_use]
85 pub fn sttbrk(&mut self) -> SttbrkW<CrSpec> {
86 SttbrkW::new(self, 9)
87 }
88 #[doc = "Bit 10 - Stop Break"]
89 #[inline(always)]
90 #[must_use]
91 pub fn stpbrk(&mut self) -> StpbrkW<CrSpec> {
92 StpbrkW::new(self, 10)
93 }
94 #[doc = "Bit 11 - Start Time-out"]
95 #[inline(always)]
96 #[must_use]
97 pub fn sttto(&mut self) -> StttoW<CrSpec> {
98 StttoW::new(self, 11)
99 }
100 #[doc = "Bit 12 - Send Address"]
101 #[inline(always)]
102 #[must_use]
103 pub fn senda(&mut self) -> SendaW<CrSpec> {
104 SendaW::new(self, 12)
105 }
106 #[doc = "Bit 13 - Reset Iterations"]
107 #[inline(always)]
108 #[must_use]
109 pub fn rstit(&mut self) -> RstitW<CrSpec> {
110 RstitW::new(self, 13)
111 }
112 #[doc = "Bit 14 - Reset Non Acknowledge"]
113 #[inline(always)]
114 #[must_use]
115 pub fn rstnack(&mut self) -> RstnackW<CrSpec> {
116 RstnackW::new(self, 14)
117 }
118 #[doc = "Bit 15 - Rearm Time-out"]
119 #[inline(always)]
120 #[must_use]
121 pub fn retto(&mut self) -> RettoW<CrSpec> {
122 RettoW::new(self, 15)
123 }
124 #[doc = "Bit 16 - Data Terminal Ready Enable"]
125 #[inline(always)]
126 #[must_use]
127 pub fn dtren(&mut self) -> DtrenW<CrSpec> {
128 DtrenW::new(self, 16)
129 }
130 #[doc = "Bit 17 - Data Terminal Ready Disable"]
131 #[inline(always)]
132 #[must_use]
133 pub fn dtrdis(&mut self) -> DtrdisW<CrSpec> {
134 DtrdisW::new(self, 17)
135 }
136 #[doc = "Bit 18 - Request to Send Enable"]
137 #[inline(always)]
138 #[must_use]
139 pub fn rtsen(&mut self) -> RtsenW<CrSpec> {
140 RtsenW::new(self, 18)
141 }
142 #[doc = "Bit 19 - Request to Send Disable"]
143 #[inline(always)]
144 #[must_use]
145 pub fn rtsdis(&mut self) -> RtsdisW<CrSpec> {
146 RtsdisW::new(self, 19)
147 }
148}
149#[doc = "Control Register\n\nYou can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
150pub struct CrSpec;
151impl crate::RegisterSpec for CrSpec {
152 type Ux = u32;
153}
154#[doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"]
155impl crate::Writable for CrSpec {
156 type Safety = crate::Unsafe;
157 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
158 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
159}