1#[doc = "Register `RCMR` reader"]
2pub type R = crate::R<RcmrSpec>;
3#[doc = "Register `RCMR` writer"]
4pub type W = crate::W<RcmrSpec>;
5#[doc = "Receive Clock Selection\n\nValue on reset: 0"]
6#[derive(Clone, Copy, Debug, PartialEq, Eq)]
7#[repr(u8)]
8pub enum Cks {
9 #[doc = "0: Divided Clock"]
10 Mck = 0,
11 #[doc = "1: TK Clock signal"]
12 Tk = 1,
13 #[doc = "2: RK pin"]
14 Rk = 2,
15}
16impl From<Cks> for u8 {
17 #[inline(always)]
18 fn from(variant: Cks) -> Self {
19 variant as _
20 }
21}
22impl crate::FieldSpec for Cks {
23 type Ux = u8;
24}
25impl crate::IsEnum for Cks {}
26#[doc = "Field `CKS` reader - Receive Clock Selection"]
27pub type CksR = crate::FieldReader<Cks>;
28impl CksR {
29 #[doc = "Get enumerated values variant"]
30 #[inline(always)]
31 pub const fn variant(&self) -> Option<Cks> {
32 match self.bits {
33 0 => Some(Cks::Mck),
34 1 => Some(Cks::Tk),
35 2 => Some(Cks::Rk),
36 _ => None,
37 }
38 }
39 #[doc = "Divided Clock"]
40 #[inline(always)]
41 pub fn is_mck(&self) -> bool {
42 *self == Cks::Mck
43 }
44 #[doc = "TK Clock signal"]
45 #[inline(always)]
46 pub fn is_tk(&self) -> bool {
47 *self == Cks::Tk
48 }
49 #[doc = "RK pin"]
50 #[inline(always)]
51 pub fn is_rk(&self) -> bool {
52 *self == Cks::Rk
53 }
54}
55#[doc = "Field `CKS` writer - Receive Clock Selection"]
56pub type CksW<'a, REG> = crate::FieldWriter<'a, REG, 2, Cks>;
57impl<'a, REG> CksW<'a, REG>
58where
59 REG: crate::Writable + crate::RegisterSpec,
60 REG::Ux: From<u8>,
61{
62 #[doc = "Divided Clock"]
63 #[inline(always)]
64 pub fn mck(self) -> &'a mut crate::W<REG> {
65 self.variant(Cks::Mck)
66 }
67 #[doc = "TK Clock signal"]
68 #[inline(always)]
69 pub fn tk(self) -> &'a mut crate::W<REG> {
70 self.variant(Cks::Tk)
71 }
72 #[doc = "RK pin"]
73 #[inline(always)]
74 pub fn rk(self) -> &'a mut crate::W<REG> {
75 self.variant(Cks::Rk)
76 }
77}
78#[doc = "Receive Clock Output Mode Selection\n\nValue on reset: 0"]
79#[derive(Clone, Copy, Debug, PartialEq, Eq)]
80#[repr(u8)]
81pub enum Cko {
82 #[doc = "0: None, RK pin is an input"]
83 None = 0,
84 #[doc = "1: Continuous Receive Clock, RK pin is an output"]
85 Continuous = 1,
86 #[doc = "2: Receive Clock only during data transfers, RK pin is an output"]
87 Transfer = 2,
88}
89impl From<Cko> for u8 {
90 #[inline(always)]
91 fn from(variant: Cko) -> Self {
92 variant as _
93 }
94}
95impl crate::FieldSpec for Cko {
96 type Ux = u8;
97}
98impl crate::IsEnum for Cko {}
99#[doc = "Field `CKO` reader - Receive Clock Output Mode Selection"]
100pub type CkoR = crate::FieldReader<Cko>;
101impl CkoR {
102 #[doc = "Get enumerated values variant"]
103 #[inline(always)]
104 pub const fn variant(&self) -> Option<Cko> {
105 match self.bits {
106 0 => Some(Cko::None),
107 1 => Some(Cko::Continuous),
108 2 => Some(Cko::Transfer),
109 _ => None,
110 }
111 }
112 #[doc = "None, RK pin is an input"]
113 #[inline(always)]
114 pub fn is_none(&self) -> bool {
115 *self == Cko::None
116 }
117 #[doc = "Continuous Receive Clock, RK pin is an output"]
118 #[inline(always)]
119 pub fn is_continuous(&self) -> bool {
120 *self == Cko::Continuous
121 }
122 #[doc = "Receive Clock only during data transfers, RK pin is an output"]
123 #[inline(always)]
124 pub fn is_transfer(&self) -> bool {
125 *self == Cko::Transfer
126 }
127}
128#[doc = "Field `CKO` writer - Receive Clock Output Mode Selection"]
129pub type CkoW<'a, REG> = crate::FieldWriter<'a, REG, 3, Cko>;
130impl<'a, REG> CkoW<'a, REG>
131where
132 REG: crate::Writable + crate::RegisterSpec,
133 REG::Ux: From<u8>,
134{
135 #[doc = "None, RK pin is an input"]
136 #[inline(always)]
137 pub fn none(self) -> &'a mut crate::W<REG> {
138 self.variant(Cko::None)
139 }
140 #[doc = "Continuous Receive Clock, RK pin is an output"]
141 #[inline(always)]
142 pub fn continuous(self) -> &'a mut crate::W<REG> {
143 self.variant(Cko::Continuous)
144 }
145 #[doc = "Receive Clock only during data transfers, RK pin is an output"]
146 #[inline(always)]
147 pub fn transfer(self) -> &'a mut crate::W<REG> {
148 self.variant(Cko::Transfer)
149 }
150}
151#[doc = "Field `CKI` reader - Receive Clock Inversion"]
152pub type CkiR = crate::BitReader;
153#[doc = "Field `CKI` writer - Receive Clock Inversion"]
154pub type CkiW<'a, REG> = crate::BitWriter<'a, REG>;
155#[doc = "Receive Clock Gating Selection\n\nValue on reset: 0"]
156#[derive(Clone, Copy, Debug, PartialEq, Eq)]
157#[repr(u8)]
158pub enum Ckg {
159 #[doc = "0: None"]
160 Continuous = 0,
161 #[doc = "1: Receive Clock enabled only if RF Low"]
162 EnRfLow = 1,
163 #[doc = "2: Receive Clock enabled only if RF High"]
164 EnRfHigh = 2,
165}
166impl From<Ckg> for u8 {
167 #[inline(always)]
168 fn from(variant: Ckg) -> Self {
169 variant as _
170 }
171}
172impl crate::FieldSpec for Ckg {
173 type Ux = u8;
174}
175impl crate::IsEnum for Ckg {}
176#[doc = "Field `CKG` reader - Receive Clock Gating Selection"]
177pub type CkgR = crate::FieldReader<Ckg>;
178impl CkgR {
179 #[doc = "Get enumerated values variant"]
180 #[inline(always)]
181 pub const fn variant(&self) -> Option<Ckg> {
182 match self.bits {
183 0 => Some(Ckg::Continuous),
184 1 => Some(Ckg::EnRfLow),
185 2 => Some(Ckg::EnRfHigh),
186 _ => None,
187 }
188 }
189 #[doc = "None"]
190 #[inline(always)]
191 pub fn is_continuous(&self) -> bool {
192 *self == Ckg::Continuous
193 }
194 #[doc = "Receive Clock enabled only if RF Low"]
195 #[inline(always)]
196 pub fn is_en_rf_low(&self) -> bool {
197 *self == Ckg::EnRfLow
198 }
199 #[doc = "Receive Clock enabled only if RF High"]
200 #[inline(always)]
201 pub fn is_en_rf_high(&self) -> bool {
202 *self == Ckg::EnRfHigh
203 }
204}
205#[doc = "Field `CKG` writer - Receive Clock Gating Selection"]
206pub type CkgW<'a, REG> = crate::FieldWriter<'a, REG, 2, Ckg>;
207impl<'a, REG> CkgW<'a, REG>
208where
209 REG: crate::Writable + crate::RegisterSpec,
210 REG::Ux: From<u8>,
211{
212 #[doc = "None"]
213 #[inline(always)]
214 pub fn continuous(self) -> &'a mut crate::W<REG> {
215 self.variant(Ckg::Continuous)
216 }
217 #[doc = "Receive Clock enabled only if RF Low"]
218 #[inline(always)]
219 pub fn en_rf_low(self) -> &'a mut crate::W<REG> {
220 self.variant(Ckg::EnRfLow)
221 }
222 #[doc = "Receive Clock enabled only if RF High"]
223 #[inline(always)]
224 pub fn en_rf_high(self) -> &'a mut crate::W<REG> {
225 self.variant(Ckg::EnRfHigh)
226 }
227}
228#[doc = "Receive Start Selection\n\nValue on reset: 0"]
229#[derive(Clone, Copy, Debug, PartialEq, Eq)]
230#[repr(u8)]
231pub enum Start {
232 #[doc = "0: Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data."]
233 Continuous = 0,
234 #[doc = "1: Transmit start"]
235 Transmit = 1,
236 #[doc = "2: Detection of a low level on RF signal"]
237 RfLow = 2,
238 #[doc = "3: Detection of a high level on RF signal"]
239 RfHigh = 3,
240 #[doc = "4: Detection of a falling edge on RF signal"]
241 RfFalling = 4,
242 #[doc = "5: Detection of a rising edge on RF signal"]
243 RfRising = 5,
244 #[doc = "6: Detection of any level change on RF signal"]
245 RfLevel = 6,
246 #[doc = "7: Detection of any edge on RF signal"]
247 RfEdge = 7,
248 #[doc = "8: Compare 0"]
249 Cmp0 = 8,
250}
251impl From<Start> for u8 {
252 #[inline(always)]
253 fn from(variant: Start) -> Self {
254 variant as _
255 }
256}
257impl crate::FieldSpec for Start {
258 type Ux = u8;
259}
260impl crate::IsEnum for Start {}
261#[doc = "Field `START` reader - Receive Start Selection"]
262pub type StartR = crate::FieldReader<Start>;
263impl StartR {
264 #[doc = "Get enumerated values variant"]
265 #[inline(always)]
266 pub const fn variant(&self) -> Option<Start> {
267 match self.bits {
268 0 => Some(Start::Continuous),
269 1 => Some(Start::Transmit),
270 2 => Some(Start::RfLow),
271 3 => Some(Start::RfHigh),
272 4 => Some(Start::RfFalling),
273 5 => Some(Start::RfRising),
274 6 => Some(Start::RfLevel),
275 7 => Some(Start::RfEdge),
276 8 => Some(Start::Cmp0),
277 _ => None,
278 }
279 }
280 #[doc = "Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data."]
281 #[inline(always)]
282 pub fn is_continuous(&self) -> bool {
283 *self == Start::Continuous
284 }
285 #[doc = "Transmit start"]
286 #[inline(always)]
287 pub fn is_transmit(&self) -> bool {
288 *self == Start::Transmit
289 }
290 #[doc = "Detection of a low level on RF signal"]
291 #[inline(always)]
292 pub fn is_rf_low(&self) -> bool {
293 *self == Start::RfLow
294 }
295 #[doc = "Detection of a high level on RF signal"]
296 #[inline(always)]
297 pub fn is_rf_high(&self) -> bool {
298 *self == Start::RfHigh
299 }
300 #[doc = "Detection of a falling edge on RF signal"]
301 #[inline(always)]
302 pub fn is_rf_falling(&self) -> bool {
303 *self == Start::RfFalling
304 }
305 #[doc = "Detection of a rising edge on RF signal"]
306 #[inline(always)]
307 pub fn is_rf_rising(&self) -> bool {
308 *self == Start::RfRising
309 }
310 #[doc = "Detection of any level change on RF signal"]
311 #[inline(always)]
312 pub fn is_rf_level(&self) -> bool {
313 *self == Start::RfLevel
314 }
315 #[doc = "Detection of any edge on RF signal"]
316 #[inline(always)]
317 pub fn is_rf_edge(&self) -> bool {
318 *self == Start::RfEdge
319 }
320 #[doc = "Compare 0"]
321 #[inline(always)]
322 pub fn is_cmp_0(&self) -> bool {
323 *self == Start::Cmp0
324 }
325}
326#[doc = "Field `START` writer - Receive Start Selection"]
327pub type StartW<'a, REG> = crate::FieldWriter<'a, REG, 4, Start>;
328impl<'a, REG> StartW<'a, REG>
329where
330 REG: crate::Writable + crate::RegisterSpec,
331 REG::Ux: From<u8>,
332{
333 #[doc = "Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data."]
334 #[inline(always)]
335 pub fn continuous(self) -> &'a mut crate::W<REG> {
336 self.variant(Start::Continuous)
337 }
338 #[doc = "Transmit start"]
339 #[inline(always)]
340 pub fn transmit(self) -> &'a mut crate::W<REG> {
341 self.variant(Start::Transmit)
342 }
343 #[doc = "Detection of a low level on RF signal"]
344 #[inline(always)]
345 pub fn rf_low(self) -> &'a mut crate::W<REG> {
346 self.variant(Start::RfLow)
347 }
348 #[doc = "Detection of a high level on RF signal"]
349 #[inline(always)]
350 pub fn rf_high(self) -> &'a mut crate::W<REG> {
351 self.variant(Start::RfHigh)
352 }
353 #[doc = "Detection of a falling edge on RF signal"]
354 #[inline(always)]
355 pub fn rf_falling(self) -> &'a mut crate::W<REG> {
356 self.variant(Start::RfFalling)
357 }
358 #[doc = "Detection of a rising edge on RF signal"]
359 #[inline(always)]
360 pub fn rf_rising(self) -> &'a mut crate::W<REG> {
361 self.variant(Start::RfRising)
362 }
363 #[doc = "Detection of any level change on RF signal"]
364 #[inline(always)]
365 pub fn rf_level(self) -> &'a mut crate::W<REG> {
366 self.variant(Start::RfLevel)
367 }
368 #[doc = "Detection of any edge on RF signal"]
369 #[inline(always)]
370 pub fn rf_edge(self) -> &'a mut crate::W<REG> {
371 self.variant(Start::RfEdge)
372 }
373 #[doc = "Compare 0"]
374 #[inline(always)]
375 pub fn cmp_0(self) -> &'a mut crate::W<REG> {
376 self.variant(Start::Cmp0)
377 }
378}
379#[doc = "Field `STOP` reader - Receive Stop Selection"]
380pub type StopR = crate::BitReader;
381#[doc = "Field `STOP` writer - Receive Stop Selection"]
382pub type StopW<'a, REG> = crate::BitWriter<'a, REG>;
383#[doc = "Field `STTDLY` reader - Receive Start Delay"]
384pub type SttdlyR = crate::FieldReader;
385#[doc = "Field `STTDLY` writer - Receive Start Delay"]
386pub type SttdlyW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
387#[doc = "Field `PERIOD` reader - Receive Period Divider Selection"]
388pub type PeriodR = crate::FieldReader;
389#[doc = "Field `PERIOD` writer - Receive Period Divider Selection"]
390pub type PeriodW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
391impl R {
392 #[doc = "Bits 0:1 - Receive Clock Selection"]
393 #[inline(always)]
394 pub fn cks(&self) -> CksR {
395 CksR::new((self.bits & 3) as u8)
396 }
397 #[doc = "Bits 2:4 - Receive Clock Output Mode Selection"]
398 #[inline(always)]
399 pub fn cko(&self) -> CkoR {
400 CkoR::new(((self.bits >> 2) & 7) as u8)
401 }
402 #[doc = "Bit 5 - Receive Clock Inversion"]
403 #[inline(always)]
404 pub fn cki(&self) -> CkiR {
405 CkiR::new(((self.bits >> 5) & 1) != 0)
406 }
407 #[doc = "Bits 6:7 - Receive Clock Gating Selection"]
408 #[inline(always)]
409 pub fn ckg(&self) -> CkgR {
410 CkgR::new(((self.bits >> 6) & 3) as u8)
411 }
412 #[doc = "Bits 8:11 - Receive Start Selection"]
413 #[inline(always)]
414 pub fn start(&self) -> StartR {
415 StartR::new(((self.bits >> 8) & 0x0f) as u8)
416 }
417 #[doc = "Bit 12 - Receive Stop Selection"]
418 #[inline(always)]
419 pub fn stop(&self) -> StopR {
420 StopR::new(((self.bits >> 12) & 1) != 0)
421 }
422 #[doc = "Bits 16:23 - Receive Start Delay"]
423 #[inline(always)]
424 pub fn sttdly(&self) -> SttdlyR {
425 SttdlyR::new(((self.bits >> 16) & 0xff) as u8)
426 }
427 #[doc = "Bits 24:31 - Receive Period Divider Selection"]
428 #[inline(always)]
429 pub fn period(&self) -> PeriodR {
430 PeriodR::new(((self.bits >> 24) & 0xff) as u8)
431 }
432}
433impl W {
434 #[doc = "Bits 0:1 - Receive Clock Selection"]
435 #[inline(always)]
436 #[must_use]
437 pub fn cks(&mut self) -> CksW<RcmrSpec> {
438 CksW::new(self, 0)
439 }
440 #[doc = "Bits 2:4 - Receive Clock Output Mode Selection"]
441 #[inline(always)]
442 #[must_use]
443 pub fn cko(&mut self) -> CkoW<RcmrSpec> {
444 CkoW::new(self, 2)
445 }
446 #[doc = "Bit 5 - Receive Clock Inversion"]
447 #[inline(always)]
448 #[must_use]
449 pub fn cki(&mut self) -> CkiW<RcmrSpec> {
450 CkiW::new(self, 5)
451 }
452 #[doc = "Bits 6:7 - Receive Clock Gating Selection"]
453 #[inline(always)]
454 #[must_use]
455 pub fn ckg(&mut self) -> CkgW<RcmrSpec> {
456 CkgW::new(self, 6)
457 }
458 #[doc = "Bits 8:11 - Receive Start Selection"]
459 #[inline(always)]
460 #[must_use]
461 pub fn start(&mut self) -> StartW<RcmrSpec> {
462 StartW::new(self, 8)
463 }
464 #[doc = "Bit 12 - Receive Stop Selection"]
465 #[inline(always)]
466 #[must_use]
467 pub fn stop(&mut self) -> StopW<RcmrSpec> {
468 StopW::new(self, 12)
469 }
470 #[doc = "Bits 16:23 - Receive Start Delay"]
471 #[inline(always)]
472 #[must_use]
473 pub fn sttdly(&mut self) -> SttdlyW<RcmrSpec> {
474 SttdlyW::new(self, 16)
475 }
476 #[doc = "Bits 24:31 - Receive Period Divider Selection"]
477 #[inline(always)]
478 #[must_use]
479 pub fn period(&mut self) -> PeriodW<RcmrSpec> {
480 PeriodW::new(self, 24)
481 }
482}
483#[doc = "Receive Clock Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rcmr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rcmr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
484pub struct RcmrSpec;
485impl crate::RegisterSpec for RcmrSpec {
486 type Ux = u32;
487}
488#[doc = "`read()` method returns [`rcmr::R`](R) reader structure"]
489impl crate::Readable for RcmrSpec {}
490#[doc = "`write(|w| ..)` method takes [`rcmr::W`](W) writer structure"]
491impl crate::Writable for RcmrSpec {
492 type Safety = crate::Unsafe;
493 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
494 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
495}
496#[doc = "`reset()` method sets RCMR to value 0"]
497impl crate::Resettable for RcmrSpec {
498 const RESET_VALUE: u32 = 0;
499}