atsam3u1c/udphs/
eptctldis4.rs

1#[doc = "Register `EPTCTLDIS4` writer"]
2pub type W = crate::W<Eptctldis4Spec>;
3#[doc = "Field `EPT_DISABL` writer - Endpoint Disable"]
4pub type EptDisablW<'a, REG> = crate::BitWriter<'a, REG>;
5#[doc = "Field `AUTO_VALID` writer - Packet Auto-Valid Disable"]
6pub type AutoValidW<'a, REG> = crate::BitWriter<'a, REG>;
7#[doc = "Field `INTDIS_DMA` writer - Interrupts Disable DMA"]
8pub type IntdisDmaW<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `NYET_DIS` writer - NYET Enable (Only for High Speed Bulk OUT endpoints)"]
10pub type NyetDisW<'a, REG> = crate::BitWriter<'a, REG>;
11#[doc = "Field `ERR_OVFLW` writer - Overflow Error Interrupt Disable"]
12pub type ErrOvflwW<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `RXRDY_TXKL` writer - Received OUT Data Interrupt Disable"]
14pub type RxrdyTxklW<'a, REG> = crate::BitWriter<'a, REG>;
15#[doc = "Field `TX_COMPLT` writer - Transmitted IN Data Complete Interrupt Disable"]
16pub type TxCompltW<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `TXRDY` writer - TX Packet Ready Interrupt Disable"]
18pub type TxrdyW<'a, REG> = crate::BitWriter<'a, REG>;
19#[doc = "Field `RX_SETUP` writer - Received SETUP Interrupt Disable"]
20pub type RxSetupW<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `STALL_SNT` writer - Stall Sent Interrupt Disable"]
22pub type StallSntW<'a, REG> = crate::BitWriter<'a, REG>;
23#[doc = "Field `NAK_IN` writer - NAKIN Interrupt Disable"]
24pub type NakInW<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `NAK_OUT` writer - NAKOUT Interrupt Disable"]
26pub type NakOutW<'a, REG> = crate::BitWriter<'a, REG>;
27#[doc = "Field `BUSY_BANK` writer - Busy Bank Interrupt Disable"]
28pub type BusyBankW<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `SHRT_PCKT` writer - Short Packet Interrupt Disable"]
30pub type ShrtPcktW<'a, REG> = crate::BitWriter<'a, REG>;
31impl W {
32    #[doc = "Bit 0 - Endpoint Disable"]
33    #[inline(always)]
34    #[must_use]
35    pub fn ept_disabl(&mut self) -> EptDisablW<Eptctldis4Spec> {
36        EptDisablW::new(self, 0)
37    }
38    #[doc = "Bit 1 - Packet Auto-Valid Disable"]
39    #[inline(always)]
40    #[must_use]
41    pub fn auto_valid(&mut self) -> AutoValidW<Eptctldis4Spec> {
42        AutoValidW::new(self, 1)
43    }
44    #[doc = "Bit 3 - Interrupts Disable DMA"]
45    #[inline(always)]
46    #[must_use]
47    pub fn intdis_dma(&mut self) -> IntdisDmaW<Eptctldis4Spec> {
48        IntdisDmaW::new(self, 3)
49    }
50    #[doc = "Bit 4 - NYET Enable (Only for High Speed Bulk OUT endpoints)"]
51    #[inline(always)]
52    #[must_use]
53    pub fn nyet_dis(&mut self) -> NyetDisW<Eptctldis4Spec> {
54        NyetDisW::new(self, 4)
55    }
56    #[doc = "Bit 8 - Overflow Error Interrupt Disable"]
57    #[inline(always)]
58    #[must_use]
59    pub fn err_ovflw(&mut self) -> ErrOvflwW<Eptctldis4Spec> {
60        ErrOvflwW::new(self, 8)
61    }
62    #[doc = "Bit 9 - Received OUT Data Interrupt Disable"]
63    #[inline(always)]
64    #[must_use]
65    pub fn rxrdy_txkl(&mut self) -> RxrdyTxklW<Eptctldis4Spec> {
66        RxrdyTxklW::new(self, 9)
67    }
68    #[doc = "Bit 10 - Transmitted IN Data Complete Interrupt Disable"]
69    #[inline(always)]
70    #[must_use]
71    pub fn tx_complt(&mut self) -> TxCompltW<Eptctldis4Spec> {
72        TxCompltW::new(self, 10)
73    }
74    #[doc = "Bit 11 - TX Packet Ready Interrupt Disable"]
75    #[inline(always)]
76    #[must_use]
77    pub fn txrdy(&mut self) -> TxrdyW<Eptctldis4Spec> {
78        TxrdyW::new(self, 11)
79    }
80    #[doc = "Bit 12 - Received SETUP Interrupt Disable"]
81    #[inline(always)]
82    #[must_use]
83    pub fn rx_setup(&mut self) -> RxSetupW<Eptctldis4Spec> {
84        RxSetupW::new(self, 12)
85    }
86    #[doc = "Bit 13 - Stall Sent Interrupt Disable"]
87    #[inline(always)]
88    #[must_use]
89    pub fn stall_snt(&mut self) -> StallSntW<Eptctldis4Spec> {
90        StallSntW::new(self, 13)
91    }
92    #[doc = "Bit 14 - NAKIN Interrupt Disable"]
93    #[inline(always)]
94    #[must_use]
95    pub fn nak_in(&mut self) -> NakInW<Eptctldis4Spec> {
96        NakInW::new(self, 14)
97    }
98    #[doc = "Bit 15 - NAKOUT Interrupt Disable"]
99    #[inline(always)]
100    #[must_use]
101    pub fn nak_out(&mut self) -> NakOutW<Eptctldis4Spec> {
102        NakOutW::new(self, 15)
103    }
104    #[doc = "Bit 18 - Busy Bank Interrupt Disable"]
105    #[inline(always)]
106    #[must_use]
107    pub fn busy_bank(&mut self) -> BusyBankW<Eptctldis4Spec> {
108        BusyBankW::new(self, 18)
109    }
110    #[doc = "Bit 31 - Short Packet Interrupt Disable"]
111    #[inline(always)]
112    #[must_use]
113    pub fn shrt_pckt(&mut self) -> ShrtPcktW<Eptctldis4Spec> {
114        ShrtPcktW::new(self, 31)
115    }
116}
117#[doc = "UDPHS Endpoint Control Disable Register (endpoint = 4)\n\nYou can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`eptctldis4::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
118pub struct Eptctldis4Spec;
119impl crate::RegisterSpec for Eptctldis4Spec {
120    type Ux = u32;
121}
122#[doc = "`write(|w| ..)` method takes [`eptctldis4::W`](W) writer structure"]
123impl crate::Writable for Eptctldis4Spec {
124    type Safety = crate::Unsafe;
125    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
126    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
127}
atsam3u1c/udphs/eptctldis4.rs

atsam3u1c/udphs/
eptctldis4.rs
