atsam3u1c/usart2/
spi_mode_mr_spi_mode.rs

1#[doc = "Register `MR_SPI_MODE` reader"]
2pub type R = crate::R<SpiModeMrSpiModeSpec>;
3#[doc = "Register `MR_SPI_MODE` writer"]
4pub type W = crate::W<SpiModeMrSpiModeSpec>;
5#[doc = "USART Mode of Operation"]
6#[derive(Clone, Copy, Debug, PartialEq, Eq)]
7#[repr(u8)]
8pub enum UsartMode {
9    #[doc = "14: SPI Master"]
10    SpiMaster = 14,
11    #[doc = "15: SPI Slave"]
12    SpiSlave = 15,
13}
14impl From<UsartMode> for u8 {
15    #[inline(always)]
16    fn from(variant: UsartMode) -> Self {
17        variant as _
18    }
19}
20impl crate::FieldSpec for UsartMode {
21    type Ux = u8;
22}
23impl crate::IsEnum for UsartMode {}
24#[doc = "Field `USART_MODE` reader - USART Mode of Operation"]
25pub type UsartModeR = crate::FieldReader<UsartMode>;
26impl UsartModeR {
27    #[doc = "Get enumerated values variant"]
28    #[inline(always)]
29    pub const fn variant(&self) -> Option<UsartMode> {
30        match self.bits {
31            14 => Some(UsartMode::SpiMaster),
32            15 => Some(UsartMode::SpiSlave),
33            _ => None,
34        }
35    }
36    #[doc = "SPI Master"]
37    #[inline(always)]
38    pub fn is_spi_master(&self) -> bool {
39        *self == UsartMode::SpiMaster
40    }
41    #[doc = "SPI Slave"]
42    #[inline(always)]
43    pub fn is_spi_slave(&self) -> bool {
44        *self == UsartMode::SpiSlave
45    }
46}
47#[doc = "Field `USART_MODE` writer - USART Mode of Operation"]
48pub type UsartModeW<'a, REG> = crate::FieldWriter<'a, REG, 4, UsartMode>;
49impl<'a, REG> UsartModeW<'a, REG>
50where
51    REG: crate::Writable + crate::RegisterSpec,
52    REG::Ux: From<u8>,
53{
54    #[doc = "SPI Master"]
55    #[inline(always)]
56    pub fn spi_master(self) -> &'a mut crate::W<REG> {
57        self.variant(UsartMode::SpiMaster)
58    }
59    #[doc = "SPI Slave"]
60    #[inline(always)]
61    pub fn spi_slave(self) -> &'a mut crate::W<REG> {
62        self.variant(UsartMode::SpiSlave)
63    }
64}
65#[doc = "Clock Selection"]
66#[derive(Clone, Copy, Debug, PartialEq, Eq)]
67#[repr(u8)]
68pub enum Usclks {
69    #[doc = "0: Master Clock MCK is selected"]
70    Mck = 0,
71    #[doc = "1: Internal Clock Divided MCK/DIV (DIV=8) is selected"]
72    Div = 1,
73    #[doc = "3: Serial Clock SLK is selected"]
74    Sck = 3,
75}
76impl From<Usclks> for u8 {
77    #[inline(always)]
78    fn from(variant: Usclks) -> Self {
79        variant as _
80    }
81}
82impl crate::FieldSpec for Usclks {
83    type Ux = u8;
84}
85impl crate::IsEnum for Usclks {}
86#[doc = "Field `USCLKS` reader - Clock Selection"]
87pub type UsclksR = crate::FieldReader<Usclks>;
88impl UsclksR {
89    #[doc = "Get enumerated values variant"]
90    #[inline(always)]
91    pub const fn variant(&self) -> Option<Usclks> {
92        match self.bits {
93            0 => Some(Usclks::Mck),
94            1 => Some(Usclks::Div),
95            3 => Some(Usclks::Sck),
96            _ => None,
97        }
98    }
99    #[doc = "Master Clock MCK is selected"]
100    #[inline(always)]
101    pub fn is_mck(&self) -> bool {
102        *self == Usclks::Mck
103    }
104    #[doc = "Internal Clock Divided MCK/DIV (DIV=8) is selected"]
105    #[inline(always)]
106    pub fn is_div(&self) -> bool {
107        *self == Usclks::Div
108    }
109    #[doc = "Serial Clock SLK is selected"]
110    #[inline(always)]
111    pub fn is_sck(&self) -> bool {
112        *self == Usclks::Sck
113    }
114}
115#[doc = "Field `USCLKS` writer - Clock Selection"]
116pub type UsclksW<'a, REG> = crate::FieldWriter<'a, REG, 2, Usclks>;
117impl<'a, REG> UsclksW<'a, REG>
118where
119    REG: crate::Writable + crate::RegisterSpec,
120    REG::Ux: From<u8>,
121{
122    #[doc = "Master Clock MCK is selected"]
123    #[inline(always)]
124    pub fn mck(self) -> &'a mut crate::W<REG> {
125        self.variant(Usclks::Mck)
126    }
127    #[doc = "Internal Clock Divided MCK/DIV (DIV=8) is selected"]
128    #[inline(always)]
129    pub fn div(self) -> &'a mut crate::W<REG> {
130        self.variant(Usclks::Div)
131    }
132    #[doc = "Serial Clock SLK is selected"]
133    #[inline(always)]
134    pub fn sck(self) -> &'a mut crate::W<REG> {
135        self.variant(Usclks::Sck)
136    }
137}
138#[doc = "Character Length."]
139#[derive(Clone, Copy, Debug, PartialEq, Eq)]
140#[repr(u8)]
141pub enum Chrl {
142    #[doc = "3: Character length is 8 bits"]
143    _8Bit = 3,
144}
145impl From<Chrl> for u8 {
146    #[inline(always)]
147    fn from(variant: Chrl) -> Self {
148        variant as _
149    }
150}
151impl crate::FieldSpec for Chrl {
152    type Ux = u8;
153}
154impl crate::IsEnum for Chrl {}
155#[doc = "Field `CHRL` reader - Character Length."]
156pub type ChrlR = crate::FieldReader<Chrl>;
157impl ChrlR {
158    #[doc = "Get enumerated values variant"]
159    #[inline(always)]
160    pub const fn variant(&self) -> Option<Chrl> {
161        match self.bits {
162            3 => Some(Chrl::_8Bit),
163            _ => None,
164        }
165    }
166    #[doc = "Character length is 8 bits"]
167    #[inline(always)]
168    pub fn is_8_bit(&self) -> bool {
169        *self == Chrl::_8Bit
170    }
171}
172#[doc = "Field `CHRL` writer - Character Length."]
173pub type ChrlW<'a, REG> = crate::FieldWriter<'a, REG, 2, Chrl>;
174impl<'a, REG> ChrlW<'a, REG>
175where
176    REG: crate::Writable + crate::RegisterSpec,
177    REG::Ux: From<u8>,
178{
179    #[doc = "Character length is 8 bits"]
180    #[inline(always)]
181    pub fn _8_bit(self) -> &'a mut crate::W<REG> {
182        self.variant(Chrl::_8Bit)
183    }
184}
185#[doc = "Field `CPHA` reader - SPI Clock Phase"]
186pub type CphaR = crate::BitReader;
187#[doc = "Field `CPHA` writer - SPI Clock Phase"]
188pub type CphaW<'a, REG> = crate::BitWriter<'a, REG>;
189#[doc = "Field `CPOL` reader - SPI Clock Polarity"]
190pub type CpolR = crate::BitReader;
191#[doc = "Field `CPOL` writer - SPI Clock Polarity"]
192pub type CpolW<'a, REG> = crate::BitWriter<'a, REG>;
193#[doc = "Field `WRDBT` reader - Wait Read Data Before Transfer"]
194pub type WrdbtR = crate::BitReader;
195#[doc = "Field `WRDBT` writer - Wait Read Data Before Transfer"]
196pub type WrdbtW<'a, REG> = crate::BitWriter<'a, REG>;
197impl R {
198    #[doc = "Bits 0:3 - USART Mode of Operation"]
199    #[inline(always)]
200    pub fn usart_mode(&self) -> UsartModeR {
201        UsartModeR::new((self.bits & 0x0f) as u8)
202    }
203    #[doc = "Bits 4:5 - Clock Selection"]
204    #[inline(always)]
205    pub fn usclks(&self) -> UsclksR {
206        UsclksR::new(((self.bits >> 4) & 3) as u8)
207    }
208    #[doc = "Bits 6:7 - Character Length."]
209    #[inline(always)]
210    pub fn chrl(&self) -> ChrlR {
211        ChrlR::new(((self.bits >> 6) & 3) as u8)
212    }
213    #[doc = "Bit 8 - SPI Clock Phase"]
214    #[inline(always)]
215    pub fn cpha(&self) -> CphaR {
216        CphaR::new(((self.bits >> 8) & 1) != 0)
217    }
218    #[doc = "Bit 16 - SPI Clock Polarity"]
219    #[inline(always)]
220    pub fn cpol(&self) -> CpolR {
221        CpolR::new(((self.bits >> 16) & 1) != 0)
222    }
223    #[doc = "Bit 20 - Wait Read Data Before Transfer"]
224    #[inline(always)]
225    pub fn wrdbt(&self) -> WrdbtR {
226        WrdbtR::new(((self.bits >> 20) & 1) != 0)
227    }
228}
229impl W {
230    #[doc = "Bits 0:3 - USART Mode of Operation"]
231    #[inline(always)]
232    #[must_use]
233    pub fn usart_mode(&mut self) -> UsartModeW<SpiModeMrSpiModeSpec> {
234        UsartModeW::new(self, 0)
235    }
236    #[doc = "Bits 4:5 - Clock Selection"]
237    #[inline(always)]
238    #[must_use]
239    pub fn usclks(&mut self) -> UsclksW<SpiModeMrSpiModeSpec> {
240        UsclksW::new(self, 4)
241    }
242    #[doc = "Bits 6:7 - Character Length."]
243    #[inline(always)]
244    #[must_use]
245    pub fn chrl(&mut self) -> ChrlW<SpiModeMrSpiModeSpec> {
246        ChrlW::new(self, 6)
247    }
248    #[doc = "Bit 8 - SPI Clock Phase"]
249    #[inline(always)]
250    #[must_use]
251    pub fn cpha(&mut self) -> CphaW<SpiModeMrSpiModeSpec> {
252        CphaW::new(self, 8)
253    }
254    #[doc = "Bit 16 - SPI Clock Polarity"]
255    #[inline(always)]
256    #[must_use]
257    pub fn cpol(&mut self) -> CpolW<SpiModeMrSpiModeSpec> {
258        CpolW::new(self, 16)
259    }
260    #[doc = "Bit 20 - Wait Read Data Before Transfer"]
261    #[inline(always)]
262    #[must_use]
263    pub fn wrdbt(&mut self) -> WrdbtW<SpiModeMrSpiModeSpec> {
264        WrdbtW::new(self, 20)
265    }
266}
267#[doc = "Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mode_mr_spi_mode::R`](R).  You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mode_mr_spi_mode::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
268pub struct SpiModeMrSpiModeSpec;
269impl crate::RegisterSpec for SpiModeMrSpiModeSpec {
270    type Ux = u32;
271}
272#[doc = "`read()` method returns [`spi_mode_mr_spi_mode::R`](R) reader structure"]
273impl crate::Readable for SpiModeMrSpiModeSpec {}
274#[doc = "`write(|w| ..)` method takes [`spi_mode_mr_spi_mode::W`](W) writer structure"]
275impl crate::Writable for SpiModeMrSpiModeSpec {
276    type Safety = crate::Unsafe;
277    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
278    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
279}
atsam3u1c/usart2/spi_mode_mr_spi_mode.rs

atsam3u1c/usart2/
spi_mode_mr_spi_mode.rs
