atsam3s2c/pmc/
pmc_imr.rs

1#[doc = "Register `PMC_IMR` reader"]
2pub type R = crate::R<PmcImrSpec>;
3#[doc = "Field `MOSCXTS` reader - Main Crystal Oscillator Status Interrupt Mask"]
4pub type MoscxtsR = crate::BitReader;
5#[doc = "Field `LOCKA` reader - PLLA Lock Interrupt Mask"]
6pub type LockaR = crate::BitReader;
7#[doc = "Field `LOCKB` reader - PLLB Lock Interrupt Mask"]
8pub type LockbR = crate::BitReader;
9#[doc = "Field `MCKRDY` reader - Master Clock Ready Interrupt Mask"]
10pub type MckrdyR = crate::BitReader;
11#[doc = "Field `PCKRDY0` reader - Programmable Clock Ready 0 Interrupt Mask"]
12pub type Pckrdy0R = crate::BitReader;
13#[doc = "Field `PCKRDY1` reader - Programmable Clock Ready 1 Interrupt Mask"]
14pub type Pckrdy1R = crate::BitReader;
15#[doc = "Field `PCKRDY2` reader - Programmable Clock Ready 2 Interrupt Mask"]
16pub type Pckrdy2R = crate::BitReader;
17#[doc = "Field `MOSCSELS` reader - Main Oscillator Selection Status Interrupt Mask"]
18pub type MoscselsR = crate::BitReader;
19#[doc = "Field `MOSCRCS` reader - Main On-Chip RC Status Interrupt Mask"]
20pub type MoscrcsR = crate::BitReader;
21#[doc = "Field `CFDEV` reader - Clock Failure Detector Event Interrupt Mask"]
22pub type CfdevR = crate::BitReader;
23impl R {
24    #[doc = "Bit 0 - Main Crystal Oscillator Status Interrupt Mask"]
25    #[inline(always)]
26    pub fn moscxts(&self) -> MoscxtsR {
27        MoscxtsR::new((self.bits & 1) != 0)
28    }
29    #[doc = "Bit 1 - PLLA Lock Interrupt Mask"]
30    #[inline(always)]
31    pub fn locka(&self) -> LockaR {
32        LockaR::new(((self.bits >> 1) & 1) != 0)
33    }
34    #[doc = "Bit 2 - PLLB Lock Interrupt Mask"]
35    #[inline(always)]
36    pub fn lockb(&self) -> LockbR {
37        LockbR::new(((self.bits >> 2) & 1) != 0)
38    }
39    #[doc = "Bit 3 - Master Clock Ready Interrupt Mask"]
40    #[inline(always)]
41    pub fn mckrdy(&self) -> MckrdyR {
42        MckrdyR::new(((self.bits >> 3) & 1) != 0)
43    }
44    #[doc = "Bit 8 - Programmable Clock Ready 0 Interrupt Mask"]
45    #[inline(always)]
46    pub fn pckrdy0(&self) -> Pckrdy0R {
47        Pckrdy0R::new(((self.bits >> 8) & 1) != 0)
48    }
49    #[doc = "Bit 9 - Programmable Clock Ready 1 Interrupt Mask"]
50    #[inline(always)]
51    pub fn pckrdy1(&self) -> Pckrdy1R {
52        Pckrdy1R::new(((self.bits >> 9) & 1) != 0)
53    }
54    #[doc = "Bit 10 - Programmable Clock Ready 2 Interrupt Mask"]
55    #[inline(always)]
56    pub fn pckrdy2(&self) -> Pckrdy2R {
57        Pckrdy2R::new(((self.bits >> 10) & 1) != 0)
58    }
59    #[doc = "Bit 16 - Main Oscillator Selection Status Interrupt Mask"]
60    #[inline(always)]
61    pub fn moscsels(&self) -> MoscselsR {
62        MoscselsR::new(((self.bits >> 16) & 1) != 0)
63    }
64    #[doc = "Bit 17 - Main On-Chip RC Status Interrupt Mask"]
65    #[inline(always)]
66    pub fn moscrcs(&self) -> MoscrcsR {
67        MoscrcsR::new(((self.bits >> 17) & 1) != 0)
68    }
69    #[doc = "Bit 18 - Clock Failure Detector Event Interrupt Mask"]
70    #[inline(always)]
71    pub fn cfdev(&self) -> CfdevR {
72        CfdevR::new(((self.bits >> 18) & 1) != 0)
73    }
74}
75#[doc = "Interrupt Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pmc_imr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
76pub struct PmcImrSpec;
77impl crate::RegisterSpec for PmcImrSpec {
78    type Ux = u32;
79}
80#[doc = "`read()` method returns [`pmc_imr::R`](R) reader structure"]
81impl crate::Readable for PmcImrSpec {}
82#[doc = "`reset()` method sets PMC_IMR to value 0"]
83impl crate::Resettable for PmcImrSpec {
84    const RESET_VALUE: u32 = 0;
85}
atsam3s2c/pmc/pmc_imr.rs

atsam3s2c/pmc/
pmc_imr.rs
