atsam3s2a/pmc/
pmc_idr.rs

1#[doc = "Register `PMC_IDR` writer"]
2pub type W = crate::W<PmcIdrSpec>;
3#[doc = "Field `MOSCXTS` writer - Main Crystal Oscillator Status Interrupt Disable"]
4pub type MoscxtsW<'a, REG> = crate::BitWriter<'a, REG>;
5#[doc = "Field `LOCKA` writer - PLLA Lock Interrupt Disable"]
6pub type LockaW<'a, REG> = crate::BitWriter<'a, REG>;
7#[doc = "Field `LOCKB` writer - PLLB Lock Interrupt Disable"]
8pub type LockbW<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `MCKRDY` writer - Master Clock Ready Interrupt Disable"]
10pub type MckrdyW<'a, REG> = crate::BitWriter<'a, REG>;
11#[doc = "Field `PCKRDY0` writer - Programmable Clock Ready 0 Interrupt Disable"]
12pub type Pckrdy0W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `PCKRDY1` writer - Programmable Clock Ready 1 Interrupt Disable"]
14pub type Pckrdy1W<'a, REG> = crate::BitWriter<'a, REG>;
15#[doc = "Field `PCKRDY2` writer - Programmable Clock Ready 2 Interrupt Disable"]
16pub type Pckrdy2W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `MOSCSELS` writer - Main Oscillator Selection Status Interrupt Disable"]
18pub type MoscselsW<'a, REG> = crate::BitWriter<'a, REG>;
19#[doc = "Field `MOSCRCS` writer - Main On-Chip RC Status Interrupt Disable"]
20pub type MoscrcsW<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `CFDEV` writer - Clock Failure Detector Event Interrupt Disable"]
22pub type CfdevW<'a, REG> = crate::BitWriter<'a, REG>;
23impl W {
24    #[doc = "Bit 0 - Main Crystal Oscillator Status Interrupt Disable"]
25    #[inline(always)]
26    #[must_use]
27    pub fn moscxts(&mut self) -> MoscxtsW<PmcIdrSpec> {
28        MoscxtsW::new(self, 0)
29    }
30    #[doc = "Bit 1 - PLLA Lock Interrupt Disable"]
31    #[inline(always)]
32    #[must_use]
33    pub fn locka(&mut self) -> LockaW<PmcIdrSpec> {
34        LockaW::new(self, 1)
35    }
36    #[doc = "Bit 2 - PLLB Lock Interrupt Disable"]
37    #[inline(always)]
38    #[must_use]
39    pub fn lockb(&mut self) -> LockbW<PmcIdrSpec> {
40        LockbW::new(self, 2)
41    }
42    #[doc = "Bit 3 - Master Clock Ready Interrupt Disable"]
43    #[inline(always)]
44    #[must_use]
45    pub fn mckrdy(&mut self) -> MckrdyW<PmcIdrSpec> {
46        MckrdyW::new(self, 3)
47    }
48    #[doc = "Bit 8 - Programmable Clock Ready 0 Interrupt Disable"]
49    #[inline(always)]
50    #[must_use]
51    pub fn pckrdy0(&mut self) -> Pckrdy0W<PmcIdrSpec> {
52        Pckrdy0W::new(self, 8)
53    }
54    #[doc = "Bit 9 - Programmable Clock Ready 1 Interrupt Disable"]
55    #[inline(always)]
56    #[must_use]
57    pub fn pckrdy1(&mut self) -> Pckrdy1W<PmcIdrSpec> {
58        Pckrdy1W::new(self, 9)
59    }
60    #[doc = "Bit 10 - Programmable Clock Ready 2 Interrupt Disable"]
61    #[inline(always)]
62    #[must_use]
63    pub fn pckrdy2(&mut self) -> Pckrdy2W<PmcIdrSpec> {
64        Pckrdy2W::new(self, 10)
65    }
66    #[doc = "Bit 16 - Main Oscillator Selection Status Interrupt Disable"]
67    #[inline(always)]
68    #[must_use]
69    pub fn moscsels(&mut self) -> MoscselsW<PmcIdrSpec> {
70        MoscselsW::new(self, 16)
71    }
72    #[doc = "Bit 17 - Main On-Chip RC Status Interrupt Disable"]
73    #[inline(always)]
74    #[must_use]
75    pub fn moscrcs(&mut self) -> MoscrcsW<PmcIdrSpec> {
76        MoscrcsW::new(self, 17)
77    }
78    #[doc = "Bit 18 - Clock Failure Detector Event Interrupt Disable"]
79    #[inline(always)]
80    #[must_use]
81    pub fn cfdev(&mut self) -> CfdevW<PmcIdrSpec> {
82        CfdevW::new(self, 18)
83    }
84}
85#[doc = "Interrupt Disable Register\n\nYou can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pmc_idr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
86pub struct PmcIdrSpec;
87impl crate::RegisterSpec for PmcIdrSpec {
88    type Ux = u32;
89}
90#[doc = "`write(|w| ..)` method takes [`pmc_idr::W`](W) writer structure"]
91impl crate::Writable for PmcIdrSpec {
92    type Safety = crate::Unsafe;
93    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
94    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
95}
atsam3s2a/pmc/pmc_idr.rs

atsam3s2a/pmc/
pmc_idr.rs
