atsam3s1c/pwm/
clk.rs

1#[doc = "Register `CLK` reader"]
2pub type R = crate::R<ClkSpec>;
3#[doc = "Register `CLK` writer"]
4pub type W = crate::W<ClkSpec>;
5#[doc = "Field `DIVA` reader - CLKA, CLKB Divide Factor"]
6pub type DivaR = crate::FieldReader;
7#[doc = "Field `DIVA` writer - CLKA, CLKB Divide Factor"]
8pub type DivaW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
9#[doc = "Field `PREA` reader - CLKA, CLKB Source Clock Selection"]
10pub type PreaR = crate::FieldReader;
11#[doc = "Field `PREA` writer - CLKA, CLKB Source Clock Selection"]
12pub type PreaW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
13#[doc = "Field `DIVB` reader - CLKA, CLKB Divide Factor"]
14pub type DivbR = crate::FieldReader;
15#[doc = "Field `DIVB` writer - CLKA, CLKB Divide Factor"]
16pub type DivbW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
17#[doc = "Field `PREB` reader - CLKA, CLKB Source Clock Selection"]
18pub type PrebR = crate::FieldReader;
19#[doc = "Field `PREB` writer - CLKA, CLKB Source Clock Selection"]
20pub type PrebW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
21impl R {
22    #[doc = "Bits 0:7 - CLKA, CLKB Divide Factor"]
23    #[inline(always)]
24    pub fn diva(&self) -> DivaR {
25        DivaR::new((self.bits & 0xff) as u8)
26    }
27    #[doc = "Bits 8:11 - CLKA, CLKB Source Clock Selection"]
28    #[inline(always)]
29    pub fn prea(&self) -> PreaR {
30        PreaR::new(((self.bits >> 8) & 0x0f) as u8)
31    }
32    #[doc = "Bits 16:23 - CLKA, CLKB Divide Factor"]
33    #[inline(always)]
34    pub fn divb(&self) -> DivbR {
35        DivbR::new(((self.bits >> 16) & 0xff) as u8)
36    }
37    #[doc = "Bits 24:27 - CLKA, CLKB Source Clock Selection"]
38    #[inline(always)]
39    pub fn preb(&self) -> PrebR {
40        PrebR::new(((self.bits >> 24) & 0x0f) as u8)
41    }
42}
43impl W {
44    #[doc = "Bits 0:7 - CLKA, CLKB Divide Factor"]
45    #[inline(always)]
46    #[must_use]
47    pub fn diva(&mut self) -> DivaW<ClkSpec> {
48        DivaW::new(self, 0)
49    }
50    #[doc = "Bits 8:11 - CLKA, CLKB Source Clock Selection"]
51    #[inline(always)]
52    #[must_use]
53    pub fn prea(&mut self) -> PreaW<ClkSpec> {
54        PreaW::new(self, 8)
55    }
56    #[doc = "Bits 16:23 - CLKA, CLKB Divide Factor"]
57    #[inline(always)]
58    #[must_use]
59    pub fn divb(&mut self) -> DivbW<ClkSpec> {
60        DivbW::new(self, 16)
61    }
62    #[doc = "Bits 24:27 - CLKA, CLKB Source Clock Selection"]
63    #[inline(always)]
64    #[must_use]
65    pub fn preb(&mut self) -> PrebW<ClkSpec> {
66        PrebW::new(self, 24)
67    }
68}
69#[doc = "PWM Clock Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
70pub struct ClkSpec;
71impl crate::RegisterSpec for ClkSpec {
72    type Ux = u32;
73}
74#[doc = "`read()` method returns [`clk::R`](R) reader structure"]
75impl crate::Readable for ClkSpec {}
76#[doc = "`write(|w| ..)` method takes [`clk::W`](W) writer structure"]
77impl crate::Writable for ClkSpec {
78    type Safety = crate::Unsafe;
79    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
80    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
81}
82#[doc = "`reset()` method sets CLK to value 0"]
83impl crate::Resettable for ClkSpec {
84    const RESET_VALUE: u32 = 0;
85}
atsam3s1c/pwm/clk.rs

atsam3s1c/pwm/
clk.rs
