atsam3s1c/pmc/
pmc_pck2.rs1#[doc = "Register `PMC_PCK2` reader"]
2pub type R = crate::R<PmcPck2Spec>;
3#[doc = "Register `PMC_PCK2` writer"]
4pub type W = crate::W<PmcPck2Spec>;
5#[doc = "Master Clock Source Selection"]
6#[derive(Clone, Copy, Debug, PartialEq, Eq)]
7#[repr(u8)]
8pub enum Css {
9 #[doc = "0: Slow Clock is selected"]
10 SlowClk = 0,
11 #[doc = "1: Main Clock is selected"]
12 MainClk = 1,
13 #[doc = "2: PLLA Clock is selected"]
14 PllaClk = 2,
15 #[doc = "3: PLLB Clock is selected"]
16 PllbClk = 3,
17 #[doc = "4: Master Clock is selected"]
18 Mck = 4,
19}
20impl From<Css> for u8 {
21 #[inline(always)]
22 fn from(variant: Css) -> Self {
23 variant as _
24 }
25}
26impl crate::FieldSpec for Css {
27 type Ux = u8;
28}
29impl crate::IsEnum for Css {}
30#[doc = "Field `CSS` reader - Master Clock Source Selection"]
31pub type CssR = crate::FieldReader<Css>;
32impl CssR {
33 #[doc = "Get enumerated values variant"]
34 #[inline(always)]
35 pub const fn variant(&self) -> Option<Css> {
36 match self.bits {
37 0 => Some(Css::SlowClk),
38 1 => Some(Css::MainClk),
39 2 => Some(Css::PllaClk),
40 3 => Some(Css::PllbClk),
41 4 => Some(Css::Mck),
42 _ => None,
43 }
44 }
45 #[doc = "Slow Clock is selected"]
46 #[inline(always)]
47 pub fn is_slow_clk(&self) -> bool {
48 *self == Css::SlowClk
49 }
50 #[doc = "Main Clock is selected"]
51 #[inline(always)]
52 pub fn is_main_clk(&self) -> bool {
53 *self == Css::MainClk
54 }
55 #[doc = "PLLA Clock is selected"]
56 #[inline(always)]
57 pub fn is_plla_clk(&self) -> bool {
58 *self == Css::PllaClk
59 }
60 #[doc = "PLLB Clock is selected"]
61 #[inline(always)]
62 pub fn is_pllb_clk(&self) -> bool {
63 *self == Css::PllbClk
64 }
65 #[doc = "Master Clock is selected"]
66 #[inline(always)]
67 pub fn is_mck(&self) -> bool {
68 *self == Css::Mck
69 }
70}
71#[doc = "Field `CSS` writer - Master Clock Source Selection"]
72pub type CssW<'a, REG> = crate::FieldWriter<'a, REG, 3, Css>;
73impl<'a, REG> CssW<'a, REG>
74where
75 REG: crate::Writable + crate::RegisterSpec,
76 REG::Ux: From<u8>,
77{
78 #[doc = "Slow Clock is selected"]
79 #[inline(always)]
80 pub fn slow_clk(self) -> &'a mut crate::W<REG> {
81 self.variant(Css::SlowClk)
82 }
83 #[doc = "Main Clock is selected"]
84 #[inline(always)]
85 pub fn main_clk(self) -> &'a mut crate::W<REG> {
86 self.variant(Css::MainClk)
87 }
88 #[doc = "PLLA Clock is selected"]
89 #[inline(always)]
90 pub fn plla_clk(self) -> &'a mut crate::W<REG> {
91 self.variant(Css::PllaClk)
92 }
93 #[doc = "PLLB Clock is selected"]
94 #[inline(always)]
95 pub fn pllb_clk(self) -> &'a mut crate::W<REG> {
96 self.variant(Css::PllbClk)
97 }
98 #[doc = "Master Clock is selected"]
99 #[inline(always)]
100 pub fn mck(self) -> &'a mut crate::W<REG> {
101 self.variant(Css::Mck)
102 }
103}
104#[doc = "Programmable Clock Prescaler"]
105#[derive(Clone, Copy, Debug, PartialEq, Eq)]
106#[repr(u8)]
107pub enum Pres {
108 #[doc = "0: Selected clock"]
109 Clk1 = 0,
110 #[doc = "1: Selected clock divided by 2"]
111 Clk2 = 1,
112 #[doc = "2: Selected clock divided by 4"]
113 Clk4 = 2,
114 #[doc = "3: Selected clock divided by 8"]
115 Clk8 = 3,
116 #[doc = "4: Selected clock divided by 16"]
117 Clk16 = 4,
118 #[doc = "5: Selected clock divided by 32"]
119 Clk32 = 5,
120 #[doc = "6: Selected clock divided by 64"]
121 Clk64 = 6,
122}
123impl From<Pres> for u8 {
124 #[inline(always)]
125 fn from(variant: Pres) -> Self {
126 variant as _
127 }
128}
129impl crate::FieldSpec for Pres {
130 type Ux = u8;
131}
132impl crate::IsEnum for Pres {}
133#[doc = "Field `PRES` reader - Programmable Clock Prescaler"]
134pub type PresR = crate::FieldReader<Pres>;
135impl PresR {
136 #[doc = "Get enumerated values variant"]
137 #[inline(always)]
138 pub const fn variant(&self) -> Option<Pres> {
139 match self.bits {
140 0 => Some(Pres::Clk1),
141 1 => Some(Pres::Clk2),
142 2 => Some(Pres::Clk4),
143 3 => Some(Pres::Clk8),
144 4 => Some(Pres::Clk16),
145 5 => Some(Pres::Clk32),
146 6 => Some(Pres::Clk64),
147 _ => None,
148 }
149 }
150 #[doc = "Selected clock"]
151 #[inline(always)]
152 pub fn is_clk_1(&self) -> bool {
153 *self == Pres::Clk1
154 }
155 #[doc = "Selected clock divided by 2"]
156 #[inline(always)]
157 pub fn is_clk_2(&self) -> bool {
158 *self == Pres::Clk2
159 }
160 #[doc = "Selected clock divided by 4"]
161 #[inline(always)]
162 pub fn is_clk_4(&self) -> bool {
163 *self == Pres::Clk4
164 }
165 #[doc = "Selected clock divided by 8"]
166 #[inline(always)]
167 pub fn is_clk_8(&self) -> bool {
168 *self == Pres::Clk8
169 }
170 #[doc = "Selected clock divided by 16"]
171 #[inline(always)]
172 pub fn is_clk_16(&self) -> bool {
173 *self == Pres::Clk16
174 }
175 #[doc = "Selected clock divided by 32"]
176 #[inline(always)]
177 pub fn is_clk_32(&self) -> bool {
178 *self == Pres::Clk32
179 }
180 #[doc = "Selected clock divided by 64"]
181 #[inline(always)]
182 pub fn is_clk_64(&self) -> bool {
183 *self == Pres::Clk64
184 }
185}
186#[doc = "Field `PRES` writer - Programmable Clock Prescaler"]
187pub type PresW<'a, REG> = crate::FieldWriter<'a, REG, 3, Pres>;
188impl<'a, REG> PresW<'a, REG>
189where
190 REG: crate::Writable + crate::RegisterSpec,
191 REG::Ux: From<u8>,
192{
193 #[doc = "Selected clock"]
194 #[inline(always)]
195 pub fn clk_1(self) -> &'a mut crate::W<REG> {
196 self.variant(Pres::Clk1)
197 }
198 #[doc = "Selected clock divided by 2"]
199 #[inline(always)]
200 pub fn clk_2(self) -> &'a mut crate::W<REG> {
201 self.variant(Pres::Clk2)
202 }
203 #[doc = "Selected clock divided by 4"]
204 #[inline(always)]
205 pub fn clk_4(self) -> &'a mut crate::W<REG> {
206 self.variant(Pres::Clk4)
207 }
208 #[doc = "Selected clock divided by 8"]
209 #[inline(always)]
210 pub fn clk_8(self) -> &'a mut crate::W<REG> {
211 self.variant(Pres::Clk8)
212 }
213 #[doc = "Selected clock divided by 16"]
214 #[inline(always)]
215 pub fn clk_16(self) -> &'a mut crate::W<REG> {
216 self.variant(Pres::Clk16)
217 }
218 #[doc = "Selected clock divided by 32"]
219 #[inline(always)]
220 pub fn clk_32(self) -> &'a mut crate::W<REG> {
221 self.variant(Pres::Clk32)
222 }
223 #[doc = "Selected clock divided by 64"]
224 #[inline(always)]
225 pub fn clk_64(self) -> &'a mut crate::W<REG> {
226 self.variant(Pres::Clk64)
227 }
228}
229impl R {
230 #[doc = "Bits 0:2 - Master Clock Source Selection"]
231 #[inline(always)]
232 pub fn css(&self) -> CssR {
233 CssR::new((self.bits & 7) as u8)
234 }
235 #[doc = "Bits 4:6 - Programmable Clock Prescaler"]
236 #[inline(always)]
237 pub fn pres(&self) -> PresR {
238 PresR::new(((self.bits >> 4) & 7) as u8)
239 }
240}
241impl W {
242 #[doc = "Bits 0:2 - Master Clock Source Selection"]
243 #[inline(always)]
244 #[must_use]
245 pub fn css(&mut self) -> CssW<PmcPck2Spec> {
246 CssW::new(self, 0)
247 }
248 #[doc = "Bits 4:6 - Programmable Clock Prescaler"]
249 #[inline(always)]
250 #[must_use]
251 pub fn pres(&mut self) -> PresW<PmcPck2Spec> {
252 PresW::new(self, 4)
253 }
254}
255#[doc = "Programmable Clock 0 Register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pmc_pck2::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pmc_pck2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
256pub struct PmcPck2Spec;
257impl crate::RegisterSpec for PmcPck2Spec {
258 type Ux = u32;
259}
260#[doc = "`read()` method returns [`pmc_pck2::R`](R) reader structure"]
261impl crate::Readable for PmcPck2Spec {}
262#[doc = "`write(|w| ..)` method takes [`pmc_pck2::W`](W) writer structure"]
263impl crate::Writable for PmcPck2Spec {
264 type Safety = crate::Unsafe;
265 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
266 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
267}