atsam3s1b/ssc/
rfmr.rs

1#[doc = "Register `RFMR` reader"]
2pub type R = crate::R<RfmrSpec>;
3#[doc = "Register `RFMR` writer"]
4pub type W = crate::W<RfmrSpec>;
5#[doc = "Field `DATLEN` reader - Data Length"]
6pub type DatlenR = crate::FieldReader;
7#[doc = "Field `DATLEN` writer - Data Length"]
8pub type DatlenW<'a, REG> = crate::FieldWriter<'a, REG, 5>;
9#[doc = "Field `LOOP` reader - Loop Mode"]
10pub type LoopR = crate::BitReader;
11#[doc = "Field `LOOP` writer - Loop Mode"]
12pub type LoopW<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `MSBF` reader - Most Significant Bit First"]
14pub type MsbfR = crate::BitReader;
15#[doc = "Field `MSBF` writer - Most Significant Bit First"]
16pub type MsbfW<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `DATNB` reader - Data Number per Frame"]
18pub type DatnbR = crate::FieldReader;
19#[doc = "Field `DATNB` writer - Data Number per Frame"]
20pub type DatnbW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
21#[doc = "Field `FSLEN` reader - Receive Frame Sync Length"]
22pub type FslenR = crate::FieldReader;
23#[doc = "Field `FSLEN` writer - Receive Frame Sync Length"]
24pub type FslenW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
25#[doc = "Receive Frame Sync Output Selection\n\nValue on reset: 0"]
26#[derive(Clone, Copy, Debug, PartialEq, Eq)]
27#[repr(u8)]
28pub enum Fsos {
29    #[doc = "0: None, RF pin is an input"]
30    None = 0,
31    #[doc = "1: Negative Pulse, RF pin is an output"]
32    Negative = 1,
33    #[doc = "2: Positive Pulse, RF pin is an output"]
34    Positive = 2,
35    #[doc = "3: Driven Low during data transfer, RF pin is an output"]
36    Low = 3,
37    #[doc = "4: Driven High during data transfer, RF pin is an output"]
38    High = 4,
39    #[doc = "5: Toggling at each start of data transfer, RF pin is an output"]
40    Toggling = 5,
41}
42impl From<Fsos> for u8 {
43    #[inline(always)]
44    fn from(variant: Fsos) -> Self {
45        variant as _
46    }
47}
48impl crate::FieldSpec for Fsos {
49    type Ux = u8;
50}
51impl crate::IsEnum for Fsos {}
52#[doc = "Field `FSOS` reader - Receive Frame Sync Output Selection"]
53pub type FsosR = crate::FieldReader<Fsos>;
54impl FsosR {
55    #[doc = "Get enumerated values variant"]
56    #[inline(always)]
57    pub const fn variant(&self) -> Option<Fsos> {
58        match self.bits {
59            0 => Some(Fsos::None),
60            1 => Some(Fsos::Negative),
61            2 => Some(Fsos::Positive),
62            3 => Some(Fsos::Low),
63            4 => Some(Fsos::High),
64            5 => Some(Fsos::Toggling),
65            _ => None,
66        }
67    }
68    #[doc = "None, RF pin is an input"]
69    #[inline(always)]
70    pub fn is_none(&self) -> bool {
71        *self == Fsos::None
72    }
73    #[doc = "Negative Pulse, RF pin is an output"]
74    #[inline(always)]
75    pub fn is_negative(&self) -> bool {
76        *self == Fsos::Negative
77    }
78    #[doc = "Positive Pulse, RF pin is an output"]
79    #[inline(always)]
80    pub fn is_positive(&self) -> bool {
81        *self == Fsos::Positive
82    }
83    #[doc = "Driven Low during data transfer, RF pin is an output"]
84    #[inline(always)]
85    pub fn is_low(&self) -> bool {
86        *self == Fsos::Low
87    }
88    #[doc = "Driven High during data transfer, RF pin is an output"]
89    #[inline(always)]
90    pub fn is_high(&self) -> bool {
91        *self == Fsos::High
92    }
93    #[doc = "Toggling at each start of data transfer, RF pin is an output"]
94    #[inline(always)]
95    pub fn is_toggling(&self) -> bool {
96        *self == Fsos::Toggling
97    }
98}
99#[doc = "Field `FSOS` writer - Receive Frame Sync Output Selection"]
100pub type FsosW<'a, REG> = crate::FieldWriter<'a, REG, 3, Fsos>;
101impl<'a, REG> FsosW<'a, REG>
102where
103    REG: crate::Writable + crate::RegisterSpec,
104    REG::Ux: From<u8>,
105{
106    #[doc = "None, RF pin is an input"]
107    #[inline(always)]
108    pub fn none(self) -> &'a mut crate::W<REG> {
109        self.variant(Fsos::None)
110    }
111    #[doc = "Negative Pulse, RF pin is an output"]
112    #[inline(always)]
113    pub fn negative(self) -> &'a mut crate::W<REG> {
114        self.variant(Fsos::Negative)
115    }
116    #[doc = "Positive Pulse, RF pin is an output"]
117    #[inline(always)]
118    pub fn positive(self) -> &'a mut crate::W<REG> {
119        self.variant(Fsos::Positive)
120    }
121    #[doc = "Driven Low during data transfer, RF pin is an output"]
122    #[inline(always)]
123    pub fn low(self) -> &'a mut crate::W<REG> {
124        self.variant(Fsos::Low)
125    }
126    #[doc = "Driven High during data transfer, RF pin is an output"]
127    #[inline(always)]
128    pub fn high(self) -> &'a mut crate::W<REG> {
129        self.variant(Fsos::High)
130    }
131    #[doc = "Toggling at each start of data transfer, RF pin is an output"]
132    #[inline(always)]
133    pub fn toggling(self) -> &'a mut crate::W<REG> {
134        self.variant(Fsos::Toggling)
135    }
136}
137#[doc = "Frame Sync Edge Detection\n\nValue on reset: 0"]
138#[derive(Clone, Copy, Debug, PartialEq, Eq)]
139pub enum Fsedge {
140    #[doc = "0: Positive Edge Detection"]
141    Positive = 0,
142    #[doc = "1: Negative Edge Detection"]
143    Negative = 1,
144}
145impl From<Fsedge> for bool {
146    #[inline(always)]
147    fn from(variant: Fsedge) -> Self {
148        variant as u8 != 0
149    }
150}
151#[doc = "Field `FSEDGE` reader - Frame Sync Edge Detection"]
152pub type FsedgeR = crate::BitReader<Fsedge>;
153impl FsedgeR {
154    #[doc = "Get enumerated values variant"]
155    #[inline(always)]
156    pub const fn variant(&self) -> Fsedge {
157        match self.bits {
158            false => Fsedge::Positive,
159            true => Fsedge::Negative,
160        }
161    }
162    #[doc = "Positive Edge Detection"]
163    #[inline(always)]
164    pub fn is_positive(&self) -> bool {
165        *self == Fsedge::Positive
166    }
167    #[doc = "Negative Edge Detection"]
168    #[inline(always)]
169    pub fn is_negative(&self) -> bool {
170        *self == Fsedge::Negative
171    }
172}
173#[doc = "Field `FSEDGE` writer - Frame Sync Edge Detection"]
174pub type FsedgeW<'a, REG> = crate::BitWriter<'a, REG, Fsedge>;
175impl<'a, REG> FsedgeW<'a, REG>
176where
177    REG: crate::Writable + crate::RegisterSpec,
178{
179    #[doc = "Positive Edge Detection"]
180    #[inline(always)]
181    pub fn positive(self) -> &'a mut crate::W<REG> {
182        self.variant(Fsedge::Positive)
183    }
184    #[doc = "Negative Edge Detection"]
185    #[inline(always)]
186    pub fn negative(self) -> &'a mut crate::W<REG> {
187        self.variant(Fsedge::Negative)
188    }
189}
190#[doc = "Field `FSLEN_EXT` reader - FSLEN Field Extension"]
191pub type FslenExtR = crate::FieldReader;
192#[doc = "Field `FSLEN_EXT` writer - FSLEN Field Extension"]
193pub type FslenExtW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
194impl R {
195    #[doc = "Bits 0:4 - Data Length"]
196    #[inline(always)]
197    pub fn datlen(&self) -> DatlenR {
198        DatlenR::new((self.bits & 0x1f) as u8)
199    }
200    #[doc = "Bit 5 - Loop Mode"]
201    #[inline(always)]
202    pub fn loop_(&self) -> LoopR {
203        LoopR::new(((self.bits >> 5) & 1) != 0)
204    }
205    #[doc = "Bit 7 - Most Significant Bit First"]
206    #[inline(always)]
207    pub fn msbf(&self) -> MsbfR {
208        MsbfR::new(((self.bits >> 7) & 1) != 0)
209    }
210    #[doc = "Bits 8:11 - Data Number per Frame"]
211    #[inline(always)]
212    pub fn datnb(&self) -> DatnbR {
213        DatnbR::new(((self.bits >> 8) & 0x0f) as u8)
214    }
215    #[doc = "Bits 16:19 - Receive Frame Sync Length"]
216    #[inline(always)]
217    pub fn fslen(&self) -> FslenR {
218        FslenR::new(((self.bits >> 16) & 0x0f) as u8)
219    }
220    #[doc = "Bits 20:22 - Receive Frame Sync Output Selection"]
221    #[inline(always)]
222    pub fn fsos(&self) -> FsosR {
223        FsosR::new(((self.bits >> 20) & 7) as u8)
224    }
225    #[doc = "Bit 24 - Frame Sync Edge Detection"]
226    #[inline(always)]
227    pub fn fsedge(&self) -> FsedgeR {
228        FsedgeR::new(((self.bits >> 24) & 1) != 0)
229    }
230    #[doc = "Bits 28:31 - FSLEN Field Extension"]
231    #[inline(always)]
232    pub fn fslen_ext(&self) -> FslenExtR {
233        FslenExtR::new(((self.bits >> 28) & 0x0f) as u8)
234    }
235}
236impl W {
237    #[doc = "Bits 0:4 - Data Length"]
238    #[inline(always)]
239    #[must_use]
240    pub fn datlen(&mut self) -> DatlenW<RfmrSpec> {
241        DatlenW::new(self, 0)
242    }
243    #[doc = "Bit 5 - Loop Mode"]
244    #[inline(always)]
245    #[must_use]
246    pub fn loop_(&mut self) -> LoopW<RfmrSpec> {
247        LoopW::new(self, 5)
248    }
249    #[doc = "Bit 7 - Most Significant Bit First"]
250    #[inline(always)]
251    #[must_use]
252    pub fn msbf(&mut self) -> MsbfW<RfmrSpec> {
253        MsbfW::new(self, 7)
254    }
255    #[doc = "Bits 8:11 - Data Number per Frame"]
256    #[inline(always)]
257    #[must_use]
258    pub fn datnb(&mut self) -> DatnbW<RfmrSpec> {
259        DatnbW::new(self, 8)
260    }
261    #[doc = "Bits 16:19 - Receive Frame Sync Length"]
262    #[inline(always)]
263    #[must_use]
264    pub fn fslen(&mut self) -> FslenW<RfmrSpec> {
265        FslenW::new(self, 16)
266    }
267    #[doc = "Bits 20:22 - Receive Frame Sync Output Selection"]
268    #[inline(always)]
269    #[must_use]
270    pub fn fsos(&mut self) -> FsosW<RfmrSpec> {
271        FsosW::new(self, 20)
272    }
273    #[doc = "Bit 24 - Frame Sync Edge Detection"]
274    #[inline(always)]
275    #[must_use]
276    pub fn fsedge(&mut self) -> FsedgeW<RfmrSpec> {
277        FsedgeW::new(self, 24)
278    }
279    #[doc = "Bits 28:31 - FSLEN Field Extension"]
280    #[inline(always)]
281    #[must_use]
282    pub fn fslen_ext(&mut self) -> FslenExtW<RfmrSpec> {
283        FslenExtW::new(self, 28)
284    }
285}
286#[doc = "Receive Frame Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rfmr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rfmr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
287pub struct RfmrSpec;
288impl crate::RegisterSpec for RfmrSpec {
289    type Ux = u32;
290}
291#[doc = "`read()` method returns [`rfmr::R`](R) reader structure"]
292impl crate::Readable for RfmrSpec {}
293#[doc = "`write(|w| ..)` method takes [`rfmr::W`](W) writer structure"]
294impl crate::Writable for RfmrSpec {
295    type Safety = crate::Unsafe;
296    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
297    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
298}
299#[doc = "`reset()` method sets RFMR to value 0"]
300impl crate::Resettable for RfmrSpec {
301    const RESET_VALUE: u32 = 0;
302}
atsam3s1b/ssc/rfmr.rs

atsam3s1b/ssc/
rfmr.rs
