atsam3n2c/usart0/
ier.rs

1#[doc = "Register `IER` writer"]
2pub type W = crate::W<IerSpec>;
3#[doc = "Field `RXRDY` writer - RXRDY Interrupt Enable"]
4pub type RxrdyW<'a, REG> = crate::BitWriter<'a, REG>;
5#[doc = "Field `TXRDY` writer - TXRDY Interrupt Enable"]
6pub type TxrdyW<'a, REG> = crate::BitWriter<'a, REG>;
7#[doc = "Field `RXBRK` writer - Receiver Break Interrupt Enable"]
8pub type RxbrkW<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `ENDRX` writer - End of Receive Transfer Interrupt Enable (available in all USART modes of operation)"]
10pub type EndrxW<'a, REG> = crate::BitWriter<'a, REG>;
11#[doc = "Field `ENDTX` writer - End of Transmit Interrupt Enable (available in all USART modes of operation)"]
12pub type EndtxW<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `OVRE` writer - Overrun Error Interrupt Enable"]
14pub type OvreW<'a, REG> = crate::BitWriter<'a, REG>;
15#[doc = "Field `FRAME` writer - Framing Error Interrupt Enable"]
16pub type FrameW<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `PARE` writer - Parity Error Interrupt Enable"]
18pub type PareW<'a, REG> = crate::BitWriter<'a, REG>;
19#[doc = "Field `TIMEOUT` writer - Time-out Interrupt Enable"]
20pub type TimeoutW<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `TXEMPTY` writer - TXEMPTY Interrupt Enable"]
22pub type TxemptyW<'a, REG> = crate::BitWriter<'a, REG>;
23#[doc = "Field `ITER` writer - Max number of Repetitions Reached Interrupt Enable"]
24pub type IterW<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `TXBUFE` writer - Buffer Empty Interrupt Enable (available in all USART modes of operation)"]
26pub type TxbufeW<'a, REG> = crate::BitWriter<'a, REG>;
27#[doc = "Field `RXBUFF` writer - Buffer Full Interrupt Enable (available in all USART modes of operation)"]
28pub type RxbuffW<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `NACK` writer - Non AcknowledgeInterrupt Enable"]
30pub type NackW<'a, REG> = crate::BitWriter<'a, REG>;
31#[doc = "Field `CTSIC` writer - Clear to Send Input Change Interrupt Enable"]
32pub type CtsicW<'a, REG> = crate::BitWriter<'a, REG>;
33impl W {
34    #[doc = "Bit 0 - RXRDY Interrupt Enable"]
35    #[inline(always)]
36    #[must_use]
37    pub fn rxrdy(&mut self) -> RxrdyW<IerSpec> {
38        RxrdyW::new(self, 0)
39    }
40    #[doc = "Bit 1 - TXRDY Interrupt Enable"]
41    #[inline(always)]
42    #[must_use]
43    pub fn txrdy(&mut self) -> TxrdyW<IerSpec> {
44        TxrdyW::new(self, 1)
45    }
46    #[doc = "Bit 2 - Receiver Break Interrupt Enable"]
47    #[inline(always)]
48    #[must_use]
49    pub fn rxbrk(&mut self) -> RxbrkW<IerSpec> {
50        RxbrkW::new(self, 2)
51    }
52    #[doc = "Bit 3 - End of Receive Transfer Interrupt Enable (available in all USART modes of operation)"]
53    #[inline(always)]
54    #[must_use]
55    pub fn endrx(&mut self) -> EndrxW<IerSpec> {
56        EndrxW::new(self, 3)
57    }
58    #[doc = "Bit 4 - End of Transmit Interrupt Enable (available in all USART modes of operation)"]
59    #[inline(always)]
60    #[must_use]
61    pub fn endtx(&mut self) -> EndtxW<IerSpec> {
62        EndtxW::new(self, 4)
63    }
64    #[doc = "Bit 5 - Overrun Error Interrupt Enable"]
65    #[inline(always)]
66    #[must_use]
67    pub fn ovre(&mut self) -> OvreW<IerSpec> {
68        OvreW::new(self, 5)
69    }
70    #[doc = "Bit 6 - Framing Error Interrupt Enable"]
71    #[inline(always)]
72    #[must_use]
73    pub fn frame(&mut self) -> FrameW<IerSpec> {
74        FrameW::new(self, 6)
75    }
76    #[doc = "Bit 7 - Parity Error Interrupt Enable"]
77    #[inline(always)]
78    #[must_use]
79    pub fn pare(&mut self) -> PareW<IerSpec> {
80        PareW::new(self, 7)
81    }
82    #[doc = "Bit 8 - Time-out Interrupt Enable"]
83    #[inline(always)]
84    #[must_use]
85    pub fn timeout(&mut self) -> TimeoutW<IerSpec> {
86        TimeoutW::new(self, 8)
87    }
88    #[doc = "Bit 9 - TXEMPTY Interrupt Enable"]
89    #[inline(always)]
90    #[must_use]
91    pub fn txempty(&mut self) -> TxemptyW<IerSpec> {
92        TxemptyW::new(self, 9)
93    }
94    #[doc = "Bit 10 - Max number of Repetitions Reached Interrupt Enable"]
95    #[inline(always)]
96    #[must_use]
97    pub fn iter(&mut self) -> IterW<IerSpec> {
98        IterW::new(self, 10)
99    }
100    #[doc = "Bit 11 - Buffer Empty Interrupt Enable (available in all USART modes of operation)"]
101    #[inline(always)]
102    #[must_use]
103    pub fn txbufe(&mut self) -> TxbufeW<IerSpec> {
104        TxbufeW::new(self, 11)
105    }
106    #[doc = "Bit 12 - Buffer Full Interrupt Enable (available in all USART modes of operation)"]
107    #[inline(always)]
108    #[must_use]
109    pub fn rxbuff(&mut self) -> RxbuffW<IerSpec> {
110        RxbuffW::new(self, 12)
111    }
112    #[doc = "Bit 13 - Non AcknowledgeInterrupt Enable"]
113    #[inline(always)]
114    #[must_use]
115    pub fn nack(&mut self) -> NackW<IerSpec> {
116        NackW::new(self, 13)
117    }
118    #[doc = "Bit 19 - Clear to Send Input Change Interrupt Enable"]
119    #[inline(always)]
120    #[must_use]
121    pub fn ctsic(&mut self) -> CtsicW<IerSpec> {
122        CtsicW::new(self, 19)
123    }
124}
125#[doc = "Interrupt Enable Register\n\nYou can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
126pub struct IerSpec;
127impl crate::RegisterSpec for IerSpec {
128    type Ux = u32;
129}
130#[doc = "`write(|w| ..)` method takes [`ier::W`](W) writer structure"]
131impl crate::Writable for IerSpec {
132    type Safety = crate::Unsafe;
133    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
134    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
135}
atsam3n2c/usart0/ier.rs

atsam3n2c/usart0/
ier.rs
