atsam3n1c/tc1/
cmr0.rs

1#[doc = "Register `CMR0` reader"]
2pub type R = crate::R<Cmr0Spec>;
3#[doc = "Register `CMR0` writer"]
4pub type W = crate::W<Cmr0Spec>;
5#[doc = "Clock Selection\n\nValue on reset: 0"]
6#[derive(Clone, Copy, Debug, PartialEq, Eq)]
7#[repr(u8)]
8pub enum Tcclks {
9    #[doc = "0: Clock selected: internal MCK/2 clock signal (from PMC)"]
10    TimerClock1 = 0,
11    #[doc = "1: Clock selected: internal MCK/8 clock signal (from PMC)"]
12    TimerClock2 = 1,
13    #[doc = "2: Clock selected: internal MCK/32 clock signal (from PMC)"]
14    TimerClock3 = 2,
15    #[doc = "3: Clock selected: internal MCK/128 clock signal (from PMC)"]
16    TimerClock4 = 3,
17    #[doc = "4: Clock selected: internal SLCK clock signal (from PMC)"]
18    TimerClock5 = 4,
19    #[doc = "5: Clock selected: XC0"]
20    Xc0 = 5,
21    #[doc = "6: Clock selected: XC1"]
22    Xc1 = 6,
23    #[doc = "7: Clock selected: XC2"]
24    Xc2 = 7,
25}
26impl From<Tcclks> for u8 {
27    #[inline(always)]
28    fn from(variant: Tcclks) -> Self {
29        variant as _
30    }
31}
32impl crate::FieldSpec for Tcclks {
33    type Ux = u8;
34}
35impl crate::IsEnum for Tcclks {}
36#[doc = "Field `TCCLKS` reader - Clock Selection"]
37pub type TcclksR = crate::FieldReader<Tcclks>;
38impl TcclksR {
39    #[doc = "Get enumerated values variant"]
40    #[inline(always)]
41    pub const fn variant(&self) -> Tcclks {
42        match self.bits {
43            0 => Tcclks::TimerClock1,
44            1 => Tcclks::TimerClock2,
45            2 => Tcclks::TimerClock3,
46            3 => Tcclks::TimerClock4,
47            4 => Tcclks::TimerClock5,
48            5 => Tcclks::Xc0,
49            6 => Tcclks::Xc1,
50            7 => Tcclks::Xc2,
51            _ => unreachable!(),
52        }
53    }
54    #[doc = "Clock selected: internal MCK/2 clock signal (from PMC)"]
55    #[inline(always)]
56    pub fn is_timer_clock1(&self) -> bool {
57        *self == Tcclks::TimerClock1
58    }
59    #[doc = "Clock selected: internal MCK/8 clock signal (from PMC)"]
60    #[inline(always)]
61    pub fn is_timer_clock2(&self) -> bool {
62        *self == Tcclks::TimerClock2
63    }
64    #[doc = "Clock selected: internal MCK/32 clock signal (from PMC)"]
65    #[inline(always)]
66    pub fn is_timer_clock3(&self) -> bool {
67        *self == Tcclks::TimerClock3
68    }
69    #[doc = "Clock selected: internal MCK/128 clock signal (from PMC)"]
70    #[inline(always)]
71    pub fn is_timer_clock4(&self) -> bool {
72        *self == Tcclks::TimerClock4
73    }
74    #[doc = "Clock selected: internal SLCK clock signal (from PMC)"]
75    #[inline(always)]
76    pub fn is_timer_clock5(&self) -> bool {
77        *self == Tcclks::TimerClock5
78    }
79    #[doc = "Clock selected: XC0"]
80    #[inline(always)]
81    pub fn is_xc0(&self) -> bool {
82        *self == Tcclks::Xc0
83    }
84    #[doc = "Clock selected: XC1"]
85    #[inline(always)]
86    pub fn is_xc1(&self) -> bool {
87        *self == Tcclks::Xc1
88    }
89    #[doc = "Clock selected: XC2"]
90    #[inline(always)]
91    pub fn is_xc2(&self) -> bool {
92        *self == Tcclks::Xc2
93    }
94}
95#[doc = "Field `TCCLKS` writer - Clock Selection"]
96pub type TcclksW<'a, REG> = crate::FieldWriter<'a, REG, 3, Tcclks, crate::Safe>;
97impl<'a, REG> TcclksW<'a, REG>
98where
99    REG: crate::Writable + crate::RegisterSpec,
100    REG::Ux: From<u8>,
101{
102    #[doc = "Clock selected: internal MCK/2 clock signal (from PMC)"]
103    #[inline(always)]
104    pub fn timer_clock1(self) -> &'a mut crate::W<REG> {
105        self.variant(Tcclks::TimerClock1)
106    }
107    #[doc = "Clock selected: internal MCK/8 clock signal (from PMC)"]
108    #[inline(always)]
109    pub fn timer_clock2(self) -> &'a mut crate::W<REG> {
110        self.variant(Tcclks::TimerClock2)
111    }
112    #[doc = "Clock selected: internal MCK/32 clock signal (from PMC)"]
113    #[inline(always)]
114    pub fn timer_clock3(self) -> &'a mut crate::W<REG> {
115        self.variant(Tcclks::TimerClock3)
116    }
117    #[doc = "Clock selected: internal MCK/128 clock signal (from PMC)"]
118    #[inline(always)]
119    pub fn timer_clock4(self) -> &'a mut crate::W<REG> {
120        self.variant(Tcclks::TimerClock4)
121    }
122    #[doc = "Clock selected: internal SLCK clock signal (from PMC)"]
123    #[inline(always)]
124    pub fn timer_clock5(self) -> &'a mut crate::W<REG> {
125        self.variant(Tcclks::TimerClock5)
126    }
127    #[doc = "Clock selected: XC0"]
128    #[inline(always)]
129    pub fn xc0(self) -> &'a mut crate::W<REG> {
130        self.variant(Tcclks::Xc0)
131    }
132    #[doc = "Clock selected: XC1"]
133    #[inline(always)]
134    pub fn xc1(self) -> &'a mut crate::W<REG> {
135        self.variant(Tcclks::Xc1)
136    }
137    #[doc = "Clock selected: XC2"]
138    #[inline(always)]
139    pub fn xc2(self) -> &'a mut crate::W<REG> {
140        self.variant(Tcclks::Xc2)
141    }
142}
143#[doc = "Field `CLKI` reader - Clock Invert"]
144pub type ClkiR = crate::BitReader;
145#[doc = "Field `CLKI` writer - Clock Invert"]
146pub type ClkiW<'a, REG> = crate::BitWriter<'a, REG>;
147#[doc = "Burst Signal Selection\n\nValue on reset: 0"]
148#[derive(Clone, Copy, Debug, PartialEq, Eq)]
149#[repr(u8)]
150pub enum Burst {
151    #[doc = "0: The clock is not gated by an external signal."]
152    None = 0,
153    #[doc = "1: XC0 is ANDed with the selected clock."]
154    Xc0 = 1,
155    #[doc = "2: XC1 is ANDed with the selected clock."]
156    Xc1 = 2,
157    #[doc = "3: XC2 is ANDed with the selected clock."]
158    Xc2 = 3,
159}
160impl From<Burst> for u8 {
161    #[inline(always)]
162    fn from(variant: Burst) -> Self {
163        variant as _
164    }
165}
166impl crate::FieldSpec for Burst {
167    type Ux = u8;
168}
169impl crate::IsEnum for Burst {}
170#[doc = "Field `BURST` reader - Burst Signal Selection"]
171pub type BurstR = crate::FieldReader<Burst>;
172impl BurstR {
173    #[doc = "Get enumerated values variant"]
174    #[inline(always)]
175    pub const fn variant(&self) -> Burst {
176        match self.bits {
177            0 => Burst::None,
178            1 => Burst::Xc0,
179            2 => Burst::Xc1,
180            3 => Burst::Xc2,
181            _ => unreachable!(),
182        }
183    }
184    #[doc = "The clock is not gated by an external signal."]
185    #[inline(always)]
186    pub fn is_none(&self) -> bool {
187        *self == Burst::None
188    }
189    #[doc = "XC0 is ANDed with the selected clock."]
190    #[inline(always)]
191    pub fn is_xc0(&self) -> bool {
192        *self == Burst::Xc0
193    }
194    #[doc = "XC1 is ANDed with the selected clock."]
195    #[inline(always)]
196    pub fn is_xc1(&self) -> bool {
197        *self == Burst::Xc1
198    }
199    #[doc = "XC2 is ANDed with the selected clock."]
200    #[inline(always)]
201    pub fn is_xc2(&self) -> bool {
202        *self == Burst::Xc2
203    }
204}
205#[doc = "Field `BURST` writer - Burst Signal Selection"]
206pub type BurstW<'a, REG> = crate::FieldWriter<'a, REG, 2, Burst, crate::Safe>;
207impl<'a, REG> BurstW<'a, REG>
208where
209    REG: crate::Writable + crate::RegisterSpec,
210    REG::Ux: From<u8>,
211{
212    #[doc = "The clock is not gated by an external signal."]
213    #[inline(always)]
214    pub fn none(self) -> &'a mut crate::W<REG> {
215        self.variant(Burst::None)
216    }
217    #[doc = "XC0 is ANDed with the selected clock."]
218    #[inline(always)]
219    pub fn xc0(self) -> &'a mut crate::W<REG> {
220        self.variant(Burst::Xc0)
221    }
222    #[doc = "XC1 is ANDed with the selected clock."]
223    #[inline(always)]
224    pub fn xc1(self) -> &'a mut crate::W<REG> {
225        self.variant(Burst::Xc1)
226    }
227    #[doc = "XC2 is ANDed with the selected clock."]
228    #[inline(always)]
229    pub fn xc2(self) -> &'a mut crate::W<REG> {
230        self.variant(Burst::Xc2)
231    }
232}
233#[doc = "Field `LDBSTOP` reader - Counter Clock Stopped with RB Loading"]
234pub type LdbstopR = crate::BitReader;
235#[doc = "Field `LDBSTOP` writer - Counter Clock Stopped with RB Loading"]
236pub type LdbstopW<'a, REG> = crate::BitWriter<'a, REG>;
237#[doc = "Field `LDBDIS` reader - Counter Clock Disable with RB Loading"]
238pub type LdbdisR = crate::BitReader;
239#[doc = "Field `LDBDIS` writer - Counter Clock Disable with RB Loading"]
240pub type LdbdisW<'a, REG> = crate::BitWriter<'a, REG>;
241#[doc = "External Trigger Edge Selection\n\nValue on reset: 0"]
242#[derive(Clone, Copy, Debug, PartialEq, Eq)]
243#[repr(u8)]
244pub enum Etrgedg {
245    #[doc = "0: The clock is not gated by an external signal."]
246    None = 0,
247    #[doc = "1: Rising edge"]
248    Rising = 1,
249    #[doc = "2: Falling edge"]
250    Falling = 2,
251    #[doc = "3: Each edge"]
252    Edge = 3,
253}
254impl From<Etrgedg> for u8 {
255    #[inline(always)]
256    fn from(variant: Etrgedg) -> Self {
257        variant as _
258    }
259}
260impl crate::FieldSpec for Etrgedg {
261    type Ux = u8;
262}
263impl crate::IsEnum for Etrgedg {}
264#[doc = "Field `ETRGEDG` reader - External Trigger Edge Selection"]
265pub type EtrgedgR = crate::FieldReader<Etrgedg>;
266impl EtrgedgR {
267    #[doc = "Get enumerated values variant"]
268    #[inline(always)]
269    pub const fn variant(&self) -> Etrgedg {
270        match self.bits {
271            0 => Etrgedg::None,
272            1 => Etrgedg::Rising,
273            2 => Etrgedg::Falling,
274            3 => Etrgedg::Edge,
275            _ => unreachable!(),
276        }
277    }
278    #[doc = "The clock is not gated by an external signal."]
279    #[inline(always)]
280    pub fn is_none(&self) -> bool {
281        *self == Etrgedg::None
282    }
283    #[doc = "Rising edge"]
284    #[inline(always)]
285    pub fn is_rising(&self) -> bool {
286        *self == Etrgedg::Rising
287    }
288    #[doc = "Falling edge"]
289    #[inline(always)]
290    pub fn is_falling(&self) -> bool {
291        *self == Etrgedg::Falling
292    }
293    #[doc = "Each edge"]
294    #[inline(always)]
295    pub fn is_edge(&self) -> bool {
296        *self == Etrgedg::Edge
297    }
298}
299#[doc = "Field `ETRGEDG` writer - External Trigger Edge Selection"]
300pub type EtrgedgW<'a, REG> = crate::FieldWriter<'a, REG, 2, Etrgedg, crate::Safe>;
301impl<'a, REG> EtrgedgW<'a, REG>
302where
303    REG: crate::Writable + crate::RegisterSpec,
304    REG::Ux: From<u8>,
305{
306    #[doc = "The clock is not gated by an external signal."]
307    #[inline(always)]
308    pub fn none(self) -> &'a mut crate::W<REG> {
309        self.variant(Etrgedg::None)
310    }
311    #[doc = "Rising edge"]
312    #[inline(always)]
313    pub fn rising(self) -> &'a mut crate::W<REG> {
314        self.variant(Etrgedg::Rising)
315    }
316    #[doc = "Falling edge"]
317    #[inline(always)]
318    pub fn falling(self) -> &'a mut crate::W<REG> {
319        self.variant(Etrgedg::Falling)
320    }
321    #[doc = "Each edge"]
322    #[inline(always)]
323    pub fn edge(self) -> &'a mut crate::W<REG> {
324        self.variant(Etrgedg::Edge)
325    }
326}
327#[doc = "Field `ABETRG` reader - TIOA or TIOB External Trigger Selection"]
328pub type AbetrgR = crate::BitReader;
329#[doc = "Field `ABETRG` writer - TIOA or TIOB External Trigger Selection"]
330pub type AbetrgW<'a, REG> = crate::BitWriter<'a, REG>;
331#[doc = "Field `CPCTRG` reader - RC Compare Trigger Enable"]
332pub type CpctrgR = crate::BitReader;
333#[doc = "Field `CPCTRG` writer - RC Compare Trigger Enable"]
334pub type CpctrgW<'a, REG> = crate::BitWriter<'a, REG>;
335#[doc = "Field `WAVE` reader - Waveform Mode"]
336pub type WaveR = crate::BitReader;
337#[doc = "Field `WAVE` writer - Waveform Mode"]
338pub type WaveW<'a, REG> = crate::BitWriter<'a, REG>;
339#[doc = "RA Loading Edge Selection\n\nValue on reset: 0"]
340#[derive(Clone, Copy, Debug, PartialEq, Eq)]
341#[repr(u8)]
342pub enum Ldra {
343    #[doc = "0: None"]
344    None = 0,
345    #[doc = "1: Rising edge of TIOA"]
346    Rising = 1,
347    #[doc = "2: Falling edge of TIOA"]
348    Falling = 2,
349    #[doc = "3: Each edge of TIOA"]
350    Edge = 3,
351}
352impl From<Ldra> for u8 {
353    #[inline(always)]
354    fn from(variant: Ldra) -> Self {
355        variant as _
356    }
357}
358impl crate::FieldSpec for Ldra {
359    type Ux = u8;
360}
361impl crate::IsEnum for Ldra {}
362#[doc = "Field `LDRA` reader - RA Loading Edge Selection"]
363pub type LdraR = crate::FieldReader<Ldra>;
364impl LdraR {
365    #[doc = "Get enumerated values variant"]
366    #[inline(always)]
367    pub const fn variant(&self) -> Ldra {
368        match self.bits {
369            0 => Ldra::None,
370            1 => Ldra::Rising,
371            2 => Ldra::Falling,
372            3 => Ldra::Edge,
373            _ => unreachable!(),
374        }
375    }
376    #[doc = "None"]
377    #[inline(always)]
378    pub fn is_none(&self) -> bool {
379        *self == Ldra::None
380    }
381    #[doc = "Rising edge of TIOA"]
382    #[inline(always)]
383    pub fn is_rising(&self) -> bool {
384        *self == Ldra::Rising
385    }
386    #[doc = "Falling edge of TIOA"]
387    #[inline(always)]
388    pub fn is_falling(&self) -> bool {
389        *self == Ldra::Falling
390    }
391    #[doc = "Each edge of TIOA"]
392    #[inline(always)]
393    pub fn is_edge(&self) -> bool {
394        *self == Ldra::Edge
395    }
396}
397#[doc = "Field `LDRA` writer - RA Loading Edge Selection"]
398pub type LdraW<'a, REG> = crate::FieldWriter<'a, REG, 2, Ldra, crate::Safe>;
399impl<'a, REG> LdraW<'a, REG>
400where
401    REG: crate::Writable + crate::RegisterSpec,
402    REG::Ux: From<u8>,
403{
404    #[doc = "None"]
405    #[inline(always)]
406    pub fn none(self) -> &'a mut crate::W<REG> {
407        self.variant(Ldra::None)
408    }
409    #[doc = "Rising edge of TIOA"]
410    #[inline(always)]
411    pub fn rising(self) -> &'a mut crate::W<REG> {
412        self.variant(Ldra::Rising)
413    }
414    #[doc = "Falling edge of TIOA"]
415    #[inline(always)]
416    pub fn falling(self) -> &'a mut crate::W<REG> {
417        self.variant(Ldra::Falling)
418    }
419    #[doc = "Each edge of TIOA"]
420    #[inline(always)]
421    pub fn edge(self) -> &'a mut crate::W<REG> {
422        self.variant(Ldra::Edge)
423    }
424}
425#[doc = "RB Loading Edge Selection\n\nValue on reset: 0"]
426#[derive(Clone, Copy, Debug, PartialEq, Eq)]
427#[repr(u8)]
428pub enum Ldrb {
429    #[doc = "0: None"]
430    None = 0,
431    #[doc = "1: Rising edge of TIOA"]
432    Rising = 1,
433    #[doc = "2: Falling edge of TIOA"]
434    Falling = 2,
435    #[doc = "3: Each edge of TIOA"]
436    Edge = 3,
437}
438impl From<Ldrb> for u8 {
439    #[inline(always)]
440    fn from(variant: Ldrb) -> Self {
441        variant as _
442    }
443}
444impl crate::FieldSpec for Ldrb {
445    type Ux = u8;
446}
447impl crate::IsEnum for Ldrb {}
448#[doc = "Field `LDRB` reader - RB Loading Edge Selection"]
449pub type LdrbR = crate::FieldReader<Ldrb>;
450impl LdrbR {
451    #[doc = "Get enumerated values variant"]
452    #[inline(always)]
453    pub const fn variant(&self) -> Ldrb {
454        match self.bits {
455            0 => Ldrb::None,
456            1 => Ldrb::Rising,
457            2 => Ldrb::Falling,
458            3 => Ldrb::Edge,
459            _ => unreachable!(),
460        }
461    }
462    #[doc = "None"]
463    #[inline(always)]
464    pub fn is_none(&self) -> bool {
465        *self == Ldrb::None
466    }
467    #[doc = "Rising edge of TIOA"]
468    #[inline(always)]
469    pub fn is_rising(&self) -> bool {
470        *self == Ldrb::Rising
471    }
472    #[doc = "Falling edge of TIOA"]
473    #[inline(always)]
474    pub fn is_falling(&self) -> bool {
475        *self == Ldrb::Falling
476    }
477    #[doc = "Each edge of TIOA"]
478    #[inline(always)]
479    pub fn is_edge(&self) -> bool {
480        *self == Ldrb::Edge
481    }
482}
483#[doc = "Field `LDRB` writer - RB Loading Edge Selection"]
484pub type LdrbW<'a, REG> = crate::FieldWriter<'a, REG, 2, Ldrb, crate::Safe>;
485impl<'a, REG> LdrbW<'a, REG>
486where
487    REG: crate::Writable + crate::RegisterSpec,
488    REG::Ux: From<u8>,
489{
490    #[doc = "None"]
491    #[inline(always)]
492    pub fn none(self) -> &'a mut crate::W<REG> {
493        self.variant(Ldrb::None)
494    }
495    #[doc = "Rising edge of TIOA"]
496    #[inline(always)]
497    pub fn rising(self) -> &'a mut crate::W<REG> {
498        self.variant(Ldrb::Rising)
499    }
500    #[doc = "Falling edge of TIOA"]
501    #[inline(always)]
502    pub fn falling(self) -> &'a mut crate::W<REG> {
503        self.variant(Ldrb::Falling)
504    }
505    #[doc = "Each edge of TIOA"]
506    #[inline(always)]
507    pub fn edge(self) -> &'a mut crate::W<REG> {
508        self.variant(Ldrb::Edge)
509    }
510}
511impl R {
512    #[doc = "Bits 0:2 - Clock Selection"]
513    #[inline(always)]
514    pub fn tcclks(&self) -> TcclksR {
515        TcclksR::new((self.bits & 7) as u8)
516    }
517    #[doc = "Bit 3 - Clock Invert"]
518    #[inline(always)]
519    pub fn clki(&self) -> ClkiR {
520        ClkiR::new(((self.bits >> 3) & 1) != 0)
521    }
522    #[doc = "Bits 4:5 - Burst Signal Selection"]
523    #[inline(always)]
524    pub fn burst(&self) -> BurstR {
525        BurstR::new(((self.bits >> 4) & 3) as u8)
526    }
527    #[doc = "Bit 6 - Counter Clock Stopped with RB Loading"]
528    #[inline(always)]
529    pub fn ldbstop(&self) -> LdbstopR {
530        LdbstopR::new(((self.bits >> 6) & 1) != 0)
531    }
532    #[doc = "Bit 7 - Counter Clock Disable with RB Loading"]
533    #[inline(always)]
534    pub fn ldbdis(&self) -> LdbdisR {
535        LdbdisR::new(((self.bits >> 7) & 1) != 0)
536    }
537    #[doc = "Bits 8:9 - External Trigger Edge Selection"]
538    #[inline(always)]
539    pub fn etrgedg(&self) -> EtrgedgR {
540        EtrgedgR::new(((self.bits >> 8) & 3) as u8)
541    }
542    #[doc = "Bit 10 - TIOA or TIOB External Trigger Selection"]
543    #[inline(always)]
544    pub fn abetrg(&self) -> AbetrgR {
545        AbetrgR::new(((self.bits >> 10) & 1) != 0)
546    }
547    #[doc = "Bit 14 - RC Compare Trigger Enable"]
548    #[inline(always)]
549    pub fn cpctrg(&self) -> CpctrgR {
550        CpctrgR::new(((self.bits >> 14) & 1) != 0)
551    }
552    #[doc = "Bit 15 - Waveform Mode"]
553    #[inline(always)]
554    pub fn wave(&self) -> WaveR {
555        WaveR::new(((self.bits >> 15) & 1) != 0)
556    }
557    #[doc = "Bits 16:17 - RA Loading Edge Selection"]
558    #[inline(always)]
559    pub fn ldra(&self) -> LdraR {
560        LdraR::new(((self.bits >> 16) & 3) as u8)
561    }
562    #[doc = "Bits 18:19 - RB Loading Edge Selection"]
563    #[inline(always)]
564    pub fn ldrb(&self) -> LdrbR {
565        LdrbR::new(((self.bits >> 18) & 3) as u8)
566    }
567}
568impl W {
569    #[doc = "Bits 0:2 - Clock Selection"]
570    #[inline(always)]
571    #[must_use]
572    pub fn tcclks(&mut self) -> TcclksW<Cmr0Spec> {
573        TcclksW::new(self, 0)
574    }
575    #[doc = "Bit 3 - Clock Invert"]
576    #[inline(always)]
577    #[must_use]
578    pub fn clki(&mut self) -> ClkiW<Cmr0Spec> {
579        ClkiW::new(self, 3)
580    }
581    #[doc = "Bits 4:5 - Burst Signal Selection"]
582    #[inline(always)]
583    #[must_use]
584    pub fn burst(&mut self) -> BurstW<Cmr0Spec> {
585        BurstW::new(self, 4)
586    }
587    #[doc = "Bit 6 - Counter Clock Stopped with RB Loading"]
588    #[inline(always)]
589    #[must_use]
590    pub fn ldbstop(&mut self) -> LdbstopW<Cmr0Spec> {
591        LdbstopW::new(self, 6)
592    }
593    #[doc = "Bit 7 - Counter Clock Disable with RB Loading"]
594    #[inline(always)]
595    #[must_use]
596    pub fn ldbdis(&mut self) -> LdbdisW<Cmr0Spec> {
597        LdbdisW::new(self, 7)
598    }
599    #[doc = "Bits 8:9 - External Trigger Edge Selection"]
600    #[inline(always)]
601    #[must_use]
602    pub fn etrgedg(&mut self) -> EtrgedgW<Cmr0Spec> {
603        EtrgedgW::new(self, 8)
604    }
605    #[doc = "Bit 10 - TIOA or TIOB External Trigger Selection"]
606    #[inline(always)]
607    #[must_use]
608    pub fn abetrg(&mut self) -> AbetrgW<Cmr0Spec> {
609        AbetrgW::new(self, 10)
610    }
611    #[doc = "Bit 14 - RC Compare Trigger Enable"]
612    #[inline(always)]
613    #[must_use]
614    pub fn cpctrg(&mut self) -> CpctrgW<Cmr0Spec> {
615        CpctrgW::new(self, 14)
616    }
617    #[doc = "Bit 15 - Waveform Mode"]
618    #[inline(always)]
619    #[must_use]
620    pub fn wave(&mut self) -> WaveW<Cmr0Spec> {
621        WaveW::new(self, 15)
622    }
623    #[doc = "Bits 16:17 - RA Loading Edge Selection"]
624    #[inline(always)]
625    #[must_use]
626    pub fn ldra(&mut self) -> LdraW<Cmr0Spec> {
627        LdraW::new(self, 16)
628    }
629    #[doc = "Bits 18:19 - RB Loading Edge Selection"]
630    #[inline(always)]
631    #[must_use]
632    pub fn ldrb(&mut self) -> LdrbW<Cmr0Spec> {
633        LdrbW::new(self, 18)
634    }
635}
636#[doc = "Channel Mode Register (channel = 0)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmr0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmr0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
637pub struct Cmr0Spec;
638impl crate::RegisterSpec for Cmr0Spec {
639    type Ux = u32;
640}
641#[doc = "`read()` method returns [`cmr0::R`](R) reader structure"]
642impl crate::Readable for Cmr0Spec {}
643#[doc = "`write(|w| ..)` method takes [`cmr0::W`](W) writer structure"]
644impl crate::Writable for Cmr0Spec {
645    type Safety = crate::Unsafe;
646    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
647    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
648}
649#[doc = "`reset()` method sets CMR0 to value 0"]
650impl crate::Resettable for Cmr0Spec {
651    const RESET_VALUE: u32 = 0;
652}
atsam3n1c/tc1/cmr0.rs

atsam3n1c/tc1/
cmr0.rs
