atsam3n0c/uart1/
idr.rs

1#[doc = "Register `IDR` writer"]
2pub type W = crate::W<IdrSpec>;
3#[doc = "Field `RXRDY` writer - Disable RXRDY Interrupt"]
4pub type RxrdyW<'a, REG> = crate::BitWriter<'a, REG>;
5#[doc = "Field `TXRDY` writer - Disable TXRDY Interrupt"]
6pub type TxrdyW<'a, REG> = crate::BitWriter<'a, REG>;
7#[doc = "Field `ENDRX` writer - Disable End of Receive Transfer Interrupt"]
8pub type EndrxW<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `ENDTX` writer - Disable End of Transmit Interrupt"]
10pub type EndtxW<'a, REG> = crate::BitWriter<'a, REG>;
11#[doc = "Field `OVRE` writer - Disable Overrun Error Interrupt"]
12pub type OvreW<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `FRAME` writer - Disable Framing Error Interrupt"]
14pub type FrameW<'a, REG> = crate::BitWriter<'a, REG>;
15#[doc = "Field `PARE` writer - Disable Parity Error Interrupt"]
16pub type PareW<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `TXEMPTY` writer - Disable TXEMPTY Interrupt"]
18pub type TxemptyW<'a, REG> = crate::BitWriter<'a, REG>;
19#[doc = "Field `TXBUFE` writer - Disable Buffer Empty Interrupt"]
20pub type TxbufeW<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `RXBUFF` writer - Disable Buffer Full Interrupt"]
22pub type RxbuffW<'a, REG> = crate::BitWriter<'a, REG>;
23impl W {
24    #[doc = "Bit 0 - Disable RXRDY Interrupt"]
25    #[inline(always)]
26    #[must_use]
27    pub fn rxrdy(&mut self) -> RxrdyW<IdrSpec> {
28        RxrdyW::new(self, 0)
29    }
30    #[doc = "Bit 1 - Disable TXRDY Interrupt"]
31    #[inline(always)]
32    #[must_use]
33    pub fn txrdy(&mut self) -> TxrdyW<IdrSpec> {
34        TxrdyW::new(self, 1)
35    }
36    #[doc = "Bit 3 - Disable End of Receive Transfer Interrupt"]
37    #[inline(always)]
38    #[must_use]
39    pub fn endrx(&mut self) -> EndrxW<IdrSpec> {
40        EndrxW::new(self, 3)
41    }
42    #[doc = "Bit 4 - Disable End of Transmit Interrupt"]
43    #[inline(always)]
44    #[must_use]
45    pub fn endtx(&mut self) -> EndtxW<IdrSpec> {
46        EndtxW::new(self, 4)
47    }
48    #[doc = "Bit 5 - Disable Overrun Error Interrupt"]
49    #[inline(always)]
50    #[must_use]
51    pub fn ovre(&mut self) -> OvreW<IdrSpec> {
52        OvreW::new(self, 5)
53    }
54    #[doc = "Bit 6 - Disable Framing Error Interrupt"]
55    #[inline(always)]
56    #[must_use]
57    pub fn frame(&mut self) -> FrameW<IdrSpec> {
58        FrameW::new(self, 6)
59    }
60    #[doc = "Bit 7 - Disable Parity Error Interrupt"]
61    #[inline(always)]
62    #[must_use]
63    pub fn pare(&mut self) -> PareW<IdrSpec> {
64        PareW::new(self, 7)
65    }
66    #[doc = "Bit 9 - Disable TXEMPTY Interrupt"]
67    #[inline(always)]
68    #[must_use]
69    pub fn txempty(&mut self) -> TxemptyW<IdrSpec> {
70        TxemptyW::new(self, 9)
71    }
72    #[doc = "Bit 11 - Disable Buffer Empty Interrupt"]
73    #[inline(always)]
74    #[must_use]
75    pub fn txbufe(&mut self) -> TxbufeW<IdrSpec> {
76        TxbufeW::new(self, 11)
77    }
78    #[doc = "Bit 12 - Disable Buffer Full Interrupt"]
79    #[inline(always)]
80    #[must_use]
81    pub fn rxbuff(&mut self) -> RxbuffW<IdrSpec> {
82        RxbuffW::new(self, 12)
83    }
84}
85#[doc = "Interrupt Disable Register\n\nYou can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`idr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
86pub struct IdrSpec;
87impl crate::RegisterSpec for IdrSpec {
88    type Ux = u32;
89}
90#[doc = "`write(|w| ..)` method takes [`idr::W`](W) writer structure"]
91impl crate::Writable for IdrSpec {
92    type Safety = crate::Unsafe;
93    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
94    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
95}
atsam3n0c/uart1/idr.rs

atsam3n0c/uart1/
idr.rs
