#[doc = "Register `IDR_SPI_MODE` writer"]
pub type W = crate::W<SpiModeIdrSpiModeSpec>;
#[doc = "Field `RXRDY` writer - RXRDY Interrupt Disable"]
pub type RxrdyW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TXRDY` writer - TXRDY Interrupt Disable"]
pub type TxrdyW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OVRE` writer - Overrun Error Interrupt Disable"]
pub type OvreW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TXEMPTY` writer - TXEMPTY Interrupt Disable"]
pub type TxemptyW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UNRE` writer - SPI Underrun Error Interrupt Disable"]
pub type UnreW<'a, REG> = crate::BitWriter<'a, REG>;
impl W {
#[doc = "Bit 0 - RXRDY Interrupt Disable"]
#[inline(always)]
#[must_use]
pub fn rxrdy(&mut self) -> RxrdyW<SpiModeIdrSpiModeSpec> {
RxrdyW::new(self, 0)
}
#[doc = "Bit 1 - TXRDY Interrupt Disable"]
#[inline(always)]
#[must_use]
pub fn txrdy(&mut self) -> TxrdyW<SpiModeIdrSpiModeSpec> {
TxrdyW::new(self, 1)
}
#[doc = "Bit 5 - Overrun Error Interrupt Disable"]
#[inline(always)]
#[must_use]
pub fn ovre(&mut self) -> OvreW<SpiModeIdrSpiModeSpec> {
OvreW::new(self, 5)
}
#[doc = "Bit 9 - TXEMPTY Interrupt Disable"]
#[inline(always)]
#[must_use]
pub fn txempty(&mut self) -> TxemptyW<SpiModeIdrSpiModeSpec> {
TxemptyW::new(self, 9)
}
#[doc = "Bit 10 - SPI Underrun Error Interrupt Disable"]
#[inline(always)]
#[must_use]
pub fn unre(&mut self) -> UnreW<SpiModeIdrSpiModeSpec> {
UnreW::new(self, 10)
}
}
#[doc = "Interrupt Disable Register\n\nYou can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mode_idr_spi_mode::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SpiModeIdrSpiModeSpec;
impl crate::RegisterSpec for SpiModeIdrSpiModeSpec {
type Ux = u32;
}
#[doc = "`write(|w| ..)` method takes [`spi_mode_idr_spi_mode::W`](W) writer structure"]
impl crate::Writable for SpiModeIdrSpiModeSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}