1#[doc = "Register `CMR0` reader"]
2pub type R = crate::R<Cmr0Spec>;
3#[doc = "Register `CMR0` writer"]
4pub type W = crate::W<Cmr0Spec>;
5#[doc = "Channel Pre-scaler\n\nValue on reset: 0"]
6#[derive(Clone, Copy, Debug, PartialEq, Eq)]
7#[repr(u8)]
8pub enum Cpre {
9 #[doc = "0: Master Clock"]
10 Mck = 0,
11 #[doc = "1: Master Clock divided by 2"]
12 Mckdiv2 = 1,
13 #[doc = "2: Master Clock divided by 4"]
14 Mckdiv4 = 2,
15 #[doc = "3: Master Clock divided by 8"]
16 Mckdiv8 = 3,
17 #[doc = "4: Master Clock divided by 16"]
18 Mckdiv16 = 4,
19 #[doc = "5: Master Clock divided by 32"]
20 Mckdiv32 = 5,
21 #[doc = "6: Master Clock divided by 64"]
22 Mckdiv64 = 6,
23 #[doc = "7: Master Clock divided by 128"]
24 Mckdiv128 = 7,
25 #[doc = "8: Master Clock divided by 256"]
26 Mckdiv256 = 8,
27 #[doc = "9: Master Clock divided by 512"]
28 Mckdiv512 = 9,
29 #[doc = "10: Master Clock divided by 1024"]
30 Mckdiv1024 = 10,
31 #[doc = "11: Clock A"]
32 Clka = 11,
33 #[doc = "12: Clock B"]
34 Clkb = 12,
35}
36impl From<Cpre> for u8 {
37 #[inline(always)]
38 fn from(variant: Cpre) -> Self {
39 variant as _
40 }
41}
42impl crate::FieldSpec for Cpre {
43 type Ux = u8;
44}
45impl crate::IsEnum for Cpre {}
46#[doc = "Field `CPRE` reader - Channel Pre-scaler"]
47pub type CpreR = crate::FieldReader<Cpre>;
48impl CpreR {
49 #[doc = "Get enumerated values variant"]
50 #[inline(always)]
51 pub const fn variant(&self) -> Option<Cpre> {
52 match self.bits {
53 0 => Some(Cpre::Mck),
54 1 => Some(Cpre::Mckdiv2),
55 2 => Some(Cpre::Mckdiv4),
56 3 => Some(Cpre::Mckdiv8),
57 4 => Some(Cpre::Mckdiv16),
58 5 => Some(Cpre::Mckdiv32),
59 6 => Some(Cpre::Mckdiv64),
60 7 => Some(Cpre::Mckdiv128),
61 8 => Some(Cpre::Mckdiv256),
62 9 => Some(Cpre::Mckdiv512),
63 10 => Some(Cpre::Mckdiv1024),
64 11 => Some(Cpre::Clka),
65 12 => Some(Cpre::Clkb),
66 _ => None,
67 }
68 }
69 #[doc = "Master Clock"]
70 #[inline(always)]
71 pub fn is_mck(&self) -> bool {
72 *self == Cpre::Mck
73 }
74 #[doc = "Master Clock divided by 2"]
75 #[inline(always)]
76 pub fn is_mckdiv2(&self) -> bool {
77 *self == Cpre::Mckdiv2
78 }
79 #[doc = "Master Clock divided by 4"]
80 #[inline(always)]
81 pub fn is_mckdiv4(&self) -> bool {
82 *self == Cpre::Mckdiv4
83 }
84 #[doc = "Master Clock divided by 8"]
85 #[inline(always)]
86 pub fn is_mckdiv8(&self) -> bool {
87 *self == Cpre::Mckdiv8
88 }
89 #[doc = "Master Clock divided by 16"]
90 #[inline(always)]
91 pub fn is_mckdiv16(&self) -> bool {
92 *self == Cpre::Mckdiv16
93 }
94 #[doc = "Master Clock divided by 32"]
95 #[inline(always)]
96 pub fn is_mckdiv32(&self) -> bool {
97 *self == Cpre::Mckdiv32
98 }
99 #[doc = "Master Clock divided by 64"]
100 #[inline(always)]
101 pub fn is_mckdiv64(&self) -> bool {
102 *self == Cpre::Mckdiv64
103 }
104 #[doc = "Master Clock divided by 128"]
105 #[inline(always)]
106 pub fn is_mckdiv128(&self) -> bool {
107 *self == Cpre::Mckdiv128
108 }
109 #[doc = "Master Clock divided by 256"]
110 #[inline(always)]
111 pub fn is_mckdiv256(&self) -> bool {
112 *self == Cpre::Mckdiv256
113 }
114 #[doc = "Master Clock divided by 512"]
115 #[inline(always)]
116 pub fn is_mckdiv512(&self) -> bool {
117 *self == Cpre::Mckdiv512
118 }
119 #[doc = "Master Clock divided by 1024"]
120 #[inline(always)]
121 pub fn is_mckdiv1024(&self) -> bool {
122 *self == Cpre::Mckdiv1024
123 }
124 #[doc = "Clock A"]
125 #[inline(always)]
126 pub fn is_clka(&self) -> bool {
127 *self == Cpre::Clka
128 }
129 #[doc = "Clock B"]
130 #[inline(always)]
131 pub fn is_clkb(&self) -> bool {
132 *self == Cpre::Clkb
133 }
134}
135#[doc = "Field `CPRE` writer - Channel Pre-scaler"]
136pub type CpreW<'a, REG> = crate::FieldWriter<'a, REG, 4, Cpre>;
137impl<'a, REG> CpreW<'a, REG>
138where
139 REG: crate::Writable + crate::RegisterSpec,
140 REG::Ux: From<u8>,
141{
142 #[doc = "Master Clock"]
143 #[inline(always)]
144 pub fn mck(self) -> &'a mut crate::W<REG> {
145 self.variant(Cpre::Mck)
146 }
147 #[doc = "Master Clock divided by 2"]
148 #[inline(always)]
149 pub fn mckdiv2(self) -> &'a mut crate::W<REG> {
150 self.variant(Cpre::Mckdiv2)
151 }
152 #[doc = "Master Clock divided by 4"]
153 #[inline(always)]
154 pub fn mckdiv4(self) -> &'a mut crate::W<REG> {
155 self.variant(Cpre::Mckdiv4)
156 }
157 #[doc = "Master Clock divided by 8"]
158 #[inline(always)]
159 pub fn mckdiv8(self) -> &'a mut crate::W<REG> {
160 self.variant(Cpre::Mckdiv8)
161 }
162 #[doc = "Master Clock divided by 16"]
163 #[inline(always)]
164 pub fn mckdiv16(self) -> &'a mut crate::W<REG> {
165 self.variant(Cpre::Mckdiv16)
166 }
167 #[doc = "Master Clock divided by 32"]
168 #[inline(always)]
169 pub fn mckdiv32(self) -> &'a mut crate::W<REG> {
170 self.variant(Cpre::Mckdiv32)
171 }
172 #[doc = "Master Clock divided by 64"]
173 #[inline(always)]
174 pub fn mckdiv64(self) -> &'a mut crate::W<REG> {
175 self.variant(Cpre::Mckdiv64)
176 }
177 #[doc = "Master Clock divided by 128"]
178 #[inline(always)]
179 pub fn mckdiv128(self) -> &'a mut crate::W<REG> {
180 self.variant(Cpre::Mckdiv128)
181 }
182 #[doc = "Master Clock divided by 256"]
183 #[inline(always)]
184 pub fn mckdiv256(self) -> &'a mut crate::W<REG> {
185 self.variant(Cpre::Mckdiv256)
186 }
187 #[doc = "Master Clock divided by 512"]
188 #[inline(always)]
189 pub fn mckdiv512(self) -> &'a mut crate::W<REG> {
190 self.variant(Cpre::Mckdiv512)
191 }
192 #[doc = "Master Clock divided by 1024"]
193 #[inline(always)]
194 pub fn mckdiv1024(self) -> &'a mut crate::W<REG> {
195 self.variant(Cpre::Mckdiv1024)
196 }
197 #[doc = "Clock A"]
198 #[inline(always)]
199 pub fn clka(self) -> &'a mut crate::W<REG> {
200 self.variant(Cpre::Clka)
201 }
202 #[doc = "Clock B"]
203 #[inline(always)]
204 pub fn clkb(self) -> &'a mut crate::W<REG> {
205 self.variant(Cpre::Clkb)
206 }
207}
208#[doc = "Field `CALG` reader - Channel Alignment"]
209pub type CalgR = crate::BitReader;
210#[doc = "Field `CALG` writer - Channel Alignment"]
211pub type CalgW<'a, REG> = crate::BitWriter<'a, REG>;
212#[doc = "Field `CPOL` reader - Channel Polarity"]
213pub type CpolR = crate::BitReader;
214#[doc = "Field `CPOL` writer - Channel Polarity"]
215pub type CpolW<'a, REG> = crate::BitWriter<'a, REG>;
216#[doc = "Field `CPD` reader - Channel Update Period"]
217pub type CpdR = crate::BitReader;
218#[doc = "Field `CPD` writer - Channel Update Period"]
219pub type CpdW<'a, REG> = crate::BitWriter<'a, REG>;
220impl R {
221 #[doc = "Bits 0:3 - Channel Pre-scaler"]
222 #[inline(always)]
223 pub fn cpre(&self) -> CpreR {
224 CpreR::new((self.bits & 0x0f) as u8)
225 }
226 #[doc = "Bit 8 - Channel Alignment"]
227 #[inline(always)]
228 pub fn calg(&self) -> CalgR {
229 CalgR::new(((self.bits >> 8) & 1) != 0)
230 }
231 #[doc = "Bit 9 - Channel Polarity"]
232 #[inline(always)]
233 pub fn cpol(&self) -> CpolR {
234 CpolR::new(((self.bits >> 9) & 1) != 0)
235 }
236 #[doc = "Bit 10 - Channel Update Period"]
237 #[inline(always)]
238 pub fn cpd(&self) -> CpdR {
239 CpdR::new(((self.bits >> 10) & 1) != 0)
240 }
241}
242impl W {
243 #[doc = "Bits 0:3 - Channel Pre-scaler"]
244 #[inline(always)]
245 #[must_use]
246 pub fn cpre(&mut self) -> CpreW<Cmr0Spec> {
247 CpreW::new(self, 0)
248 }
249 #[doc = "Bit 8 - Channel Alignment"]
250 #[inline(always)]
251 #[must_use]
252 pub fn calg(&mut self) -> CalgW<Cmr0Spec> {
253 CalgW::new(self, 8)
254 }
255 #[doc = "Bit 9 - Channel Polarity"]
256 #[inline(always)]
257 #[must_use]
258 pub fn cpol(&mut self) -> CpolW<Cmr0Spec> {
259 CpolW::new(self, 9)
260 }
261 #[doc = "Bit 10 - Channel Update Period"]
262 #[inline(always)]
263 #[must_use]
264 pub fn cpd(&mut self) -> CpdW<Cmr0Spec> {
265 CpdW::new(self, 10)
266 }
267}
268#[doc = "PWM Channel Mode Register (ch_num = 0)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmr0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmr0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
269pub struct Cmr0Spec;
270impl crate::RegisterSpec for Cmr0Spec {
271 type Ux = u32;
272}
273#[doc = "`read()` method returns [`cmr0::R`](R) reader structure"]
274impl crate::Readable for Cmr0Spec {}
275#[doc = "`write(|w| ..)` method takes [`cmr0::W`](W) writer structure"]
276impl crate::Writable for Cmr0Spec {
277 type Safety = crate::Unsafe;
278 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
279 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
280}
281#[doc = "`reset()` method sets CMR0 to value 0"]
282impl crate::Resettable for Cmr0Spec {
283 const RESET_VALUE: u32 = 0;
284}