atsam3a4c/hsmci/
dma.rs

1#[doc = "Register `DMA` reader"]
2pub type R = crate::R<DmaSpec>;
3#[doc = "Register `DMA` writer"]
4pub type W = crate::W<DmaSpec>;
5#[doc = "Field `OFFSET` reader - DMA Write Buffer Offset"]
6pub type OffsetR = crate::FieldReader;
7#[doc = "Field `OFFSET` writer - DMA Write Buffer Offset"]
8pub type OffsetW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
9#[doc = "DMA Channel Read and Write Chunk Size\n\nValue on reset: 0"]
10#[derive(Clone, Copy, Debug, PartialEq, Eq)]
11pub enum Chksize {
12    #[doc = "0: 1 data available"]
13    _1 = 0,
14    #[doc = "1: 4 data available"]
15    _4 = 1,
16}
17impl From<Chksize> for bool {
18    #[inline(always)]
19    fn from(variant: Chksize) -> Self {
20        variant as u8 != 0
21    }
22}
23#[doc = "Field `CHKSIZE` reader - DMA Channel Read and Write Chunk Size"]
24pub type ChksizeR = crate::BitReader<Chksize>;
25impl ChksizeR {
26    #[doc = "Get enumerated values variant"]
27    #[inline(always)]
28    pub const fn variant(&self) -> Chksize {
29        match self.bits {
30            false => Chksize::_1,
31            true => Chksize::_4,
32        }
33    }
34    #[doc = "1 data available"]
35    #[inline(always)]
36    pub fn is_1(&self) -> bool {
37        *self == Chksize::_1
38    }
39    #[doc = "4 data available"]
40    #[inline(always)]
41    pub fn is_4(&self) -> bool {
42        *self == Chksize::_4
43    }
44}
45#[doc = "Field `CHKSIZE` writer - DMA Channel Read and Write Chunk Size"]
46pub type ChksizeW<'a, REG> = crate::BitWriter<'a, REG, Chksize>;
47impl<'a, REG> ChksizeW<'a, REG>
48where
49    REG: crate::Writable + crate::RegisterSpec,
50{
51    #[doc = "1 data available"]
52    #[inline(always)]
53    pub fn _1(self) -> &'a mut crate::W<REG> {
54        self.variant(Chksize::_1)
55    }
56    #[doc = "4 data available"]
57    #[inline(always)]
58    pub fn _4(self) -> &'a mut crate::W<REG> {
59        self.variant(Chksize::_4)
60    }
61}
62#[doc = "Field `DMAEN` reader - DMA Hardware Handshaking Enable"]
63pub type DmaenR = crate::BitReader;
64#[doc = "Field `DMAEN` writer - DMA Hardware Handshaking Enable"]
65pub type DmaenW<'a, REG> = crate::BitWriter<'a, REG>;
66#[doc = "Field `ROPT` reader - Read Optimization with padding"]
67pub type RoptR = crate::BitReader;
68#[doc = "Field `ROPT` writer - Read Optimization with padding"]
69pub type RoptW<'a, REG> = crate::BitWriter<'a, REG>;
70impl R {
71    #[doc = "Bits 0:1 - DMA Write Buffer Offset"]
72    #[inline(always)]
73    pub fn offset(&self) -> OffsetR {
74        OffsetR::new((self.bits & 3) as u8)
75    }
76    #[doc = "Bit 4 - DMA Channel Read and Write Chunk Size"]
77    #[inline(always)]
78    pub fn chksize(&self) -> ChksizeR {
79        ChksizeR::new(((self.bits >> 4) & 1) != 0)
80    }
81    #[doc = "Bit 8 - DMA Hardware Handshaking Enable"]
82    #[inline(always)]
83    pub fn dmaen(&self) -> DmaenR {
84        DmaenR::new(((self.bits >> 8) & 1) != 0)
85    }
86    #[doc = "Bit 12 - Read Optimization with padding"]
87    #[inline(always)]
88    pub fn ropt(&self) -> RoptR {
89        RoptR::new(((self.bits >> 12) & 1) != 0)
90    }
91}
92impl W {
93    #[doc = "Bits 0:1 - DMA Write Buffer Offset"]
94    #[inline(always)]
95    #[must_use]
96    pub fn offset(&mut self) -> OffsetW<DmaSpec> {
97        OffsetW::new(self, 0)
98    }
99    #[doc = "Bit 4 - DMA Channel Read and Write Chunk Size"]
100    #[inline(always)]
101    #[must_use]
102    pub fn chksize(&mut self) -> ChksizeW<DmaSpec> {
103        ChksizeW::new(self, 4)
104    }
105    #[doc = "Bit 8 - DMA Hardware Handshaking Enable"]
106    #[inline(always)]
107    #[must_use]
108    pub fn dmaen(&mut self) -> DmaenW<DmaSpec> {
109        DmaenW::new(self, 8)
110    }
111    #[doc = "Bit 12 - Read Optimization with padding"]
112    #[inline(always)]
113    #[must_use]
114    pub fn ropt(&mut self) -> RoptW<DmaSpec> {
115        RoptW::new(self, 12)
116    }
117}
118#[doc = "DMA Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
119pub struct DmaSpec;
120impl crate::RegisterSpec for DmaSpec {
121    type Ux = u32;
122}
123#[doc = "`read()` method returns [`dma::R`](R) reader structure"]
124impl crate::Readable for DmaSpec {}
125#[doc = "`write(|w| ..)` method takes [`dma::W`](W) writer structure"]
126impl crate::Writable for DmaSpec {
127    type Safety = crate::Unsafe;
128    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
129    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
130}
131#[doc = "`reset()` method sets DMA to value 0"]
132impl crate::Resettable for DmaSpec {
133    const RESET_VALUE: u32 = 0;
134}
atsam3a4c/hsmci/dma.rs

atsam3a4c/hsmci/
dma.rs
