atomic-maybe-uninit 0.2.4

Atomic operations on potentially uninitialized integers.
Documentation 
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# atomic-maybe-uninit

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Atomic operations on potentially uninitialized integers.

## Motivation

Copying types containing uninitialized bytes (e.g., padding), via the standard library's atomic types is [undefined behavior because the copy goes through integers][undefined-behavior].

This crate provides a way to soundly perform such operations.

## Platform Support

Currently, x86, x86_64, ARM (v7+), AArch64, RISC-V, MIPS32r2, and MIPS64r2 are supported.

| target_arch     | primitives                                          | [load]/[store] | [swap] |
| --------------- | --------------------------------------------------- |:--------------:|:------:|
| x86             | isize,usize,i8,u8,i16,u16,i32,u32                   | ✓              | ✓      |
| x86_64          | isize,usize,i8,u8,i16,u16,i32,u32,i64,u64           | ✓              | ✓      |
| arm (v7+)       | isize,usize,i8,u8,i16,u16,i32,u32                   | ✓              | ✓      |
| arm (v7-a)      | i64,u64                                             | ✓              | ✓      |
| aarch64         | isize,usize,i8,u8,i16,u16,i32,u32,i64,u64,i128,u128 | ✓              | ✓\[1]  |
| riscv32         | isize,usize,i32,u32                                 | ✓              | ✓\[2]  |
| riscv32         | i8,u8,i16,u16                                       | ✓              |        |
| riscv64         | isize,usize,i32,u32,i64,u64                         | ✓              | ✓\[2]  |
| riscv64         | i8,u8,i16,u16                                       | ✓              |        |
| mips \[3]       | isize,usize,i32,u32                                 | ✓              | ✓      |
| mips \[3]       | i8,u8,i16,u16                                       | ✓              |        |
| mips64 \[3]     | isize,usize,i32,u32,i64,u64                         | ✓              | ✓      |
| mips64 \[3]     | i8,u8,i16,u16                                       | ✓              |        |

\[1] If the `lse` target feature is enabled at compile-time, more efficient instructions are used instead of increasing the CPU requirement to ARMv8.1+.<br>
\[2] RISC-V's atomic swap is not available on targets without the A (or G) extension such as riscv32i-unknown-none-elf, riscv32imc-unknown-none-elf, etc.<br>
\[3] Requires nightly due to `#![feature(asm_experimental_arch)]`.<br>

Feel free to submit an issue if your target is not supported yet.

## Related Projects

- [portable-atomic]: Portable atomic types including support for 128-bit atomics, atomic float, etc.
- [atomic-memcpy]: Byte-wise atomic memcpy.

[load]: https://docs.rs/atomic-maybe-uninit/latest/atomic_maybe_uninit/struct.AtomicMaybeUninit.html#method.load
[store]: https://docs.rs/atomic-maybe-uninit/latest/atomic_maybe_uninit/struct.AtomicMaybeUninit.html#method.store
[swap]: https://docs.rs/atomic-maybe-uninit/latest/atomic_maybe_uninit/struct.AtomicMaybeUninit.html#method.swap
[atomic-memcpy]: https://github.com/taiki-e/atomic-memcpy
[portable-atomic]: https://github.com/taiki-e/portable-atomic
[undefined-behavior]: https://doc.rust-lang.org/reference/behavior-considered-undefined.html

## License

Licensed under either of [Apache License, Version 2.0](LICENSE-APACHE) or
[MIT license](LICENSE-MIT) at your option.

Unless you explicitly state otherwise, any contribution intentionally submitted
for inclusion in the work by you, as defined in the Apache-2.0 license, shall
be dual licensed as above, without any additional terms or conditions.