Enum X86Feature 

#[repr(u8)]
pub enum X86Feature {
    None = 0,
    MT = 1,
    NX = 2,
    ADX = 3,
    ALTMOVCR8 = 4,
    APX_F = 5,
    BMI = 6,
    BMI2 = 7,
    CET_IBT = 8,
    CET_SS = 9,
    CET_SSS = 10,
    CLDEMOTE = 11,
    CLFLUSH = 12,
    CLFLUSHOPT = 13,
    CLWB = 14,
    CLZERO = 15,
    CMOV = 16,
    CMPCCXADD = 17,
    CMPXCHG16B = 18,
    CMPXCHG8B = 19,
    ENCLV = 20,
    ENQCMD = 21,
    ERMS = 22,
    FSGSBASE = 23,
    FSRM = 24,
    FSRC = 25,
    FSRS = 26,
    FXSR = 27,
    FXSROPT = 28,
    FZRM = 29,
    HRESET = 30,
    I486 = 31,
    INVLPGB = 32,
    LAHFSAHF = 33,
    LAM = 34,
    LWP = 35,
    LZCNT = 36,
    MCOMMIT = 37,
    MONITOR = 38,
    MONITORX = 39,
    MOVBE = 40,
    MOVDIR64B = 41,
    MOVDIRI = 42,
    MOVRS = 43,
    MPX = 44,
    MSR = 45,
    MSRLIST = 46,
    MSR_IMM = 47,
    MSSE = 48,
    OSXSAVE = 49,
    OSPKE = 50,
    PCONFIG = 51,
    POPCNT = 52,
    PREFETCHI = 53,
    PREFETCHW = 54,
    PREFETCHWT1 = 55,
    PTWRITE = 56,
    RAO_INT = 57,
    RMPQUERY = 58,
    RDPID = 59,
    RDPRU = 60,
    RDRAND = 61,
    RDSEED = 62,
    RDTSC = 63,
    RDTSCP = 64,
    RTM = 65,
    SEAM = 66,
    SERIALIZE = 67,
    SEV = 68,
    SEV_ES = 69,
    SEV_SNP = 70,
    SKINIT = 71,
    SMAP = 72,
    SME = 73,
    SMEP = 74,
    SMX = 75,
    SVM = 76,
    TBM = 77,
    TSE = 78,
    TSXLDTRK = 79,
    UINTR = 80,
    VMX = 81,
    WAITPKG = 82,
    WBNOINVD = 83,
    WRMSRNS = 84,
    XSAVE = 85,
    XSAVEC = 86,
    XSAVEOPT = 87,
    XSAVES = 88,
    FPU = 89,
    MMX = 90,
    MMX2 = 91,
    _3DNOW = 92,
    _3DNOW2 = 93,
    GEODE = 94,
    SSE = 95,
    SSE2 = 96,
    SSE3 = 97,
    SSSE3 = 98,
    SSE4_1 = 99,
    SSE4_2 = 100,
    SSE4A = 101,
    PCLMULQDQ = 102,
    AVX = 103,
    AVX2 = 104,
    AVX_IFMA = 105,
    AVX_NE_CONVERT = 106,
    AVX_VNNI = 107,
    AVX_VNNI_INT16 = 108,
    AVX_VNNI_INT8 = 109,
    F16C = 110,
    FMA = 111,
    FMA4 = 112,
    XOP = 113,
    AVX512_BF16 = 114,
    AVX512_BITALG = 115,
    AVX512_BW = 116,
    AVX512_CD = 117,
    AVX512_DQ = 118,
    AVX512_F = 119,
    AVX512_FP16 = 120,
    AVX512_IFMA = 121,
    AVX512_VBMI = 122,
    AVX512_VBMI2 = 123,
    AVX512_VL = 124,
    AVX512_VNNI = 125,
    AVX512_VP2INTERSECT = 126,
    AVX512_VPOPCNTDQ = 127,
    AESNI = 128,
    GFNI = 129,
    SHA = 130,
    SHA512 = 131,
    SM3 = 132,
    SM4 = 133,
    VAES = 134,
    VPCLMULQDQ = 135,
    KL = 136,
    AESKLE = 137,
    AESKLEWIDE_KL = 138,
    AVX10_1 = 139,
    AVX10_2 = 140,
    AMX_AVX512 = 141,
    AMX_BF16 = 142,
    AMX_COMPLEX = 143,
    AMX_FP16 = 144,
    AMX_FP8 = 145,
    AMX_INT8 = 146,
    AMX_MOVRS = 147,
    AMX_TF32 = 148,
    AMX_TILE = 149,
    AMX_TRANSPOSE = 150,
}

X86 CPU feature identifiers (port of AsmJit’s CpuFeatures::X86).

Variants

None = 0

No feature (never set, used internally).

MT = 1

CPU has multi-threading capabilities.

NX = 2

CPU has Not-Execute-Bit aka DEP (data-execution prevention).

ADX = 3

CPU has ADX (multi-precision add-carry instruction extensions).

ALTMOVCR8 = 4

CPU has LOCK MOV R<->CR0 (supports MOV R<->CR8 via LOCK MOV R<->CR0 in 32-bit mode) {AMD}.

APX_F = 5

CPU has APX_F (advanced performance extensions - 32 GP registers, REX2 prefix, …) {X86_64}.

BMI = 6

CPU has BMI (bit manipulation instructions #1).

BMI2 = 7

CPU has BMI2 (bit manipulation instructions #2).

CET_IBT = 8

CPU has CET-IBT (indirect branch tracking).

CET_SS = 9

CPU has CET-SS.

CET_SSS = 10

CPU has CET-SSS.

CLDEMOTE = 11

CPU has CLDEMOTE (cache line demote).

CLFLUSH = 12

CPU has CLFUSH (cache Line flush).

CLFLUSHOPT = 13

CPU has CLFUSHOPT (cache Line flush - optimized).

CLWB = 14

CPU has CLWB.

CLZERO = 15

CPU has CLZERO.

CMOV = 16

CPU has CMOV (CMOV and FCMOV instructions).

CMPCCXADD = 17

CPU has CMPCCXADD.

CMPXCHG16B = 18

CPU has CMPXCHG16B (compare-exchange 16 bytes) {X86_64}.

CMPXCHG8B = 19

CPU has CMPXCHG8B (compare-exchange 8 bytes).

ENCLV = 20

CPU has ENCLV.

ENQCMD = 21

CPU has ENQCMD (enqueue stores).

ERMS = 22

CPU has ERMS (enhanced REP MOVSB/STOSB).

FSGSBASE = 23

CPU has FSGSBASE.

FSRM = 24

CPU has FSRM (fast short REP MOVSB).

FSRC = 25

CPU has FSRC (fast short REP CMPSB|SCASB).

FSRS = 26

CPU has FSRS (fast short REP STOSB)

FXSR = 27

CPU has FXSR (FXSAVE/FXRSTOR instructions).

FXSROPT = 28

CPU has FXSROTP (FXSAVE/FXRSTOR is optimized).

FZRM = 29

CPU has FZRM (fast zero-length REP MOVSB).

HRESET = 30

CPU has HRESET.

I486 = 31

CPU has I486 features (I486+ support).

INVLPGB = 32

CPU has INVLPGB.

LAHFSAHF = 33

CPU has LAHF/SAHF (LAHF/SAHF in 64-bit mode) {X86_64}.

LAM = 34

CPU has LAM (linear address masking) {X86_64}.

LWP = 35

CPU has LWP (lightweight profiling) {AMD}.

LZCNT = 36

CPU has LZCNT (LZCNT instruction).

MCOMMIT = 37

CPU has MCOMMIT (MCOMMIT instruction).

MONITOR = 38

CPU has MONITOR (MONITOR/MWAIT instructions).

MONITORX = 39

CPU has MONITORX (MONITORX/MWAITX instructions).

MOVBE = 40

CPU has MOVBE (move with byte-order swap).

MOVDIR64B = 41

CPU has MOVDIR64B (move 64 bytes as direct store).

MOVDIRI = 42

CPU has MOVDIRI (move dword/qword as direct store).

MOVRS = 43

CPU has MOVRS (move from shared memory).

MPX = 44

CPU has MPX (memory protection extensions).

MSR = 45

CPU has MSR (RDMSR/WRMSR instructions).

MSRLIST = 46

CPU has MSRLIST.

MSR_IMM = 47

CPU has MSR_IMM (RDMSR/WRMSR immediate encoding).

MSSE = 48

CPU has MSSE (misaligned SSE support).

OSXSAVE = 49

CPU has OSXSAVE (XSAVE enabled by OS).

OSPKE = 50

CPU has OSPKE (PKE enabled by OS).

PCONFIG = 51

CPU has PCONFIG (PCONFIG instruction).

POPCNT = 52

CPU has POPCNT (POPCNT instruction).

PREFETCHI = 53

CPU has PREFETCHI.

PREFETCHW = 54

CPU has PREFETCHW.

PREFETCHWT1 = 55

CPU has PREFETCHWT1.

PTWRITE = 56

CPU has PTWRITE.

RAO_INT = 57

CPU has RAO_INT (AADD, AAND, AOR, AXOR instructions).

RMPQUERY = 58

CPU has RMPQUERY (RMPQUERY instruction).

RDPID = 59

CPU has RDPID (RDPID instruction).

RDPRU = 60

CPU has RDPRU (RDPRU instruction).

RDRAND = 61

CPU has RDRAND (RDRAND instruction).

RDSEED = 62

CPU has RDSEED (RDSEED instruction).

RDTSC = 63

CPU has RDTSC.

RDTSCP = 64

CPU has RDTSCP.

RTM = 65

CPU has RTM (RTM instructions - deprecated).

SEAM = 66

CPU has SEAM.

SERIALIZE = 67

CPU has SERIALIZE.

SEV = 68

CPU has SEV (secure encrypted virtualization).

SEV_ES = 69

CPU has SEV_ES (SEV encrypted state).

SEV_SNP = 70

CPU has SEV_SNP (SEV secure nested paging).

SKINIT = 71

CPU has SKINIT (SKINIT/STGI instructions) {AMD}.

SMAP = 72

CPU has SMAP (supervisor-mode access prevention).

SME = 73

CPU has SME (secure memory encryption).

SMEP = 74

CPU has SMEP (supervisor-mode execution prevention).

SMX = 75

CPU has SMX (safer mode extensions).

SVM = 76

CPU has SVM (virtualization) {AMD}.

TBM = 77

CPU has TBM (trailing bit manipulation) {AMD}.

TSE = 78

CPU has TSE.

TSXLDTRK = 79

CPU has TSXLDTRK.

UINTR = 80

CPU has UINTR (user interrupts).

VMX = 81

CPU has VMX (virtualization) {INTEL}.

WAITPKG = 82

CPU has WAITPKG (UMONITOR, UMWAIT, TPAUSE).

WBNOINVD = 83

CPU has WBNOINVD.

WRMSRNS = 84

CPU has WRMSRNS.

XSAVE = 85

CPU has XSAVE.

XSAVEC = 86

CPU has XSAVEC.

XSAVEOPT = 87

CPU has XSAVEOPT.

XSAVES = 88

CPU has XSAVES.

FPU = 89

CPU has FPU (FPU support).

MMX = 90

CPU has MMX (MMX base instructions) (deprecated).

MMX2 = 91

CPU has MMX2 (MMX2 extensions or initial SSE extensions) (deprecated).

_3DNOW = 92

CPU has 3DNOW (3DNOW base instructions) {AMD} (deprecated).

_3DNOW2 = 93

CPU has 3DNOW2 (enhanced 3DNOW) {AMD} (deprecated).

GEODE = 94

CPU has GEODE extensions (GEODE 3DNOW additions) (deprecated).

SSE = 95

CPU has SSE (SSE instructions).

SSE2 = 96

CPU has SSE2 (SSE2 instructions).

SSE3 = 97

CPU has SSE3 (SSE3 instructions).

SSSE3 = 98

CPU has SSSE3 (SSSE3 instructions).

SSE4_1 = 99

CPU has SSE4.1 (SSE4.1 instructions).

SSE4_2 = 100

CPU has SSE4.2 (SSE4.2 instructions).

SSE4A = 101

CPU has SSE4A (SSE4.A instructions) {AMD} (deprecated).

PCLMULQDQ = 102

CPU has PCLMULQDQ (packed carry-less multiplication).

AVX = 103

CPU has AVX (advanced vector extensions).

AVX2 = 104

CPU has AVX2 (advanced vector extensions 2).

AVX_IFMA = 105

CPU has AVX_IFMA (AVX/VEX encoding of vpmadd52huq/vpmadd52luq).

AVX_NE_CONVERT = 106

CPU has AVX_NE_CONVERT.

AVX_VNNI = 107

CPU has AVX_VNNI (AVX/VEX encoding of vpdpbusd/vpdpbusds/vpdpwssd/vpdpwssds).

AVX_VNNI_INT16 = 108

CPU has AVX_VNNI_INT16.

AVX_VNNI_INT8 = 109

CPU has AVX_VNNI_INT8.

F16C = 110

CPU has F16C (AVX FP16 conversion instructions).

FMA = 111

CPU has FMA (AVX fused-multiply-add - 3 operand form).

FMA4 = 112

CPU has FMA4 (AVX fused-multiply-add - 4 operand form) (deprecated).

XOP = 113

CPU has XOP (XOP instructions) {AMD} (deprecated).

AVX512_BF16 = 114

CPU has AVX512_BF16 (AVX512 BFLOAT16 support instructions).

AVX512_BITALG = 115

CPU has AVX512_BITALG (AVX512 VPOPCNT[B|W] and VPSHUFBITQMB instructions).

AVX512_BW = 116

CPU has AVX512_BW (AVX512 integer BYTE|WORD instructions).

AVX512_CD = 117

CPU has AVX512_CD (AVX512 conflict detection DWORD|QWORD instructions).

AVX512_DQ = 118

CPU has AVX512_DQ (AVX512 integer DWORD|QWORD instructions).

AVX512_F = 119

CPU has AVX512_F (AVX512 foundation).

AVX512_FP16 = 120

CPU has AVX512_FP16 (AVX512 FP16 instructions).

AVX512_IFMA = 121

CPU has AVX512_IFMA (AVX512 integer fused-multiply-add using 52-bit precision).

AVX512_VBMI = 122

CPU has AVX512_VBMI (AVX512 vector byte manipulation instructions).

AVX512_VBMI2 = 123

CPU has AVX512_VBMI2 (AVX512 vector byte manipulation instructions v2).

AVX512_VL = 124

CPU has AVX512_VL (AVX512 vector length extensions).

AVX512_VNNI = 125

CPU has AVX512_VNNI (AVX512 vector neural network instructions).

AVX512_VP2INTERSECT = 126

CPU has AVX512_VP2INTERSECT

AVX512_VPOPCNTDQ = 127

CPU has AVX512_VPOPCNTDQ (AVX512 VPOPCNT[D|Q] instructions).

AESNI = 128

CPU has AESNI (AES encode/decode instructions).

GFNI = 129

CPU has GFNI (galois field instructions).

SHA = 130

CPU has SHA (SHA-1 and SHA-256 instructions).

SHA512 = 131

CPU has SHA512 (SHA-512 instructions).

SM3 = 132

CPU has SM3 (SM3 hash extensions).

SM4 = 133

CPU has SM4 (SM4 cipher extensions).

VAES = 134

CPU has VAES (vector AES 256|512 bit support).

VPCLMULQDQ = 135

CPU has VPCLMULQDQ (vector PCLMULQDQ 256|512-bit support).

KL = 136

CPU has KL (Key Locker).

AESKLE = 137

CPU has AESKLE (AESKLE).

AESKLEWIDE_KL = 138

CPU has AESKLE+WIDEKL+KL (AESKLE & WIDEKL instructions and KL enabled)

AVX10_1 = 139

CPU has AVX10.1/512 (AVX10.1 with 512-bit vectors).

AVX10_2 = 140

CPU has AVX10.2/512 (AVX10.2 with 512-bit vectors).

AMX_AVX512 = 141

CPU has AMX_AVX512 (AMX-AVX512 instructions).

AMX_BF16 = 142

CPU has AMX_BF16 (AMX-BF16 instructions).

AMX_COMPLEX = 143

CPU has AMX_COMPLEX (AMX-COMPLEX instructions).

AMX_FP16 = 144

CPU has AMX_FP16 (AMX-FP16 instructions).

AMX_FP8 = 145

CPU has AMX_FP8 (AMX-FP8 instructions).

AMX_INT8 = 146

CPU has AMX_INT8 (AMX-INT8 instructions).

AMX_MOVRS = 147

CPU has AMX_MOVRS (AMX-MOVRS instructions).

AMX_TF32 = 148

CPU has AMX_TF32 (AMX-TF32 instructions).

AMX_TILE = 149

CPU has AMX_TILE (advanced matrix extensions).

AMX_TRANSPOSE = 150

CPU has AMX_TRANSPOSE (AMX-TRANSPOSE instructions).

Implementations

impl CpuFeature

pub const AVX512F: Self = Self::AVX512_F

pub const AVX512BW: Self = Self::AVX512_BW

pub const AVX512CD: Self = Self::AVX512_CD

pub const AVX512DQ: Self = Self::AVX512_DQ

pub const AVX512VL: Self = Self::AVX512_VL

Trait Implementations

impl Clone for CpuFeature

fn clone(&self) -> CpuFeature

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Copy for CpuFeature

impl Debug for CpuFeature

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Eq for CpuFeature

impl PartialEq for CpuFeature

fn eq(&self, other: &CpuFeature) -> bool

Equality operator ==.

fn ne(&self, other: &Rhs) -> bool

Inequality operator !=.

impl StructuralPartialEq for CpuFeature