asmkit-rs 0.5.0

//! RISC-V instruction info database: per-opcode effects.
//!
//! For every [`Opcode`] this records the operand read/write pattern (indexed into
//! [`RW_PATTERN_TABLE`]), the operand-class signature for debug asserts
//! ([`SIGNATURE_TABLE`]), the memory access kind and width, implicit fixed-register
//! effects ([`IMPLICIT_REG_TABLE`]), and implicit CSR flag effects
//! (`read_flags`/`write_flags`, `CpuRwFlags::RISCV_*` bits).
//!
//! Modeling notes:
//! - Public operand order comes only from the generator's reviewed declarative
//!   encoding-shape table; unknown shapes fail generation.
//! - The `csr` immediate operand of CSR instructions carries R/W bits describing
//!   the CSR access itself.
//! - Vector instructions with a `vm` field conservatively read v0 (vm=0 masking);
//!   reads/writes of vtype/vl/vxrm are not modeled (`CpuRwFlags` has no bits).
//! - `mem_width` is the access width in bytes; 0 means no memory access or a width
//!   that is not instruction-fixed (whole-register vector loads/stores).
//!
//! Automatically generated by parse_opcodes (meta/riscv.py). Do not edit by hand.
//! Derived from riscv-opcodes (BSD-3-Clause) and riscv-unified-db
//! (BSD-3-Clause-Clear); see meta/README.md for the input pins.
use crate::core::rwinfo::{CpuRwFlags, OpRwFlags};

use super::opcodes::Opcode;

/// RISC-V extension identifiers from the pinned riscv-opcodes input files.
#[derive(Clone, Copy, Debug, PartialEq, Eq, PartialOrd, Ord)]
#[repr(u8)]
pub enum CpuFeature {
    Rv32C,
    Rv32CF,
    Rv32DZfa,
    Rv32I,
    Rv32Zbb,
    Rv32Zbkb,
    Rv32Zbs,
    Rv32Zclsd,
    Rv32Zicntr,
    Rv32Zk,
    Rv32Zkn,
    Rv32Zknd,
    Rv32Zkne,
    Rv32Zknh,
    Rv32Zks,
    Rv64A,
    Rv64C,
    Rv64D,
    Rv64F,
    Rv64H,
    Rv64I,
    Rv64M,
    Rv64Q,
    Rv64QZfa,
    Rv64Zacas,
    Rv64Zba,
    Rv64Zbb,
    Rv64Zbkb,
    Rv64Zbs,
    Rv64Zcb,
    Rv64Zfh,
    Rv64Zk,
    Rv64Zkn,
    Rv64Zknd,
    Rv64Zkne,
    Rv64Zknh,
    Rv64Zks,
    RvA,
    RvC,
    RvCD,
    RvCZicfiss,
    RvCZihintntl,
    RvD,
    RvDZfa,
    RvDZfhmin,
    RvF,
    RvFZfa,
    RvH,
    RvI,
    RvM,
    RvQ,
    RvQZfa,
    RvQZfhmin,
    RvS,
    RvSdext,
    RvSmrnmi,
    RvSsctr,
    RvSvinval,
    RvSvinvalH,
    RvSystem,
    RvV,
    RvVAliases,
    RvZabha,
    RvZabhaZacas,
    RvZacas,
    RvZawrs,
    RvZba,
    RvZbb,
    RvZbc,
    RvZbkb,
    RvZbkc,
    RvZbkx,
    RvZbs,
    RvZcb,
    RvZcmop,
    RvZcmp,
    RvZcmt,
    RvZfbfmin,
    RvZfh,
    RvZfhZfa,
    RvZfhmin,
    RvZicbo,
    RvZicfilp,
    RvZicfiss,
    RvZicntr,
    RvZicond,
    RvZicsr,
    RvZifencei,
    RvZihintntl,
    RvZimop,
    RvZk,
    RvZkn,
    RvZknh,
    RvZks,
    RvZksed,
    RvZksh,
    RvZvbb,
    RvZvbc,
    RvZvfbfmin,
    RvZvfbfwma,
    RvZvkg,
    RvZvkn,
    RvZvkned,
    RvZvknha,
    RvZvknhb,
    RvZvks,
    RvZvksed,
    RvZvksh,
}

pub const CPU_FEATURE_COUNT: usize = 108;
pub const CPU_FEATURE_WORDS: usize = 2;
pub const CPU_FEATURE_NAMES: [&str; CPU_FEATURE_COUNT] = [
    "rv32_c",
    "rv32_c_f",
    "rv32_d_zfa",
    "rv32_i",
    "rv32_zbb",
    "rv32_zbkb",
    "rv32_zbs",
    "rv32_zclsd",
    "rv32_zicntr",
    "rv32_zk",
    "rv32_zkn",
    "rv32_zknd",
    "rv32_zkne",
    "rv32_zknh",
    "rv32_zks",
    "rv64_a",
    "rv64_c",
    "rv64_d",
    "rv64_f",
    "rv64_h",
    "rv64_i",
    "rv64_m",
    "rv64_q",
    "rv64_q_zfa",
    "rv64_zacas",
    "rv64_zba",
    "rv64_zbb",
    "rv64_zbkb",
    "rv64_zbs",
    "rv64_zcb",
    "rv64_zfh",
    "rv64_zk",
    "rv64_zkn",
    "rv64_zknd",
    "rv64_zkne",
    "rv64_zknh",
    "rv64_zks",
    "rv_a",
    "rv_c",
    "rv_c_d",
    "rv_c_zicfiss",
    "rv_c_zihintntl",
    "rv_d",
    "rv_d_zfa",
    "rv_d_zfhmin",
    "rv_f",
    "rv_f_zfa",
    "rv_h",
    "rv_i",
    "rv_m",
    "rv_q",
    "rv_q_zfa",
    "rv_q_zfhmin",
    "rv_s",
    "rv_sdext",
    "rv_smrnmi",
    "rv_ssctr",
    "rv_svinval",
    "rv_svinval_h",
    "rv_system",
    "rv_v",
    "rv_v_aliases",
    "rv_zabha",
    "rv_zabha_zacas",
    "rv_zacas",
    "rv_zawrs",
    "rv_zba",
    "rv_zbb",
    "rv_zbc",
    "rv_zbkb",
    "rv_zbkc",
    "rv_zbkx",
    "rv_zbs",
    "rv_zcb",
    "rv_zcmop",
    "rv_zcmp",
    "rv_zcmt",
    "rv_zfbfmin",
    "rv_zfh",
    "rv_zfh_zfa",
    "rv_zfhmin",
    "rv_zicbo",
    "rv_zicfilp",
    "rv_zicfiss",
    "rv_zicntr",
    "rv_zicond",
    "rv_zicsr",
    "rv_zifencei",
    "rv_zihintntl",
    "rv_zimop",
    "rv_zk",
    "rv_zkn",
    "rv_zknh",
    "rv_zks",
    "rv_zksed",
    "rv_zksh",
    "rv_zvbb",
    "rv_zvbc",
    "rv_zvfbfmin",
    "rv_zvfbfwma",
    "rv_zvkg",
    "rv_zvkn",
    "rv_zvkned",
    "rv_zvknha",
    "rv_zvknhb",
    "rv_zvks",
    "rv_zvksed",
    "rv_zvksh",
];

pub const ALL_CPU_FEATURES: [CpuFeature; CPU_FEATURE_COUNT] = [
    CpuFeature::Rv32C,
    CpuFeature::Rv32CF,
    CpuFeature::Rv32DZfa,
    CpuFeature::Rv32I,
    CpuFeature::Rv32Zbb,
    CpuFeature::Rv32Zbkb,
    CpuFeature::Rv32Zbs,
    CpuFeature::Rv32Zclsd,
    CpuFeature::Rv32Zicntr,
    CpuFeature::Rv32Zk,
    CpuFeature::Rv32Zkn,
    CpuFeature::Rv32Zknd,
    CpuFeature::Rv32Zkne,
    CpuFeature::Rv32Zknh,
    CpuFeature::Rv32Zks,
    CpuFeature::Rv64A,
    CpuFeature::Rv64C,
    CpuFeature::Rv64D,
    CpuFeature::Rv64F,
    CpuFeature::Rv64H,
    CpuFeature::Rv64I,
    CpuFeature::Rv64M,
    CpuFeature::Rv64Q,
    CpuFeature::Rv64QZfa,
    CpuFeature::Rv64Zacas,
    CpuFeature::Rv64Zba,
    CpuFeature::Rv64Zbb,
    CpuFeature::Rv64Zbkb,
    CpuFeature::Rv64Zbs,
    CpuFeature::Rv64Zcb,
    CpuFeature::Rv64Zfh,
    CpuFeature::Rv64Zk,
    CpuFeature::Rv64Zkn,
    CpuFeature::Rv64Zknd,
    CpuFeature::Rv64Zkne,
    CpuFeature::Rv64Zknh,
    CpuFeature::Rv64Zks,
    CpuFeature::RvA,
    CpuFeature::RvC,
    CpuFeature::RvCD,
    CpuFeature::RvCZicfiss,
    CpuFeature::RvCZihintntl,
    CpuFeature::RvD,
    CpuFeature::RvDZfa,
    CpuFeature::RvDZfhmin,
    CpuFeature::RvF,
    CpuFeature::RvFZfa,
    CpuFeature::RvH,
    CpuFeature::RvI,
    CpuFeature::RvM,
    CpuFeature::RvQ,
    CpuFeature::RvQZfa,
    CpuFeature::RvQZfhmin,
    CpuFeature::RvS,
    CpuFeature::RvSdext,
    CpuFeature::RvSmrnmi,
    CpuFeature::RvSsctr,
    CpuFeature::RvSvinval,
    CpuFeature::RvSvinvalH,
    CpuFeature::RvSystem,
    CpuFeature::RvV,
    CpuFeature::RvVAliases,
    CpuFeature::RvZabha,
    CpuFeature::RvZabhaZacas,
    CpuFeature::RvZacas,
    CpuFeature::RvZawrs,
    CpuFeature::RvZba,
    CpuFeature::RvZbb,
    CpuFeature::RvZbc,
    CpuFeature::RvZbkb,
    CpuFeature::RvZbkc,
    CpuFeature::RvZbkx,
    CpuFeature::RvZbs,
    CpuFeature::RvZcb,
    CpuFeature::RvZcmop,
    CpuFeature::RvZcmp,
    CpuFeature::RvZcmt,
    CpuFeature::RvZfbfmin,
    CpuFeature::RvZfh,
    CpuFeature::RvZfhZfa,
    CpuFeature::RvZfhmin,
    CpuFeature::RvZicbo,
    CpuFeature::RvZicfilp,
    CpuFeature::RvZicfiss,
    CpuFeature::RvZicntr,
    CpuFeature::RvZicond,
    CpuFeature::RvZicsr,
    CpuFeature::RvZifencei,
    CpuFeature::RvZihintntl,
    CpuFeature::RvZimop,
    CpuFeature::RvZk,
    CpuFeature::RvZkn,
    CpuFeature::RvZknh,
    CpuFeature::RvZks,
    CpuFeature::RvZksed,
    CpuFeature::RvZksh,
    CpuFeature::RvZvbb,
    CpuFeature::RvZvbc,
    CpuFeature::RvZvfbfmin,
    CpuFeature::RvZvfbfwma,
    CpuFeature::RvZvkg,
    CpuFeature::RvZvkn,
    CpuFeature::RvZvkned,
    CpuFeature::RvZvknha,
    CpuFeature::RvZvknhb,
    CpuFeature::RvZvks,
    CpuFeature::RvZvksed,
    CpuFeature::RvZvksh,
];

/// Base-I database inputs enabled by [`Environment::baseline`](crate::Environment::baseline).
pub const BASELINE_CPU_FEATURES: &[CpuFeature] = &[
    CpuFeature::RvI,
    CpuFeature::Rv32I,
    CpuFeature::Rv64I,
    CpuFeature::RvSystem,
];

impl CpuFeature {
    pub const fn name(self) -> &'static str {
        CPU_FEATURE_NAMES[self as usize]
    }
}

/// Accepted source-extension alternatives per opcode. At least one bit must be enabled.
#[rustfmt::skip]
pub static OPCODE_FEATURE_MASKS: [[u64; CPU_FEATURE_WORDS]; 1039] = [
    [0x0001000000000000, 0x0000000000000000], // add
    [0x0000000002000000, 0x0000000000000000], // add.uw
    [0x0001000000000000, 0x0000000000000000], // addi
    [0x0000000000100000, 0x0000000000000000], // addiw
    [0x0000000000100000, 0x0000000000000000], // addw
    [0x0000000000000e00, 0x0000000000000000], // aes32dsi
    [0x0000000000000e00, 0x0000000000000000], // aes32dsmi
    [0x0000000000001600, 0x0000000000000000], // aes32esi
    [0x0000000000001600, 0x0000000000000000], // aes32esmi
    [0x0000000380000000, 0x0000000000000000], // aes64ds
    [0x0000000380000000, 0x0000000000000000], // aes64dsm
    [0x0000000580000000, 0x0000000000000000], // aes64es
    [0x0000000580000000, 0x0000000000000000], // aes64esm
    [0x0000000380000000, 0x0000000000000000], // aes64im
    [0x0000000780000000, 0x0000000000000000], // aes64ks1i
    [0x0000000780000000, 0x0000000000000000], // aes64ks2
    [0x4000000000000000, 0x0000000000000000], // amoadd.b
    [0x0000000000008000, 0x0000000000000000], // amoadd.d
    [0x4000000000000000, 0x0000000000000000], // amoadd.h
    [0x0000002000000000, 0x0000000000000000], // amoadd.w
    [0x4000000000000000, 0x0000000000000000], // amoand.b
    [0x0000000000008000, 0x0000000000000000], // amoand.d
    [0x4000000000000000, 0x0000000000000000], // amoand.h
    [0x0000002000000000, 0x0000000000000000], // amoand.w
    [0x8000000000000000, 0x0000000000000000], // amocas.b
    [0x0000000000000000, 0x0000000000000001], // amocas.d
    [0x8000000000000000, 0x0000000000000000], // amocas.h
    [0x0000000001000000, 0x0000000000000000], // amocas.q
    [0x0000000000000000, 0x0000000000000001], // amocas.w
    [0x4000000000000000, 0x0000000000000000], // amomax.b
    [0x0000000000008000, 0x0000000000000000], // amomax.d
    [0x4000000000000000, 0x0000000000000000], // amomax.h
    [0x0000002000000000, 0x0000000000000000], // amomax.w
    [0x4000000000000000, 0x0000000000000000], // amomaxu.b
    [0x0000000000008000, 0x0000000000000000], // amomaxu.d
    [0x4000000000000000, 0x0000000000000000], // amomaxu.h
    [0x0000002000000000, 0x0000000000000000], // amomaxu.w
    [0x4000000000000000, 0x0000000000000000], // amomin.b
    [0x0000000000008000, 0x0000000000000000], // amomin.d
    [0x4000000000000000, 0x0000000000000000], // amomin.h
    [0x0000002000000000, 0x0000000000000000], // amomin.w
    [0x4000000000000000, 0x0000000000000000], // amominu.b
    [0x0000000000008000, 0x0000000000000000], // amominu.d
    [0x4000000000000000, 0x0000000000000000], // amominu.h
    [0x0000002000000000, 0x0000000000000000], // amominu.w
    [0x4000000000000000, 0x0000000000000000], // amoor.b
    [0x0000000000008000, 0x0000000000000000], // amoor.d
    [0x4000000000000000, 0x0000000000000000], // amoor.h
    [0x0000002000000000, 0x0000000000000000], // amoor.w
    [0x4000000000000000, 0x0000000000000000], // amoswap.b
    [0x0000000000008000, 0x0000000000000000], // amoswap.d
    [0x4000000000000000, 0x0000000000000000], // amoswap.h
    [0x0000002000000000, 0x0000000000000000], // amoswap.w
    [0x4000000000000000, 0x0000000000000000], // amoxor.b
    [0x0000000000008000, 0x0000000000000000], // amoxor.d
    [0x4000000000000000, 0x0000000000000000], // amoxor.h
    [0x0000002000000000, 0x0000000000000000], // amoxor.w
    [0x0001000000000000, 0x0000000000000000], // and
    [0x0001000000000000, 0x0000000000000000], // andi
    [0x0000000000000000, 0x000000002c000028], // andn
    [0x0001000000000000, 0x0000000000000000], // auipc
    [0x0000000000000000, 0x0000000000000100], // bclr
    [0x0000000010000000, 0x0000000000000000], // bclri
    [0x0000000000000040, 0x0000000000000000], // bclri.rv32
    [0x0001000000000000, 0x0000000000000000], // beq
    [0x0001000000000000, 0x0000000000000000], // beqz
    [0x0000000000000000, 0x0000000000000100], // bext
    [0x0000000010000000, 0x0000000000000000], // bexti
    [0x0000000000000040, 0x0000000000000000], // bexti.rv32
    [0x0001000000000000, 0x0000000000000000], // bge
    [0x0001000000000000, 0x0000000000000000], // bgeu
    [0x0001000000000000, 0x0000000000000000], // bgez
    [0x0001000000000000, 0x0000000000000000], // bgt
    [0x0001000000000000, 0x0000000000000000], // bgtu
    [0x0001000000000000, 0x0000000000000000], // bgtz
    [0x0000000000000000, 0x0000000000000100], // binv
    [0x0000000010000000, 0x0000000000000000], // binvi
    [0x0000000000000040, 0x0000000000000000], // binvi.rv32
    [0x0001000000000000, 0x0000000000000000], // ble
    [0x0001000000000000, 0x0000000000000000], // bleu
    [0x0001000000000000, 0x0000000000000000], // blez
    [0x0001000000000000, 0x0000000000000000], // blt
    [0x0001000000000000, 0x0000000000000000], // bltu
    [0x0001000000000000, 0x0000000000000000], // bltz
    [0x0001000000000000, 0x0000000000000000], // bne
    [0x0001000000000000, 0x0000000000000000], // bnez
    [0x0000000000000000, 0x000000002c000020], // brev8
    [0x0000000000000000, 0x0000000000000100], // bset
    [0x0000000010000000, 0x0000000000000000], // bseti
    [0x0000000000000040, 0x0000000000000000], // bseti.rv32
    [0x0000004000000000, 0x0000000000000000], // c.add
    [0x0000004000000000, 0x0000000000000000], // c.addi
    [0x0000004000000000, 0x0000000000000000], // c.addi16sp
    [0x0000004000000000, 0x0000000000000000], // c.addi4spn
    [0x0000000000010000, 0x0000000000000000], // c.addiw
    [0x0000000000010000, 0x0000000000000000], // c.addw
    [0x0000004000000000, 0x0000000000000000], // c.and
    [0x0000004000000000, 0x0000000000000000], // c.andi
    [0x0000004000000000, 0x0000000000000000], // c.beqz
    [0x0000004000000000, 0x0000000000000000], // c.bnez
    [0x0000004000000000, 0x0000000000000000], // c.ebreak
    [0x0000008000000000, 0x0000000000000000], // c.fld
    [0x0000008000000000, 0x0000000000000000], // c.fldsp
    [0x0000000000000002, 0x0000000000000000], // c.flw
    [0x0000000000000002, 0x0000000000000000], // c.flwsp
    [0x0000008000000000, 0x0000000000000000], // c.fsd
    [0x0000008000000000, 0x0000000000000000], // c.fsdsp
    [0x0000000000000002, 0x0000000000000000], // c.fsw
    [0x0000000000000002, 0x0000000000000000], // c.fswsp
    [0x0000004000000000, 0x0000000000000000], // c.j
    [0x0000000000000001, 0x0000000000000000], // c.jal
    [0x0000004000000000, 0x0000000000000000], // c.jalr
    [0x0000004000000000, 0x0000000000000000], // c.jr
    [0x0000000000000000, 0x0000000000000200], // c.lbu
    [0x0000000000010080, 0x0000000000000000], // c.ld
    [0x0000000000010080, 0x0000000000000000], // c.ldsp
    [0x0000000000000000, 0x0000000000000200], // c.lh
    [0x0000000000000000, 0x0000000000000200], // c.lhu
    [0x0000004000000000, 0x0000000000000000], // c.li
    [0x0000004000000000, 0x0000000000000000], // c.lui
    [0x0000004000000000, 0x0000000000000000], // c.lw
    [0x0000004000000000, 0x0000000000000000], // c.lwsp
    [0x0000000000000000, 0x0000000000000400], // c.mop.1
    [0x0000000000000000, 0x0000000000000400], // c.mop.11
    [0x0000000000000000, 0x0000000000000400], // c.mop.13
    [0x0000000000000000, 0x0000000000000400], // c.mop.15
    [0x0000000000000000, 0x0000000000000400], // c.mop.3
    [0x0000000000000000, 0x0000000000000400], // c.mop.5
    [0x0000000000000000, 0x0000000000000400], // c.mop.7
    [0x0000000000000000, 0x0000000000000400], // c.mop.9
    [0x0000000000000000, 0x0000000000000400], // c.mop.n
    [0x0000000000000000, 0x0000000000000200], // c.mul
    [0x0000004000000000, 0x0000000000000000], // c.mv
    [0x0000004000000000, 0x0000000000000000], // c.nop
    [0x0000000000000000, 0x0000000000000200], // c.not
    [0x0000020000000000, 0x0000000000000000], // c.ntl.all
    [0x0000020000000000, 0x0000000000000000], // c.ntl.p1
    [0x0000020000000000, 0x0000000000000000], // c.ntl.pall
    [0x0000020000000000, 0x0000000000000000], // c.ntl.s1
    [0x0000004000000000, 0x0000000000000000], // c.or
    [0x0000000000000000, 0x0000000000000200], // c.sb
    [0x0000000000010080, 0x0000000000000000], // c.sd
    [0x0000000000010080, 0x0000000000000000], // c.sdsp
    [0x0000000000000000, 0x0000000000000200], // c.sext.b
    [0x0000000000000000, 0x0000000000000200], // c.sext.h
    [0x0000000020000000, 0x0000000000000000], // c.sext.w
    [0x0000000000000000, 0x0000000000000200], // c.sh
    [0x0000000000010001, 0x0000000000000000], // c.slli
    [0x0000000000000001, 0x0000000000000000], // c.slli.rv32
    [0x0000000000010001, 0x0000000000000000], // c.srai
    [0x0000000000000001, 0x0000000000000000], // c.srai.rv32
    [0x0000000000010001, 0x0000000000000000], // c.srli
    [0x0000000000000001, 0x0000000000000000], // c.srli.rv32
    [0x0000010000000000, 0x0000000000000000], // c.sspopchk.x5
    [0x0000010000000000, 0x0000000000000000], // c.sspush.x1
    [0x0000004000000000, 0x0000000000000000], // c.sub
    [0x0000000000010000, 0x0000000000000000], // c.subw
    [0x0000004000000000, 0x0000000000000000], // c.sw
    [0x0000004000000000, 0x0000000000000000], // c.swsp
    [0x0000004000000000, 0x0000000000000000], // c.xor
    [0x0000000000000000, 0x0000000000000200], // c.zext.b
    [0x0000000000000000, 0x0000000000000200], // c.zext.h
    [0x0000000020000000, 0x0000000000000000], // c.zext.w
    [0x0000000000000000, 0x0000000000020000], // cbo.clean
    [0x0000000000000000, 0x0000000000020000], // cbo.flush
    [0x0000000000000000, 0x0000000000020000], // cbo.inval
    [0x0000000000000000, 0x0000000000020000], // cbo.zero
    [0x0000000000000000, 0x000000002c000050], // clmul
    [0x0000000000000000, 0x000000002c000050], // clmulh
    [0x0000000000000000, 0x0000000000000010], // clmulr
    [0x0000000000000000, 0x0000000000000008], // clz
    [0x0000000004000000, 0x0000000000000000], // clzw
    [0x0000000000000000, 0x0000000000001000], // cm.jalt
    [0x0000000000000000, 0x0000000000000800], // cm.mva01s
    [0x0000000000000000, 0x0000000000000800], // cm.mvsa01
    [0x0000000000000000, 0x0000000000000800], // cm.pop
    [0x0000000000000000, 0x0000000000000800], // cm.popret
    [0x0000000000000000, 0x0000000000000800], // cm.popretz
    [0x0000000000000000, 0x0000000000000800], // cm.push
    [0x0000000000000000, 0x0000000000000008], // cpop
    [0x0000000004000000, 0x0000000000000000], // cpopw
    [0x0000000000000000, 0x0000000000400000], // csrc
    [0x0000000000000000, 0x0000000000400000], // csrci
    [0x0000000000000000, 0x0000000000400000], // csrr
    [0x0000000000000000, 0x0000000000400000], // csrrc
    [0x0000000000000000, 0x0000000000400000], // csrrci
    [0x0000000000000000, 0x0000000000400000], // csrrs
    [0x0000000000000000, 0x0000000000400000], // csrrsi
    [0x0000000000000000, 0x0000000000400000], // csrrw
    [0x0000000000000000, 0x0000000000400000], // csrrwi
    [0x0000000000000000, 0x0000000000400000], // csrs
    [0x0000000000000000, 0x0000000000400000], // csrsi
    [0x0000000000000000, 0x0000000000400000], // csrw
    [0x0000000000000000, 0x0000000000400000], // csrwi
    [0x0000000000000000, 0x0000000000000008], // ctz
    [0x0000000004000000, 0x0000000000000000], // ctzw
    [0x0000000000000000, 0x0000000000200000], // czero.eqz
    [0x0000000000000000, 0x0000000000200000], // czero.nez
    [0x0002000000000000, 0x0000000000000000], // div
    [0x0002000000000000, 0x0000000000000000], // divu
    [0x0000000000200000, 0x0000000000000000], // divuw
    [0x0000000000200000, 0x0000000000000000], // divw
    [0x0040000000000000, 0x0000000000000000], // dret
    [0x0001000000000000, 0x0000000000000000], // ebreak
    [0x0001000000000000, 0x0000000000000000], // ecall
    [0x0000040000000000, 0x0000000000000000], // fabs.d
    [0x0000000000000000, 0x0000000000004000], // fabs.h
    [0x0004000000000000, 0x0000000000000000], // fabs.q
    [0x0000200000000000, 0x0000000000000000], // fabs.s
    [0x0000040000000000, 0x0000000000000000], // fadd.d
    [0x0000000000000000, 0x0000000000004000], // fadd.h
    [0x0004000000000000, 0x0000000000000000], // fadd.q
    [0x0000200000000000, 0x0000000000000000], // fadd.s
    [0x0000040000000000, 0x0000000000000000], // fclass.d
    [0x0000000000000000, 0x0000000000004000], // fclass.h
    [0x0004000000000000, 0x0000000000000000], // fclass.q
    [0x0000200000000000, 0x0000000000000000], // fclass.s
    [0x0000000000000000, 0x0000000000002000], // fcvt.bf16.s
    [0x0000100000000000, 0x0000000000000000], // fcvt.d.h
    [0x0000000000020000, 0x0000000000000000], // fcvt.d.l
    [0x0000000000020000, 0x0000000000000000], // fcvt.d.lu
    [0x0004000000000000, 0x0000000000000000], // fcvt.d.q
    [0x0000040000000000, 0x0000000000000000], // fcvt.d.s
    [0x0000040000000000, 0x0000000000000000], // fcvt.d.w
    [0x0000040000000000, 0x0000000000000000], // fcvt.d.wu
    [0x0000100000000000, 0x0000000000000000], // fcvt.h.d
    [0x0000000040000000, 0x0000000000000000], // fcvt.h.l
    [0x0000000040000000, 0x0000000000000000], // fcvt.h.lu
    [0x0010000000000000, 0x0000000000000000], // fcvt.h.q
    [0x0000000000000000, 0x0000000000010000], // fcvt.h.s
    [0x0000000000000000, 0x0000000000004000], // fcvt.h.w
    [0x0000000000000000, 0x0000000000004000], // fcvt.h.wu
    [0x0000000000020000, 0x0000000000000000], // fcvt.l.d
    [0x0000000040000000, 0x0000000000000000], // fcvt.l.h
    [0x0000000000400000, 0x0000000000000000], // fcvt.l.q
    [0x0000000000040000, 0x0000000000000000], // fcvt.l.s
    [0x0000000000020000, 0x0000000000000000], // fcvt.lu.d
    [0x0000000040000000, 0x0000000000000000], // fcvt.lu.h
    [0x0000000000400000, 0x0000000000000000], // fcvt.lu.q
    [0x0000000000040000, 0x0000000000000000], // fcvt.lu.s
    [0x0004000000000000, 0x0000000000000000], // fcvt.q.d
    [0x0010000000000000, 0x0000000000000000], // fcvt.q.h
    [0x0000000000400000, 0x0000000000000000], // fcvt.q.l
    [0x0000000000400000, 0x0000000000000000], // fcvt.q.lu
    [0x0004000000000000, 0x0000000000000000], // fcvt.q.s
    [0x0004000000000000, 0x0000000000000000], // fcvt.q.w
    [0x0004000000000000, 0x0000000000000000], // fcvt.q.wu
    [0x0000000000000000, 0x0000000000002000], // fcvt.s.bf16
    [0x0000040000000000, 0x0000000000000000], // fcvt.s.d
    [0x0000000000000000, 0x0000000000010000], // fcvt.s.h
    [0x0000000000040000, 0x0000000000000000], // fcvt.s.l
    [0x0000000000040000, 0x0000000000000000], // fcvt.s.lu
    [0x0004000000000000, 0x0000000000000000], // fcvt.s.q
    [0x0000200000000000, 0x0000000000000000], // fcvt.s.w
    [0x0000200000000000, 0x0000000000000000], // fcvt.s.wu
    [0x0000040000000000, 0x0000000000000000], // fcvt.w.d
    [0x0000000000000000, 0x0000000000004000], // fcvt.w.h
    [0x0004000000000000, 0x0000000000000000], // fcvt.w.q
    [0x0000200000000000, 0x0000000000000000], // fcvt.w.s
    [0x0000040000000000, 0x0000000000000000], // fcvt.wu.d
    [0x0000000000000000, 0x0000000000004000], // fcvt.wu.h
    [0x0004000000000000, 0x0000000000000000], // fcvt.wu.q
    [0x0000200000000000, 0x0000000000000000], // fcvt.wu.s
    [0x0000080000000000, 0x0000000000000000], // fcvtmod.w.d
    [0x0000040000000000, 0x0000000000000000], // fdiv.d
    [0x0000000000000000, 0x0000000000004000], // fdiv.h
    [0x0004000000000000, 0x0000000000000000], // fdiv.q
    [0x0000200000000000, 0x0000000000000000], // fdiv.s
    [0x0001000000000000, 0x0000000000000000], // fence
    [0x0000000000000000, 0x0000000000800000], // fence.i
    [0x0001000000000000, 0x0000000000000000], // fence.tso
    [0x0000040000000000, 0x0000000000000000], // feq.d
    [0x0000000000000000, 0x0000000000004000], // feq.h
    [0x0004000000000000, 0x0000000000000000], // feq.q
    [0x0000200000000000, 0x0000000000000000], // feq.s
    [0x0000040000000000, 0x0000000000000000], // fld
    [0x0000040000000000, 0x0000000000000000], // fle.d
    [0x0000000000000000, 0x0000000000004000], // fle.h
    [0x0004000000000000, 0x0000000000000000], // fle.q
    [0x0000200000000000, 0x0000000000000000], // fle.s
    [0x0000080000000000, 0x0000000000000000], // fleq.d
    [0x0000000000000000, 0x0000000000008000], // fleq.h
    [0x0008000000000000, 0x0000000000000000], // fleq.q
    [0x0000400000000000, 0x0000000000000000], // fleq.s
    [0x0000000000000000, 0x0000000000010000], // flh
    [0x0000080000000000, 0x0000000000000000], // fli.d
    [0x0000000000000000, 0x0000000000008000], // fli.h
    [0x0008000000000000, 0x0000000000000000], // fli.q
    [0x0000400000000000, 0x0000000000000000], // fli.s
    [0x0004000000000000, 0x0000000000000000], // flq
    [0x0000040000000000, 0x0000000000000000], // flt.d
    [0x0000000000000000, 0x0000000000004000], // flt.h
    [0x0004000000000000, 0x0000000000000000], // flt.q
    [0x0000200000000000, 0x0000000000000000], // flt.s
    [0x0000080000000000, 0x0000000000000000], // fltq.d
    [0x0000000000000000, 0x0000000000008000], // fltq.h
    [0x0008000000000000, 0x0000000000000000], // fltq.q
    [0x0000400000000000, 0x0000000000000000], // fltq.s
    [0x0000200000000000, 0x0000000000000000], // flw
    [0x0000040000000000, 0x0000000000000000], // fmadd.d
    [0x0000000000000000, 0x0000000000004000], // fmadd.h
    [0x0004000000000000, 0x0000000000000000], // fmadd.q
    [0x0000200000000000, 0x0000000000000000], // fmadd.s
    [0x0000040000000000, 0x0000000000000000], // fmax.d
    [0x0000000000000000, 0x0000000000004000], // fmax.h
    [0x0004000000000000, 0x0000000000000000], // fmax.q
    [0x0000200000000000, 0x0000000000000000], // fmax.s
    [0x0000080000000000, 0x0000000000000000], // fmaxm.d
    [0x0000000000000000, 0x0000000000008000], // fmaxm.h
    [0x0008000000000000, 0x0000000000000000], // fmaxm.q
    [0x0000400000000000, 0x0000000000000000], // fmaxm.s
    [0x0000040000000000, 0x0000000000000000], // fmin.d
    [0x0000000000000000, 0x0000000000004000], // fmin.h
    [0x0004000000000000, 0x0000000000000000], // fmin.q
    [0x0000200000000000, 0x0000000000000000], // fmin.s
    [0x0000080000000000, 0x0000000000000000], // fminm.d
    [0x0000000000000000, 0x0000000000008000], // fminm.h
    [0x0008000000000000, 0x0000000000000000], // fminm.q
    [0x0000400000000000, 0x0000000000000000], // fminm.s
    [0x0000040000000000, 0x0000000000000000], // fmsub.d
    [0x0000000000000000, 0x0000000000004000], // fmsub.h
    [0x0004000000000000, 0x0000000000000000], // fmsub.q
    [0x0000200000000000, 0x0000000000000000], // fmsub.s
    [0x0000040000000000, 0x0000000000000000], // fmul.d
    [0x0000000000000000, 0x0000000000004000], // fmul.h
    [0x0004000000000000, 0x0000000000000000], // fmul.q
    [0x0000200000000000, 0x0000000000000000], // fmul.s
    [0x0000040000000000, 0x0000000000000000], // fmv.d
    [0x0000000000020000, 0x0000000000000000], // fmv.d.x
    [0x0000000000000000, 0x0000000000004000], // fmv.h
    [0x0000000000000000, 0x0000000000010000], // fmv.h.x
    [0x0004000000000000, 0x0000000000000000], // fmv.q
    [0x0000200000000000, 0x0000000000000000], // fmv.s
    [0x0000200000000000, 0x0000000000000000], // fmv.s.x
    [0x0000200000000000, 0x0000000000000000], // fmv.w.x
    [0x0000000000020000, 0x0000000000000000], // fmv.x.d
    [0x0000000000000000, 0x0000000000010000], // fmv.x.h
    [0x0000200000000000, 0x0000000000000000], // fmv.x.s
    [0x0000200000000000, 0x0000000000000000], // fmv.x.w
    [0x0000000000000004, 0x0000000000000000], // fmvh.x.d
    [0x0000000000800000, 0x0000000000000000], // fmvh.x.q
    [0x0000000000000004, 0x0000000000000000], // fmvp.d.x
    [0x0000000000800000, 0x0000000000000000], // fmvp.q.x
    [0x0000040000000000, 0x0000000000000000], // fneg.d
    [0x0000000000000000, 0x0000000000004000], // fneg.h
    [0x0004000000000000, 0x0000000000000000], // fneg.q
    [0x0000200000000000, 0x0000000000000000], // fneg.s
    [0x0000040000000000, 0x0000000000000000], // fnmadd.d
    [0x0000000000000000, 0x0000000000004000], // fnmadd.h
    [0x0004000000000000, 0x0000000000000000], // fnmadd.q
    [0x0000200000000000, 0x0000000000000000], // fnmadd.s
    [0x0000040000000000, 0x0000000000000000], // fnmsub.d
    [0x0000000000000000, 0x0000000000004000], // fnmsub.h
    [0x0004000000000000, 0x0000000000000000], // fnmsub.q
    [0x0000200000000000, 0x0000000000000000], // fnmsub.s
    [0x0000200000000000, 0x0000000000000000], // frcsr
    [0x0000200000000000, 0x0000000000000000], // frflags
    [0x0000080000000000, 0x0000000000000000], // fround.d
    [0x0000000000000000, 0x0000000000008000], // fround.h
    [0x0008000000000000, 0x0000000000000000], // fround.q
    [0x0000400000000000, 0x0000000000000000], // fround.s
    [0x0000080000000000, 0x0000000000000000], // froundnx.d
    [0x0000000000000000, 0x0000000000008000], // froundnx.h
    [0x0008000000000000, 0x0000000000000000], // froundnx.q
    [0x0000400000000000, 0x0000000000000000], // froundnx.s
    [0x0000200000000000, 0x0000000000000000], // frrm
    [0x0000200000000000, 0x0000000000000000], // fscsr
    [0x0000040000000000, 0x0000000000000000], // fsd
    [0x0000200000000000, 0x0000000000000000], // fsflags
    [0x0000200000000000, 0x0000000000000000], // fsflagsi
    [0x0000040000000000, 0x0000000000000000], // fsgnj.d
    [0x0000000000000000, 0x0000000000004000], // fsgnj.h
    [0x0004000000000000, 0x0000000000000000], // fsgnj.q
    [0x0000200000000000, 0x0000000000000000], // fsgnj.s
    [0x0000040000000000, 0x0000000000000000], // fsgnjn.d
    [0x0000000000000000, 0x0000000000004000], // fsgnjn.h
    [0x0004000000000000, 0x0000000000000000], // fsgnjn.q
    [0x0000200000000000, 0x0000000000000000], // fsgnjn.s
    [0x0000040000000000, 0x0000000000000000], // fsgnjx.d
    [0x0000000000000000, 0x0000000000004000], // fsgnjx.h
    [0x0004000000000000, 0x0000000000000000], // fsgnjx.q
    [0x0000200000000000, 0x0000000000000000], // fsgnjx.s
    [0x0000000000000000, 0x0000000000010000], // fsh
    [0x0004000000000000, 0x0000000000000000], // fsq
    [0x0000040000000000, 0x0000000000000000], // fsqrt.d
    [0x0000000000000000, 0x0000000000004000], // fsqrt.h
    [0x0004000000000000, 0x0000000000000000], // fsqrt.q
    [0x0000200000000000, 0x0000000000000000], // fsqrt.s
    [0x0000200000000000, 0x0000000000000000], // fsrm
    [0x0000200000000000, 0x0000000000000000], // fsrmi
    [0x0000040000000000, 0x0000000000000000], // fsub.d
    [0x0000000000000000, 0x0000000000004000], // fsub.h
    [0x0004000000000000, 0x0000000000000000], // fsub.q
    [0x0000200000000000, 0x0000000000000000], // fsub.s
    [0x0000200000000000, 0x0000000000000000], // fsw
    [0x0000800000000000, 0x0000000000000000], // hfence.gvma
    [0x0000800000000000, 0x0000000000000000], // hfence.vvma
    [0x0400000000000000, 0x0000000000000000], // hinval.gvma
    [0x0400000000000000, 0x0000000000000000], // hinval.vvma
    [0x0000800000000000, 0x0000000000000000], // hlv.b
    [0x0000800000000000, 0x0000000000000000], // hlv.bu
    [0x0000000000080000, 0x0000000000000000], // hlv.d
    [0x0000800000000000, 0x0000000000000000], // hlv.h
    [0x0000800000000000, 0x0000000000000000], // hlv.hu
    [0x0000800000000000, 0x0000000000000000], // hlv.w
    [0x0000000000080000, 0x0000000000000000], // hlv.wu
    [0x0000800000000000, 0x0000000000000000], // hlvx.hu
    [0x0000800000000000, 0x0000000000000000], // hlvx.wu
    [0x0000800000000000, 0x0000000000000000], // hsv.b
    [0x0000000000080000, 0x0000000000000000], // hsv.d
    [0x0000800000000000, 0x0000000000000000], // hsv.h
    [0x0000800000000000, 0x0000000000000000], // hsv.w
    [0x0001000000000000, 0x0000000000000000], // j
    [0x0001000000000000, 0x0000000000000000], // jal
    [0x0001000000000000, 0x0000000000000000], // jal.pseudo
    [0x0001000000000000, 0x0000000000000000], // jalr
    [0x0001000000000000, 0x0000000000000000], // jalr.pseudo
    [0x0001000000000000, 0x0000000000000000], // jr
    [0x0001000000000000, 0x0000000000000000], // lb
    [0x0001000000000000, 0x0000000000000000], // lbu
    [0x0000000000100000, 0x0000000000000000], // ld
    [0x0001000000000000, 0x0000000000000000], // lh
    [0x0001000000000000, 0x0000000000000000], // lhu
    [0x0000000000000000, 0x0000000000040000], // lpad
    [0x0000000000008000, 0x0000000000000000], // lr.d
    [0x0000002000000000, 0x0000000000000000], // lr.w
    [0x0001000000000000, 0x0000000000000000], // lui
    [0x0001000000000000, 0x0000000000000000], // lw
    [0x0000000000100000, 0x0000000000000000], // lwu
    [0x0000000000000000, 0x0000000000000008], // max
    [0x0000000000000000, 0x0000000000000008], // maxu
    [0x0000000000000000, 0x0000000000000008], // min
    [0x0000000000000000, 0x0000000000000008], // minu
    [0x0080000000000000, 0x0000000000000000], // mnret
    [0x0000000000000000, 0x0000000002000000], // mop.r.0
    [0x0000000000000000, 0x0000000002000000], // mop.r.1
    [0x0000000000000000, 0x0000000002000000], // mop.r.10
    [0x0000000000000000, 0x0000000002000000], // mop.r.11
    [0x0000000000000000, 0x0000000002000000], // mop.r.12
    [0x0000000000000000, 0x0000000002000000], // mop.r.13
    [0x0000000000000000, 0x0000000002000000], // mop.r.14
    [0x0000000000000000, 0x0000000002000000], // mop.r.15
    [0x0000000000000000, 0x0000000002000000], // mop.r.16
    [0x0000000000000000, 0x0000000002000000], // mop.r.17
    [0x0000000000000000, 0x0000000002000000], // mop.r.18
    [0x0000000000000000, 0x0000000002000000], // mop.r.19
    [0x0000000000000000, 0x0000000002000000], // mop.r.2
    [0x0000000000000000, 0x0000000002000000], // mop.r.20
    [0x0000000000000000, 0x0000000002000000], // mop.r.21
    [0x0000000000000000, 0x0000000002000000], // mop.r.22
    [0x0000000000000000, 0x0000000002000000], // mop.r.23
    [0x0000000000000000, 0x0000000002000000], // mop.r.24
    [0x0000000000000000, 0x0000000002000000], // mop.r.25
    [0x0000000000000000, 0x0000000002000000], // mop.r.26
    [0x0000000000000000, 0x0000000002000000], // mop.r.27
    [0x0000000000000000, 0x0000000002000000], // mop.r.28
    [0x0000000000000000, 0x0000000002000000], // mop.r.29
    [0x0000000000000000, 0x0000000002000000], // mop.r.3
    [0x0000000000000000, 0x0000000002000000], // mop.r.30
    [0x0000000000000000, 0x0000000002000000], // mop.r.31
    [0x0000000000000000, 0x0000000002000000], // mop.r.4
    [0x0000000000000000, 0x0000000002000000], // mop.r.5
    [0x0000000000000000, 0x0000000002000000], // mop.r.6
    [0x0000000000000000, 0x0000000002000000], // mop.r.7
    [0x0000000000000000, 0x0000000002000000], // mop.r.8
    [0x0000000000000000, 0x0000000002000000], // mop.r.9
    [0x0000000000000000, 0x0000000002000000], // mop.r.n
    [0x0000000000000000, 0x0000000002000000], // mop.rr.0
    [0x0000000000000000, 0x0000000002000000], // mop.rr.1
    [0x0000000000000000, 0x0000000002000000], // mop.rr.2
    [0x0000000000000000, 0x0000000002000000], // mop.rr.3
    [0x0000000000000000, 0x0000000002000000], // mop.rr.4
    [0x0000000000000000, 0x0000000002000000], // mop.rr.5
    [0x0000000000000000, 0x0000000002000000], // mop.rr.6
    [0x0000000000000000, 0x0000000002000000], // mop.rr.7
    [0x0000000000000000, 0x0000000002000000], // mop.rr.n
    [0x0800000000000000, 0x0000000000000000], // mret
    [0x0002000000000000, 0x0000000000000000], // mul
    [0x0002000000000000, 0x0000000000000000], // mulh
    [0x0002000000000000, 0x0000000000000000], // mulhsu
    [0x0002000000000000, 0x0000000000000000], // mulhu
    [0x0000000000200000, 0x0000000000000000], // mulw
    [0x0001000000000000, 0x0000000000000000], // mv
    [0x0001000000000000, 0x0000000000000000], // neg
    [0x0001000000000000, 0x0000000000000000], // nop
    [0x0000000000000000, 0x0000000001000000], // ntl.all
    [0x0000000000000000, 0x0000000001000000], // ntl.p1
    [0x0000000000000000, 0x0000000001000000], // ntl.pall
    [0x0000000000000000, 0x0000000001000000], // ntl.s1
    [0x0001000000000000, 0x0000000000000000], // or
    [0x0000000000000000, 0x0000000000000008], // orc.b
    [0x0001000000000000, 0x0000000000000000], // ori
    [0x0000000000000000, 0x000000002c000028], // orn
    [0x0000000000000000, 0x000000002c000020], // pack
    [0x0000000000000000, 0x000000002c000020], // packh
    [0x0000001188000000, 0x0000000000000000], // packw
    [0x0001000000000000, 0x0000000000000000], // pause
    [0x0000000000000000, 0x0000000000020000], // prefetch.i
    [0x0000000000000000, 0x0000000000020000], // prefetch.r
    [0x0000000000000000, 0x0000000000020000], // prefetch.w
    [0x0000000000000000, 0x0000000000100000], // rdcycle
    [0x0000000000000100, 0x0000000000000000], // rdcycleh
    [0x0000000000000000, 0x0000000000100000], // rdinstret
    [0x0000000000000100, 0x0000000000000000], // rdinstreth
    [0x0000000000000000, 0x0000000000100000], // rdtime
    [0x0000000000000100, 0x0000000000000000], // rdtimeh
    [0x0002000000000000, 0x0000000000000000], // rem
    [0x0002000000000000, 0x0000000000000000], // remu
    [0x0000000000200000, 0x0000000000000000], // remuw
    [0x0000000000200000, 0x0000000000000000], // remw
    [0x0001000000000000, 0x0000000000000000], // ret
    [0x000000118c000000, 0x0000000000000000], // rev8
    [0x0000000000004630, 0x0000000000000000], // rev8.rv32
    [0x0000000000000000, 0x000000002c000028], // rol
    [0x000000118c000000, 0x0000000000000000], // rolw
    [0x0000000000000000, 0x000000002c000028], // ror
    [0x000000118c000000, 0x0000000000000000], // rori
    [0x0000000000004630, 0x0000000000000000], // rori.rv32
    [0x000000118c000000, 0x0000000000000000], // roriw
    [0x000000118c000000, 0x0000000000000000], // rorw
    [0x0001000000000000, 0x0000000000000000], // sb
    [0x0001000000000000, 0x0000000000000000], // sbreak
    [0x0000000000008000, 0x0000000000000000], // sc.d
    [0x0000002000000000, 0x0000000000000000], // sc.w
    [0x0001000000000000, 0x0000000000000000], // scall
    [0x0100000000000000, 0x0000000000000000], // sctrclr
    [0x0000000000100000, 0x0000000000000000], // sd
    [0x0001000000000000, 0x0000000000000000], // seqz
    [0x0000000000000000, 0x0000000000000008], // sext.b
    [0x0000000000000000, 0x0000000000000008], // sext.h
    [0x0000000000100000, 0x0000000000000000], // sext.w
    [0x0200000000000000, 0x0000000000000000], // sfence.inval.ir
    [0x0020000000000000, 0x0000000000000000], // sfence.vma
    [0x0200000000000000, 0x0000000000000000], // sfence.w.inval
    [0x0001000000000000, 0x0000000000000000], // sgtz
    [0x0001000000000000, 0x0000000000000000], // sh
    [0x0000000000000000, 0x0000000000000004], // sh1add
    [0x0000000002000000, 0x0000000000000000], // sh1add.uw
    [0x0000000000000000, 0x0000000000000004], // sh2add
    [0x0000000002000000, 0x0000000000000000], // sh2add.uw
    [0x0000000000000000, 0x0000000000000004], // sh3add
    [0x0000000002000000, 0x0000000000000000], // sh3add.uw
    [0x0000000000000000, 0x000000001c000000], // sha256sig0
    [0x0000000000000000, 0x000000001c000000], // sha256sig1
    [0x0000000000000000, 0x000000001c000000], // sha256sum0
    [0x0000000000000000, 0x000000001c000000], // sha256sum1
    [0x0000000980000000, 0x0000000000000000], // sha512sig0
    [0x0000000000002600, 0x0000000000000000], // sha512sig0h
    [0x0000000000002600, 0x0000000000000000], // sha512sig0l
    [0x0000000980000000, 0x0000000000000000], // sha512sig1
    [0x0000000000002600, 0x0000000000000000], // sha512sig1h
    [0x0000000000002600, 0x0000000000000000], // sha512sig1l
    [0x0000000980000000, 0x0000000000000000], // sha512sum0
    [0x0000000000002600, 0x0000000000000000], // sha512sum0r
    [0x0000000980000000, 0x0000000000000000], // sha512sum1
    [0x0000000000002600, 0x0000000000000000], // sha512sum1r
    [0x0200000000000000, 0x0000000000000000], // sinval.vma
    [0x0001000000000000, 0x0000000000000000], // sll
    [0x0000000000100008, 0x0000000000000000], // slli
    [0x0000000000000008, 0x0000000000000000], // slli.rv32
    [0x0000000002000000, 0x0000000000000000], // slli.uw
    [0x0000000000100000, 0x0000000000000000], // slliw
    [0x0000000000100000, 0x0000000000000000], // sllw
    [0x0001000000000000, 0x0000000000000000], // slt
    [0x0001000000000000, 0x0000000000000000], // slti
    [0x0001000000000000, 0x0000000000000000], // sltiu
    [0x0001000000000000, 0x0000000000000000], // sltu
    [0x0001000000000000, 0x0000000000000000], // sltz
    [0x0000000000000000, 0x00000000a0000000], // sm3p0
    [0x0000000000000000, 0x00000000a0000000], // sm3p1
    [0x0000000000000000, 0x0000000060000000], // sm4ed
    [0x0000000000000000, 0x0000000060000000], // sm4ks
    [0x0001000000000000, 0x0000000000000000], // snez
    [0x0001000000000000, 0x0000000000000000], // sra
    [0x0000000000100008, 0x0000000000000000], // srai
    [0x0000000000000008, 0x0000000000000000], // srai.rv32
    [0x0000000000100000, 0x0000000000000000], // sraiw
    [0x0000000000100000, 0x0000000000000000], // sraw
    [0x0020000000000000, 0x0000000000000000], // sret
    [0x0001000000000000, 0x0000000000000000], // srl
    [0x0000000000100008, 0x0000000000000000], // srli
    [0x0000000000000008, 0x0000000000000000], // srli.rv32
    [0x0000000000100000, 0x0000000000000000], // srliw
    [0x0000000000100000, 0x0000000000000000], // srlw
    [0x0000000000000000, 0x0000000000080000], // ssamoswap.d
    [0x0000000000000000, 0x0000000000080000], // ssamoswap.w
    [0x0000000000000000, 0x0000000000080000], // sspopchk.x1
    [0x0000000000000000, 0x0000000000080000], // sspopchk.x5
    [0x0000000000000000, 0x0000000000080000], // sspush.x1
    [0x0000000000000000, 0x0000000000080000], // sspush.x5
    [0x0000000000000000, 0x0000000000080000], // ssrdp
    [0x0001000000000000, 0x0000000000000000], // sub
    [0x0000000000100000, 0x0000000000000000], // subw
    [0x0001000000000000, 0x0000000000000000], // sw
    [0x0000000000004620, 0x0000000000000000], // unzip
    [0x1000000000000000, 0x0000000000000000], // vaadd.vv
    [0x1000000000000000, 0x0000000000000000], // vaadd.vx
    [0x1000000000000000, 0x0000000000000000], // vaaddu.vv
    [0x1000000000000000, 0x0000000000000000], // vaaddu.vx
    [0x1000000000000000, 0x0000000000000000], // vadc.vim
    [0x1000000000000000, 0x0000000000000000], // vadc.vvm
    [0x1000000000000000, 0x0000000000000000], // vadc.vxm
    [0x1000000000000000, 0x0000000000000000], // vadd.vi
    [0x1000000000000000, 0x0000000000000000], // vadd.vv
    [0x1000000000000000, 0x0000000000000000], // vadd.vx
    [0x0000000000000000, 0x0000006000000000], // vaesdf.vs
    [0x0000000000000000, 0x0000006000000000], // vaesdf.vv
    [0x0000000000000000, 0x0000006000000000], // vaesdm.vs
    [0x0000000000000000, 0x0000006000000000], // vaesdm.vv
    [0x0000000000000000, 0x0000006000000000], // vaesef.vs
    [0x0000000000000000, 0x0000006000000000], // vaesef.vv
    [0x0000000000000000, 0x0000006000000000], // vaesem.vs
    [0x0000000000000000, 0x0000006000000000], // vaesem.vv
    [0x0000000000000000, 0x0000006000000000], // vaeskf1.vi
    [0x0000000000000000, 0x0000006000000000], // vaeskf2.vi
    [0x0000000000000000, 0x0000006000000000], // vaesz.vs
    [0x1000000000000000, 0x0000000000000000], // vand.vi
    [0x1000000000000000, 0x0000000000000000], // vand.vv
    [0x1000000000000000, 0x0000000000000000], // vand.vx
    [0x0000000000000000, 0x0000022100000000], // vandn.vv
    [0x0000000000000000, 0x0000022100000000], // vandn.vx
    [0x1000000000000000, 0x0000000000000000], // vasub.vv
    [0x1000000000000000, 0x0000000000000000], // vasub.vx
    [0x1000000000000000, 0x0000000000000000], // vasubu.vv
    [0x1000000000000000, 0x0000000000000000], // vasubu.vx
    [0x0000000000000000, 0x0000022100000000], // vbrev8.v
    [0x0000000000000000, 0x0000000100000000], // vbrev.v
    [0x0000000000000000, 0x0000000200000000], // vclmul.vv
    [0x0000000000000000, 0x0000000200000000], // vclmul.vx
    [0x0000000000000000, 0x0000000200000000], // vclmulh.vv
    [0x0000000000000000, 0x0000000200000000], // vclmulh.vx
    [0x0000000000000000, 0x0000000100000000], // vclz.v
    [0x1000000000000000, 0x0000000000000000], // vcompress.vm
    [0x1000000000000000, 0x0000000000000000], // vcpop.m
    [0x0000000000000000, 0x0000000100000000], // vcpop.v
    [0x0000000000000000, 0x0000000100000000], // vctz.v
    [0x1000000000000000, 0x0000000000000000], // vdiv.vv
    [0x1000000000000000, 0x0000000000000000], // vdiv.vx
    [0x1000000000000000, 0x0000000000000000], // vdivu.vv
    [0x1000000000000000, 0x0000000000000000], // vdivu.vx
    [0x1000000000000000, 0x0000000000000000], // vfadd.vf
    [0x1000000000000000, 0x0000000000000000], // vfadd.vv
    [0x1000000000000000, 0x0000000000000000], // vfclass.v
    [0x1000000000000000, 0x0000000000000000], // vfcvt.f.x.v
    [0x1000000000000000, 0x0000000000000000], // vfcvt.f.xu.v
    [0x1000000000000000, 0x0000000000000000], // vfcvt.rtz.x.f.v
    [0x1000000000000000, 0x0000000000000000], // vfcvt.rtz.xu.f.v
    [0x1000000000000000, 0x0000000000000000], // vfcvt.x.f.v
    [0x1000000000000000, 0x0000000000000000], // vfcvt.xu.f.v
    [0x1000000000000000, 0x0000000000000000], // vfdiv.vf
    [0x1000000000000000, 0x0000000000000000], // vfdiv.vv
    [0x1000000000000000, 0x0000000000000000], // vfirst.m
    [0x1000000000000000, 0x0000000000000000], // vfmacc.vf
    [0x1000000000000000, 0x0000000000000000], // vfmacc.vv
    [0x1000000000000000, 0x0000000000000000], // vfmadd.vf
    [0x1000000000000000, 0x0000000000000000], // vfmadd.vv
    [0x1000000000000000, 0x0000000000000000], // vfmax.vf
    [0x1000000000000000, 0x0000000000000000], // vfmax.vv
    [0x1000000000000000, 0x0000000000000000], // vfmerge.vfm
    [0x1000000000000000, 0x0000000000000000], // vfmin.vf
    [0x1000000000000000, 0x0000000000000000], // vfmin.vv
    [0x1000000000000000, 0x0000000000000000], // vfmsac.vf
    [0x1000000000000000, 0x0000000000000000], // vfmsac.vv
    [0x1000000000000000, 0x0000000000000000], // vfmsub.vf
    [0x1000000000000000, 0x0000000000000000], // vfmsub.vv
    [0x1000000000000000, 0x0000000000000000], // vfmul.vf
    [0x1000000000000000, 0x0000000000000000], // vfmul.vv
    [0x1000000000000000, 0x0000000000000000], // vfmv.f.s
    [0x1000000000000000, 0x0000000000000000], // vfmv.s.f
    [0x1000000000000000, 0x0000000000000000], // vfmv.v.f
    [0x1000000000000000, 0x0000000000000000], // vfncvt.f.f.w
    [0x1000000000000000, 0x0000000000000000], // vfncvt.f.x.w
    [0x1000000000000000, 0x0000000000000000], // vfncvt.f.xu.w
    [0x1000000000000000, 0x0000000000000000], // vfncvt.rod.f.f.w
    [0x1000000000000000, 0x0000000000000000], // vfncvt.rtz.x.f.w
    [0x1000000000000000, 0x0000000000000000], // vfncvt.rtz.xu.f.w
    [0x1000000000000000, 0x0000000000000000], // vfncvt.x.f.w
    [0x1000000000000000, 0x0000000000000000], // vfncvt.xu.f.w
    [0x0000000000000000, 0x0000000400000000], // vfncvtbf16.f.f.w
    [0x1000000000000000, 0x0000000000000000], // vfnmacc.vf
    [0x1000000000000000, 0x0000000000000000], // vfnmacc.vv
    [0x1000000000000000, 0x0000000000000000], // vfnmadd.vf
    [0x1000000000000000, 0x0000000000000000], // vfnmadd.vv
    [0x1000000000000000, 0x0000000000000000], // vfnmsac.vf
    [0x1000000000000000, 0x0000000000000000], // vfnmsac.vv
    [0x1000000000000000, 0x0000000000000000], // vfnmsub.vf
    [0x1000000000000000, 0x0000000000000000], // vfnmsub.vv
    [0x1000000000000000, 0x0000000000000000], // vfrdiv.vf
    [0x1000000000000000, 0x0000000000000000], // vfrec7.v
    [0x1000000000000000, 0x0000000000000000], // vfredmax.vs
    [0x1000000000000000, 0x0000000000000000], // vfredmin.vs
    [0x1000000000000000, 0x0000000000000000], // vfredosum.vs
    [0x2000000000000000, 0x0000000000000000], // vfredsum.vs
    [0x1000000000000000, 0x0000000000000000], // vfredusum.vs
    [0x1000000000000000, 0x0000000000000000], // vfrsqrt7.v
    [0x1000000000000000, 0x0000000000000000], // vfrsub.vf
    [0x1000000000000000, 0x0000000000000000], // vfsgnj.vf
    [0x1000000000000000, 0x0000000000000000], // vfsgnj.vv
    [0x1000000000000000, 0x0000000000000000], // vfsgnjn.vf
    [0x1000000000000000, 0x0000000000000000], // vfsgnjn.vv
    [0x1000000000000000, 0x0000000000000000], // vfsgnjx.vf
    [0x1000000000000000, 0x0000000000000000], // vfsgnjx.vv
    [0x1000000000000000, 0x0000000000000000], // vfslide1down.vf
    [0x1000000000000000, 0x0000000000000000], // vfslide1up.vf
    [0x1000000000000000, 0x0000000000000000], // vfsqrt.v
    [0x1000000000000000, 0x0000000000000000], // vfsub.vf
    [0x1000000000000000, 0x0000000000000000], // vfsub.vv
    [0x1000000000000000, 0x0000000000000000], // vfwadd.vf
    [0x1000000000000000, 0x0000000000000000], // vfwadd.vv
    [0x1000000000000000, 0x0000000000000000], // vfwadd.wf
    [0x1000000000000000, 0x0000000000000000], // vfwadd.wv
    [0x1000000000000000, 0x0000000000000000], // vfwcvt.f.f.v
    [0x1000000000000000, 0x0000000000000000], // vfwcvt.f.x.v
    [0x1000000000000000, 0x0000000000000000], // vfwcvt.f.xu.v
    [0x1000000000000000, 0x0000000000000000], // vfwcvt.rtz.x.f.v
    [0x1000000000000000, 0x0000000000000000], // vfwcvt.rtz.xu.f.v
    [0x1000000000000000, 0x0000000000000000], // vfwcvt.x.f.v
    [0x1000000000000000, 0x0000000000000000], // vfwcvt.xu.f.v
    [0x0000000000000000, 0x0000000400000000], // vfwcvtbf16.f.f.v
    [0x1000000000000000, 0x0000000000000000], // vfwmacc.vf
    [0x1000000000000000, 0x0000000000000000], // vfwmacc.vv
    [0x0000000000000000, 0x0000000800000000], // vfwmaccbf16.vf
    [0x0000000000000000, 0x0000000800000000], // vfwmaccbf16.vv
    [0x1000000000000000, 0x0000000000000000], // vfwmsac.vf
    [0x1000000000000000, 0x0000000000000000], // vfwmsac.vv
    [0x1000000000000000, 0x0000000000000000], // vfwmul.vf
    [0x1000000000000000, 0x0000000000000000], // vfwmul.vv
    [0x1000000000000000, 0x0000000000000000], // vfwnmacc.vf
    [0x1000000000000000, 0x0000000000000000], // vfwnmacc.vv
    [0x1000000000000000, 0x0000000000000000], // vfwnmsac.vf
    [0x1000000000000000, 0x0000000000000000], // vfwnmsac.vv
    [0x1000000000000000, 0x0000000000000000], // vfwredosum.vs
    [0x2000000000000000, 0x0000000000000000], // vfwredsum.vs
    [0x1000000000000000, 0x0000000000000000], // vfwredusum.vs
    [0x1000000000000000, 0x0000000000000000], // vfwsub.vf
    [0x1000000000000000, 0x0000000000000000], // vfwsub.vv
    [0x1000000000000000, 0x0000000000000000], // vfwsub.wf
    [0x1000000000000000, 0x0000000000000000], // vfwsub.wv
    [0x0000000000000000, 0x0000001000000000], // vghsh.vv
    [0x0000000000000000, 0x0000001000000000], // vgmul.vv
    [0x1000000000000000, 0x0000000000000000], // vid.v
    [0x1000000000000000, 0x0000000000000000], // viota.m
    [0x2000000000000000, 0x0000000000000000], // vl1r.v
    [0x1000000000000000, 0x0000000000000000], // vl1re16.v
    [0x1000000000000000, 0x0000000000000000], // vl1re32.v
    [0x1000000000000000, 0x0000000000000000], // vl1re64.v
    [0x1000000000000000, 0x0000000000000000], // vl1re8.v
    [0x2000000000000000, 0x0000000000000000], // vl2r.v
    [0x1000000000000000, 0x0000000000000000], // vl2re16.v
    [0x1000000000000000, 0x0000000000000000], // vl2re32.v
    [0x1000000000000000, 0x0000000000000000], // vl2re64.v
    [0x1000000000000000, 0x0000000000000000], // vl2re8.v
    [0x2000000000000000, 0x0000000000000000], // vl4r.v
    [0x1000000000000000, 0x0000000000000000], // vl4re16.v
    [0x1000000000000000, 0x0000000000000000], // vl4re32.v
    [0x1000000000000000, 0x0000000000000000], // vl4re64.v
    [0x1000000000000000, 0x0000000000000000], // vl4re8.v
    [0x2000000000000000, 0x0000000000000000], // vl8r.v
    [0x1000000000000000, 0x0000000000000000], // vl8re16.v
    [0x1000000000000000, 0x0000000000000000], // vl8re32.v
    [0x1000000000000000, 0x0000000000000000], // vl8re64.v
    [0x1000000000000000, 0x0000000000000000], // vl8re8.v
    [0x1000000000000000, 0x0000000000000000], // vle16.v
    [0x1000000000000000, 0x0000000000000000], // vle16ff.v
    [0x2000000000000000, 0x0000000000000000], // vle1.v
    [0x1000000000000000, 0x0000000000000000], // vle32.v
    [0x1000000000000000, 0x0000000000000000], // vle32ff.v
    [0x1000000000000000, 0x0000000000000000], // vle64.v
    [0x1000000000000000, 0x0000000000000000], // vle64ff.v
    [0x1000000000000000, 0x0000000000000000], // vle8.v
    [0x1000000000000000, 0x0000000000000000], // vle8ff.v
    [0x1000000000000000, 0x0000000000000000], // vlm.v
    [0x1000000000000000, 0x0000000000000000], // vloxei16.v
    [0x1000000000000000, 0x0000000000000000], // vloxei32.v
    [0x1000000000000000, 0x0000000000000000], // vloxei64.v
    [0x1000000000000000, 0x0000000000000000], // vloxei8.v
    [0x1000000000000000, 0x0000000000000000], // vlse16.v
    [0x1000000000000000, 0x0000000000000000], // vlse32.v
    [0x1000000000000000, 0x0000000000000000], // vlse64.v
    [0x1000000000000000, 0x0000000000000000], // vlse8.v
    [0x1000000000000000, 0x0000000000000000], // vluxei16.v
    [0x1000000000000000, 0x0000000000000000], // vluxei32.v
    [0x1000000000000000, 0x0000000000000000], // vluxei64.v
    [0x1000000000000000, 0x0000000000000000], // vluxei8.v
    [0x1000000000000000, 0x0000000000000000], // vmacc.vv
    [0x1000000000000000, 0x0000000000000000], // vmacc.vx
    [0x1000000000000000, 0x0000000000000000], // vmadc.vi
    [0x1000000000000000, 0x0000000000000000], // vmadc.vim
    [0x1000000000000000, 0x0000000000000000], // vmadc.vv
    [0x1000000000000000, 0x0000000000000000], // vmadc.vvm
    [0x1000000000000000, 0x0000000000000000], // vmadc.vx
    [0x1000000000000000, 0x0000000000000000], // vmadc.vxm
    [0x1000000000000000, 0x0000000000000000], // vmadd.vv
    [0x1000000000000000, 0x0000000000000000], // vmadd.vx
    [0x1000000000000000, 0x0000000000000000], // vmand.mm
    [0x1000000000000000, 0x0000000000000000], // vmandn.mm
    [0x2000000000000000, 0x0000000000000000], // vmandnot.mm
    [0x1000000000000000, 0x0000000000000000], // vmax.vv
    [0x1000000000000000, 0x0000000000000000], // vmax.vx
    [0x1000000000000000, 0x0000000000000000], // vmaxu.vv
    [0x1000000000000000, 0x0000000000000000], // vmaxu.vx
    [0x1000000000000000, 0x0000000000000000], // vmerge.vim
    [0x1000000000000000, 0x0000000000000000], // vmerge.vvm
    [0x1000000000000000, 0x0000000000000000], // vmerge.vxm
    [0x1000000000000000, 0x0000000000000000], // vmfeq.vf
    [0x1000000000000000, 0x0000000000000000], // vmfeq.vv
    [0x1000000000000000, 0x0000000000000000], // vmfge.vf
    [0x1000000000000000, 0x0000000000000000], // vmfgt.vf
    [0x1000000000000000, 0x0000000000000000], // vmfle.vf
    [0x1000000000000000, 0x0000000000000000], // vmfle.vv
    [0x1000000000000000, 0x0000000000000000], // vmflt.vf
    [0x1000000000000000, 0x0000000000000000], // vmflt.vv
    [0x1000000000000000, 0x0000000000000000], // vmfne.vf
    [0x1000000000000000, 0x0000000000000000], // vmfne.vv
    [0x1000000000000000, 0x0000000000000000], // vmin.vv
    [0x1000000000000000, 0x0000000000000000], // vmin.vx
    [0x1000000000000000, 0x0000000000000000], // vminu.vv
    [0x1000000000000000, 0x0000000000000000], // vminu.vx
    [0x1000000000000000, 0x0000000000000000], // vmnand.mm
    [0x1000000000000000, 0x0000000000000000], // vmnor.mm
    [0x1000000000000000, 0x0000000000000000], // vmor.mm
    [0x1000000000000000, 0x0000000000000000], // vmorn.mm
    [0x2000000000000000, 0x0000000000000000], // vmornot.mm
    [0x1000000000000000, 0x0000000000000000], // vmsbc.vv
    [0x1000000000000000, 0x0000000000000000], // vmsbc.vvm
    [0x1000000000000000, 0x0000000000000000], // vmsbc.vx
    [0x1000000000000000, 0x0000000000000000], // vmsbc.vxm
    [0x1000000000000000, 0x0000000000000000], // vmsbf.m
    [0x1000000000000000, 0x0000000000000000], // vmseq.vi
    [0x1000000000000000, 0x0000000000000000], // vmseq.vv
    [0x1000000000000000, 0x0000000000000000], // vmseq.vx
    [0x1000000000000000, 0x0000000000000000], // vmsgt.vi
    [0x1000000000000000, 0x0000000000000000], // vmsgt.vx
    [0x1000000000000000, 0x0000000000000000], // vmsgtu.vi
    [0x1000000000000000, 0x0000000000000000], // vmsgtu.vx
    [0x1000000000000000, 0x0000000000000000], // vmsif.m
    [0x1000000000000000, 0x0000000000000000], // vmsle.vi
    [0x1000000000000000, 0x0000000000000000], // vmsle.vv
    [0x1000000000000000, 0x0000000000000000], // vmsle.vx
    [0x1000000000000000, 0x0000000000000000], // vmsleu.vi
    [0x1000000000000000, 0x0000000000000000], // vmsleu.vv
    [0x1000000000000000, 0x0000000000000000], // vmsleu.vx
    [0x1000000000000000, 0x0000000000000000], // vmslt.vv
    [0x1000000000000000, 0x0000000000000000], // vmslt.vx
    [0x1000000000000000, 0x0000000000000000], // vmsltu.vv
    [0x1000000000000000, 0x0000000000000000], // vmsltu.vx
    [0x1000000000000000, 0x0000000000000000], // vmsne.vi
    [0x1000000000000000, 0x0000000000000000], // vmsne.vv
    [0x1000000000000000, 0x0000000000000000], // vmsne.vx
    [0x1000000000000000, 0x0000000000000000], // vmsof.m
    [0x1000000000000000, 0x0000000000000000], // vmul.vv
    [0x1000000000000000, 0x0000000000000000], // vmul.vx
    [0x1000000000000000, 0x0000000000000000], // vmulh.vv
    [0x1000000000000000, 0x0000000000000000], // vmulh.vx
    [0x1000000000000000, 0x0000000000000000], // vmulhsu.vv
    [0x1000000000000000, 0x0000000000000000], // vmulhsu.vx
    [0x1000000000000000, 0x0000000000000000], // vmulhu.vv
    [0x1000000000000000, 0x0000000000000000], // vmulhu.vx
    [0x1000000000000000, 0x0000000000000000], // vmv1r.v
    [0x1000000000000000, 0x0000000000000000], // vmv2r.v
    [0x1000000000000000, 0x0000000000000000], // vmv4r.v
    [0x1000000000000000, 0x0000000000000000], // vmv8r.v
    [0x1000000000000000, 0x0000000000000000], // vmv.s.x
    [0x1000000000000000, 0x0000000000000000], // vmv.v.i
    [0x1000000000000000, 0x0000000000000000], // vmv.v.v
    [0x1000000000000000, 0x0000000000000000], // vmv.v.x
    [0x1000000000000000, 0x0000000000000000], // vmv.x.s
    [0x1000000000000000, 0x0000000000000000], // vmxnor.mm
    [0x1000000000000000, 0x0000000000000000], // vmxor.mm
    [0x1000000000000000, 0x0000000000000000], // vnclip.wi
    [0x1000000000000000, 0x0000000000000000], // vnclip.wv
    [0x1000000000000000, 0x0000000000000000], // vnclip.wx
    [0x1000000000000000, 0x0000000000000000], // vnclipu.wi
    [0x1000000000000000, 0x0000000000000000], // vnclipu.wv
    [0x1000000000000000, 0x0000000000000000], // vnclipu.wx
    [0x1000000000000000, 0x0000000000000000], // vnmsac.vv
    [0x1000000000000000, 0x0000000000000000], // vnmsac.vx
    [0x1000000000000000, 0x0000000000000000], // vnmsub.vv
    [0x1000000000000000, 0x0000000000000000], // vnmsub.vx
    [0x1000000000000000, 0x0000000000000000], // vnsra.wi
    [0x1000000000000000, 0x0000000000000000], // vnsra.wv
    [0x1000000000000000, 0x0000000000000000], // vnsra.wx
    [0x1000000000000000, 0x0000000000000000], // vnsrl.wi
    [0x1000000000000000, 0x0000000000000000], // vnsrl.wv
    [0x1000000000000000, 0x0000000000000000], // vnsrl.wx
    [0x1000000000000000, 0x0000000000000000], // vor.vi
    [0x1000000000000000, 0x0000000000000000], // vor.vv
    [0x1000000000000000, 0x0000000000000000], // vor.vx
    [0x2000000000000000, 0x0000000000000000], // vpopc.m
    [0x1000000000000000, 0x0000000000000000], // vredand.vs
    [0x1000000000000000, 0x0000000000000000], // vredmax.vs
    [0x1000000000000000, 0x0000000000000000], // vredmaxu.vs
    [0x1000000000000000, 0x0000000000000000], // vredmin.vs
    [0x1000000000000000, 0x0000000000000000], // vredminu.vs
    [0x1000000000000000, 0x0000000000000000], // vredor.vs
    [0x1000000000000000, 0x0000000000000000], // vredsum.vs
    [0x1000000000000000, 0x0000000000000000], // vredxor.vs
    [0x1000000000000000, 0x0000000000000000], // vrem.vv
    [0x1000000000000000, 0x0000000000000000], // vrem.vx
    [0x1000000000000000, 0x0000000000000000], // vremu.vv
    [0x1000000000000000, 0x0000000000000000], // vremu.vx
    [0x0000000000000000, 0x0000022100000000], // vrev8.v
    [0x1000000000000000, 0x0000000000000000], // vrgather.vi
    [0x1000000000000000, 0x0000000000000000], // vrgather.vv
    [0x1000000000000000, 0x0000000000000000], // vrgather.vx
    [0x1000000000000000, 0x0000000000000000], // vrgatherei16.vv
    [0x0000000000000000, 0x0000022100000000], // vrol.vv
    [0x0000000000000000, 0x0000022100000000], // vrol.vx
    [0x0000000000000000, 0x0000022100000000], // vror.vi
    [0x0000000000000000, 0x0000022100000000], // vror.vv
    [0x0000000000000000, 0x0000022100000000], // vror.vx
    [0x1000000000000000, 0x0000000000000000], // vrsub.vi
    [0x1000000000000000, 0x0000000000000000], // vrsub.vx
    [0x1000000000000000, 0x0000000000000000], // vs1r.v
    [0x1000000000000000, 0x0000000000000000], // vs2r.v
    [0x1000000000000000, 0x0000000000000000], // vs4r.v
    [0x1000000000000000, 0x0000000000000000], // vs8r.v
    [0x1000000000000000, 0x0000000000000000], // vsadd.vi
    [0x1000000000000000, 0x0000000000000000], // vsadd.vv
    [0x1000000000000000, 0x0000000000000000], // vsadd.vx
    [0x1000000000000000, 0x0000000000000000], // vsaddu.vi
    [0x1000000000000000, 0x0000000000000000], // vsaddu.vv
    [0x1000000000000000, 0x0000000000000000], // vsaddu.vx
    [0x1000000000000000, 0x0000000000000000], // vsbc.vvm
    [0x1000000000000000, 0x0000000000000000], // vsbc.vxm
    [0x1000000000000000, 0x0000000000000000], // vse16.v
    [0x2000000000000000, 0x0000000000000000], // vse1.v
    [0x1000000000000000, 0x0000000000000000], // vse32.v
    [0x1000000000000000, 0x0000000000000000], // vse64.v
    [0x1000000000000000, 0x0000000000000000], // vse8.v
    [0x1000000000000000, 0x0000000000000000], // vsetivli
    [0x1000000000000000, 0x0000000000000000], // vsetvl
    [0x1000000000000000, 0x0000000000000000], // vsetvli
    [0x1000000000000000, 0x0000000000000000], // vsext.vf2
    [0x1000000000000000, 0x0000000000000000], // vsext.vf4
    [0x1000000000000000, 0x0000000000000000], // vsext.vf8
    [0x0000000000000000, 0x000001a000000000], // vsha2ch.vv
    [0x0000000000000000, 0x000001a000000000], // vsha2cl.vv
    [0x0000000000000000, 0x000001a000000000], // vsha2ms.vv
    [0x1000000000000000, 0x0000000000000000], // vslide1down.vx
    [0x1000000000000000, 0x0000000000000000], // vslide1up.vx
    [0x1000000000000000, 0x0000000000000000], // vslidedown.vi
    [0x1000000000000000, 0x0000000000000000], // vslidedown.vx
    [0x1000000000000000, 0x0000000000000000], // vslideup.vi
    [0x1000000000000000, 0x0000000000000000], // vslideup.vx
    [0x1000000000000000, 0x0000000000000000], // vsll.vi
    [0x1000000000000000, 0x0000000000000000], // vsll.vv
    [0x1000000000000000, 0x0000000000000000], // vsll.vx
    [0x0000000000000000, 0x00000a0000000000], // vsm3c.vi
    [0x0000000000000000, 0x00000a0000000000], // vsm3me.vv
    [0x0000000000000000, 0x0000060000000000], // vsm4k.vi
    [0x0000000000000000, 0x0000060000000000], // vsm4r.vs
    [0x0000000000000000, 0x0000060000000000], // vsm4r.vv
    [0x1000000000000000, 0x0000000000000000], // vsm.v
    [0x1000000000000000, 0x0000000000000000], // vsmul.vv
    [0x1000000000000000, 0x0000000000000000], // vsmul.vx
    [0x1000000000000000, 0x0000000000000000], // vsoxei16.v
    [0x1000000000000000, 0x0000000000000000], // vsoxei32.v
    [0x1000000000000000, 0x0000000000000000], // vsoxei64.v
    [0x1000000000000000, 0x0000000000000000], // vsoxei8.v
    [0x1000000000000000, 0x0000000000000000], // vsra.vi
    [0x1000000000000000, 0x0000000000000000], // vsra.vv
    [0x1000000000000000, 0x0000000000000000], // vsra.vx
    [0x1000000000000000, 0x0000000000000000], // vsrl.vi
    [0x1000000000000000, 0x0000000000000000], // vsrl.vv
    [0x1000000000000000, 0x0000000000000000], // vsrl.vx
    [0x1000000000000000, 0x0000000000000000], // vsse16.v
    [0x1000000000000000, 0x0000000000000000], // vsse32.v
    [0x1000000000000000, 0x0000000000000000], // vsse64.v
    [0x1000000000000000, 0x0000000000000000], // vsse8.v
    [0x1000000000000000, 0x0000000000000000], // vssra.vi
    [0x1000000000000000, 0x0000000000000000], // vssra.vv
    [0x1000000000000000, 0x0000000000000000], // vssra.vx
    [0x1000000000000000, 0x0000000000000000], // vssrl.vi
    [0x1000000000000000, 0x0000000000000000], // vssrl.vv
    [0x1000000000000000, 0x0000000000000000], // vssrl.vx
    [0x1000000000000000, 0x0000000000000000], // vssub.vv
    [0x1000000000000000, 0x0000000000000000], // vssub.vx
    [0x1000000000000000, 0x0000000000000000], // vssubu.vv
    [0x1000000000000000, 0x0000000000000000], // vssubu.vx
    [0x1000000000000000, 0x0000000000000000], // vsub.vv
    [0x1000000000000000, 0x0000000000000000], // vsub.vx
    [0x1000000000000000, 0x0000000000000000], // vsuxei16.v
    [0x1000000000000000, 0x0000000000000000], // vsuxei32.v
    [0x1000000000000000, 0x0000000000000000], // vsuxei64.v
    [0x1000000000000000, 0x0000000000000000], // vsuxei8.v
    [0x1000000000000000, 0x0000000000000000], // vwadd.vv
    [0x1000000000000000, 0x0000000000000000], // vwadd.vx
    [0x1000000000000000, 0x0000000000000000], // vwadd.wv
    [0x1000000000000000, 0x0000000000000000], // vwadd.wx
    [0x1000000000000000, 0x0000000000000000], // vwaddu.vv
    [0x1000000000000000, 0x0000000000000000], // vwaddu.vx
    [0x1000000000000000, 0x0000000000000000], // vwaddu.wv
    [0x1000000000000000, 0x0000000000000000], // vwaddu.wx
    [0x1000000000000000, 0x0000000000000000], // vwmacc.vv
    [0x1000000000000000, 0x0000000000000000], // vwmacc.vx
    [0x1000000000000000, 0x0000000000000000], // vwmaccsu.vv
    [0x1000000000000000, 0x0000000000000000], // vwmaccsu.vx
    [0x1000000000000000, 0x0000000000000000], // vwmaccu.vv
    [0x1000000000000000, 0x0000000000000000], // vwmaccu.vx
    [0x1000000000000000, 0x0000000000000000], // vwmaccus.vx
    [0x1000000000000000, 0x0000000000000000], // vwmul.vv
    [0x1000000000000000, 0x0000000000000000], // vwmul.vx
    [0x1000000000000000, 0x0000000000000000], // vwmulsu.vv
    [0x1000000000000000, 0x0000000000000000], // vwmulsu.vx
    [0x1000000000000000, 0x0000000000000000], // vwmulu.vv
    [0x1000000000000000, 0x0000000000000000], // vwmulu.vx
    [0x1000000000000000, 0x0000000000000000], // vwredsum.vs
    [0x1000000000000000, 0x0000000000000000], // vwredsumu.vs
    [0x0000000000000000, 0x0000000100000000], // vwsll.vi
    [0x0000000000000000, 0x0000000100000000], // vwsll.vv
    [0x0000000000000000, 0x0000000100000000], // vwsll.vx
    [0x1000000000000000, 0x0000000000000000], // vwsub.vv
    [0x1000000000000000, 0x0000000000000000], // vwsub.vx
    [0x1000000000000000, 0x0000000000000000], // vwsub.wv
    [0x1000000000000000, 0x0000000000000000], // vwsub.wx
    [0x1000000000000000, 0x0000000000000000], // vwsubu.vv
    [0x1000000000000000, 0x0000000000000000], // vwsubu.vx
    [0x1000000000000000, 0x0000000000000000], // vwsubu.wv
    [0x1000000000000000, 0x0000000000000000], // vwsubu.wx
    [0x1000000000000000, 0x0000000000000000], // vxor.vi
    [0x1000000000000000, 0x0000000000000000], // vxor.vv
    [0x1000000000000000, 0x0000000000000000], // vxor.vx
    [0x1000000000000000, 0x0000000000000000], // vzext.vf2
    [0x1000000000000000, 0x0000000000000000], // vzext.vf4
    [0x1000000000000000, 0x0000000000000000], // vzext.vf8
    [0x0800000000000000, 0x0000000000000000], // wfi
    [0x0000000000000000, 0x0000000000000002], // wrs.nto
    [0x0000000000000000, 0x0000000000000002], // wrs.sto
    [0x0000000000000000, 0x000000002c000028], // xnor
    [0x0001000000000000, 0x0000000000000000], // xor
    [0x0001000000000000, 0x0000000000000000], // xori
    [0x0000000000000000, 0x000000002c000080], // xperm4
    [0x0000000000000000, 0x000000002c000080], // xperm8
    [0x0001000000000000, 0x0000000000000000], // zext.b
    [0x0000000004000000, 0x0000000000000000], // zext.h
    [0x0000000000000010, 0x0000000000000000], // zext.h.rv32
    [0x0000000002000000, 0x0000000000000000], // zext.w
    [0x0000000000004620, 0x0000000000000000], // zip
];

/// Missing-feature diagnostics, indexed by `Opcode as usize`.
pub static OPCODE_FEATURE_CONTEXT: [&str; 1039] = [
    "add requires one of: rv_i",
    "add.uw requires one of: rv64_zba",
    "addi requires one of: rv_i",
    "addiw requires one of: rv64_i",
    "addw requires one of: rv64_i",
    "aes32dsi requires one of: rv32_zknd, rv32_zkn, rv32_zk",
    "aes32dsmi requires one of: rv32_zknd, rv32_zkn, rv32_zk",
    "aes32esi requires one of: rv32_zkne, rv32_zkn, rv32_zk",
    "aes32esmi requires one of: rv32_zkne, rv32_zkn, rv32_zk",
    "aes64ds requires one of: rv64_zknd, rv64_zkn, rv64_zk",
    "aes64dsm requires one of: rv64_zknd, rv64_zkn, rv64_zk",
    "aes64es requires one of: rv64_zkne, rv64_zkn, rv64_zk",
    "aes64esm requires one of: rv64_zkne, rv64_zkn, rv64_zk",
    "aes64im requires one of: rv64_zknd, rv64_zkn, rv64_zk",
    "aes64ks1i requires one of: rv64_zknd, rv64_zkne, rv64_zkn, rv64_zk",
    "aes64ks2 requires one of: rv64_zknd, rv64_zkne, rv64_zkn, rv64_zk",
    "amoadd.b requires one of: rv_zabha",
    "amoadd.d requires one of: rv64_a",
    "amoadd.h requires one of: rv_zabha",
    "amoadd.w requires one of: rv_a",
    "amoand.b requires one of: rv_zabha",
    "amoand.d requires one of: rv64_a",
    "amoand.h requires one of: rv_zabha",
    "amoand.w requires one of: rv_a",
    "amocas.b requires one of: rv_zabha_zacas",
    "amocas.d requires one of: rv_zacas",
    "amocas.h requires one of: rv_zabha_zacas",
    "amocas.q requires one of: rv64_zacas",
    "amocas.w requires one of: rv_zacas",
    "amomax.b requires one of: rv_zabha",
    "amomax.d requires one of: rv64_a",
    "amomax.h requires one of: rv_zabha",
    "amomax.w requires one of: rv_a",
    "amomaxu.b requires one of: rv_zabha",
    "amomaxu.d requires one of: rv64_a",
    "amomaxu.h requires one of: rv_zabha",
    "amomaxu.w requires one of: rv_a",
    "amomin.b requires one of: rv_zabha",
    "amomin.d requires one of: rv64_a",
    "amomin.h requires one of: rv_zabha",
    "amomin.w requires one of: rv_a",
    "amominu.b requires one of: rv_zabha",
    "amominu.d requires one of: rv64_a",
    "amominu.h requires one of: rv_zabha",
    "amominu.w requires one of: rv_a",
    "amoor.b requires one of: rv_zabha",
    "amoor.d requires one of: rv64_a",
    "amoor.h requires one of: rv_zabha",
    "amoor.w requires one of: rv_a",
    "amoswap.b requires one of: rv_zabha",
    "amoswap.d requires one of: rv64_a",
    "amoswap.h requires one of: rv_zabha",
    "amoswap.w requires one of: rv_a",
    "amoxor.b requires one of: rv_zabha",
    "amoxor.d requires one of: rv64_a",
    "amoxor.h requires one of: rv_zabha",
    "amoxor.w requires one of: rv_a",
    "and requires one of: rv_i",
    "andi requires one of: rv_i",
    "andn requires one of: rv_zbb, rv_zks, rv_zkn, rv_zk, rv_zbkb",
    "auipc requires one of: rv_i",
    "bclr requires one of: rv_zbs",
    "bclri requires one of: rv64_zbs",
    "bclri.rv32 requires one of: rv32_zbs",
    "beq requires one of: rv_i",
    "beqz requires one of: rv_i",
    "bext requires one of: rv_zbs",
    "bexti requires one of: rv64_zbs",
    "bexti.rv32 requires one of: rv32_zbs",
    "bge requires one of: rv_i",
    "bgeu requires one of: rv_i",
    "bgez requires one of: rv_i",
    "bgt requires one of: rv_i",
    "bgtu requires one of: rv_i",
    "bgtz requires one of: rv_i",
    "binv requires one of: rv_zbs",
    "binvi requires one of: rv64_zbs",
    "binvi.rv32 requires one of: rv32_zbs",
    "ble requires one of: rv_i",
    "bleu requires one of: rv_i",
    "blez requires one of: rv_i",
    "blt requires one of: rv_i",
    "bltu requires one of: rv_i",
    "bltz requires one of: rv_i",
    "bne requires one of: rv_i",
    "bnez requires one of: rv_i",
    "brev8 requires one of: rv_zbkb, rv_zks, rv_zkn, rv_zk",
    "bset requires one of: rv_zbs",
    "bseti requires one of: rv64_zbs",
    "bseti.rv32 requires one of: rv32_zbs",
    "c.add requires one of: rv_c",
    "c.addi requires one of: rv_c",
    "c.addi16sp requires one of: rv_c",
    "c.addi4spn requires one of: rv_c",
    "c.addiw requires one of: rv64_c",
    "c.addw requires one of: rv64_c",
    "c.and requires one of: rv_c",
    "c.andi requires one of: rv_c",
    "c.beqz requires one of: rv_c",
    "c.bnez requires one of: rv_c",
    "c.ebreak requires one of: rv_c",
    "c.fld requires one of: rv_c_d",
    "c.fldsp requires one of: rv_c_d",
    "c.flw requires one of: rv32_c_f",
    "c.flwsp requires one of: rv32_c_f",
    "c.fsd requires one of: rv_c_d",
    "c.fsdsp requires one of: rv_c_d",
    "c.fsw requires one of: rv32_c_f",
    "c.fswsp requires one of: rv32_c_f",
    "c.j requires one of: rv_c",
    "c.jal requires one of: rv32_c",
    "c.jalr requires one of: rv_c",
    "c.jr requires one of: rv_c",
    "c.lbu requires one of: rv_zcb",
    "c.ld requires one of: rv64_c, rv32_zclsd",
    "c.ldsp requires one of: rv64_c, rv32_zclsd",
    "c.lh requires one of: rv_zcb",
    "c.lhu requires one of: rv_zcb",
    "c.li requires one of: rv_c",
    "c.lui requires one of: rv_c",
    "c.lw requires one of: rv_c",
    "c.lwsp requires one of: rv_c",
    "c.mop.1 requires one of: rv_zcmop",
    "c.mop.11 requires one of: rv_zcmop",
    "c.mop.13 requires one of: rv_zcmop",
    "c.mop.15 requires one of: rv_zcmop",
    "c.mop.3 requires one of: rv_zcmop",
    "c.mop.5 requires one of: rv_zcmop",
    "c.mop.7 requires one of: rv_zcmop",
    "c.mop.9 requires one of: rv_zcmop",
    "c.mop.n requires one of: rv_zcmop",
    "c.mul requires one of: rv_zcb",
    "c.mv requires one of: rv_c",
    "c.nop requires one of: rv_c",
    "c.not requires one of: rv_zcb",
    "c.ntl.all requires one of: rv_c_zihintntl",
    "c.ntl.p1 requires one of: rv_c_zihintntl",
    "c.ntl.pall requires one of: rv_c_zihintntl",
    "c.ntl.s1 requires one of: rv_c_zihintntl",
    "c.or requires one of: rv_c",
    "c.sb requires one of: rv_zcb",
    "c.sd requires one of: rv64_c, rv32_zclsd",
    "c.sdsp requires one of: rv64_c, rv32_zclsd",
    "c.sext.b requires one of: rv_zcb",
    "c.sext.h requires one of: rv_zcb",
    "c.sext.w requires one of: rv64_zcb",
    "c.sh requires one of: rv_zcb",
    "c.slli requires one of: rv64_c, rv32_c",
    "c.slli.rv32 requires one of: rv32_c",
    "c.srai requires one of: rv64_c, rv32_c",
    "c.srai.rv32 requires one of: rv32_c",
    "c.srli requires one of: rv64_c, rv32_c",
    "c.srli.rv32 requires one of: rv32_c",
    "c.sspopchk.x5 requires one of: rv_c_zicfiss",
    "c.sspush.x1 requires one of: rv_c_zicfiss",
    "c.sub requires one of: rv_c",
    "c.subw requires one of: rv64_c",
    "c.sw requires one of: rv_c",
    "c.swsp requires one of: rv_c",
    "c.xor requires one of: rv_c",
    "c.zext.b requires one of: rv_zcb",
    "c.zext.h requires one of: rv_zcb",
    "c.zext.w requires one of: rv64_zcb",
    "cbo.clean requires one of: rv_zicbo",
    "cbo.flush requires one of: rv_zicbo",
    "cbo.inval requires one of: rv_zicbo",
    "cbo.zero requires one of: rv_zicbo",
    "clmul requires one of: rv_zbc, rv_zks, rv_zkn, rv_zk, rv_zbkc",
    "clmulh requires one of: rv_zbc, rv_zks, rv_zkn, rv_zk, rv_zbkc",
    "clmulr requires one of: rv_zbc",
    "clz requires one of: rv_zbb",
    "clzw requires one of: rv64_zbb",
    "cm.jalt requires one of: rv_zcmt",
    "cm.mva01s requires one of: rv_zcmp",
    "cm.mvsa01 requires one of: rv_zcmp",
    "cm.pop requires one of: rv_zcmp",
    "cm.popret requires one of: rv_zcmp",
    "cm.popretz requires one of: rv_zcmp",
    "cm.push requires one of: rv_zcmp",
    "cpop requires one of: rv_zbb",
    "cpopw requires one of: rv64_zbb",
    "csrc requires one of: rv_zicsr",
    "csrci requires one of: rv_zicsr",
    "csrr requires one of: rv_zicsr",
    "csrrc requires one of: rv_zicsr",
    "csrrci requires one of: rv_zicsr",
    "csrrs requires one of: rv_zicsr",
    "csrrsi requires one of: rv_zicsr",
    "csrrw requires one of: rv_zicsr",
    "csrrwi requires one of: rv_zicsr",
    "csrs requires one of: rv_zicsr",
    "csrsi requires one of: rv_zicsr",
    "csrw requires one of: rv_zicsr",
    "csrwi requires one of: rv_zicsr",
    "ctz requires one of: rv_zbb",
    "ctzw requires one of: rv64_zbb",
    "czero.eqz requires one of: rv_zicond",
    "czero.nez requires one of: rv_zicond",
    "div requires one of: rv_m",
    "divu requires one of: rv_m",
    "divuw requires one of: rv64_m",
    "divw requires one of: rv64_m",
    "dret requires one of: rv_sdext",
    "ebreak requires one of: rv_i",
    "ecall requires one of: rv_i",
    "fabs.d requires one of: rv_d",
    "fabs.h requires one of: rv_zfh",
    "fabs.q requires one of: rv_q",
    "fabs.s requires one of: rv_f",
    "fadd.d requires one of: rv_d",
    "fadd.h requires one of: rv_zfh",
    "fadd.q requires one of: rv_q",
    "fadd.s requires one of: rv_f",
    "fclass.d requires one of: rv_d",
    "fclass.h requires one of: rv_zfh",
    "fclass.q requires one of: rv_q",
    "fclass.s requires one of: rv_f",
    "fcvt.bf16.s requires one of: rv_zfbfmin",
    "fcvt.d.h requires one of: rv_d_zfhmin",
    "fcvt.d.l requires one of: rv64_d",
    "fcvt.d.lu requires one of: rv64_d",
    "fcvt.d.q requires one of: rv_q",
    "fcvt.d.s requires one of: rv_d",
    "fcvt.d.w requires one of: rv_d",
    "fcvt.d.wu requires one of: rv_d",
    "fcvt.h.d requires one of: rv_d_zfhmin",
    "fcvt.h.l requires one of: rv64_zfh",
    "fcvt.h.lu requires one of: rv64_zfh",
    "fcvt.h.q requires one of: rv_q_zfhmin",
    "fcvt.h.s requires one of: rv_zfhmin",
    "fcvt.h.w requires one of: rv_zfh",
    "fcvt.h.wu requires one of: rv_zfh",
    "fcvt.l.d requires one of: rv64_d",
    "fcvt.l.h requires one of: rv64_zfh",
    "fcvt.l.q requires one of: rv64_q",
    "fcvt.l.s requires one of: rv64_f",
    "fcvt.lu.d requires one of: rv64_d",
    "fcvt.lu.h requires one of: rv64_zfh",
    "fcvt.lu.q requires one of: rv64_q",
    "fcvt.lu.s requires one of: rv64_f",
    "fcvt.q.d requires one of: rv_q",
    "fcvt.q.h requires one of: rv_q_zfhmin",
    "fcvt.q.l requires one of: rv64_q",
    "fcvt.q.lu requires one of: rv64_q",
    "fcvt.q.s requires one of: rv_q",
    "fcvt.q.w requires one of: rv_q",
    "fcvt.q.wu requires one of: rv_q",
    "fcvt.s.bf16 requires one of: rv_zfbfmin",
    "fcvt.s.d requires one of: rv_d",
    "fcvt.s.h requires one of: rv_zfhmin",
    "fcvt.s.l requires one of: rv64_f",
    "fcvt.s.lu requires one of: rv64_f",
    "fcvt.s.q requires one of: rv_q",
    "fcvt.s.w requires one of: rv_f",
    "fcvt.s.wu requires one of: rv_f",
    "fcvt.w.d requires one of: rv_d",
    "fcvt.w.h requires one of: rv_zfh",
    "fcvt.w.q requires one of: rv_q",
    "fcvt.w.s requires one of: rv_f",
    "fcvt.wu.d requires one of: rv_d",
    "fcvt.wu.h requires one of: rv_zfh",
    "fcvt.wu.q requires one of: rv_q",
    "fcvt.wu.s requires one of: rv_f",
    "fcvtmod.w.d requires one of: rv_d_zfa",
    "fdiv.d requires one of: rv_d",
    "fdiv.h requires one of: rv_zfh",
    "fdiv.q requires one of: rv_q",
    "fdiv.s requires one of: rv_f",
    "fence requires one of: rv_i",
    "fence.i requires one of: rv_zifencei",
    "fence.tso requires one of: rv_i",
    "feq.d requires one of: rv_d",
    "feq.h requires one of: rv_zfh",
    "feq.q requires one of: rv_q",
    "feq.s requires one of: rv_f",
    "fld requires one of: rv_d",
    "fle.d requires one of: rv_d",
    "fle.h requires one of: rv_zfh",
    "fle.q requires one of: rv_q",
    "fle.s requires one of: rv_f",
    "fleq.d requires one of: rv_d_zfa",
    "fleq.h requires one of: rv_zfh_zfa",
    "fleq.q requires one of: rv_q_zfa",
    "fleq.s requires one of: rv_f_zfa",
    "flh requires one of: rv_zfhmin",
    "fli.d requires one of: rv_d_zfa",
    "fli.h requires one of: rv_zfh_zfa",
    "fli.q requires one of: rv_q_zfa",
    "fli.s requires one of: rv_f_zfa",
    "flq requires one of: rv_q",
    "flt.d requires one of: rv_d",
    "flt.h requires one of: rv_zfh",
    "flt.q requires one of: rv_q",
    "flt.s requires one of: rv_f",
    "fltq.d requires one of: rv_d_zfa",
    "fltq.h requires one of: rv_zfh_zfa",
    "fltq.q requires one of: rv_q_zfa",
    "fltq.s requires one of: rv_f_zfa",
    "flw requires one of: rv_f",
    "fmadd.d requires one of: rv_d",
    "fmadd.h requires one of: rv_zfh",
    "fmadd.q requires one of: rv_q",
    "fmadd.s requires one of: rv_f",
    "fmax.d requires one of: rv_d",
    "fmax.h requires one of: rv_zfh",
    "fmax.q requires one of: rv_q",
    "fmax.s requires one of: rv_f",
    "fmaxm.d requires one of: rv_d_zfa",
    "fmaxm.h requires one of: rv_zfh_zfa",
    "fmaxm.q requires one of: rv_q_zfa",
    "fmaxm.s requires one of: rv_f_zfa",
    "fmin.d requires one of: rv_d",
    "fmin.h requires one of: rv_zfh",
    "fmin.q requires one of: rv_q",
    "fmin.s requires one of: rv_f",
    "fminm.d requires one of: rv_d_zfa",
    "fminm.h requires one of: rv_zfh_zfa",
    "fminm.q requires one of: rv_q_zfa",
    "fminm.s requires one of: rv_f_zfa",
    "fmsub.d requires one of: rv_d",
    "fmsub.h requires one of: rv_zfh",
    "fmsub.q requires one of: rv_q",
    "fmsub.s requires one of: rv_f",
    "fmul.d requires one of: rv_d",
    "fmul.h requires one of: rv_zfh",
    "fmul.q requires one of: rv_q",
    "fmul.s requires one of: rv_f",
    "fmv.d requires one of: rv_d",
    "fmv.d.x requires one of: rv64_d",
    "fmv.h requires one of: rv_zfh",
    "fmv.h.x requires one of: rv_zfhmin",
    "fmv.q requires one of: rv_q",
    "fmv.s requires one of: rv_f",
    "fmv.s.x requires one of: rv_f",
    "fmv.w.x requires one of: rv_f",
    "fmv.x.d requires one of: rv64_d",
    "fmv.x.h requires one of: rv_zfhmin",
    "fmv.x.s requires one of: rv_f",
    "fmv.x.w requires one of: rv_f",
    "fmvh.x.d requires one of: rv32_d_zfa",
    "fmvh.x.q requires one of: rv64_q_zfa",
    "fmvp.d.x requires one of: rv32_d_zfa",
    "fmvp.q.x requires one of: rv64_q_zfa",
    "fneg.d requires one of: rv_d",
    "fneg.h requires one of: rv_zfh",
    "fneg.q requires one of: rv_q",
    "fneg.s requires one of: rv_f",
    "fnmadd.d requires one of: rv_d",
    "fnmadd.h requires one of: rv_zfh",
    "fnmadd.q requires one of: rv_q",
    "fnmadd.s requires one of: rv_f",
    "fnmsub.d requires one of: rv_d",
    "fnmsub.h requires one of: rv_zfh",
    "fnmsub.q requires one of: rv_q",
    "fnmsub.s requires one of: rv_f",
    "frcsr requires one of: rv_f",
    "frflags requires one of: rv_f",
    "fround.d requires one of: rv_d_zfa",
    "fround.h requires one of: rv_zfh_zfa",
    "fround.q requires one of: rv_q_zfa",
    "fround.s requires one of: rv_f_zfa",
    "froundnx.d requires one of: rv_d_zfa",
    "froundnx.h requires one of: rv_zfh_zfa",
    "froundnx.q requires one of: rv_q_zfa",
    "froundnx.s requires one of: rv_f_zfa",
    "frrm requires one of: rv_f",
    "fscsr requires one of: rv_f",
    "fsd requires one of: rv_d",
    "fsflags requires one of: rv_f",
    "fsflagsi requires one of: rv_f",
    "fsgnj.d requires one of: rv_d",
    "fsgnj.h requires one of: rv_zfh",
    "fsgnj.q requires one of: rv_q",
    "fsgnj.s requires one of: rv_f",
    "fsgnjn.d requires one of: rv_d",
    "fsgnjn.h requires one of: rv_zfh",
    "fsgnjn.q requires one of: rv_q",
    "fsgnjn.s requires one of: rv_f",
    "fsgnjx.d requires one of: rv_d",
    "fsgnjx.h requires one of: rv_zfh",
    "fsgnjx.q requires one of: rv_q",
    "fsgnjx.s requires one of: rv_f",
    "fsh requires one of: rv_zfhmin",
    "fsq requires one of: rv_q",
    "fsqrt.d requires one of: rv_d",
    "fsqrt.h requires one of: rv_zfh",
    "fsqrt.q requires one of: rv_q",
    "fsqrt.s requires one of: rv_f",
    "fsrm requires one of: rv_f",
    "fsrmi requires one of: rv_f",
    "fsub.d requires one of: rv_d",
    "fsub.h requires one of: rv_zfh",
    "fsub.q requires one of: rv_q",
    "fsub.s requires one of: rv_f",
    "fsw requires one of: rv_f",
    "hfence.gvma requires one of: rv_h",
    "hfence.vvma requires one of: rv_h",
    "hinval.gvma requires one of: rv_svinval_h",
    "hinval.vvma requires one of: rv_svinval_h",
    "hlv.b requires one of: rv_h",
    "hlv.bu requires one of: rv_h",
    "hlv.d requires one of: rv64_h",
    "hlv.h requires one of: rv_h",
    "hlv.hu requires one of: rv_h",
    "hlv.w requires one of: rv_h",
    "hlv.wu requires one of: rv64_h",
    "hlvx.hu requires one of: rv_h",
    "hlvx.wu requires one of: rv_h",
    "hsv.b requires one of: rv_h",
    "hsv.d requires one of: rv64_h",
    "hsv.h requires one of: rv_h",
    "hsv.w requires one of: rv_h",
    "j requires one of: rv_i",
    "jal requires one of: rv_i",
    "jal.pseudo requires one of: rv_i",
    "jalr requires one of: rv_i",
    "jalr.pseudo requires one of: rv_i",
    "jr requires one of: rv_i",
    "lb requires one of: rv_i",
    "lbu requires one of: rv_i",
    "ld requires one of: rv64_i",
    "lh requires one of: rv_i",
    "lhu requires one of: rv_i",
    "lpad requires one of: rv_zicfilp",
    "lr.d requires one of: rv64_a",
    "lr.w requires one of: rv_a",
    "lui requires one of: rv_i",
    "lw requires one of: rv_i",
    "lwu requires one of: rv64_i",
    "max requires one of: rv_zbb",
    "maxu requires one of: rv_zbb",
    "min requires one of: rv_zbb",
    "minu requires one of: rv_zbb",
    "mnret requires one of: rv_smrnmi",
    "mop.r.0 requires one of: rv_zimop",
    "mop.r.1 requires one of: rv_zimop",
    "mop.r.10 requires one of: rv_zimop",
    "mop.r.11 requires one of: rv_zimop",
    "mop.r.12 requires one of: rv_zimop",
    "mop.r.13 requires one of: rv_zimop",
    "mop.r.14 requires one of: rv_zimop",
    "mop.r.15 requires one of: rv_zimop",
    "mop.r.16 requires one of: rv_zimop",
    "mop.r.17 requires one of: rv_zimop",
    "mop.r.18 requires one of: rv_zimop",
    "mop.r.19 requires one of: rv_zimop",
    "mop.r.2 requires one of: rv_zimop",
    "mop.r.20 requires one of: rv_zimop",
    "mop.r.21 requires one of: rv_zimop",
    "mop.r.22 requires one of: rv_zimop",
    "mop.r.23 requires one of: rv_zimop",
    "mop.r.24 requires one of: rv_zimop",
    "mop.r.25 requires one of: rv_zimop",
    "mop.r.26 requires one of: rv_zimop",
    "mop.r.27 requires one of: rv_zimop",
    "mop.r.28 requires one of: rv_zimop",
    "mop.r.29 requires one of: rv_zimop",
    "mop.r.3 requires one of: rv_zimop",
    "mop.r.30 requires one of: rv_zimop",
    "mop.r.31 requires one of: rv_zimop",
    "mop.r.4 requires one of: rv_zimop",
    "mop.r.5 requires one of: rv_zimop",
    "mop.r.6 requires one of: rv_zimop",
    "mop.r.7 requires one of: rv_zimop",
    "mop.r.8 requires one of: rv_zimop",
    "mop.r.9 requires one of: rv_zimop",
    "mop.r.n requires one of: rv_zimop",
    "mop.rr.0 requires one of: rv_zimop",
    "mop.rr.1 requires one of: rv_zimop",
    "mop.rr.2 requires one of: rv_zimop",
    "mop.rr.3 requires one of: rv_zimop",
    "mop.rr.4 requires one of: rv_zimop",
    "mop.rr.5 requires one of: rv_zimop",
    "mop.rr.6 requires one of: rv_zimop",
    "mop.rr.7 requires one of: rv_zimop",
    "mop.rr.n requires one of: rv_zimop",
    "mret requires one of: rv_system",
    "mul requires one of: rv_m",
    "mulh requires one of: rv_m",
    "mulhsu requires one of: rv_m",
    "mulhu requires one of: rv_m",
    "mulw requires one of: rv64_m",
    "mv requires one of: rv_i",
    "neg requires one of: rv_i",
    "nop requires one of: rv_i",
    "ntl.all requires one of: rv_zihintntl",
    "ntl.p1 requires one of: rv_zihintntl",
    "ntl.pall requires one of: rv_zihintntl",
    "ntl.s1 requires one of: rv_zihintntl",
    "or requires one of: rv_i",
    "orc.b requires one of: rv_zbb",
    "ori requires one of: rv_i",
    "orn requires one of: rv_zbb, rv_zks, rv_zkn, rv_zk, rv_zbkb",
    "pack requires one of: rv_zbkb, rv_zks, rv_zkn, rv_zk",
    "packh requires one of: rv_zbkb, rv_zks, rv_zkn, rv_zk",
    "packw requires one of: rv64_zbkb, rv64_zks, rv64_zkn, rv64_zk",
    "pause requires one of: rv_i",
    "prefetch.i requires one of: rv_zicbo",
    "prefetch.r requires one of: rv_zicbo",
    "prefetch.w requires one of: rv_zicbo",
    "rdcycle requires one of: rv_zicntr",
    "rdcycleh requires one of: rv32_zicntr",
    "rdinstret requires one of: rv_zicntr",
    "rdinstreth requires one of: rv32_zicntr",
    "rdtime requires one of: rv_zicntr",
    "rdtimeh requires one of: rv32_zicntr",
    "rem requires one of: rv_m",
    "remu requires one of: rv_m",
    "remuw requires one of: rv64_m",
    "remw requires one of: rv64_m",
    "ret requires one of: rv_i",
    "rev8 requires one of: rv64_zbb, rv64_zks, rv64_zkn, rv64_zk, rv64_zbkb",
    "rev8.rv32 requires one of: rv32_zbkb, rv32_zks, rv32_zkn, rv32_zk, rv32_zbb",
    "rol requires one of: rv_zbb, rv_zks, rv_zkn, rv_zk, rv_zbkb",
    "rolw requires one of: rv64_zbb, rv64_zks, rv64_zkn, rv64_zk, rv64_zbkb",
    "ror requires one of: rv_zbb, rv_zks, rv_zkn, rv_zk, rv_zbkb",
    "rori requires one of: rv64_zbb, rv64_zks, rv64_zkn, rv64_zk, rv64_zbkb",
    "rori.rv32 requires one of: rv32_zks, rv32_zkn, rv32_zk, rv32_zbkb, rv32_zbb",
    "roriw requires one of: rv64_zbb, rv64_zks, rv64_zkn, rv64_zk, rv64_zbkb",
    "rorw requires one of: rv64_zbb, rv64_zks, rv64_zkn, rv64_zk, rv64_zbkb",
    "sb requires one of: rv_i",
    "sbreak requires one of: rv_i",
    "sc.d requires one of: rv64_a",
    "sc.w requires one of: rv_a",
    "scall requires one of: rv_i",
    "sctrclr requires one of: rv_ssctr",
    "sd requires one of: rv64_i",
    "seqz requires one of: rv_i",
    "sext.b requires one of: rv_zbb",
    "sext.h requires one of: rv_zbb",
    "sext.w requires one of: rv64_i",
    "sfence.inval.ir requires one of: rv_svinval",
    "sfence.vma requires one of: rv_s",
    "sfence.w.inval requires one of: rv_svinval",
    "sgtz requires one of: rv_i",
    "sh requires one of: rv_i",
    "sh1add requires one of: rv_zba",
    "sh1add.uw requires one of: rv64_zba",
    "sh2add requires one of: rv_zba",
    "sh2add.uw requires one of: rv64_zba",
    "sh3add requires one of: rv_zba",
    "sh3add.uw requires one of: rv64_zba",
    "sha256sig0 requires one of: rv_zknh, rv_zkn, rv_zk",
    "sha256sig1 requires one of: rv_zknh, rv_zkn, rv_zk",
    "sha256sum0 requires one of: rv_zknh, rv_zkn, rv_zk",
    "sha256sum1 requires one of: rv_zknh, rv_zkn, rv_zk",
    "sha512sig0 requires one of: rv64_zknh, rv64_zkn, rv64_zk",
    "sha512sig0h requires one of: rv32_zknh, rv32_zkn, rv32_zk",
    "sha512sig0l requires one of: rv32_zknh, rv32_zkn, rv32_zk",
    "sha512sig1 requires one of: rv64_zknh, rv64_zkn, rv64_zk",
    "sha512sig1h requires one of: rv32_zknh, rv32_zkn, rv32_zk",
    "sha512sig1l requires one of: rv32_zknh, rv32_zkn, rv32_zk",
    "sha512sum0 requires one of: rv64_zknh, rv64_zkn, rv64_zk",
    "sha512sum0r requires one of: rv32_zknh, rv32_zkn, rv32_zk",
    "sha512sum1 requires one of: rv64_zknh, rv64_zkn, rv64_zk",
    "sha512sum1r requires one of: rv32_zknh, rv32_zkn, rv32_zk",
    "sinval.vma requires one of: rv_svinval",
    "sll requires one of: rv_i",
    "slli requires one of: rv64_i, rv32_i",
    "slli.rv32 requires one of: rv32_i",
    "slli.uw requires one of: rv64_zba",
    "slliw requires one of: rv64_i",
    "sllw requires one of: rv64_i",
    "slt requires one of: rv_i",
    "slti requires one of: rv_i",
    "sltiu requires one of: rv_i",
    "sltu requires one of: rv_i",
    "sltz requires one of: rv_i",
    "sm3p0 requires one of: rv_zksh, rv_zks",
    "sm3p1 requires one of: rv_zksh, rv_zks",
    "sm4ed requires one of: rv_zksed, rv_zks",
    "sm4ks requires one of: rv_zksed, rv_zks",
    "snez requires one of: rv_i",
    "sra requires one of: rv_i",
    "srai requires one of: rv64_i, rv32_i",
    "srai.rv32 requires one of: rv32_i",
    "sraiw requires one of: rv64_i",
    "sraw requires one of: rv64_i",
    "sret requires one of: rv_s",
    "srl requires one of: rv_i",
    "srli requires one of: rv64_i, rv32_i",
    "srli.rv32 requires one of: rv32_i",
    "srliw requires one of: rv64_i",
    "srlw requires one of: rv64_i",
    "ssamoswap.d requires one of: rv_zicfiss",
    "ssamoswap.w requires one of: rv_zicfiss",
    "sspopchk.x1 requires one of: rv_zicfiss",
    "sspopchk.x5 requires one of: rv_zicfiss",
    "sspush.x1 requires one of: rv_zicfiss",
    "sspush.x5 requires one of: rv_zicfiss",
    "ssrdp requires one of: rv_zicfiss",
    "sub requires one of: rv_i",
    "subw requires one of: rv64_i",
    "sw requires one of: rv_i",
    "unzip requires one of: rv32_zbkb, rv32_zks, rv32_zkn, rv32_zk",
    "vaadd.vv requires one of: rv_v",
    "vaadd.vx requires one of: rv_v",
    "vaaddu.vv requires one of: rv_v",
    "vaaddu.vx requires one of: rv_v",
    "vadc.vim requires one of: rv_v",
    "vadc.vvm requires one of: rv_v",
    "vadc.vxm requires one of: rv_v",
    "vadd.vi requires one of: rv_v",
    "vadd.vv requires one of: rv_v",
    "vadd.vx requires one of: rv_v",
    "vaesdf.vs requires one of: rv_zvkned, rv_zvkn",
    "vaesdf.vv requires one of: rv_zvkned, rv_zvkn",
    "vaesdm.vs requires one of: rv_zvkned, rv_zvkn",
    "vaesdm.vv requires one of: rv_zvkned, rv_zvkn",
    "vaesef.vs requires one of: rv_zvkned, rv_zvkn",
    "vaesef.vv requires one of: rv_zvkned, rv_zvkn",
    "vaesem.vs requires one of: rv_zvkned, rv_zvkn",
    "vaesem.vv requires one of: rv_zvkned, rv_zvkn",
    "vaeskf1.vi requires one of: rv_zvkned, rv_zvkn",
    "vaeskf2.vi requires one of: rv_zvkned, rv_zvkn",
    "vaesz.vs requires one of: rv_zvkned, rv_zvkn",
    "vand.vi requires one of: rv_v",
    "vand.vv requires one of: rv_v",
    "vand.vx requires one of: rv_v",
    "vandn.vv requires one of: rv_zvbb, rv_zvks, rv_zvkn",
    "vandn.vx requires one of: rv_zvbb, rv_zvks, rv_zvkn",
    "vasub.vv requires one of: rv_v",
    "vasub.vx requires one of: rv_v",
    "vasubu.vv requires one of: rv_v",
    "vasubu.vx requires one of: rv_v",
    "vbrev8.v requires one of: rv_zvbb, rv_zvks, rv_zvkn",
    "vbrev.v requires one of: rv_zvbb",
    "vclmul.vv requires one of: rv_zvbc",
    "vclmul.vx requires one of: rv_zvbc",
    "vclmulh.vv requires one of: rv_zvbc",
    "vclmulh.vx requires one of: rv_zvbc",
    "vclz.v requires one of: rv_zvbb",
    "vcompress.vm requires one of: rv_v",
    "vcpop.m requires one of: rv_v",
    "vcpop.v requires one of: rv_zvbb",
    "vctz.v requires one of: rv_zvbb",
    "vdiv.vv requires one of: rv_v",
    "vdiv.vx requires one of: rv_v",
    "vdivu.vv requires one of: rv_v",
    "vdivu.vx requires one of: rv_v",
    "vfadd.vf requires one of: rv_v",
    "vfadd.vv requires one of: rv_v",
    "vfclass.v requires one of: rv_v",
    "vfcvt.f.x.v requires one of: rv_v",
    "vfcvt.f.xu.v requires one of: rv_v",
    "vfcvt.rtz.x.f.v requires one of: rv_v",
    "vfcvt.rtz.xu.f.v requires one of: rv_v",
    "vfcvt.x.f.v requires one of: rv_v",
    "vfcvt.xu.f.v requires one of: rv_v",
    "vfdiv.vf requires one of: rv_v",
    "vfdiv.vv requires one of: rv_v",
    "vfirst.m requires one of: rv_v",
    "vfmacc.vf requires one of: rv_v",
    "vfmacc.vv requires one of: rv_v",
    "vfmadd.vf requires one of: rv_v",
    "vfmadd.vv requires one of: rv_v",
    "vfmax.vf requires one of: rv_v",
    "vfmax.vv requires one of: rv_v",
    "vfmerge.vfm requires one of: rv_v",
    "vfmin.vf requires one of: rv_v",
    "vfmin.vv requires one of: rv_v",
    "vfmsac.vf requires one of: rv_v",
    "vfmsac.vv requires one of: rv_v",
    "vfmsub.vf requires one of: rv_v",
    "vfmsub.vv requires one of: rv_v",
    "vfmul.vf requires one of: rv_v",
    "vfmul.vv requires one of: rv_v",
    "vfmv.f.s requires one of: rv_v",
    "vfmv.s.f requires one of: rv_v",
    "vfmv.v.f requires one of: rv_v",
    "vfncvt.f.f.w requires one of: rv_v",
    "vfncvt.f.x.w requires one of: rv_v",
    "vfncvt.f.xu.w requires one of: rv_v",
    "vfncvt.rod.f.f.w requires one of: rv_v",
    "vfncvt.rtz.x.f.w requires one of: rv_v",
    "vfncvt.rtz.xu.f.w requires one of: rv_v",
    "vfncvt.x.f.w requires one of: rv_v",
    "vfncvt.xu.f.w requires one of: rv_v",
    "vfncvtbf16.f.f.w requires one of: rv_zvfbfmin",
    "vfnmacc.vf requires one of: rv_v",
    "vfnmacc.vv requires one of: rv_v",
    "vfnmadd.vf requires one of: rv_v",
    "vfnmadd.vv requires one of: rv_v",
    "vfnmsac.vf requires one of: rv_v",
    "vfnmsac.vv requires one of: rv_v",
    "vfnmsub.vf requires one of: rv_v",
    "vfnmsub.vv requires one of: rv_v",
    "vfrdiv.vf requires one of: rv_v",
    "vfrec7.v requires one of: rv_v",
    "vfredmax.vs requires one of: rv_v",
    "vfredmin.vs requires one of: rv_v",
    "vfredosum.vs requires one of: rv_v",
    "vfredsum.vs requires one of: rv_v_aliases",
    "vfredusum.vs requires one of: rv_v",
    "vfrsqrt7.v requires one of: rv_v",
    "vfrsub.vf requires one of: rv_v",
    "vfsgnj.vf requires one of: rv_v",
    "vfsgnj.vv requires one of: rv_v",
    "vfsgnjn.vf requires one of: rv_v",
    "vfsgnjn.vv requires one of: rv_v",
    "vfsgnjx.vf requires one of: rv_v",
    "vfsgnjx.vv requires one of: rv_v",
    "vfslide1down.vf requires one of: rv_v",
    "vfslide1up.vf requires one of: rv_v",
    "vfsqrt.v requires one of: rv_v",
    "vfsub.vf requires one of: rv_v",
    "vfsub.vv requires one of: rv_v",
    "vfwadd.vf requires one of: rv_v",
    "vfwadd.vv requires one of: rv_v",
    "vfwadd.wf requires one of: rv_v",
    "vfwadd.wv requires one of: rv_v",
    "vfwcvt.f.f.v requires one of: rv_v",
    "vfwcvt.f.x.v requires one of: rv_v",
    "vfwcvt.f.xu.v requires one of: rv_v",
    "vfwcvt.rtz.x.f.v requires one of: rv_v",
    "vfwcvt.rtz.xu.f.v requires one of: rv_v",
    "vfwcvt.x.f.v requires one of: rv_v",
    "vfwcvt.xu.f.v requires one of: rv_v",
    "vfwcvtbf16.f.f.v requires one of: rv_zvfbfmin",
    "vfwmacc.vf requires one of: rv_v",
    "vfwmacc.vv requires one of: rv_v",
    "vfwmaccbf16.vf requires one of: rv_zvfbfwma",
    "vfwmaccbf16.vv requires one of: rv_zvfbfwma",
    "vfwmsac.vf requires one of: rv_v",
    "vfwmsac.vv requires one of: rv_v",
    "vfwmul.vf requires one of: rv_v",
    "vfwmul.vv requires one of: rv_v",
    "vfwnmacc.vf requires one of: rv_v",
    "vfwnmacc.vv requires one of: rv_v",
    "vfwnmsac.vf requires one of: rv_v",
    "vfwnmsac.vv requires one of: rv_v",
    "vfwredosum.vs requires one of: rv_v",
    "vfwredsum.vs requires one of: rv_v_aliases",
    "vfwredusum.vs requires one of: rv_v",
    "vfwsub.vf requires one of: rv_v",
    "vfwsub.vv requires one of: rv_v",
    "vfwsub.wf requires one of: rv_v",
    "vfwsub.wv requires one of: rv_v",
    "vghsh.vv requires one of: rv_zvkg",
    "vgmul.vv requires one of: rv_zvkg",
    "vid.v requires one of: rv_v",
    "viota.m requires one of: rv_v",
    "vl1r.v requires one of: rv_v_aliases",
    "vl1re16.v requires one of: rv_v",
    "vl1re32.v requires one of: rv_v",
    "vl1re64.v requires one of: rv_v",
    "vl1re8.v requires one of: rv_v",
    "vl2r.v requires one of: rv_v_aliases",
    "vl2re16.v requires one of: rv_v",
    "vl2re32.v requires one of: rv_v",
    "vl2re64.v requires one of: rv_v",
    "vl2re8.v requires one of: rv_v",
    "vl4r.v requires one of: rv_v_aliases",
    "vl4re16.v requires one of: rv_v",
    "vl4re32.v requires one of: rv_v",
    "vl4re64.v requires one of: rv_v",
    "vl4re8.v requires one of: rv_v",
    "vl8r.v requires one of: rv_v_aliases",
    "vl8re16.v requires one of: rv_v",
    "vl8re32.v requires one of: rv_v",
    "vl8re64.v requires one of: rv_v",
    "vl8re8.v requires one of: rv_v",
    "vle16.v requires one of: rv_v",
    "vle16ff.v requires one of: rv_v",
    "vle1.v requires one of: rv_v_aliases",
    "vle32.v requires one of: rv_v",
    "vle32ff.v requires one of: rv_v",
    "vle64.v requires one of: rv_v",
    "vle64ff.v requires one of: rv_v",
    "vle8.v requires one of: rv_v",
    "vle8ff.v requires one of: rv_v",
    "vlm.v requires one of: rv_v",
    "vloxei16.v requires one of: rv_v",
    "vloxei32.v requires one of: rv_v",
    "vloxei64.v requires one of: rv_v",
    "vloxei8.v requires one of: rv_v",
    "vlse16.v requires one of: rv_v",
    "vlse32.v requires one of: rv_v",
    "vlse64.v requires one of: rv_v",
    "vlse8.v requires one of: rv_v",
    "vluxei16.v requires one of: rv_v",
    "vluxei32.v requires one of: rv_v",
    "vluxei64.v requires one of: rv_v",
    "vluxei8.v requires one of: rv_v",
    "vmacc.vv requires one of: rv_v",
    "vmacc.vx requires one of: rv_v",
    "vmadc.vi requires one of: rv_v",
    "vmadc.vim requires one of: rv_v",
    "vmadc.vv requires one of: rv_v",
    "vmadc.vvm requires one of: rv_v",
    "vmadc.vx requires one of: rv_v",
    "vmadc.vxm requires one of: rv_v",
    "vmadd.vv requires one of: rv_v",
    "vmadd.vx requires one of: rv_v",
    "vmand.mm requires one of: rv_v",
    "vmandn.mm requires one of: rv_v",
    "vmandnot.mm requires one of: rv_v_aliases",
    "vmax.vv requires one of: rv_v",
    "vmax.vx requires one of: rv_v",
    "vmaxu.vv requires one of: rv_v",
    "vmaxu.vx requires one of: rv_v",
    "vmerge.vim requires one of: rv_v",
    "vmerge.vvm requires one of: rv_v",
    "vmerge.vxm requires one of: rv_v",
    "vmfeq.vf requires one of: rv_v",
    "vmfeq.vv requires one of: rv_v",
    "vmfge.vf requires one of: rv_v",
    "vmfgt.vf requires one of: rv_v",
    "vmfle.vf requires one of: rv_v",
    "vmfle.vv requires one of: rv_v",
    "vmflt.vf requires one of: rv_v",
    "vmflt.vv requires one of: rv_v",
    "vmfne.vf requires one of: rv_v",
    "vmfne.vv requires one of: rv_v",
    "vmin.vv requires one of: rv_v",
    "vmin.vx requires one of: rv_v",
    "vminu.vv requires one of: rv_v",
    "vminu.vx requires one of: rv_v",
    "vmnand.mm requires one of: rv_v",
    "vmnor.mm requires one of: rv_v",
    "vmor.mm requires one of: rv_v",
    "vmorn.mm requires one of: rv_v",
    "vmornot.mm requires one of: rv_v_aliases",
    "vmsbc.vv requires one of: rv_v",
    "vmsbc.vvm requires one of: rv_v",
    "vmsbc.vx requires one of: rv_v",
    "vmsbc.vxm requires one of: rv_v",
    "vmsbf.m requires one of: rv_v",
    "vmseq.vi requires one of: rv_v",
    "vmseq.vv requires one of: rv_v",
    "vmseq.vx requires one of: rv_v",
    "vmsgt.vi requires one of: rv_v",
    "vmsgt.vx requires one of: rv_v",
    "vmsgtu.vi requires one of: rv_v",
    "vmsgtu.vx requires one of: rv_v",
    "vmsif.m requires one of: rv_v",
    "vmsle.vi requires one of: rv_v",
    "vmsle.vv requires one of: rv_v",
    "vmsle.vx requires one of: rv_v",
    "vmsleu.vi requires one of: rv_v",
    "vmsleu.vv requires one of: rv_v",
    "vmsleu.vx requires one of: rv_v",
    "vmslt.vv requires one of: rv_v",
    "vmslt.vx requires one of: rv_v",
    "vmsltu.vv requires one of: rv_v",
    "vmsltu.vx requires one of: rv_v",
    "vmsne.vi requires one of: rv_v",
    "vmsne.vv requires one of: rv_v",
    "vmsne.vx requires one of: rv_v",
    "vmsof.m requires one of: rv_v",
    "vmul.vv requires one of: rv_v",
    "vmul.vx requires one of: rv_v",
    "vmulh.vv requires one of: rv_v",
    "vmulh.vx requires one of: rv_v",
    "vmulhsu.vv requires one of: rv_v",
    "vmulhsu.vx requires one of: rv_v",
    "vmulhu.vv requires one of: rv_v",
    "vmulhu.vx requires one of: rv_v",
    "vmv1r.v requires one of: rv_v",
    "vmv2r.v requires one of: rv_v",
    "vmv4r.v requires one of: rv_v",
    "vmv8r.v requires one of: rv_v",
    "vmv.s.x requires one of: rv_v",
    "vmv.v.i requires one of: rv_v",
    "vmv.v.v requires one of: rv_v",
    "vmv.v.x requires one of: rv_v",
    "vmv.x.s requires one of: rv_v",
    "vmxnor.mm requires one of: rv_v",
    "vmxor.mm requires one of: rv_v",
    "vnclip.wi requires one of: rv_v",
    "vnclip.wv requires one of: rv_v",
    "vnclip.wx requires one of: rv_v",
    "vnclipu.wi requires one of: rv_v",
    "vnclipu.wv requires one of: rv_v",
    "vnclipu.wx requires one of: rv_v",
    "vnmsac.vv requires one of: rv_v",
    "vnmsac.vx requires one of: rv_v",
    "vnmsub.vv requires one of: rv_v",
    "vnmsub.vx requires one of: rv_v",
    "vnsra.wi requires one of: rv_v",
    "vnsra.wv requires one of: rv_v",
    "vnsra.wx requires one of: rv_v",
    "vnsrl.wi requires one of: rv_v",
    "vnsrl.wv requires one of: rv_v",
    "vnsrl.wx requires one of: rv_v",
    "vor.vi requires one of: rv_v",
    "vor.vv requires one of: rv_v",
    "vor.vx requires one of: rv_v",
    "vpopc.m requires one of: rv_v_aliases",
    "vredand.vs requires one of: rv_v",
    "vredmax.vs requires one of: rv_v",
    "vredmaxu.vs requires one of: rv_v",
    "vredmin.vs requires one of: rv_v",
    "vredminu.vs requires one of: rv_v",
    "vredor.vs requires one of: rv_v",
    "vredsum.vs requires one of: rv_v",
    "vredxor.vs requires one of: rv_v",
    "vrem.vv requires one of: rv_v",
    "vrem.vx requires one of: rv_v",
    "vremu.vv requires one of: rv_v",
    "vremu.vx requires one of: rv_v",
    "vrev8.v requires one of: rv_zvbb, rv_zvks, rv_zvkn",
    "vrgather.vi requires one of: rv_v",
    "vrgather.vv requires one of: rv_v",
    "vrgather.vx requires one of: rv_v",
    "vrgatherei16.vv requires one of: rv_v",
    "vrol.vv requires one of: rv_zvbb, rv_zvks, rv_zvkn",
    "vrol.vx requires one of: rv_zvbb, rv_zvks, rv_zvkn",
    "vror.vi requires one of: rv_zvbb, rv_zvks, rv_zvkn",
    "vror.vv requires one of: rv_zvbb, rv_zvks, rv_zvkn",
    "vror.vx requires one of: rv_zvbb, rv_zvks, rv_zvkn",
    "vrsub.vi requires one of: rv_v",
    "vrsub.vx requires one of: rv_v",
    "vs1r.v requires one of: rv_v",
    "vs2r.v requires one of: rv_v",
    "vs4r.v requires one of: rv_v",
    "vs8r.v requires one of: rv_v",
    "vsadd.vi requires one of: rv_v",
    "vsadd.vv requires one of: rv_v",
    "vsadd.vx requires one of: rv_v",
    "vsaddu.vi requires one of: rv_v",
    "vsaddu.vv requires one of: rv_v",
    "vsaddu.vx requires one of: rv_v",
    "vsbc.vvm requires one of: rv_v",
    "vsbc.vxm requires one of: rv_v",
    "vse16.v requires one of: rv_v",
    "vse1.v requires one of: rv_v_aliases",
    "vse32.v requires one of: rv_v",
    "vse64.v requires one of: rv_v",
    "vse8.v requires one of: rv_v",
    "vsetivli requires one of: rv_v",
    "vsetvl requires one of: rv_v",
    "vsetvli requires one of: rv_v",
    "vsext.vf2 requires one of: rv_v",
    "vsext.vf4 requires one of: rv_v",
    "vsext.vf8 requires one of: rv_v",
    "vsha2ch.vv requires one of: rv_zvknha, rv_zvknhb, rv_zvkn",
    "vsha2cl.vv requires one of: rv_zvknha, rv_zvknhb, rv_zvkn",
    "vsha2ms.vv requires one of: rv_zvknha, rv_zvknhb, rv_zvkn",
    "vslide1down.vx requires one of: rv_v",
    "vslide1up.vx requires one of: rv_v",
    "vslidedown.vi requires one of: rv_v",
    "vslidedown.vx requires one of: rv_v",
    "vslideup.vi requires one of: rv_v",
    "vslideup.vx requires one of: rv_v",
    "vsll.vi requires one of: rv_v",
    "vsll.vv requires one of: rv_v",
    "vsll.vx requires one of: rv_v",
    "vsm3c.vi requires one of: rv_zvksh, rv_zvks",
    "vsm3me.vv requires one of: rv_zvksh, rv_zvks",
    "vsm4k.vi requires one of: rv_zvksed, rv_zvks",
    "vsm4r.vs requires one of: rv_zvksed, rv_zvks",
    "vsm4r.vv requires one of: rv_zvksed, rv_zvks",
    "vsm.v requires one of: rv_v",
    "vsmul.vv requires one of: rv_v",
    "vsmul.vx requires one of: rv_v",
    "vsoxei16.v requires one of: rv_v",
    "vsoxei32.v requires one of: rv_v",
    "vsoxei64.v requires one of: rv_v",
    "vsoxei8.v requires one of: rv_v",
    "vsra.vi requires one of: rv_v",
    "vsra.vv requires one of: rv_v",
    "vsra.vx requires one of: rv_v",
    "vsrl.vi requires one of: rv_v",
    "vsrl.vv requires one of: rv_v",
    "vsrl.vx requires one of: rv_v",
    "vsse16.v requires one of: rv_v",
    "vsse32.v requires one of: rv_v",
    "vsse64.v requires one of: rv_v",
    "vsse8.v requires one of: rv_v",
    "vssra.vi requires one of: rv_v",
    "vssra.vv requires one of: rv_v",
    "vssra.vx requires one of: rv_v",
    "vssrl.vi requires one of: rv_v",
    "vssrl.vv requires one of: rv_v",
    "vssrl.vx requires one of: rv_v",
    "vssub.vv requires one of: rv_v",
    "vssub.vx requires one of: rv_v",
    "vssubu.vv requires one of: rv_v",
    "vssubu.vx requires one of: rv_v",
    "vsub.vv requires one of: rv_v",
    "vsub.vx requires one of: rv_v",
    "vsuxei16.v requires one of: rv_v",
    "vsuxei32.v requires one of: rv_v",
    "vsuxei64.v requires one of: rv_v",
    "vsuxei8.v requires one of: rv_v",
    "vwadd.vv requires one of: rv_v",
    "vwadd.vx requires one of: rv_v",
    "vwadd.wv requires one of: rv_v",
    "vwadd.wx requires one of: rv_v",
    "vwaddu.vv requires one of: rv_v",
    "vwaddu.vx requires one of: rv_v",
    "vwaddu.wv requires one of: rv_v",
    "vwaddu.wx requires one of: rv_v",
    "vwmacc.vv requires one of: rv_v",
    "vwmacc.vx requires one of: rv_v",
    "vwmaccsu.vv requires one of: rv_v",
    "vwmaccsu.vx requires one of: rv_v",
    "vwmaccu.vv requires one of: rv_v",
    "vwmaccu.vx requires one of: rv_v",
    "vwmaccus.vx requires one of: rv_v",
    "vwmul.vv requires one of: rv_v",
    "vwmul.vx requires one of: rv_v",
    "vwmulsu.vv requires one of: rv_v",
    "vwmulsu.vx requires one of: rv_v",
    "vwmulu.vv requires one of: rv_v",
    "vwmulu.vx requires one of: rv_v",
    "vwredsum.vs requires one of: rv_v",
    "vwredsumu.vs requires one of: rv_v",
    "vwsll.vi requires one of: rv_zvbb",
    "vwsll.vv requires one of: rv_zvbb",
    "vwsll.vx requires one of: rv_zvbb",
    "vwsub.vv requires one of: rv_v",
    "vwsub.vx requires one of: rv_v",
    "vwsub.wv requires one of: rv_v",
    "vwsub.wx requires one of: rv_v",
    "vwsubu.vv requires one of: rv_v",
    "vwsubu.vx requires one of: rv_v",
    "vwsubu.wv requires one of: rv_v",
    "vwsubu.wx requires one of: rv_v",
    "vxor.vi requires one of: rv_v",
    "vxor.vv requires one of: rv_v",
    "vxor.vx requires one of: rv_v",
    "vzext.vf2 requires one of: rv_v",
    "vzext.vf4 requires one of: rv_v",
    "vzext.vf8 requires one of: rv_v",
    "wfi requires one of: rv_system",
    "wrs.nto requires one of: rv_zawrs",
    "wrs.sto requires one of: rv_zawrs",
    "xnor requires one of: rv_zbb, rv_zks, rv_zkn, rv_zk, rv_zbkb",
    "xor requires one of: rv_i",
    "xori requires one of: rv_i",
    "xperm4 requires one of: rv_zbkx, rv_zks, rv_zkn, rv_zk",
    "xperm8 requires one of: rv_zbkx, rv_zks, rv_zkn, rv_zk",
    "zext.b requires one of: rv_i",
    "zext.h requires one of: rv64_zbb",
    "zext.h.rv32 requires one of: rv32_zbb",
    "zext.w requires one of: rv64_zba",
    "zip requires one of: rv32_zbkb, rv32_zks, rv32_zkn, rv32_zk",
];

/// One opcode carrying each represented extension, for generated coverage checks.
pub static CPU_FEATURE_REPRESENTATIVE: [Opcode; CPU_FEATURE_COUNT] = [
    Opcode::CJAL,
    Opcode::CFLW,
    Opcode::FMVHXD,
    Opcode::SLLI,
    Opcode::REV8RV32,
    Opcode::REV8RV32,
    Opcode::BCLRIRV32,
    Opcode::CLD,
    Opcode::RDCYCLEH,
    Opcode::AES32DSI,
    Opcode::AES32DSI,
    Opcode::AES32DSI,
    Opcode::AES32ESI,
    Opcode::SHA512SIG0H,
    Opcode::REV8RV32,
    Opcode::AMOADDD,
    Opcode::CADDIW,
    Opcode::FCVTDL,
    Opcode::FCVTLS,
    Opcode::HLVD,
    Opcode::ADDIW,
    Opcode::DIVUW,
    Opcode::FCVTLQ,
    Opcode::FMVHXQ,
    Opcode::AMOCASQ,
    Opcode::ADDUW,
    Opcode::CLZW,
    Opcode::PACKW,
    Opcode::BCLRI,
    Opcode::CSEXTW,
    Opcode::FCVTHL,
    Opcode::AES64DS,
    Opcode::AES64DS,
    Opcode::AES64DS,
    Opcode::AES64ES,
    Opcode::SHA512SIG0,
    Opcode::PACKW,
    Opcode::AMOADDW,
    Opcode::CADD,
    Opcode::CFLD,
    Opcode::CSSPOPCHKX5,
    Opcode::CNTLALL,
    Opcode::FABSD,
    Opcode::FCVTMODWD,
    Opcode::FCVTDH,
    Opcode::FABSS,
    Opcode::FLEQS,
    Opcode::HFENCEGVMA,
    Opcode::ADD,
    Opcode::DIV,
    Opcode::FABSQ,
    Opcode::FLEQQ,
    Opcode::FCVTHQ,
    Opcode::SFENCEVMA,
    Opcode::DRET,
    Opcode::MNRET,
    Opcode::SCTRCLR,
    Opcode::SFENCEINVALIR,
    Opcode::HINVALGVMA,
    Opcode::MRET,
    Opcode::VAADDVV,
    Opcode::VFREDSUMVS,
    Opcode::AMOADDB,
    Opcode::AMOCASB,
    Opcode::AMOCASD,
    Opcode::WRSNTO,
    Opcode::SH1ADD,
    Opcode::ANDN,
    Opcode::CLMUL,
    Opcode::ANDN,
    Opcode::CLMUL,
    Opcode::XPERM4,
    Opcode::BCLR,
    Opcode::CLBU,
    Opcode::CMOP1,
    Opcode::CMMVA01S,
    Opcode::CMJALT,
    Opcode::FCVTBF16S,
    Opcode::FABSH,
    Opcode::FLEQH,
    Opcode::FCVTHS,
    Opcode::CBOCLEAN,
    Opcode::LPAD,
    Opcode::SSAMOSWAPD,
    Opcode::RDCYCLE,
    Opcode::CZEROEQZ,
    Opcode::CSRC,
    Opcode::FENCEI,
    Opcode::NTLALL,
    Opcode::MOPR0,
    Opcode::ANDN,
    Opcode::ANDN,
    Opcode::SHA256SIG0,
    Opcode::ANDN,
    Opcode::SM4ED,
    Opcode::SM3P0,
    Opcode::VANDNVV,
    Opcode::VCLMULVV,
    Opcode::VFNCVTBF16FFW,
    Opcode::VFWMACCBF16VF,
    Opcode::VGHSHVV,
    Opcode::VAESDFVS,
    Opcode::VAESDFVS,
    Opcode::VSHA2CHVV,
    Opcode::VSHA2CHVV,
    Opcode::VANDNVV,
    Opcode::VSM4KVI,
    Opcode::VSM3CVI,
];

/// Pattern value: no effects.
pub const NONE: u32 = 0;
/// Pattern value: operand is read (`OpRwFlags::READ`).
pub const R: u32 = OpRwFlags::READ.bits();
/// Pattern value: operand is written (`OpRwFlags::WRITE`).
pub const W: u32 = OpRwFlags::WRITE.bits();
/// Pattern value: operand is read and written (`OpRwFlags::RW`).
pub const X: u32 = OpRwFlags::RW.bits();
/// Pattern value: memory address base register, read (`OpRwFlags::READ | MEM_BASE_READ`).
pub const B: u32 = OpRwFlags::READ.bits() | OpRwFlags::MEM_BASE_READ.bits();

/// No memory access (`InstInfo::mem_access`).
pub const MEM_NONE: u8 = 0;
/// Memory load (`InstInfo::mem_access`).
pub const MEM_LOAD: u8 = 1;
/// Memory store (`InstInfo::mem_access`).
pub const MEM_STORE: u8 = 2;
/// Atomic memory read-modify-write (`InstInfo::mem_access`).
pub const MEM_READ_MODIFY_WRITE: u8 = 3;

/// `InstInfo::flags` bit: machine-level side effects, no allocatable effects
/// (ecall/ebreak/xret/wfi).
pub const FLAG_VOLATILE: u8 = 0x1;

/// Signature value: operand class unconstrained (`SIGNATURE_TABLE`).
pub const ANY: u8 = 0;
/// Signature value: general-purpose register (`SIGNATURE_TABLE`).
pub const GP: u8 = 1;
/// Signature value: floating-point register (`SIGNATURE_TABLE`).
pub const FP: u8 = 2;
/// Signature value: vector register (`SIGNATURE_TABLE`).
pub const VEC: u8 = 3;
/// Signature value: immediate or label (`SIGNATURE_TABLE`).
pub const IMM: u8 = 4;

/// Per-opcode instruction information.
#[derive(Clone, Copy, Debug)]
pub struct InstInfo {
    /// Index into [`RW_PATTERN_TABLE`].
    pub rw_info_index: u8,
    /// Index into [`SIGNATURE_TABLE`].
    pub signature_index: u8,
    /// `MEM_*` access kind.
    pub mem_access: u8,
    /// Access width in bytes (0 = none or not instruction-fixed).
    pub mem_width: u8,
    /// Index into [`IMPLICIT_REG_TABLE`].
    pub implicit_index: u8,
    /// `FLAG_*` bits.
    pub flags: u8,
    /// Implicit CSR flag reads (`CpuRwFlags::RISCV_*` bits).
    pub read_flags: u32,
    /// Implicit CSR flag writes (`CpuRwFlags::RISCV_*` bits).
    pub write_flags: u32,
}

/// Implicit fixed-register effects. Bits 0..=31 name GP registers x0..x31; bit 32
/// names the vector mask register v0.
#[derive(Clone, Copy, Debug, Default, PartialEq, Eq)]
pub struct ImplicitRegEffects {
    /// Mask of implicitly read fixed registers.
    pub read: u64,
    /// Mask of implicitly written fixed registers.
    pub write: u64,
}

/// Deduplicated operand read/write patterns (`OpRwFlags` values per position).
#[rustfmt::skip]
pub static RW_PATTERN_TABLE: [[u32; 6]; 20] = [
    [W, R, R, 0, 0, 0],
    [W, R, 0, 0, 0, 0],
    [W, B, R, 0, 0, 0],
    [W, 0, 0, 0, 0, 0],
    [R, R, 0, 0, 0, 0],
    [R, 0, 0, 0, 0, 0],
    [X, R, 0, 0, 0, 0],
    [X, 0, 0, 0, 0, 0],
    [0, 0, 0, 0, 0, 0],
    [W, B, 0, 0, 0, 0],
    [B, R, 0, 0, 0, 0],
    [R, X, 0, 0, 0, 0],
    [W, R, X, 0, 0, 0],
    [W, X, 0, 0, 0, 0],
    [R, W, 0, 0, 0, 0],
    [W, R, R, R, 0, 0],
    [0, 0, 0, W, R, 0],
    [0, 0, W, R, R, 0],
    [R, B, 0, 0, 0, 0],
    [R, B, R, 0, 0, 0],
];

/// Deduplicated operand-class signatures (`ANY`/`GP`/`FP`/`VEC`/`IMM` per position).
#[rustfmt::skip]
pub static SIGNATURE_TABLE: [[u8; 6]; 45] = [
    [GP, GP, GP, ANY, ANY, ANY],
    [GP, GP, IMM, ANY, ANY, ANY],
    [GP, GP, GP, IMM, ANY, ANY],
    [GP, GP, ANY, ANY, ANY, ANY],
    [GP, GP, GP, IMM, IMM, ANY],
    [GP, IMM, ANY, ANY, ANY, ANY],
    [IMM, ANY, ANY, ANY, ANY, ANY],
    [ANY, ANY, ANY, ANY, ANY, ANY],
    [FP, GP, IMM, ANY, ANY, ANY],
    [FP, IMM, ANY, ANY, ANY, ANY],
    [GP, FP, IMM, ANY, ANY, ANY],
    [GP, ANY, ANY, ANY, ANY, ANY],
    [IMM, IMM, ANY, ANY, ANY, ANY],
    [GP, IMM, IMM, ANY, ANY, ANY],
    [FP, FP, FP, ANY, ANY, ANY],
    [FP, FP, FP, IMM, ANY, ANY],
    [GP, FP, ANY, ANY, ANY, ANY],
    [FP, FP, IMM, ANY, ANY, ANY],
    [IMM, IMM, IMM, IMM, IMM, ANY],
    [GP, FP, FP, ANY, ANY, ANY],
    [FP, FP, ANY, ANY, ANY, ANY],
    [FP, FP, FP, FP, IMM, ANY],
    [FP, GP, ANY, ANY, ANY, ANY],
    [FP, GP, GP, ANY, ANY, ANY],
    [GP, GP, IMM, IMM, ANY, ANY],
    [IMM, IMM, IMM, GP, GP, ANY],
    [IMM, IMM, GP, GP, GP, ANY],
    [VEC, VEC, VEC, IMM, ANY, ANY],
    [VEC, VEC, GP, IMM, ANY, ANY],
    [VEC, VEC, IMM, ANY, ANY, ANY],
    [VEC, VEC, VEC, ANY, ANY, ANY],
    [VEC, GP, VEC, ANY, ANY, ANY],
    [VEC, VEC, IMM, IMM, ANY, ANY],
    [VEC, VEC, ANY, ANY, ANY, ANY],
    [GP, VEC, IMM, ANY, ANY, ANY],
    [VEC, VEC, FP, IMM, ANY, ANY],
    [VEC, FP, VEC, ANY, ANY, ANY],
    [FP, VEC, ANY, ANY, ANY, ANY],
    [VEC, FP, ANY, ANY, ANY, ANY],
    [VEC, IMM, ANY, ANY, ANY, ANY],
    [VEC, GP, ANY, ANY, ANY, ANY],
    [VEC, GP, IMM, IMM, ANY, ANY],
    [VEC, GP, VEC, IMM, IMM, ANY],
    [VEC, GP, GP, IMM, IMM, ANY],
    [GP, VEC, ANY, ANY, ANY, ANY],
];

/// Deduplicated implicit fixed-register effects (index 0 = none).
pub static IMPLICIT_REG_TABLE: [ImplicitRegEffects; 7] = [
    ImplicitRegEffects {
        read: 0x0,
        write: 0x0,
    },
    ImplicitRegEffects {
        read: 0x4,
        write: 0x4,
    },
    ImplicitRegEffects {
        read: 0x4,
        write: 0x0,
    },
    ImplicitRegEffects {
        read: 0x0,
        write: 0x2,
    },
    ImplicitRegEffects {
        read: 0x20,
        write: 0x0,
    },
    ImplicitRegEffects {
        read: 0x2,
        write: 0x0,
    },
    ImplicitRegEffects {
        read: 0x100000000,
        write: 0x0,
    },
];

/// Per-opcode effects, indexed by `Opcode as usize`.
#[rustfmt::skip]
pub static INST_INFO_TABLE: [InstInfo; 1039] = [
    InstInfo { rw_info_index: 0, signature_index: 0, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // add
    InstInfo { rw_info_index: 0, signature_index: 0, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // add.uw
    InstInfo { rw_info_index: 1, signature_index: 1, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // addi
    InstInfo { rw_info_index: 1, signature_index: 1, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // addiw
    InstInfo { rw_info_index: 0, signature_index: 0, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // addw
    InstInfo { rw_info_index: 0, signature_index: 2, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // aes32dsi
    InstInfo { rw_info_index: 0, signature_index: 2, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // aes32dsmi
    InstInfo { rw_info_index: 0, signature_index: 2, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // aes32esi
    InstInfo { rw_info_index: 0, signature_index: 2, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // aes32esmi
    InstInfo { rw_info_index: 0, signature_index: 0, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // aes64ds
    InstInfo { rw_info_index: 0, signature_index: 0, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // aes64dsm
    InstInfo { rw_info_index: 0, signature_index: 0, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // aes64es
    InstInfo { rw_info_index: 0, signature_index: 0, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // aes64esm
    InstInfo { rw_info_index: 1, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // aes64im
    InstInfo { rw_info_index: 1, signature_index: 1, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // aes64ks1i
    InstInfo { rw_info_index: 0, signature_index: 0, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // aes64ks2
    InstInfo { rw_info_index: 2, signature_index: 4, mem_access: MEM_READ_MODIFY_WRITE, mem_width: 1, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // amoadd.b
    InstInfo { rw_info_index: 2, signature_index: 4, mem_access: MEM_READ_MODIFY_WRITE, mem_width: 8, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // amoadd.d
    InstInfo { rw_info_index: 2, signature_index: 4, mem_access: MEM_READ_MODIFY_WRITE, mem_width: 2, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // amoadd.h
    InstInfo { rw_info_index: 2, signature_index: 4, mem_access: MEM_READ_MODIFY_WRITE, mem_width: 4, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // amoadd.w
    InstInfo { rw_info_index: 2, signature_index: 4, mem_access: MEM_READ_MODIFY_WRITE, mem_width: 1, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // amoand.b
    InstInfo { rw_info_index: 2, signature_index: 4, mem_access: MEM_READ_MODIFY_WRITE, mem_width: 8, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // amoand.d
    InstInfo { rw_info_index: 2, signature_index: 4, mem_access: MEM_READ_MODIFY_WRITE, mem_width: 2, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // amoand.h
    InstInfo { rw_info_index: 2, signature_index: 4, mem_access: MEM_READ_MODIFY_WRITE, mem_width: 4, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // amoand.w
    InstInfo { rw_info_index: 2, signature_index: 4, mem_access: MEM_READ_MODIFY_WRITE, mem_width: 1, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // amocas.b
    InstInfo { rw_info_index: 2, signature_index: 4, mem_access: MEM_READ_MODIFY_WRITE, mem_width: 8, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // amocas.d
    InstInfo { rw_info_index: 2, signature_index: 4, mem_access: MEM_READ_MODIFY_WRITE, mem_width: 2, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // amocas.h
    InstInfo { rw_info_index: 2, signature_index: 4, mem_access: MEM_READ_MODIFY_WRITE, mem_width: 16, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // amocas.q
    InstInfo { rw_info_index: 2, signature_index: 4, mem_access: MEM_READ_MODIFY_WRITE, mem_width: 4, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // amocas.w
    InstInfo { rw_info_index: 2, signature_index: 4, mem_access: MEM_READ_MODIFY_WRITE, mem_width: 1, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // amomax.b
    InstInfo { rw_info_index: 2, signature_index: 4, mem_access: MEM_READ_MODIFY_WRITE, mem_width: 8, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // amomax.d
    InstInfo { rw_info_index: 2, signature_index: 4, mem_access: MEM_READ_MODIFY_WRITE, mem_width: 2, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // amomax.h
    InstInfo { rw_info_index: 2, signature_index: 4, mem_access: MEM_READ_MODIFY_WRITE, mem_width: 4, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // amomax.w
    InstInfo { rw_info_index: 2, signature_index: 4, mem_access: MEM_READ_MODIFY_WRITE, mem_width: 1, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // amomaxu.b
    InstInfo { rw_info_index: 2, signature_index: 4, mem_access: MEM_READ_MODIFY_WRITE, mem_width: 8, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // amomaxu.d
    InstInfo { rw_info_index: 2, signature_index: 4, mem_access: MEM_READ_MODIFY_WRITE, mem_width: 2, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // amomaxu.h
    InstInfo { rw_info_index: 2, signature_index: 4, mem_access: MEM_READ_MODIFY_WRITE, mem_width: 4, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // amomaxu.w
    InstInfo { rw_info_index: 2, signature_index: 4, mem_access: MEM_READ_MODIFY_WRITE, mem_width: 1, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // amomin.b
    InstInfo { rw_info_index: 2, signature_index: 4, mem_access: MEM_READ_MODIFY_WRITE, mem_width: 8, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // amomin.d
    InstInfo { rw_info_index: 2, signature_index: 4, mem_access: MEM_READ_MODIFY_WRITE, mem_width: 2, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // amomin.h
    InstInfo { rw_info_index: 2, signature_index: 4, mem_access: MEM_READ_MODIFY_WRITE, mem_width: 4, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // amomin.w
    InstInfo { rw_info_index: 2, signature_index: 4, mem_access: MEM_READ_MODIFY_WRITE, mem_width: 1, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // amominu.b
    InstInfo { rw_info_index: 2, signature_index: 4, mem_access: MEM_READ_MODIFY_WRITE, mem_width: 8, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // amominu.d
    InstInfo { rw_info_index: 2, signature_index: 4, mem_access: MEM_READ_MODIFY_WRITE, mem_width: 2, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // amominu.h
    InstInfo { rw_info_index: 2, signature_index: 4, mem_access: MEM_READ_MODIFY_WRITE, mem_width: 4, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // amominu.w
    InstInfo { rw_info_index: 2, signature_index: 4, mem_access: MEM_READ_MODIFY_WRITE, mem_width: 1, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // amoor.b
    InstInfo { rw_info_index: 2, signature_index: 4, mem_access: MEM_READ_MODIFY_WRITE, mem_width: 8, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // amoor.d
    InstInfo { rw_info_index: 2, signature_index: 4, mem_access: MEM_READ_MODIFY_WRITE, mem_width: 2, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // amoor.h
    InstInfo { rw_info_index: 2, signature_index: 4, mem_access: MEM_READ_MODIFY_WRITE, mem_width: 4, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // amoor.w
    InstInfo { rw_info_index: 2, signature_index: 4, mem_access: MEM_READ_MODIFY_WRITE, mem_width: 1, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // amoswap.b
    InstInfo { rw_info_index: 2, signature_index: 4, mem_access: MEM_READ_MODIFY_WRITE, mem_width: 8, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // amoswap.d
    InstInfo { rw_info_index: 2, signature_index: 4, mem_access: MEM_READ_MODIFY_WRITE, mem_width: 2, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // amoswap.h
    InstInfo { rw_info_index: 2, signature_index: 4, mem_access: MEM_READ_MODIFY_WRITE, mem_width: 4, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // amoswap.w
    InstInfo { rw_info_index: 2, signature_index: 4, mem_access: MEM_READ_MODIFY_WRITE, mem_width: 1, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // amoxor.b
    InstInfo { rw_info_index: 2, signature_index: 4, mem_access: MEM_READ_MODIFY_WRITE, mem_width: 8, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // amoxor.d
    InstInfo { rw_info_index: 2, signature_index: 4, mem_access: MEM_READ_MODIFY_WRITE, mem_width: 2, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // amoxor.h
    InstInfo { rw_info_index: 2, signature_index: 4, mem_access: MEM_READ_MODIFY_WRITE, mem_width: 4, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // amoxor.w
    InstInfo { rw_info_index: 0, signature_index: 0, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // and
    InstInfo { rw_info_index: 1, signature_index: 1, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // andi
    InstInfo { rw_info_index: 0, signature_index: 0, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // andn
    InstInfo { rw_info_index: 3, signature_index: 5, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // auipc
    InstInfo { rw_info_index: 0, signature_index: 0, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // bclr
    InstInfo { rw_info_index: 1, signature_index: 1, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // bclri
    InstInfo { rw_info_index: 1, signature_index: 1, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // bclri.rv32
    InstInfo { rw_info_index: 4, signature_index: 1, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // beq
    InstInfo { rw_info_index: 5, signature_index: 5, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // beqz
    InstInfo { rw_info_index: 0, signature_index: 0, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // bext
    InstInfo { rw_info_index: 1, signature_index: 1, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // bexti
    InstInfo { rw_info_index: 1, signature_index: 1, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // bexti.rv32
    InstInfo { rw_info_index: 4, signature_index: 1, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // bge
    InstInfo { rw_info_index: 4, signature_index: 1, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // bgeu
    InstInfo { rw_info_index: 5, signature_index: 5, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // bgez
    InstInfo { rw_info_index: 4, signature_index: 1, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // bgt
    InstInfo { rw_info_index: 4, signature_index: 1, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // bgtu
    InstInfo { rw_info_index: 5, signature_index: 5, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // bgtz
    InstInfo { rw_info_index: 0, signature_index: 0, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // binv
    InstInfo { rw_info_index: 1, signature_index: 1, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // binvi
    InstInfo { rw_info_index: 1, signature_index: 1, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // binvi.rv32
    InstInfo { rw_info_index: 4, signature_index: 1, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // ble
    InstInfo { rw_info_index: 4, signature_index: 1, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // bleu
    InstInfo { rw_info_index: 5, signature_index: 5, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // blez
    InstInfo { rw_info_index: 4, signature_index: 1, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // blt
    InstInfo { rw_info_index: 4, signature_index: 1, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // bltu
    InstInfo { rw_info_index: 5, signature_index: 5, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // bltz
    InstInfo { rw_info_index: 4, signature_index: 1, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // bne
    InstInfo { rw_info_index: 5, signature_index: 5, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // bnez
    InstInfo { rw_info_index: 1, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // brev8
    InstInfo { rw_info_index: 0, signature_index: 0, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // bset
    InstInfo { rw_info_index: 1, signature_index: 1, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // bseti
    InstInfo { rw_info_index: 1, signature_index: 1, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // bseti.rv32
    InstInfo { rw_info_index: 6, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // c.add
    InstInfo { rw_info_index: 7, signature_index: 5, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // c.addi
    InstInfo { rw_info_index: 8, signature_index: 6, mem_access: MEM_NONE, mem_width: 0, implicit_index: 1, flags: 0, read_flags: 0, write_flags: 0 }, // c.addi16sp
    InstInfo { rw_info_index: 3, signature_index: 5, mem_access: MEM_NONE, mem_width: 0, implicit_index: 2, flags: 0, read_flags: 0, write_flags: 0 }, // c.addi4spn
    InstInfo { rw_info_index: 7, signature_index: 5, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // c.addiw
    InstInfo { rw_info_index: 6, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // c.addw
    InstInfo { rw_info_index: 6, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // c.and
    InstInfo { rw_info_index: 7, signature_index: 5, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // c.andi
    InstInfo { rw_info_index: 5, signature_index: 5, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // c.beqz
    InstInfo { rw_info_index: 5, signature_index: 5, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // c.bnez
    InstInfo { rw_info_index: 8, signature_index: 7, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // c.ebreak
    InstInfo { rw_info_index: 9, signature_index: 8, mem_access: MEM_LOAD, mem_width: 8, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // c.fld
    InstInfo { rw_info_index: 3, signature_index: 9, mem_access: MEM_LOAD, mem_width: 8, implicit_index: 2, flags: 0, read_flags: 0, write_flags: 0 }, // c.fldsp
    InstInfo { rw_info_index: 9, signature_index: 8, mem_access: MEM_LOAD, mem_width: 4, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // c.flw
    InstInfo { rw_info_index: 3, signature_index: 9, mem_access: MEM_LOAD, mem_width: 4, implicit_index: 2, flags: 0, read_flags: 0, write_flags: 0 }, // c.flwsp
    InstInfo { rw_info_index: 10, signature_index: 10, mem_access: MEM_STORE, mem_width: 8, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // c.fsd
    InstInfo { rw_info_index: 5, signature_index: 9, mem_access: MEM_STORE, mem_width: 8, implicit_index: 2, flags: 0, read_flags: 0, write_flags: 0 }, // c.fsdsp
    InstInfo { rw_info_index: 10, signature_index: 10, mem_access: MEM_STORE, mem_width: 4, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // c.fsw
    InstInfo { rw_info_index: 5, signature_index: 9, mem_access: MEM_STORE, mem_width: 4, implicit_index: 2, flags: 0, read_flags: 0, write_flags: 0 }, // c.fswsp
    InstInfo { rw_info_index: 8, signature_index: 6, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // c.j
    InstInfo { rw_info_index: 8, signature_index: 6, mem_access: MEM_NONE, mem_width: 0, implicit_index: 3, flags: 0, read_flags: 0, write_flags: 0 }, // c.jal
    InstInfo { rw_info_index: 5, signature_index: 11, mem_access: MEM_NONE, mem_width: 0, implicit_index: 3, flags: 0, read_flags: 0, write_flags: 0 }, // c.jalr
    InstInfo { rw_info_index: 5, signature_index: 11, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // c.jr
    InstInfo { rw_info_index: 1, signature_index: 1, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // c.lbu
    InstInfo { rw_info_index: 9, signature_index: 1, mem_access: MEM_LOAD, mem_width: 8, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // c.ld
    InstInfo { rw_info_index: 3, signature_index: 5, mem_access: MEM_LOAD, mem_width: 8, implicit_index: 2, flags: 0, read_flags: 0, write_flags: 0 }, // c.ldsp
    InstInfo { rw_info_index: 1, signature_index: 1, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // c.lh
    InstInfo { rw_info_index: 1, signature_index: 1, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // c.lhu
    InstInfo { rw_info_index: 3, signature_index: 5, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // c.li
    InstInfo { rw_info_index: 3, signature_index: 5, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // c.lui
    InstInfo { rw_info_index: 9, signature_index: 1, mem_access: MEM_LOAD, mem_width: 4, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // c.lw
    InstInfo { rw_info_index: 3, signature_index: 5, mem_access: MEM_LOAD, mem_width: 4, implicit_index: 2, flags: 0, read_flags: 0, write_flags: 0 }, // c.lwsp
    InstInfo { rw_info_index: 8, signature_index: 7, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // c.mop.1
    InstInfo { rw_info_index: 8, signature_index: 7, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // c.mop.11
    InstInfo { rw_info_index: 8, signature_index: 7, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // c.mop.13
    InstInfo { rw_info_index: 8, signature_index: 7, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // c.mop.15
    InstInfo { rw_info_index: 8, signature_index: 7, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // c.mop.3
    InstInfo { rw_info_index: 8, signature_index: 7, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // c.mop.5
    InstInfo { rw_info_index: 8, signature_index: 7, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // c.mop.7
    InstInfo { rw_info_index: 8, signature_index: 7, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // c.mop.9
    InstInfo { rw_info_index: 8, signature_index: 6, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // c.mop.n
    InstInfo { rw_info_index: 6, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // c.mul
    InstInfo { rw_info_index: 1, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // c.mv
    InstInfo { rw_info_index: 8, signature_index: 6, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // c.nop
    InstInfo { rw_info_index: 7, signature_index: 11, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // c.not
    InstInfo { rw_info_index: 8, signature_index: 7, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // c.ntl.all
    InstInfo { rw_info_index: 8, signature_index: 7, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // c.ntl.p1
    InstInfo { rw_info_index: 8, signature_index: 7, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // c.ntl.pall
    InstInfo { rw_info_index: 8, signature_index: 7, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // c.ntl.s1
    InstInfo { rw_info_index: 6, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // c.or
    InstInfo { rw_info_index: 4, signature_index: 1, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // c.sb
    InstInfo { rw_info_index: 10, signature_index: 1, mem_access: MEM_STORE, mem_width: 8, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // c.sd
    InstInfo { rw_info_index: 5, signature_index: 5, mem_access: MEM_STORE, mem_width: 8, implicit_index: 2, flags: 0, read_flags: 0, write_flags: 0 }, // c.sdsp
    InstInfo { rw_info_index: 7, signature_index: 11, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // c.sext.b
    InstInfo { rw_info_index: 7, signature_index: 11, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // c.sext.h
    InstInfo { rw_info_index: 7, signature_index: 11, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // c.sext.w
    InstInfo { rw_info_index: 4, signature_index: 1, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // c.sh
    InstInfo { rw_info_index: 7, signature_index: 5, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // c.slli
    InstInfo { rw_info_index: 7, signature_index: 5, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // c.slli.rv32
    InstInfo { rw_info_index: 7, signature_index: 5, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // c.srai
    InstInfo { rw_info_index: 7, signature_index: 5, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // c.srai.rv32
    InstInfo { rw_info_index: 7, signature_index: 5, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // c.srli
    InstInfo { rw_info_index: 7, signature_index: 5, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // c.srli.rv32
    InstInfo { rw_info_index: 8, signature_index: 7, mem_access: MEM_NONE, mem_width: 0, implicit_index: 4, flags: 0, read_flags: 0, write_flags: 0 }, // c.sspopchk.x5
    InstInfo { rw_info_index: 8, signature_index: 7, mem_access: MEM_NONE, mem_width: 0, implicit_index: 5, flags: 0, read_flags: 0, write_flags: 0 }, // c.sspush.x1
    InstInfo { rw_info_index: 6, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // c.sub
    InstInfo { rw_info_index: 6, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // c.subw
    InstInfo { rw_info_index: 10, signature_index: 1, mem_access: MEM_STORE, mem_width: 4, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // c.sw
    InstInfo { rw_info_index: 5, signature_index: 5, mem_access: MEM_STORE, mem_width: 4, implicit_index: 2, flags: 0, read_flags: 0, write_flags: 0 }, // c.swsp
    InstInfo { rw_info_index: 6, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // c.xor
    InstInfo { rw_info_index: 7, signature_index: 11, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // c.zext.b
    InstInfo { rw_info_index: 7, signature_index: 11, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // c.zext.h
    InstInfo { rw_info_index: 7, signature_index: 11, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // c.zext.w
    InstInfo { rw_info_index: 5, signature_index: 11, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // cbo.clean
    InstInfo { rw_info_index: 5, signature_index: 11, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // cbo.flush
    InstInfo { rw_info_index: 5, signature_index: 11, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // cbo.inval
    InstInfo { rw_info_index: 5, signature_index: 11, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // cbo.zero
    InstInfo { rw_info_index: 0, signature_index: 0, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // clmul
    InstInfo { rw_info_index: 0, signature_index: 0, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // clmulh
    InstInfo { rw_info_index: 0, signature_index: 0, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // clmulr
    InstInfo { rw_info_index: 1, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // clz
    InstInfo { rw_info_index: 1, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // clzw
    InstInfo { rw_info_index: 8, signature_index: 6, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // cm.jalt
    InstInfo { rw_info_index: 4, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // cm.mva01s
    InstInfo { rw_info_index: 4, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // cm.mvsa01
    InstInfo { rw_info_index: 8, signature_index: 12, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // cm.pop
    InstInfo { rw_info_index: 8, signature_index: 12, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // cm.popret
    InstInfo { rw_info_index: 8, signature_index: 12, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // cm.popretz
    InstInfo { rw_info_index: 8, signature_index: 12, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // cm.push
    InstInfo { rw_info_index: 1, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // cpop
    InstInfo { rw_info_index: 1, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // cpopw
    InstInfo { rw_info_index: 11, signature_index: 5, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // csrc
    InstInfo { rw_info_index: 7, signature_index: 12, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // csrci
    InstInfo { rw_info_index: 1, signature_index: 5, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // csrr
    InstInfo { rw_info_index: 12, signature_index: 1, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // csrrc
    InstInfo { rw_info_index: 13, signature_index: 13, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // csrrci
    InstInfo { rw_info_index: 12, signature_index: 1, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // csrrs
    InstInfo { rw_info_index: 13, signature_index: 13, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // csrrsi
    InstInfo { rw_info_index: 12, signature_index: 1, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // csrrw
    InstInfo { rw_info_index: 13, signature_index: 13, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // csrrwi
    InstInfo { rw_info_index: 11, signature_index: 5, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // csrs
    InstInfo { rw_info_index: 7, signature_index: 12, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // csrsi
    InstInfo { rw_info_index: 14, signature_index: 5, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // csrw
    InstInfo { rw_info_index: 3, signature_index: 12, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // csrwi
    InstInfo { rw_info_index: 1, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // ctz
    InstInfo { rw_info_index: 1, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // ctzw
    InstInfo { rw_info_index: 0, signature_index: 0, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // czero.eqz
    InstInfo { rw_info_index: 0, signature_index: 0, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // czero.nez
    InstInfo { rw_info_index: 0, signature_index: 0, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // div
    InstInfo { rw_info_index: 0, signature_index: 0, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // divu
    InstInfo { rw_info_index: 0, signature_index: 0, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // divuw
    InstInfo { rw_info_index: 0, signature_index: 0, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // divw
    InstInfo { rw_info_index: 8, signature_index: 7, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: FLAG_VOLATILE, read_flags: 0, write_flags: 0 }, // dret
    InstInfo { rw_info_index: 8, signature_index: 7, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: FLAG_VOLATILE, read_flags: 0, write_flags: 0 }, // ebreak
    InstInfo { rw_info_index: 8, signature_index: 7, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: FLAG_VOLATILE, read_flags: 0, write_flags: 0 }, // ecall
    InstInfo { rw_info_index: 0, signature_index: 14, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fabs.d
    InstInfo { rw_info_index: 0, signature_index: 14, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fabs.h
    InstInfo { rw_info_index: 0, signature_index: 14, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fabs.q
    InstInfo { rw_info_index: 0, signature_index: 14, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fabs.s
    InstInfo { rw_info_index: 0, signature_index: 15, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FRM.bits(), write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fadd.d
    InstInfo { rw_info_index: 0, signature_index: 15, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FRM.bits(), write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fadd.h
    InstInfo { rw_info_index: 0, signature_index: 15, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FRM.bits(), write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fadd.q
    InstInfo { rw_info_index: 0, signature_index: 15, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FRM.bits(), write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fadd.s
    InstInfo { rw_info_index: 1, signature_index: 16, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // fclass.d
    InstInfo { rw_info_index: 1, signature_index: 16, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // fclass.h
    InstInfo { rw_info_index: 1, signature_index: 16, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // fclass.q
    InstInfo { rw_info_index: 1, signature_index: 16, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // fclass.s
    InstInfo { rw_info_index: 1, signature_index: 17, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FRM.bits(), write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fcvt.bf16.s
    InstInfo { rw_info_index: 1, signature_index: 17, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FRM.bits(), write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fcvt.d.h
    InstInfo { rw_info_index: 1, signature_index: 8, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FRM.bits(), write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fcvt.d.l
    InstInfo { rw_info_index: 1, signature_index: 8, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FRM.bits(), write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fcvt.d.lu
    InstInfo { rw_info_index: 1, signature_index: 17, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FRM.bits(), write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fcvt.d.q
    InstInfo { rw_info_index: 1, signature_index: 17, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FRM.bits(), write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fcvt.d.s
    InstInfo { rw_info_index: 1, signature_index: 8, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FRM.bits(), write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fcvt.d.w
    InstInfo { rw_info_index: 1, signature_index: 8, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FRM.bits(), write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fcvt.d.wu
    InstInfo { rw_info_index: 1, signature_index: 17, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FRM.bits(), write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fcvt.h.d
    InstInfo { rw_info_index: 1, signature_index: 8, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FRM.bits(), write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fcvt.h.l
    InstInfo { rw_info_index: 1, signature_index: 8, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FRM.bits(), write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fcvt.h.lu
    InstInfo { rw_info_index: 1, signature_index: 17, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FRM.bits(), write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fcvt.h.q
    InstInfo { rw_info_index: 1, signature_index: 17, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FRM.bits(), write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fcvt.h.s
    InstInfo { rw_info_index: 1, signature_index: 8, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FRM.bits(), write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fcvt.h.w
    InstInfo { rw_info_index: 1, signature_index: 8, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FRM.bits(), write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fcvt.h.wu
    InstInfo { rw_info_index: 1, signature_index: 10, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FRM.bits(), write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fcvt.l.d
    InstInfo { rw_info_index: 1, signature_index: 10, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FRM.bits(), write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fcvt.l.h
    InstInfo { rw_info_index: 1, signature_index: 10, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FRM.bits(), write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fcvt.l.q
    InstInfo { rw_info_index: 1, signature_index: 10, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FRM.bits(), write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fcvt.l.s
    InstInfo { rw_info_index: 1, signature_index: 10, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FRM.bits(), write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fcvt.lu.d
    InstInfo { rw_info_index: 1, signature_index: 10, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FRM.bits(), write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fcvt.lu.h
    InstInfo { rw_info_index: 1, signature_index: 10, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FRM.bits(), write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fcvt.lu.q
    InstInfo { rw_info_index: 1, signature_index: 10, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FRM.bits(), write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fcvt.lu.s
    InstInfo { rw_info_index: 1, signature_index: 17, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FRM.bits(), write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fcvt.q.d
    InstInfo { rw_info_index: 1, signature_index: 17, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FRM.bits(), write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fcvt.q.h
    InstInfo { rw_info_index: 1, signature_index: 8, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FRM.bits(), write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fcvt.q.l
    InstInfo { rw_info_index: 1, signature_index: 8, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FRM.bits(), write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fcvt.q.lu
    InstInfo { rw_info_index: 1, signature_index: 17, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FRM.bits(), write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fcvt.q.s
    InstInfo { rw_info_index: 1, signature_index: 8, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FRM.bits(), write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fcvt.q.w
    InstInfo { rw_info_index: 1, signature_index: 8, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FRM.bits(), write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fcvt.q.wu
    InstInfo { rw_info_index: 1, signature_index: 17, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FRM.bits(), write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fcvt.s.bf16
    InstInfo { rw_info_index: 1, signature_index: 17, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FRM.bits(), write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fcvt.s.d
    InstInfo { rw_info_index: 1, signature_index: 17, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FRM.bits(), write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fcvt.s.h
    InstInfo { rw_info_index: 1, signature_index: 8, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FRM.bits(), write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fcvt.s.l
    InstInfo { rw_info_index: 1, signature_index: 8, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FRM.bits(), write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fcvt.s.lu
    InstInfo { rw_info_index: 1, signature_index: 17, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FRM.bits(), write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fcvt.s.q
    InstInfo { rw_info_index: 1, signature_index: 8, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FRM.bits(), write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fcvt.s.w
    InstInfo { rw_info_index: 1, signature_index: 8, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FRM.bits(), write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fcvt.s.wu
    InstInfo { rw_info_index: 1, signature_index: 10, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FRM.bits(), write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fcvt.w.d
    InstInfo { rw_info_index: 1, signature_index: 10, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FRM.bits(), write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fcvt.w.h
    InstInfo { rw_info_index: 1, signature_index: 10, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FRM.bits(), write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fcvt.w.q
    InstInfo { rw_info_index: 1, signature_index: 10, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FRM.bits(), write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fcvt.w.s
    InstInfo { rw_info_index: 1, signature_index: 10, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FRM.bits(), write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fcvt.wu.d
    InstInfo { rw_info_index: 1, signature_index: 10, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FRM.bits(), write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fcvt.wu.h
    InstInfo { rw_info_index: 1, signature_index: 10, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FRM.bits(), write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fcvt.wu.q
    InstInfo { rw_info_index: 1, signature_index: 10, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FRM.bits(), write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fcvt.wu.s
    InstInfo { rw_info_index: 1, signature_index: 16, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fcvtmod.w.d
    InstInfo { rw_info_index: 0, signature_index: 15, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FRM.bits(), write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fdiv.d
    InstInfo { rw_info_index: 0, signature_index: 15, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FRM.bits(), write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fdiv.h
    InstInfo { rw_info_index: 0, signature_index: 15, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FRM.bits(), write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fdiv.q
    InstInfo { rw_info_index: 0, signature_index: 15, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FRM.bits(), write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fdiv.s
    InstInfo { rw_info_index: 8, signature_index: 18, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // fence
    InstInfo { rw_info_index: 8, signature_index: 7, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // fence.i
    InstInfo { rw_info_index: 8, signature_index: 7, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // fence.tso
    InstInfo { rw_info_index: 0, signature_index: 19, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // feq.d
    InstInfo { rw_info_index: 0, signature_index: 19, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // feq.h
    InstInfo { rw_info_index: 0, signature_index: 19, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // feq.q
    InstInfo { rw_info_index: 0, signature_index: 19, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // feq.s
    InstInfo { rw_info_index: 9, signature_index: 8, mem_access: MEM_LOAD, mem_width: 8, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // fld
    InstInfo { rw_info_index: 0, signature_index: 19, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fle.d
    InstInfo { rw_info_index: 0, signature_index: 19, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fle.h
    InstInfo { rw_info_index: 0, signature_index: 19, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fle.q
    InstInfo { rw_info_index: 0, signature_index: 19, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fle.s
    InstInfo { rw_info_index: 0, signature_index: 14, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fleq.d
    InstInfo { rw_info_index: 0, signature_index: 14, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fleq.h
    InstInfo { rw_info_index: 0, signature_index: 14, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fleq.q
    InstInfo { rw_info_index: 0, signature_index: 14, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fleq.s
    InstInfo { rw_info_index: 9, signature_index: 8, mem_access: MEM_LOAD, mem_width: 2, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // flh
    InstInfo { rw_info_index: 1, signature_index: 20, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fli.d
    InstInfo { rw_info_index: 1, signature_index: 20, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fli.h
    InstInfo { rw_info_index: 1, signature_index: 20, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fli.q
    InstInfo { rw_info_index: 1, signature_index: 20, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fli.s
    InstInfo { rw_info_index: 9, signature_index: 8, mem_access: MEM_LOAD, mem_width: 16, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // flq
    InstInfo { rw_info_index: 0, signature_index: 19, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // flt.d
    InstInfo { rw_info_index: 0, signature_index: 19, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // flt.h
    InstInfo { rw_info_index: 0, signature_index: 19, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // flt.q
    InstInfo { rw_info_index: 0, signature_index: 19, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // flt.s
    InstInfo { rw_info_index: 0, signature_index: 14, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fltq.d
    InstInfo { rw_info_index: 0, signature_index: 14, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fltq.h
    InstInfo { rw_info_index: 0, signature_index: 14, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fltq.q
    InstInfo { rw_info_index: 0, signature_index: 14, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fltq.s
    InstInfo { rw_info_index: 9, signature_index: 8, mem_access: MEM_LOAD, mem_width: 4, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // flw
    InstInfo { rw_info_index: 15, signature_index: 21, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FRM.bits(), write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fmadd.d
    InstInfo { rw_info_index: 15, signature_index: 21, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FRM.bits(), write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fmadd.h
    InstInfo { rw_info_index: 15, signature_index: 21, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FRM.bits(), write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fmadd.q
    InstInfo { rw_info_index: 15, signature_index: 21, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FRM.bits(), write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fmadd.s
    InstInfo { rw_info_index: 0, signature_index: 14, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fmax.d
    InstInfo { rw_info_index: 0, signature_index: 14, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fmax.h
    InstInfo { rw_info_index: 0, signature_index: 14, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fmax.q
    InstInfo { rw_info_index: 0, signature_index: 14, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fmax.s
    InstInfo { rw_info_index: 0, signature_index: 14, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fmaxm.d
    InstInfo { rw_info_index: 0, signature_index: 14, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fmaxm.h
    InstInfo { rw_info_index: 0, signature_index: 14, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fmaxm.q
    InstInfo { rw_info_index: 0, signature_index: 14, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fmaxm.s
    InstInfo { rw_info_index: 0, signature_index: 14, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fmin.d
    InstInfo { rw_info_index: 0, signature_index: 14, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fmin.h
    InstInfo { rw_info_index: 0, signature_index: 14, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fmin.q
    InstInfo { rw_info_index: 0, signature_index: 14, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fmin.s
    InstInfo { rw_info_index: 0, signature_index: 14, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fminm.d
    InstInfo { rw_info_index: 0, signature_index: 14, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fminm.h
    InstInfo { rw_info_index: 0, signature_index: 14, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fminm.q
    InstInfo { rw_info_index: 0, signature_index: 14, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fminm.s
    InstInfo { rw_info_index: 15, signature_index: 21, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FRM.bits(), write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fmsub.d
    InstInfo { rw_info_index: 15, signature_index: 21, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FRM.bits(), write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fmsub.h
    InstInfo { rw_info_index: 15, signature_index: 21, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FRM.bits(), write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fmsub.q
    InstInfo { rw_info_index: 15, signature_index: 21, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FRM.bits(), write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fmsub.s
    InstInfo { rw_info_index: 0, signature_index: 15, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FRM.bits(), write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fmul.d
    InstInfo { rw_info_index: 0, signature_index: 15, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FRM.bits(), write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fmul.h
    InstInfo { rw_info_index: 0, signature_index: 15, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FRM.bits(), write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fmul.q
    InstInfo { rw_info_index: 0, signature_index: 15, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FRM.bits(), write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fmul.s
    InstInfo { rw_info_index: 0, signature_index: 14, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // fmv.d
    InstInfo { rw_info_index: 1, signature_index: 22, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // fmv.d.x
    InstInfo { rw_info_index: 0, signature_index: 14, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // fmv.h
    InstInfo { rw_info_index: 1, signature_index: 22, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // fmv.h.x
    InstInfo { rw_info_index: 0, signature_index: 14, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // fmv.q
    InstInfo { rw_info_index: 0, signature_index: 14, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // fmv.s
    InstInfo { rw_info_index: 1, signature_index: 22, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // fmv.s.x
    InstInfo { rw_info_index: 1, signature_index: 22, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // fmv.w.x
    InstInfo { rw_info_index: 1, signature_index: 16, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // fmv.x.d
    InstInfo { rw_info_index: 1, signature_index: 16, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // fmv.x.h
    InstInfo { rw_info_index: 1, signature_index: 16, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // fmv.x.s
    InstInfo { rw_info_index: 1, signature_index: 16, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // fmv.x.w
    InstInfo { rw_info_index: 1, signature_index: 16, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // fmvh.x.d
    InstInfo { rw_info_index: 1, signature_index: 16, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // fmvh.x.q
    InstInfo { rw_info_index: 0, signature_index: 23, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // fmvp.d.x
    InstInfo { rw_info_index: 0, signature_index: 23, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // fmvp.q.x
    InstInfo { rw_info_index: 0, signature_index: 14, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fneg.d
    InstInfo { rw_info_index: 0, signature_index: 14, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fneg.h
    InstInfo { rw_info_index: 0, signature_index: 14, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fneg.q
    InstInfo { rw_info_index: 0, signature_index: 14, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fneg.s
    InstInfo { rw_info_index: 15, signature_index: 21, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FRM.bits(), write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fnmadd.d
    InstInfo { rw_info_index: 15, signature_index: 21, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FRM.bits(), write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fnmadd.h
    InstInfo { rw_info_index: 15, signature_index: 21, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FRM.bits(), write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fnmadd.q
    InstInfo { rw_info_index: 15, signature_index: 21, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FRM.bits(), write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fnmadd.s
    InstInfo { rw_info_index: 15, signature_index: 21, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FRM.bits(), write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fnmsub.d
    InstInfo { rw_info_index: 15, signature_index: 21, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FRM.bits(), write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fnmsub.h
    InstInfo { rw_info_index: 15, signature_index: 21, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FRM.bits(), write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fnmsub.q
    InstInfo { rw_info_index: 15, signature_index: 21, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FRM.bits(), write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fnmsub.s
    InstInfo { rw_info_index: 3, signature_index: 11, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FFLAGS.bits() | CpuRwFlags::RISCV_FRM.bits(), write_flags: 0 }, // frcsr
    InstInfo { rw_info_index: 3, signature_index: 11, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FFLAGS.bits(), write_flags: 0 }, // frflags
    InstInfo { rw_info_index: 1, signature_index: 17, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FRM.bits(), write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fround.d
    InstInfo { rw_info_index: 1, signature_index: 17, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FRM.bits(), write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fround.h
    InstInfo { rw_info_index: 1, signature_index: 17, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FRM.bits(), write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fround.q
    InstInfo { rw_info_index: 1, signature_index: 17, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FRM.bits(), write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fround.s
    InstInfo { rw_info_index: 1, signature_index: 17, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FRM.bits(), write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // froundnx.d
    InstInfo { rw_info_index: 1, signature_index: 17, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FRM.bits(), write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // froundnx.h
    InstInfo { rw_info_index: 1, signature_index: 17, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FRM.bits(), write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // froundnx.q
    InstInfo { rw_info_index: 1, signature_index: 17, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FRM.bits(), write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // froundnx.s
    InstInfo { rw_info_index: 3, signature_index: 11, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FRM.bits(), write_flags: 0 }, // frrm
    InstInfo { rw_info_index: 1, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FFLAGS.bits() | CpuRwFlags::RISCV_FRM.bits(), write_flags: CpuRwFlags::RISCV_FFLAGS.bits() | CpuRwFlags::RISCV_FRM.bits() }, // fscsr
    InstInfo { rw_info_index: 10, signature_index: 10, mem_access: MEM_STORE, mem_width: 8, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // fsd
    InstInfo { rw_info_index: 1, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FFLAGS.bits(), write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fsflags
    InstInfo { rw_info_index: 3, signature_index: 5, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FFLAGS.bits(), write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fsflagsi
    InstInfo { rw_info_index: 0, signature_index: 14, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // fsgnj.d
    InstInfo { rw_info_index: 0, signature_index: 14, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // fsgnj.h
    InstInfo { rw_info_index: 0, signature_index: 14, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // fsgnj.q
    InstInfo { rw_info_index: 0, signature_index: 14, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // fsgnj.s
    InstInfo { rw_info_index: 0, signature_index: 14, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // fsgnjn.d
    InstInfo { rw_info_index: 0, signature_index: 14, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // fsgnjn.h
    InstInfo { rw_info_index: 0, signature_index: 14, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // fsgnjn.q
    InstInfo { rw_info_index: 0, signature_index: 14, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // fsgnjn.s
    InstInfo { rw_info_index: 0, signature_index: 14, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // fsgnjx.d
    InstInfo { rw_info_index: 0, signature_index: 14, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // fsgnjx.h
    InstInfo { rw_info_index: 0, signature_index: 14, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // fsgnjx.q
    InstInfo { rw_info_index: 0, signature_index: 14, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // fsgnjx.s
    InstInfo { rw_info_index: 10, signature_index: 10, mem_access: MEM_STORE, mem_width: 2, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // fsh
    InstInfo { rw_info_index: 10, signature_index: 10, mem_access: MEM_STORE, mem_width: 16, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // fsq
    InstInfo { rw_info_index: 1, signature_index: 17, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FRM.bits(), write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fsqrt.d
    InstInfo { rw_info_index: 1, signature_index: 17, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FRM.bits(), write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fsqrt.h
    InstInfo { rw_info_index: 1, signature_index: 17, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FRM.bits(), write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fsqrt.q
    InstInfo { rw_info_index: 1, signature_index: 17, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FRM.bits(), write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fsqrt.s
    InstInfo { rw_info_index: 1, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FRM.bits(), write_flags: CpuRwFlags::RISCV_FRM.bits() }, // fsrm
    InstInfo { rw_info_index: 3, signature_index: 5, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FRM.bits(), write_flags: CpuRwFlags::RISCV_FRM.bits() }, // fsrmi
    InstInfo { rw_info_index: 0, signature_index: 15, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FRM.bits(), write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fsub.d
    InstInfo { rw_info_index: 0, signature_index: 15, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FRM.bits(), write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fsub.h
    InstInfo { rw_info_index: 0, signature_index: 15, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FRM.bits(), write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fsub.q
    InstInfo { rw_info_index: 0, signature_index: 15, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: CpuRwFlags::RISCV_FRM.bits(), write_flags: CpuRwFlags::RISCV_FFLAGS.bits() }, // fsub.s
    InstInfo { rw_info_index: 10, signature_index: 10, mem_access: MEM_STORE, mem_width: 4, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // fsw
    InstInfo { rw_info_index: 4, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // hfence.gvma
    InstInfo { rw_info_index: 4, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // hfence.vvma
    InstInfo { rw_info_index: 4, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // hinval.gvma
    InstInfo { rw_info_index: 4, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // hinval.vvma
    InstInfo { rw_info_index: 1, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // hlv.b
    InstInfo { rw_info_index: 1, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // hlv.bu
    InstInfo { rw_info_index: 1, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // hlv.d
    InstInfo { rw_info_index: 1, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // hlv.h
    InstInfo { rw_info_index: 1, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // hlv.hu
    InstInfo { rw_info_index: 1, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // hlv.w
    InstInfo { rw_info_index: 1, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // hlv.wu
    InstInfo { rw_info_index: 1, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // hlvx.hu
    InstInfo { rw_info_index: 1, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // hlvx.wu
    InstInfo { rw_info_index: 4, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // hsv.b
    InstInfo { rw_info_index: 4, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // hsv.d
    InstInfo { rw_info_index: 4, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // hsv.h
    InstInfo { rw_info_index: 4, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // hsv.w
    InstInfo { rw_info_index: 8, signature_index: 6, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // j
    InstInfo { rw_info_index: 3, signature_index: 5, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // jal
    InstInfo { rw_info_index: 8, signature_index: 6, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // jal.pseudo
    InstInfo { rw_info_index: 1, signature_index: 1, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // jalr
    InstInfo { rw_info_index: 5, signature_index: 11, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // jalr.pseudo
    InstInfo { rw_info_index: 5, signature_index: 11, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // jr
    InstInfo { rw_info_index: 9, signature_index: 1, mem_access: MEM_LOAD, mem_width: 1, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // lb
    InstInfo { rw_info_index: 9, signature_index: 1, mem_access: MEM_LOAD, mem_width: 1, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // lbu
    InstInfo { rw_info_index: 9, signature_index: 1, mem_access: MEM_LOAD, mem_width: 8, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // ld
    InstInfo { rw_info_index: 9, signature_index: 1, mem_access: MEM_LOAD, mem_width: 2, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // lh
    InstInfo { rw_info_index: 9, signature_index: 1, mem_access: MEM_LOAD, mem_width: 2, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // lhu
    InstInfo { rw_info_index: 8, signature_index: 6, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // lpad
    InstInfo { rw_info_index: 9, signature_index: 24, mem_access: MEM_LOAD, mem_width: 8, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // lr.d
    InstInfo { rw_info_index: 9, signature_index: 24, mem_access: MEM_LOAD, mem_width: 4, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // lr.w
    InstInfo { rw_info_index: 3, signature_index: 5, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // lui
    InstInfo { rw_info_index: 9, signature_index: 1, mem_access: MEM_LOAD, mem_width: 4, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // lw
    InstInfo { rw_info_index: 9, signature_index: 1, mem_access: MEM_LOAD, mem_width: 4, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // lwu
    InstInfo { rw_info_index: 0, signature_index: 0, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // max
    InstInfo { rw_info_index: 0, signature_index: 0, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // maxu
    InstInfo { rw_info_index: 0, signature_index: 0, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // min
    InstInfo { rw_info_index: 0, signature_index: 0, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // minu
    InstInfo { rw_info_index: 8, signature_index: 7, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: FLAG_VOLATILE, read_flags: 0, write_flags: 0 }, // mnret
    InstInfo { rw_info_index: 1, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // mop.r.0
    InstInfo { rw_info_index: 1, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // mop.r.1
    InstInfo { rw_info_index: 1, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // mop.r.10
    InstInfo { rw_info_index: 1, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // mop.r.11
    InstInfo { rw_info_index: 1, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // mop.r.12
    InstInfo { rw_info_index: 1, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // mop.r.13
    InstInfo { rw_info_index: 1, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // mop.r.14
    InstInfo { rw_info_index: 1, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // mop.r.15
    InstInfo { rw_info_index: 1, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // mop.r.16
    InstInfo { rw_info_index: 1, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // mop.r.17
    InstInfo { rw_info_index: 1, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // mop.r.18
    InstInfo { rw_info_index: 1, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // mop.r.19
    InstInfo { rw_info_index: 1, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // mop.r.2
    InstInfo { rw_info_index: 1, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // mop.r.20
    InstInfo { rw_info_index: 1, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // mop.r.21
    InstInfo { rw_info_index: 1, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // mop.r.22
    InstInfo { rw_info_index: 1, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // mop.r.23
    InstInfo { rw_info_index: 1, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // mop.r.24
    InstInfo { rw_info_index: 1, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // mop.r.25
    InstInfo { rw_info_index: 1, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // mop.r.26
    InstInfo { rw_info_index: 1, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // mop.r.27
    InstInfo { rw_info_index: 1, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // mop.r.28
    InstInfo { rw_info_index: 1, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // mop.r.29
    InstInfo { rw_info_index: 1, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // mop.r.3
    InstInfo { rw_info_index: 1, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // mop.r.30
    InstInfo { rw_info_index: 1, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // mop.r.31
    InstInfo { rw_info_index: 1, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // mop.r.4
    InstInfo { rw_info_index: 1, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // mop.r.5
    InstInfo { rw_info_index: 1, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // mop.r.6
    InstInfo { rw_info_index: 1, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // mop.r.7
    InstInfo { rw_info_index: 1, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // mop.r.8
    InstInfo { rw_info_index: 1, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // mop.r.9
    InstInfo { rw_info_index: 16, signature_index: 25, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // mop.r.n
    InstInfo { rw_info_index: 0, signature_index: 0, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // mop.rr.0
    InstInfo { rw_info_index: 0, signature_index: 0, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // mop.rr.1
    InstInfo { rw_info_index: 0, signature_index: 0, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // mop.rr.2
    InstInfo { rw_info_index: 0, signature_index: 0, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // mop.rr.3
    InstInfo { rw_info_index: 0, signature_index: 0, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // mop.rr.4
    InstInfo { rw_info_index: 0, signature_index: 0, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // mop.rr.5
    InstInfo { rw_info_index: 0, signature_index: 0, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // mop.rr.6
    InstInfo { rw_info_index: 0, signature_index: 0, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // mop.rr.7
    InstInfo { rw_info_index: 17, signature_index: 26, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // mop.rr.n
    InstInfo { rw_info_index: 8, signature_index: 7, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: FLAG_VOLATILE, read_flags: 0, write_flags: 0 }, // mret
    InstInfo { rw_info_index: 0, signature_index: 0, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // mul
    InstInfo { rw_info_index: 0, signature_index: 0, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // mulh
    InstInfo { rw_info_index: 0, signature_index: 0, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // mulhsu
    InstInfo { rw_info_index: 0, signature_index: 0, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // mulhu
    InstInfo { rw_info_index: 0, signature_index: 0, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // mulw
    InstInfo { rw_info_index: 1, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // mv
    InstInfo { rw_info_index: 1, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // neg
    InstInfo { rw_info_index: 8, signature_index: 7, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // nop
    InstInfo { rw_info_index: 8, signature_index: 7, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // ntl.all
    InstInfo { rw_info_index: 8, signature_index: 7, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // ntl.p1
    InstInfo { rw_info_index: 8, signature_index: 7, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // ntl.pall
    InstInfo { rw_info_index: 8, signature_index: 7, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // ntl.s1
    InstInfo { rw_info_index: 0, signature_index: 0, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // or
    InstInfo { rw_info_index: 1, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // orc.b
    InstInfo { rw_info_index: 1, signature_index: 1, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // ori
    InstInfo { rw_info_index: 0, signature_index: 0, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // orn
    InstInfo { rw_info_index: 0, signature_index: 0, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // pack
    InstInfo { rw_info_index: 0, signature_index: 0, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // packh
    InstInfo { rw_info_index: 0, signature_index: 0, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // packw
    InstInfo { rw_info_index: 8, signature_index: 7, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // pause
    InstInfo { rw_info_index: 5, signature_index: 5, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // prefetch.i
    InstInfo { rw_info_index: 5, signature_index: 5, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // prefetch.r
    InstInfo { rw_info_index: 5, signature_index: 5, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // prefetch.w
    InstInfo { rw_info_index: 3, signature_index: 11, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // rdcycle
    InstInfo { rw_info_index: 3, signature_index: 11, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // rdcycleh
    InstInfo { rw_info_index: 3, signature_index: 11, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // rdinstret
    InstInfo { rw_info_index: 3, signature_index: 11, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // rdinstreth
    InstInfo { rw_info_index: 3, signature_index: 11, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // rdtime
    InstInfo { rw_info_index: 3, signature_index: 11, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // rdtimeh
    InstInfo { rw_info_index: 0, signature_index: 0, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // rem
    InstInfo { rw_info_index: 0, signature_index: 0, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // remu
    InstInfo { rw_info_index: 0, signature_index: 0, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // remuw
    InstInfo { rw_info_index: 0, signature_index: 0, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // remw
    InstInfo { rw_info_index: 8, signature_index: 7, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // ret
    InstInfo { rw_info_index: 1, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // rev8
    InstInfo { rw_info_index: 1, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // rev8.rv32
    InstInfo { rw_info_index: 0, signature_index: 0, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // rol
    InstInfo { rw_info_index: 0, signature_index: 0, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // rolw
    InstInfo { rw_info_index: 0, signature_index: 0, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // ror
    InstInfo { rw_info_index: 1, signature_index: 1, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // rori
    InstInfo { rw_info_index: 1, signature_index: 1, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // rori.rv32
    InstInfo { rw_info_index: 1, signature_index: 1, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // roriw
    InstInfo { rw_info_index: 0, signature_index: 0, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // rorw
    InstInfo { rw_info_index: 10, signature_index: 1, mem_access: MEM_STORE, mem_width: 1, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // sb
    InstInfo { rw_info_index: 8, signature_index: 7, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // sbreak
    InstInfo { rw_info_index: 2, signature_index: 4, mem_access: MEM_STORE, mem_width: 8, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // sc.d
    InstInfo { rw_info_index: 2, signature_index: 4, mem_access: MEM_STORE, mem_width: 4, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // sc.w
    InstInfo { rw_info_index: 8, signature_index: 7, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // scall
    InstInfo { rw_info_index: 8, signature_index: 7, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // sctrclr
    InstInfo { rw_info_index: 10, signature_index: 1, mem_access: MEM_STORE, mem_width: 8, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // sd
    InstInfo { rw_info_index: 1, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // seqz
    InstInfo { rw_info_index: 1, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // sext.b
    InstInfo { rw_info_index: 1, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // sext.h
    InstInfo { rw_info_index: 1, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // sext.w
    InstInfo { rw_info_index: 8, signature_index: 7, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // sfence.inval.ir
    InstInfo { rw_info_index: 4, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // sfence.vma
    InstInfo { rw_info_index: 8, signature_index: 7, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // sfence.w.inval
    InstInfo { rw_info_index: 1, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // sgtz
    InstInfo { rw_info_index: 10, signature_index: 1, mem_access: MEM_STORE, mem_width: 2, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // sh
    InstInfo { rw_info_index: 0, signature_index: 0, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // sh1add
    InstInfo { rw_info_index: 0, signature_index: 0, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // sh1add.uw
    InstInfo { rw_info_index: 0, signature_index: 0, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // sh2add
    InstInfo { rw_info_index: 0, signature_index: 0, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // sh2add.uw
    InstInfo { rw_info_index: 0, signature_index: 0, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // sh3add
    InstInfo { rw_info_index: 0, signature_index: 0, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // sh3add.uw
    InstInfo { rw_info_index: 1, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // sha256sig0
    InstInfo { rw_info_index: 1, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // sha256sig1
    InstInfo { rw_info_index: 1, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // sha256sum0
    InstInfo { rw_info_index: 1, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // sha256sum1
    InstInfo { rw_info_index: 1, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // sha512sig0
    InstInfo { rw_info_index: 0, signature_index: 0, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // sha512sig0h
    InstInfo { rw_info_index: 0, signature_index: 0, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // sha512sig0l
    InstInfo { rw_info_index: 1, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // sha512sig1
    InstInfo { rw_info_index: 0, signature_index: 0, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // sha512sig1h
    InstInfo { rw_info_index: 0, signature_index: 0, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // sha512sig1l
    InstInfo { rw_info_index: 1, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // sha512sum0
    InstInfo { rw_info_index: 0, signature_index: 0, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // sha512sum0r
    InstInfo { rw_info_index: 1, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // sha512sum1
    InstInfo { rw_info_index: 0, signature_index: 0, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // sha512sum1r
    InstInfo { rw_info_index: 4, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // sinval.vma
    InstInfo { rw_info_index: 0, signature_index: 0, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // sll
    InstInfo { rw_info_index: 1, signature_index: 1, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // slli
    InstInfo { rw_info_index: 1, signature_index: 1, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // slli.rv32
    InstInfo { rw_info_index: 1, signature_index: 1, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // slli.uw
    InstInfo { rw_info_index: 1, signature_index: 1, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // slliw
    InstInfo { rw_info_index: 0, signature_index: 0, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // sllw
    InstInfo { rw_info_index: 0, signature_index: 0, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // slt
    InstInfo { rw_info_index: 1, signature_index: 1, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // slti
    InstInfo { rw_info_index: 1, signature_index: 1, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // sltiu
    InstInfo { rw_info_index: 0, signature_index: 0, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // sltu
    InstInfo { rw_info_index: 1, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // sltz
    InstInfo { rw_info_index: 1, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // sm3p0
    InstInfo { rw_info_index: 1, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // sm3p1
    InstInfo { rw_info_index: 0, signature_index: 2, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // sm4ed
    InstInfo { rw_info_index: 0, signature_index: 2, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // sm4ks
    InstInfo { rw_info_index: 1, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // snez
    InstInfo { rw_info_index: 0, signature_index: 0, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // sra
    InstInfo { rw_info_index: 1, signature_index: 1, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // srai
    InstInfo { rw_info_index: 1, signature_index: 1, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // srai.rv32
    InstInfo { rw_info_index: 1, signature_index: 1, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // sraiw
    InstInfo { rw_info_index: 0, signature_index: 0, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // sraw
    InstInfo { rw_info_index: 8, signature_index: 7, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: FLAG_VOLATILE, read_flags: 0, write_flags: 0 }, // sret
    InstInfo { rw_info_index: 0, signature_index: 0, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // srl
    InstInfo { rw_info_index: 1, signature_index: 1, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // srli
    InstInfo { rw_info_index: 1, signature_index: 1, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // srli.rv32
    InstInfo { rw_info_index: 1, signature_index: 1, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // srliw
    InstInfo { rw_info_index: 0, signature_index: 0, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // srlw
    InstInfo { rw_info_index: 2, signature_index: 4, mem_access: MEM_READ_MODIFY_WRITE, mem_width: 8, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // ssamoswap.d
    InstInfo { rw_info_index: 2, signature_index: 4, mem_access: MEM_READ_MODIFY_WRITE, mem_width: 4, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // ssamoswap.w
    InstInfo { rw_info_index: 8, signature_index: 7, mem_access: MEM_NONE, mem_width: 0, implicit_index: 5, flags: 0, read_flags: 0, write_flags: 0 }, // sspopchk.x1
    InstInfo { rw_info_index: 8, signature_index: 7, mem_access: MEM_NONE, mem_width: 0, implicit_index: 4, flags: 0, read_flags: 0, write_flags: 0 }, // sspopchk.x5
    InstInfo { rw_info_index: 8, signature_index: 7, mem_access: MEM_NONE, mem_width: 0, implicit_index: 5, flags: 0, read_flags: 0, write_flags: 0 }, // sspush.x1
    InstInfo { rw_info_index: 8, signature_index: 7, mem_access: MEM_NONE, mem_width: 0, implicit_index: 4, flags: 0, read_flags: 0, write_flags: 0 }, // sspush.x5
    InstInfo { rw_info_index: 3, signature_index: 11, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // ssrdp
    InstInfo { rw_info_index: 0, signature_index: 0, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // sub
    InstInfo { rw_info_index: 0, signature_index: 0, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // subw
    InstInfo { rw_info_index: 10, signature_index: 1, mem_access: MEM_STORE, mem_width: 4, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // sw
    InstInfo { rw_info_index: 1, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // unzip
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: CpuRwFlags::RISCV_VXSAT.bits() }, // vaadd.vv
    InstInfo { rw_info_index: 0, signature_index: 28, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: CpuRwFlags::RISCV_VXSAT.bits() }, // vaadd.vx
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: CpuRwFlags::RISCV_VXSAT.bits() }, // vaaddu.vv
    InstInfo { rw_info_index: 0, signature_index: 28, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: CpuRwFlags::RISCV_VXSAT.bits() }, // vaaddu.vx
    InstInfo { rw_info_index: 1, signature_index: 29, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // vadc.vim
    InstInfo { rw_info_index: 0, signature_index: 30, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // vadc.vvm
    InstInfo { rw_info_index: 0, signature_index: 31, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // vadc.vxm
    InstInfo { rw_info_index: 1, signature_index: 32, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vadd.vi
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vadd.vv
    InstInfo { rw_info_index: 0, signature_index: 28, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vadd.vx
    InstInfo { rw_info_index: 1, signature_index: 33, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // vaesdf.vs
    InstInfo { rw_info_index: 1, signature_index: 33, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // vaesdf.vv
    InstInfo { rw_info_index: 1, signature_index: 33, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // vaesdm.vs
    InstInfo { rw_info_index: 1, signature_index: 33, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // vaesdm.vv
    InstInfo { rw_info_index: 1, signature_index: 33, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // vaesef.vs
    InstInfo { rw_info_index: 1, signature_index: 33, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // vaesef.vv
    InstInfo { rw_info_index: 1, signature_index: 33, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // vaesem.vs
    InstInfo { rw_info_index: 1, signature_index: 33, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // vaesem.vv
    InstInfo { rw_info_index: 1, signature_index: 29, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // vaeskf1.vi
    InstInfo { rw_info_index: 1, signature_index: 29, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // vaeskf2.vi
    InstInfo { rw_info_index: 1, signature_index: 33, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // vaesz.vs
    InstInfo { rw_info_index: 1, signature_index: 32, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vand.vi
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vand.vv
    InstInfo { rw_info_index: 0, signature_index: 28, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vand.vx
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vandn.vv
    InstInfo { rw_info_index: 0, signature_index: 28, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vandn.vx
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: CpuRwFlags::RISCV_VXSAT.bits() }, // vasub.vv
    InstInfo { rw_info_index: 0, signature_index: 28, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: CpuRwFlags::RISCV_VXSAT.bits() }, // vasub.vx
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: CpuRwFlags::RISCV_VXSAT.bits() }, // vasubu.vv
    InstInfo { rw_info_index: 0, signature_index: 28, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: CpuRwFlags::RISCV_VXSAT.bits() }, // vasubu.vx
    InstInfo { rw_info_index: 1, signature_index: 29, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vbrev8.v
    InstInfo { rw_info_index: 1, signature_index: 29, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vbrev.v
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vclmul.vv
    InstInfo { rw_info_index: 0, signature_index: 28, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vclmul.vx
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vclmulh.vv
    InstInfo { rw_info_index: 0, signature_index: 28, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vclmulh.vx
    InstInfo { rw_info_index: 1, signature_index: 29, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vclz.v
    InstInfo { rw_info_index: 0, signature_index: 30, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // vcompress.vm
    InstInfo { rw_info_index: 1, signature_index: 34, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vcpop.m
    InstInfo { rw_info_index: 1, signature_index: 29, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vcpop.v
    InstInfo { rw_info_index: 1, signature_index: 29, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vctz.v
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vdiv.vv
    InstInfo { rw_info_index: 0, signature_index: 28, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vdiv.vx
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vdivu.vv
    InstInfo { rw_info_index: 0, signature_index: 28, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vdivu.vx
    InstInfo { rw_info_index: 0, signature_index: 35, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vfadd.vf
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vfadd.vv
    InstInfo { rw_info_index: 1, signature_index: 29, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vfclass.v
    InstInfo { rw_info_index: 1, signature_index: 29, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vfcvt.f.x.v
    InstInfo { rw_info_index: 1, signature_index: 29, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vfcvt.f.xu.v
    InstInfo { rw_info_index: 1, signature_index: 29, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vfcvt.rtz.x.f.v
    InstInfo { rw_info_index: 1, signature_index: 29, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vfcvt.rtz.xu.f.v
    InstInfo { rw_info_index: 1, signature_index: 29, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vfcvt.x.f.v
    InstInfo { rw_info_index: 1, signature_index: 29, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vfcvt.xu.f.v
    InstInfo { rw_info_index: 0, signature_index: 35, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vfdiv.vf
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vfdiv.vv
    InstInfo { rw_info_index: 1, signature_index: 34, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vfirst.m
    InstInfo { rw_info_index: 0, signature_index: 35, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vfmacc.vf
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vfmacc.vv
    InstInfo { rw_info_index: 0, signature_index: 35, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vfmadd.vf
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vfmadd.vv
    InstInfo { rw_info_index: 0, signature_index: 35, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vfmax.vf
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vfmax.vv
    InstInfo { rw_info_index: 0, signature_index: 36, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // vfmerge.vfm
    InstInfo { rw_info_index: 0, signature_index: 35, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vfmin.vf
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vfmin.vv
    InstInfo { rw_info_index: 0, signature_index: 35, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vfmsac.vf
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vfmsac.vv
    InstInfo { rw_info_index: 0, signature_index: 35, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vfmsub.vf
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vfmsub.vv
    InstInfo { rw_info_index: 0, signature_index: 35, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vfmul.vf
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vfmul.vv
    InstInfo { rw_info_index: 1, signature_index: 37, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // vfmv.f.s
    InstInfo { rw_info_index: 1, signature_index: 38, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // vfmv.s.f
    InstInfo { rw_info_index: 1, signature_index: 38, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // vfmv.v.f
    InstInfo { rw_info_index: 1, signature_index: 29, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vfncvt.f.f.w
    InstInfo { rw_info_index: 1, signature_index: 29, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vfncvt.f.x.w
    InstInfo { rw_info_index: 1, signature_index: 29, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vfncvt.f.xu.w
    InstInfo { rw_info_index: 1, signature_index: 29, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vfncvt.rod.f.f.w
    InstInfo { rw_info_index: 1, signature_index: 29, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vfncvt.rtz.x.f.w
    InstInfo { rw_info_index: 1, signature_index: 29, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vfncvt.rtz.xu.f.w
    InstInfo { rw_info_index: 1, signature_index: 29, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vfncvt.x.f.w
    InstInfo { rw_info_index: 1, signature_index: 29, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vfncvt.xu.f.w
    InstInfo { rw_info_index: 1, signature_index: 29, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vfncvtbf16.f.f.w
    InstInfo { rw_info_index: 0, signature_index: 35, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vfnmacc.vf
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vfnmacc.vv
    InstInfo { rw_info_index: 0, signature_index: 35, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vfnmadd.vf
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vfnmadd.vv
    InstInfo { rw_info_index: 0, signature_index: 35, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vfnmsac.vf
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vfnmsac.vv
    InstInfo { rw_info_index: 0, signature_index: 35, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vfnmsub.vf
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vfnmsub.vv
    InstInfo { rw_info_index: 0, signature_index: 35, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vfrdiv.vf
    InstInfo { rw_info_index: 1, signature_index: 29, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vfrec7.v
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vfredmax.vs
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vfredmin.vs
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vfredosum.vs
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vfredsum.vs
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vfredusum.vs
    InstInfo { rw_info_index: 1, signature_index: 29, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vfrsqrt7.v
    InstInfo { rw_info_index: 0, signature_index: 35, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vfrsub.vf
    InstInfo { rw_info_index: 0, signature_index: 35, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vfsgnj.vf
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vfsgnj.vv
    InstInfo { rw_info_index: 0, signature_index: 35, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vfsgnjn.vf
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vfsgnjn.vv
    InstInfo { rw_info_index: 0, signature_index: 35, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vfsgnjx.vf
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vfsgnjx.vv
    InstInfo { rw_info_index: 0, signature_index: 35, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vfslide1down.vf
    InstInfo { rw_info_index: 0, signature_index: 35, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vfslide1up.vf
    InstInfo { rw_info_index: 1, signature_index: 29, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vfsqrt.v
    InstInfo { rw_info_index: 0, signature_index: 35, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vfsub.vf
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vfsub.vv
    InstInfo { rw_info_index: 0, signature_index: 35, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vfwadd.vf
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vfwadd.vv
    InstInfo { rw_info_index: 0, signature_index: 35, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vfwadd.wf
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vfwadd.wv
    InstInfo { rw_info_index: 1, signature_index: 29, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vfwcvt.f.f.v
    InstInfo { rw_info_index: 1, signature_index: 29, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vfwcvt.f.x.v
    InstInfo { rw_info_index: 1, signature_index: 29, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vfwcvt.f.xu.v
    InstInfo { rw_info_index: 1, signature_index: 29, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vfwcvt.rtz.x.f.v
    InstInfo { rw_info_index: 1, signature_index: 29, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vfwcvt.rtz.xu.f.v
    InstInfo { rw_info_index: 1, signature_index: 29, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vfwcvt.x.f.v
    InstInfo { rw_info_index: 1, signature_index: 29, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vfwcvt.xu.f.v
    InstInfo { rw_info_index: 1, signature_index: 29, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vfwcvtbf16.f.f.v
    InstInfo { rw_info_index: 0, signature_index: 35, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vfwmacc.vf
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vfwmacc.vv
    InstInfo { rw_info_index: 0, signature_index: 35, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vfwmaccbf16.vf
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vfwmaccbf16.vv
    InstInfo { rw_info_index: 0, signature_index: 35, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vfwmsac.vf
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vfwmsac.vv
    InstInfo { rw_info_index: 0, signature_index: 35, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vfwmul.vf
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vfwmul.vv
    InstInfo { rw_info_index: 0, signature_index: 35, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vfwnmacc.vf
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vfwnmacc.vv
    InstInfo { rw_info_index: 0, signature_index: 35, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vfwnmsac.vf
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vfwnmsac.vv
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vfwredosum.vs
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vfwredsum.vs
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vfwredusum.vs
    InstInfo { rw_info_index: 0, signature_index: 35, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vfwsub.vf
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vfwsub.vv
    InstInfo { rw_info_index: 0, signature_index: 35, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vfwsub.wf
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vfwsub.wv
    InstInfo { rw_info_index: 0, signature_index: 30, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // vghsh.vv
    InstInfo { rw_info_index: 1, signature_index: 33, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // vgmul.vv
    InstInfo { rw_info_index: 3, signature_index: 39, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vid.v
    InstInfo { rw_info_index: 1, signature_index: 29, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // viota.m
    InstInfo { rw_info_index: 9, signature_index: 40, mem_access: MEM_LOAD, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // vl1r.v
    InstInfo { rw_info_index: 9, signature_index: 40, mem_access: MEM_LOAD, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // vl1re16.v
    InstInfo { rw_info_index: 9, signature_index: 40, mem_access: MEM_LOAD, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // vl1re32.v
    InstInfo { rw_info_index: 9, signature_index: 40, mem_access: MEM_LOAD, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // vl1re64.v
    InstInfo { rw_info_index: 9, signature_index: 40, mem_access: MEM_LOAD, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // vl1re8.v
    InstInfo { rw_info_index: 9, signature_index: 40, mem_access: MEM_LOAD, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // vl2r.v
    InstInfo { rw_info_index: 9, signature_index: 40, mem_access: MEM_LOAD, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // vl2re16.v
    InstInfo { rw_info_index: 9, signature_index: 40, mem_access: MEM_LOAD, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // vl2re32.v
    InstInfo { rw_info_index: 9, signature_index: 40, mem_access: MEM_LOAD, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // vl2re64.v
    InstInfo { rw_info_index: 9, signature_index: 40, mem_access: MEM_LOAD, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // vl2re8.v
    InstInfo { rw_info_index: 9, signature_index: 40, mem_access: MEM_LOAD, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // vl4r.v
    InstInfo { rw_info_index: 9, signature_index: 40, mem_access: MEM_LOAD, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // vl4re16.v
    InstInfo { rw_info_index: 9, signature_index: 40, mem_access: MEM_LOAD, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // vl4re32.v
    InstInfo { rw_info_index: 9, signature_index: 40, mem_access: MEM_LOAD, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // vl4re64.v
    InstInfo { rw_info_index: 9, signature_index: 40, mem_access: MEM_LOAD, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // vl4re8.v
    InstInfo { rw_info_index: 9, signature_index: 40, mem_access: MEM_LOAD, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // vl8r.v
    InstInfo { rw_info_index: 9, signature_index: 40, mem_access: MEM_LOAD, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // vl8re16.v
    InstInfo { rw_info_index: 9, signature_index: 40, mem_access: MEM_LOAD, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // vl8re32.v
    InstInfo { rw_info_index: 9, signature_index: 40, mem_access: MEM_LOAD, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // vl8re64.v
    InstInfo { rw_info_index: 9, signature_index: 40, mem_access: MEM_LOAD, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // vl8re8.v
    InstInfo { rw_info_index: 9, signature_index: 41, mem_access: MEM_LOAD, mem_width: 2, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vle16.v
    InstInfo { rw_info_index: 9, signature_index: 41, mem_access: MEM_LOAD, mem_width: 2, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vle16ff.v
    InstInfo { rw_info_index: 9, signature_index: 40, mem_access: MEM_LOAD, mem_width: 1, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // vle1.v
    InstInfo { rw_info_index: 9, signature_index: 41, mem_access: MEM_LOAD, mem_width: 4, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vle32.v
    InstInfo { rw_info_index: 9, signature_index: 41, mem_access: MEM_LOAD, mem_width: 4, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vle32ff.v
    InstInfo { rw_info_index: 9, signature_index: 41, mem_access: MEM_LOAD, mem_width: 8, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vle64.v
    InstInfo { rw_info_index: 9, signature_index: 41, mem_access: MEM_LOAD, mem_width: 8, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vle64ff.v
    InstInfo { rw_info_index: 9, signature_index: 41, mem_access: MEM_LOAD, mem_width: 1, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vle8.v
    InstInfo { rw_info_index: 9, signature_index: 41, mem_access: MEM_LOAD, mem_width: 1, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vle8ff.v
    InstInfo { rw_info_index: 9, signature_index: 40, mem_access: MEM_LOAD, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // vlm.v
    InstInfo { rw_info_index: 2, signature_index: 42, mem_access: MEM_LOAD, mem_width: 2, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vloxei16.v
    InstInfo { rw_info_index: 2, signature_index: 42, mem_access: MEM_LOAD, mem_width: 4, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vloxei32.v
    InstInfo { rw_info_index: 2, signature_index: 42, mem_access: MEM_LOAD, mem_width: 8, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vloxei64.v
    InstInfo { rw_info_index: 2, signature_index: 42, mem_access: MEM_LOAD, mem_width: 1, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vloxei8.v
    InstInfo { rw_info_index: 2, signature_index: 43, mem_access: MEM_LOAD, mem_width: 2, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vlse16.v
    InstInfo { rw_info_index: 2, signature_index: 43, mem_access: MEM_LOAD, mem_width: 4, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vlse32.v
    InstInfo { rw_info_index: 2, signature_index: 43, mem_access: MEM_LOAD, mem_width: 8, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vlse64.v
    InstInfo { rw_info_index: 2, signature_index: 43, mem_access: MEM_LOAD, mem_width: 1, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vlse8.v
    InstInfo { rw_info_index: 2, signature_index: 42, mem_access: MEM_LOAD, mem_width: 2, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vluxei16.v
    InstInfo { rw_info_index: 2, signature_index: 42, mem_access: MEM_LOAD, mem_width: 4, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vluxei32.v
    InstInfo { rw_info_index: 2, signature_index: 42, mem_access: MEM_LOAD, mem_width: 8, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vluxei64.v
    InstInfo { rw_info_index: 2, signature_index: 42, mem_access: MEM_LOAD, mem_width: 1, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vluxei8.v
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vmacc.vv
    InstInfo { rw_info_index: 0, signature_index: 28, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vmacc.vx
    InstInfo { rw_info_index: 1, signature_index: 29, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // vmadc.vi
    InstInfo { rw_info_index: 1, signature_index: 29, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // vmadc.vim
    InstInfo { rw_info_index: 0, signature_index: 30, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // vmadc.vv
    InstInfo { rw_info_index: 0, signature_index: 30, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // vmadc.vvm
    InstInfo { rw_info_index: 0, signature_index: 31, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // vmadc.vx
    InstInfo { rw_info_index: 0, signature_index: 31, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // vmadc.vxm
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vmadd.vv
    InstInfo { rw_info_index: 0, signature_index: 28, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vmadd.vx
    InstInfo { rw_info_index: 0, signature_index: 30, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // vmand.mm
    InstInfo { rw_info_index: 0, signature_index: 30, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // vmandn.mm
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vmandnot.mm
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vmax.vv
    InstInfo { rw_info_index: 0, signature_index: 28, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vmax.vx
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vmaxu.vv
    InstInfo { rw_info_index: 0, signature_index: 28, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vmaxu.vx
    InstInfo { rw_info_index: 1, signature_index: 29, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // vmerge.vim
    InstInfo { rw_info_index: 0, signature_index: 30, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // vmerge.vvm
    InstInfo { rw_info_index: 0, signature_index: 31, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // vmerge.vxm
    InstInfo { rw_info_index: 0, signature_index: 35, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vmfeq.vf
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vmfeq.vv
    InstInfo { rw_info_index: 0, signature_index: 35, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vmfge.vf
    InstInfo { rw_info_index: 0, signature_index: 35, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vmfgt.vf
    InstInfo { rw_info_index: 0, signature_index: 35, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vmfle.vf
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vmfle.vv
    InstInfo { rw_info_index: 0, signature_index: 35, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vmflt.vf
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vmflt.vv
    InstInfo { rw_info_index: 0, signature_index: 35, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vmfne.vf
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vmfne.vv
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vmin.vv
    InstInfo { rw_info_index: 0, signature_index: 28, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vmin.vx
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vminu.vv
    InstInfo { rw_info_index: 0, signature_index: 28, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vminu.vx
    InstInfo { rw_info_index: 0, signature_index: 30, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // vmnand.mm
    InstInfo { rw_info_index: 0, signature_index: 30, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // vmnor.mm
    InstInfo { rw_info_index: 0, signature_index: 30, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // vmor.mm
    InstInfo { rw_info_index: 0, signature_index: 30, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // vmorn.mm
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vmornot.mm
    InstInfo { rw_info_index: 0, signature_index: 30, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // vmsbc.vv
    InstInfo { rw_info_index: 0, signature_index: 30, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // vmsbc.vvm
    InstInfo { rw_info_index: 0, signature_index: 31, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // vmsbc.vx
    InstInfo { rw_info_index: 0, signature_index: 31, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // vmsbc.vxm
    InstInfo { rw_info_index: 1, signature_index: 29, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vmsbf.m
    InstInfo { rw_info_index: 1, signature_index: 32, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vmseq.vi
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vmseq.vv
    InstInfo { rw_info_index: 0, signature_index: 28, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vmseq.vx
    InstInfo { rw_info_index: 1, signature_index: 32, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vmsgt.vi
    InstInfo { rw_info_index: 0, signature_index: 28, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vmsgt.vx
    InstInfo { rw_info_index: 1, signature_index: 32, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vmsgtu.vi
    InstInfo { rw_info_index: 0, signature_index: 28, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vmsgtu.vx
    InstInfo { rw_info_index: 1, signature_index: 29, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vmsif.m
    InstInfo { rw_info_index: 1, signature_index: 32, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vmsle.vi
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vmsle.vv
    InstInfo { rw_info_index: 0, signature_index: 28, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vmsle.vx
    InstInfo { rw_info_index: 1, signature_index: 32, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vmsleu.vi
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vmsleu.vv
    InstInfo { rw_info_index: 0, signature_index: 28, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vmsleu.vx
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vmslt.vv
    InstInfo { rw_info_index: 0, signature_index: 28, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vmslt.vx
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vmsltu.vv
    InstInfo { rw_info_index: 0, signature_index: 28, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vmsltu.vx
    InstInfo { rw_info_index: 1, signature_index: 32, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vmsne.vi
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vmsne.vv
    InstInfo { rw_info_index: 0, signature_index: 28, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vmsne.vx
    InstInfo { rw_info_index: 1, signature_index: 29, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vmsof.m
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vmul.vv
    InstInfo { rw_info_index: 0, signature_index: 28, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vmul.vx
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vmulh.vv
    InstInfo { rw_info_index: 0, signature_index: 28, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vmulh.vx
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vmulhsu.vv
    InstInfo { rw_info_index: 0, signature_index: 28, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vmulhsu.vx
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vmulhu.vv
    InstInfo { rw_info_index: 0, signature_index: 28, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vmulhu.vx
    InstInfo { rw_info_index: 1, signature_index: 33, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // vmv1r.v
    InstInfo { rw_info_index: 1, signature_index: 33, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // vmv2r.v
    InstInfo { rw_info_index: 1, signature_index: 33, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // vmv4r.v
    InstInfo { rw_info_index: 1, signature_index: 33, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // vmv8r.v
    InstInfo { rw_info_index: 1, signature_index: 40, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // vmv.s.x
    InstInfo { rw_info_index: 3, signature_index: 39, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // vmv.v.i
    InstInfo { rw_info_index: 1, signature_index: 33, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // vmv.v.v
    InstInfo { rw_info_index: 1, signature_index: 40, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // vmv.v.x
    InstInfo { rw_info_index: 1, signature_index: 44, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // vmv.x.s
    InstInfo { rw_info_index: 0, signature_index: 30, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // vmxnor.mm
    InstInfo { rw_info_index: 0, signature_index: 30, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // vmxor.mm
    InstInfo { rw_info_index: 1, signature_index: 32, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: CpuRwFlags::RISCV_VXSAT.bits() }, // vnclip.wi
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: CpuRwFlags::RISCV_VXSAT.bits() }, // vnclip.wv
    InstInfo { rw_info_index: 0, signature_index: 28, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: CpuRwFlags::RISCV_VXSAT.bits() }, // vnclip.wx
    InstInfo { rw_info_index: 1, signature_index: 32, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: CpuRwFlags::RISCV_VXSAT.bits() }, // vnclipu.wi
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: CpuRwFlags::RISCV_VXSAT.bits() }, // vnclipu.wv
    InstInfo { rw_info_index: 0, signature_index: 28, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: CpuRwFlags::RISCV_VXSAT.bits() }, // vnclipu.wx
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vnmsac.vv
    InstInfo { rw_info_index: 0, signature_index: 28, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vnmsac.vx
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vnmsub.vv
    InstInfo { rw_info_index: 0, signature_index: 28, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vnmsub.vx
    InstInfo { rw_info_index: 1, signature_index: 32, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vnsra.wi
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vnsra.wv
    InstInfo { rw_info_index: 0, signature_index: 28, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vnsra.wx
    InstInfo { rw_info_index: 1, signature_index: 32, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vnsrl.wi
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vnsrl.wv
    InstInfo { rw_info_index: 0, signature_index: 28, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vnsrl.wx
    InstInfo { rw_info_index: 1, signature_index: 32, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vor.vi
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vor.vv
    InstInfo { rw_info_index: 0, signature_index: 28, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vor.vx
    InstInfo { rw_info_index: 1, signature_index: 34, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vpopc.m
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vredand.vs
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vredmax.vs
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vredmaxu.vs
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vredmin.vs
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vredminu.vs
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vredor.vs
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vredsum.vs
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vredxor.vs
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vrem.vv
    InstInfo { rw_info_index: 0, signature_index: 28, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vrem.vx
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vremu.vv
    InstInfo { rw_info_index: 0, signature_index: 28, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vremu.vx
    InstInfo { rw_info_index: 1, signature_index: 29, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vrev8.v
    InstInfo { rw_info_index: 1, signature_index: 32, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vrgather.vi
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vrgather.vv
    InstInfo { rw_info_index: 0, signature_index: 28, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vrgather.vx
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vrgatherei16.vv
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vrol.vv
    InstInfo { rw_info_index: 0, signature_index: 28, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vrol.vx
    InstInfo { rw_info_index: 1, signature_index: 32, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vror.vi
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vror.vv
    InstInfo { rw_info_index: 0, signature_index: 28, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vror.vx
    InstInfo { rw_info_index: 1, signature_index: 32, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vrsub.vi
    InstInfo { rw_info_index: 0, signature_index: 28, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vrsub.vx
    InstInfo { rw_info_index: 18, signature_index: 40, mem_access: MEM_STORE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // vs1r.v
    InstInfo { rw_info_index: 18, signature_index: 40, mem_access: MEM_STORE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // vs2r.v
    InstInfo { rw_info_index: 18, signature_index: 40, mem_access: MEM_STORE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // vs4r.v
    InstInfo { rw_info_index: 18, signature_index: 40, mem_access: MEM_STORE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // vs8r.v
    InstInfo { rw_info_index: 1, signature_index: 32, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: CpuRwFlags::RISCV_VXSAT.bits() }, // vsadd.vi
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: CpuRwFlags::RISCV_VXSAT.bits() }, // vsadd.vv
    InstInfo { rw_info_index: 0, signature_index: 28, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: CpuRwFlags::RISCV_VXSAT.bits() }, // vsadd.vx
    InstInfo { rw_info_index: 1, signature_index: 32, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: CpuRwFlags::RISCV_VXSAT.bits() }, // vsaddu.vi
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: CpuRwFlags::RISCV_VXSAT.bits() }, // vsaddu.vv
    InstInfo { rw_info_index: 0, signature_index: 28, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: CpuRwFlags::RISCV_VXSAT.bits() }, // vsaddu.vx
    InstInfo { rw_info_index: 0, signature_index: 30, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // vsbc.vvm
    InstInfo { rw_info_index: 0, signature_index: 31, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // vsbc.vxm
    InstInfo { rw_info_index: 18, signature_index: 41, mem_access: MEM_STORE, mem_width: 2, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vse16.v
    InstInfo { rw_info_index: 18, signature_index: 40, mem_access: MEM_STORE, mem_width: 1, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // vse1.v
    InstInfo { rw_info_index: 18, signature_index: 41, mem_access: MEM_STORE, mem_width: 4, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vse32.v
    InstInfo { rw_info_index: 18, signature_index: 41, mem_access: MEM_STORE, mem_width: 8, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vse64.v
    InstInfo { rw_info_index: 18, signature_index: 41, mem_access: MEM_STORE, mem_width: 1, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vse8.v
    InstInfo { rw_info_index: 3, signature_index: 13, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // vsetivli
    InstInfo { rw_info_index: 0, signature_index: 0, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // vsetvl
    InstInfo { rw_info_index: 1, signature_index: 1, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // vsetvli
    InstInfo { rw_info_index: 1, signature_index: 29, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vsext.vf2
    InstInfo { rw_info_index: 1, signature_index: 29, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vsext.vf4
    InstInfo { rw_info_index: 1, signature_index: 29, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vsext.vf8
    InstInfo { rw_info_index: 0, signature_index: 30, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // vsha2ch.vv
    InstInfo { rw_info_index: 0, signature_index: 30, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // vsha2cl.vv
    InstInfo { rw_info_index: 0, signature_index: 30, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // vsha2ms.vv
    InstInfo { rw_info_index: 0, signature_index: 28, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vslide1down.vx
    InstInfo { rw_info_index: 0, signature_index: 28, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vslide1up.vx
    InstInfo { rw_info_index: 1, signature_index: 32, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vslidedown.vi
    InstInfo { rw_info_index: 0, signature_index: 28, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vslidedown.vx
    InstInfo { rw_info_index: 1, signature_index: 32, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vslideup.vi
    InstInfo { rw_info_index: 0, signature_index: 28, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vslideup.vx
    InstInfo { rw_info_index: 1, signature_index: 32, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vsll.vi
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vsll.vv
    InstInfo { rw_info_index: 0, signature_index: 28, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vsll.vx
    InstInfo { rw_info_index: 1, signature_index: 29, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // vsm3c.vi
    InstInfo { rw_info_index: 0, signature_index: 30, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // vsm3me.vv
    InstInfo { rw_info_index: 1, signature_index: 29, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // vsm4k.vi
    InstInfo { rw_info_index: 1, signature_index: 33, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // vsm4r.vs
    InstInfo { rw_info_index: 1, signature_index: 33, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // vsm4r.vv
    InstInfo { rw_info_index: 18, signature_index: 40, mem_access: MEM_STORE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // vsm.v
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: CpuRwFlags::RISCV_VXSAT.bits() }, // vsmul.vv
    InstInfo { rw_info_index: 0, signature_index: 28, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: CpuRwFlags::RISCV_VXSAT.bits() }, // vsmul.vx
    InstInfo { rw_info_index: 19, signature_index: 42, mem_access: MEM_STORE, mem_width: 2, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vsoxei16.v
    InstInfo { rw_info_index: 19, signature_index: 42, mem_access: MEM_STORE, mem_width: 4, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vsoxei32.v
    InstInfo { rw_info_index: 19, signature_index: 42, mem_access: MEM_STORE, mem_width: 8, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vsoxei64.v
    InstInfo { rw_info_index: 19, signature_index: 42, mem_access: MEM_STORE, mem_width: 1, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vsoxei8.v
    InstInfo { rw_info_index: 1, signature_index: 32, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vsra.vi
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vsra.vv
    InstInfo { rw_info_index: 0, signature_index: 28, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vsra.vx
    InstInfo { rw_info_index: 1, signature_index: 32, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vsrl.vi
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vsrl.vv
    InstInfo { rw_info_index: 0, signature_index: 28, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vsrl.vx
    InstInfo { rw_info_index: 19, signature_index: 43, mem_access: MEM_STORE, mem_width: 2, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vsse16.v
    InstInfo { rw_info_index: 19, signature_index: 43, mem_access: MEM_STORE, mem_width: 4, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vsse32.v
    InstInfo { rw_info_index: 19, signature_index: 43, mem_access: MEM_STORE, mem_width: 8, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vsse64.v
    InstInfo { rw_info_index: 19, signature_index: 43, mem_access: MEM_STORE, mem_width: 1, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vsse8.v
    InstInfo { rw_info_index: 1, signature_index: 32, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vssra.vi
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vssra.vv
    InstInfo { rw_info_index: 0, signature_index: 28, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vssra.vx
    InstInfo { rw_info_index: 1, signature_index: 32, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vssrl.vi
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vssrl.vv
    InstInfo { rw_info_index: 0, signature_index: 28, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vssrl.vx
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: CpuRwFlags::RISCV_VXSAT.bits() }, // vssub.vv
    InstInfo { rw_info_index: 0, signature_index: 28, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: CpuRwFlags::RISCV_VXSAT.bits() }, // vssub.vx
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: CpuRwFlags::RISCV_VXSAT.bits() }, // vssubu.vv
    InstInfo { rw_info_index: 0, signature_index: 28, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: CpuRwFlags::RISCV_VXSAT.bits() }, // vssubu.vx
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vsub.vv
    InstInfo { rw_info_index: 0, signature_index: 28, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vsub.vx
    InstInfo { rw_info_index: 19, signature_index: 42, mem_access: MEM_STORE, mem_width: 2, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vsuxei16.v
    InstInfo { rw_info_index: 19, signature_index: 42, mem_access: MEM_STORE, mem_width: 4, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vsuxei32.v
    InstInfo { rw_info_index: 19, signature_index: 42, mem_access: MEM_STORE, mem_width: 8, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vsuxei64.v
    InstInfo { rw_info_index: 19, signature_index: 42, mem_access: MEM_STORE, mem_width: 1, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vsuxei8.v
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vwadd.vv
    InstInfo { rw_info_index: 0, signature_index: 28, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vwadd.vx
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vwadd.wv
    InstInfo { rw_info_index: 0, signature_index: 28, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vwadd.wx
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vwaddu.vv
    InstInfo { rw_info_index: 0, signature_index: 28, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vwaddu.vx
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vwaddu.wv
    InstInfo { rw_info_index: 0, signature_index: 28, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vwaddu.wx
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vwmacc.vv
    InstInfo { rw_info_index: 0, signature_index: 28, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vwmacc.vx
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vwmaccsu.vv
    InstInfo { rw_info_index: 0, signature_index: 28, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vwmaccsu.vx
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vwmaccu.vv
    InstInfo { rw_info_index: 0, signature_index: 28, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vwmaccu.vx
    InstInfo { rw_info_index: 0, signature_index: 28, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vwmaccus.vx
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vwmul.vv
    InstInfo { rw_info_index: 0, signature_index: 28, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vwmul.vx
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vwmulsu.vv
    InstInfo { rw_info_index: 0, signature_index: 28, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vwmulsu.vx
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vwmulu.vv
    InstInfo { rw_info_index: 0, signature_index: 28, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vwmulu.vx
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vwredsum.vs
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vwredsumu.vs
    InstInfo { rw_info_index: 1, signature_index: 32, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vwsll.vi
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vwsll.vv
    InstInfo { rw_info_index: 0, signature_index: 28, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vwsll.vx
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vwsub.vv
    InstInfo { rw_info_index: 0, signature_index: 28, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vwsub.vx
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vwsub.wv
    InstInfo { rw_info_index: 0, signature_index: 28, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vwsub.wx
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vwsubu.vv
    InstInfo { rw_info_index: 0, signature_index: 28, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vwsubu.vx
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vwsubu.wv
    InstInfo { rw_info_index: 0, signature_index: 28, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vwsubu.wx
    InstInfo { rw_info_index: 1, signature_index: 32, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vxor.vi
    InstInfo { rw_info_index: 0, signature_index: 27, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vxor.vv
    InstInfo { rw_info_index: 0, signature_index: 28, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vxor.vx
    InstInfo { rw_info_index: 1, signature_index: 29, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vzext.vf2
    InstInfo { rw_info_index: 1, signature_index: 29, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vzext.vf4
    InstInfo { rw_info_index: 1, signature_index: 29, mem_access: MEM_NONE, mem_width: 0, implicit_index: 6, flags: 0, read_flags: 0, write_flags: 0 }, // vzext.vf8
    InstInfo { rw_info_index: 8, signature_index: 7, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: FLAG_VOLATILE, read_flags: 0, write_flags: 0 }, // wfi
    InstInfo { rw_info_index: 8, signature_index: 7, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // wrs.nto
    InstInfo { rw_info_index: 8, signature_index: 7, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // wrs.sto
    InstInfo { rw_info_index: 0, signature_index: 0, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // xnor
    InstInfo { rw_info_index: 0, signature_index: 0, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // xor
    InstInfo { rw_info_index: 1, signature_index: 1, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // xori
    InstInfo { rw_info_index: 0, signature_index: 0, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // xperm4
    InstInfo { rw_info_index: 0, signature_index: 0, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // xperm8
    InstInfo { rw_info_index: 1, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // zext.b
    InstInfo { rw_info_index: 1, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // zext.h
    InstInfo { rw_info_index: 1, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // zext.h.rv32
    InstInfo { rw_info_index: 1, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // zext.w
    InstInfo { rw_info_index: 1, signature_index: 3, mem_access: MEM_NONE, mem_width: 0, implicit_index: 0, flags: 0, read_flags: 0, write_flags: 0 }, // zip
];

impl Opcode {
    /// Returns the effects database entry for this opcode.
    pub fn inst_info(self) -> &'static InstInfo {
        &INST_INFO_TABLE[self as usize]
    }

    /// Returns the implicit fixed-register effects of this opcode.
    pub fn implicit_reg_effects(self) -> &'static ImplicitRegEffects {
        &IMPLICIT_REG_TABLE[self.inst_info().implicit_index as usize]
    }
}