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asmkit/aarch64/
emit.rs

1//! Top-level emit path: InstInfo lookup, signature validation, operand
2//! analysis, and dispatch to the emit handlers (port of AsmJit's
3//! `Assembler::_emit` from `a64assembler.cpp`).
4//!
5//! AsmJit's `goto EmitOp` / `goto EmitOp_DispImm` / `goto EmitOp_Rel` targets
6//! become the [`Handler`] enum: the encoding arms (a `match` on [`Encoding`])
7//! validate operands and compose the opcode in [`A64EmitState`], while the
8//! actual word emission is done by the handlers in [`super::encoder`].
9//!
10//! Derived from AsmJit (Zlib license) — this file is an altered version; see LICENSE notices.
11
12#![allow(clippy::eq_op, clippy::erasing_op, dead_code, unused)]
13use crate::AsmError;
14use crate::aarch64::encoder::*;
15use crate::aarch64::encoder_tables::*;
16use crate::aarch64::operands::*;
17use crate::aarch64::{Assembler, Gp, Reg, ShiftOp, instdb::*};
18use crate::core::arch_traits::Arch;
19use crate::core::buffer::{Constant, LabelUse, Reloc, RelocDistance, RelocTarget};
20use crate::core::globals::CondCode;
21use crate::core::operand::*;
22use crate::core::{buffer::CodeBuffer, patch::PatchSiteId};
23
24macro_rules! B {
25    ($e: expr) => {
26        1 << $e
27    };
28}
29
30macro_rules! check_signature {
31    ($op0: expr, $op1: expr) => {
32        $op0.signature() == $op1.signature()
33    };
34    ($op0: expr, $op1: expr, $op2: expr) => {
35        $op0.signature() == $op1.signature() && $op1.signature() == $op2.signature()
36    };
37
38    ($op0: expr, $op1: expr, $op2: expr, $op3: expr) => {
39        $op0.signature() == $op1.signature()
40            && $op1.signature() == $op2.signature()
41            && $op2.signature() == $op3.signature()
42    };
43}
44
45macro_rules! enc_ops {
46    ($op0: ident) => {
47        OperandType::$op0 as u32
48    };
49
50    ($op0: ident, $op1: ident) => {
51        OperandType::$op0 as u32 | (OperandType::$op1 as u32) << 3
52    };
53    ($op0: ident, $op1: ident, $op2: ident) => {
54        OperandType::$op0 as u32 | (OperandType::$op1 as u32) << 3 | (OperandType::$op2 as u32) << 6
55    };
56    ($op0: ident, $op1: ident, $op2: ident, $op3: ident) => {
57        OperandType::$op0 as u32
58            | (OperandType::$op1 as u32) << 3
59            | (OperandType::$op2 as u32) << 6
60            | (OperandType::$op3 as u32) << 9
61    };
62}
63
64/// Emit handler selected by an encoding arm (AsmJit's `goto EmitXxx` labels).
65#[derive(Clone, Copy, PartialEq, Eq, Debug)]
66pub(crate) enum Handler {
67    /// `EmitOp`: write the composed opcode word.
68    Op,
69    /// `EmitOp_DispImm`: pack the displacement immediate, then `EmitOp`.
70    OpDispImm,
71    /// `EmitOp_Rel`: resolve a label/immediate pc-relative operand, then
72    /// `EmitOp_DispImm`. Falls through when `rm_rel` is not relative.
73    OpRel,
74    /// Multi-word emission (mov sequences in `multiple_op_data`).
75    Multi,
76}
77
78impl<'a> Assembler<'a> {
79    /// Port of AsmJit's `Assembler::_emit`: validates the instruction's
80    /// operand signature, composes the opcode, and dispatches to the emit
81    /// handlers. Errors are recorded in `last_error`.
82    pub(crate) fn _emit(&mut self, id: u32, ops: &[&Operand]) {
83        if id & !(InstId::REAL_ID | InstId::ARM_COND) != 0 {
84            self.last_error = Some(AsmError::InvalidInstruction);
85            return;
86        }
87
88        let inst_cc = InstId::extract_cc(id);
89        let inst_id = InstId::extract_real_id(id);
90
91        if inst_id == InstId::None as u32 || inst_id >= InstId::_Count as u32 {
92            self.last_error = Some(AsmError::InvalidInstruction);
93            return;
94        }
95
96        let inst_info = &INST_INFO_TABLE[inst_id as usize];
97        let mut encoding_index = inst_info.encoding_data_index as usize;
98
99        let mut st = A64EmitState::new();
100
101        let isign4;
102        let inst_flags;
103
104        const NOREG: &Operand = &Operand::new();
105
106        let op0 = *ops.get(0).unwrap_or(&NOREG);
107        let op1 = *ops.get(1).unwrap_or(&NOREG);
108        let op2 = *ops.get(2).unwrap_or(&NOREG);
109        let op3 = *ops.get(3).unwrap_or(&NOREG);
110        let op4 = *ops.get(4).unwrap_or(&NOREG);
111        let op5 = *ops.get(5).unwrap_or(&NOREG);
112
113        isign4 = op0.op_type() as u32
114            + ((op1.op_type() as u32) << 3)
115            + ((op2.op_type() as u32) << 6)
116            + ((op3.op_type() as u32) << 9);
117        inst_flags = inst_info.flags;
118
119        macro_rules! check_features {
120            () => {{
121                let (required, context) =
122                    required_features_for_form(inst_id as usize, st.opcode.get(), ops);
123                if !self.environment().supports_aarch64_features(required) {
124                    self.last_error = Some(AsmError::MissingCpuFeature { feature: context });
125                    return;
126                }
127            }};
128        }
129
130        macro_rules! emit_op {
131            () => {{
132                check_features!();
133                self.emit_handler(Handler::Op, &mut st);
134                return;
135            }};
136        }
137
138        macro_rules! emit_disp_imm {
139            () => {{
140                check_features!();
141                self.emit_handler(Handler::OpDispImm, &mut st);
142                return;
143            }};
144        }
145
146        macro_rules! emit_rel {
147            () => {{
148                check_features!();
149                if self.emit_handler(Handler::OpRel, &mut st) {
150                    return;
151                }
152            }};
153        }
154
155        macro_rules! emit_rd0 {
156            () => {
157                st.opcode.add_reg(op0.id(), 0);
158                emit_op!();
159            };
160        }
161
162        macro_rules! emit_rn5 {
163            () => {
164                st.opcode.add_reg(op0.id(), 5);
165                emit_op!();
166            };
167        }
168
169        macro_rules! emit_rn5_rm16 {
170            () => {
171                st.opcode.add_reg(op0.id(), 5);
172                st.opcode.add_reg(op1.id(), 16);
173                emit_op!();
174            };
175        }
176
177        macro_rules! emit_rd0_rn5 {
178            () => {
179                st.opcode.add_reg(op0.id(), 0);
180                st.opcode.add_reg(op1.id(), 5);
181                emit_op!();
182            };
183        }
184
185        macro_rules! emit_rd0_rn5_rm16_ra10 {
186            () => {
187                st.opcode.add_reg(op0.id(), 0);
188                st.opcode.add_reg(op1.id(), 5);
189                st.opcode.add_reg(op2.id(), 16);
190                st.opcode.add_reg(op3.id(), 10);
191                emit_op!();
192            };
193        }
194
195        macro_rules! emit_rd0_rn5_rm16 {
196            () => {
197                st.opcode.add_reg(op0.id(), 0);
198                st.opcode.add_reg(op1.id(), 5);
199                st.opcode.add_reg(op2.id(), 16);
200                emit_op!();
201            };
202        }
203
204        macro_rules! emit_mem_base_rn5 {
205            () => {
206                st.opcode.add_reg(op0.as_::<Mem>().base_id(), 5);
207                emit_op!();
208            };
209        }
210
211        macro_rules! emit_mem_base_index_rn5_rm16 {
212            () => {
213                st.opcode.add_reg(op0.as_::<Mem>().base_id(), 5);
214                st.opcode.add_reg(op0.as_::<Mem>().index_id(), 16);
215                emit_op!();
216            };
217        }
218
219        macro_rules! emit_mem_base_no_imm_rn5 {
220            () => {
221                st.opcode.add_reg(st.rm_rel.as_::<Mem>().base_id(), 5);
222                emit_op!();
223            };
224        }
225
226        let mut encoding = Encoding::try_from(inst_info.encoding).expect("Invalid encoding index");
227
228        macro_rules! simd_insn {
229            () => {
230                if isign4 == enc_ops!(Reg, Reg) && op0.as_::<Reg>().is_vec128() {
231                    if !op0.as_::<Vec>().has_element_index() {
232                        self.last_error = Some(AsmError::InvalidInstruction);
233                        return;
234                    }
235                    let element_type = op0.as_::<Vec>().element_type() as u32;
236                    let dst_index = op0.as_::<Vec>().element_index();
237                    let lsb_index = element_type - 1;
238                    let imm5 = ((dst_index << 1) | 1) << lsb_index;
239                    if imm5 > 31 {
240                        self.last_error = Some(AsmError::InvalidOperand);
241                        return;
242                    }
243                    if op1.as_::<Reg>().is_gp() {
244                        // INS - Vec[N] <- GP register.
245                        st.opcode.reset(0b0100111000000000000111 << 10);
246                        st.opcode.add_imm(imm5, 16);
247                        emit_rd0_rn5!();
248                        return;
249                    } else if op1.as_::<Reg>().is_vec128() && op1.as_::<Vec>().has_element_index() {
250                        // INS - Vec[N] <- Vec[M].
251                        if op0.as_::<Vec>().element_type() != op1.as_::<Vec>().element_type() {
252                            self.last_error = Some(AsmError::InvalidInstruction);
253                            return;
254                        }
255                        let src_index = op1.as_::<Vec>().element_index();
256                        if op0.as_::<Reg>().reg_type() != op1.as_::<Reg>().reg_type() {
257                            self.last_error = Some(AsmError::InvalidInstruction);
258                            return;
259                        }
260                        let imm4 = src_index << lsb_index;
261                        if imm4 > 15 {
262                            self.last_error = Some(AsmError::InvalidOperand);
263                            return;
264                        }
265                        st.opcode.reset(0b0110111000000000000001 << 10);
266                        st.opcode.add_imm(imm5, 16);
267                        st.opcode.add_imm(imm4, 11);
268                        emit_rd0_rn5!();
269                        return;
270                    }
271                }
272            };
273        }
274
275        macro_rules! simd_dup {
276            () => {
277                if isign4 == enc_ops!(Reg, Reg) {
278                    let k_valid_encodings = B!(VecElementType::B as u32 + 0)
279                        | B!(VecElementType::H as u32 + 0)
280                        | B!(VecElementType::S as u32 + 0)
281                        | B!(VecElementType::B as u32 + 8)
282                        | B!(VecElementType::H as u32 + 8)
283                        | B!(VecElementType::S as u32 + 8)
284                        | B!(VecElementType::D as u32 + 8);
285
286                    let q =
287                        (op0.as_::<Reg>().reg_type() as u32).wrapping_sub(RegType::Vec64 as u32);
288
289                    if op1.as_::<Reg>().is_gp() {
290                        let element_type = op0.as_::<Vec>().element_type() as u32;
291                        if q > 1 || !bit_test(k_valid_encodings, (q << 3) | element_type) {
292                            self.last_error = Some(AsmError::InvalidInstruction);
293                            return;
294                        }
295
296                        let lsb_index = element_type - 1;
297                        let imm5 = 1u32 << lsb_index;
298
299                        st.opcode.reset(0b0000111000000000000011 << 10);
300                        st.opcode.add_imm(q, 30);
301                        st.opcode.add_imm(imm5, 16);
302                        emit_rd0_rn5!();
303                    } else if !op1.as_::<Reg>().is_vec() || !op1.as_::<Vec>().has_element_index() {
304                        self.last_error = Some(AsmError::InvalidInstruction);
305                        return;
306                    } else {
307                        let dst_index = op1.as_::<Vec>().element_index();
308                        if !op0.as_::<Vec>().has_element_type() {
309                            let lsb_index = (op0.as_::<Reg>().reg_type() as u32)
310                                .wrapping_sub(RegType::Vec8 as u32);
311                            if lsb_index
312                                != op1.as_::<Vec>().element_type() as u32 - VecElementType::B as u32
313                                || lsb_index > 3
314                            {
315                                self.last_error = Some(AsmError::InvalidInstruction);
316                                return;
317                            }
318
319                            let imm5 = ((dst_index << 1) | 1u32) << lsb_index;
320                            if imm5 > 31 {
321                                self.last_error = Some(AsmError::InvalidOperand);
322                                return;
323                            }
324
325                            st.opcode.reset(0b0101111000000000000001 << 10);
326                            st.opcode.add_imm(imm5, 16);
327                            emit_rd0_rn5!();
328                        } else {
329                            let element_type = op0.as_::<Vec>().element_type() as u32;
330                            if q > 1 || !bit_test(k_valid_encodings, (q << 3) | element_type) {
331                                self.last_error = Some(AsmError::InvalidInstruction);
332                                return;
333                            }
334
335                            let lsb_index = element_type - 1;
336                            let imm5 = ((dst_index << 1) | 1u32) << lsb_index;
337                            if imm5 > 31 {
338                                self.last_error = Some(AsmError::InvalidOperand);
339                                return;
340                            }
341
342                            st.opcode.reset(0b0000111000000000000001 << 10);
343                            st.opcode.add_imm(q, 30);
344                            st.opcode.add_imm(imm5, 16);
345                            emit_rd0_rn5!();
346                        }
347                    }
348                }
349            };
350        }
351
352        macro_rules! simd_umov {
353            () => {
354                let op_data = &SIMD_SMOV_UMOV[encoding_index];
355                if isign4 == enc_ops!(Reg, Reg)
356                    && op0.as_::<Reg>().is_gp()
357                    && op1.as_::<Reg>().is_vec()
358                {
359                    let size_op = element_type_to_size_op(
360                        op_data.vec_op_type,
361                        op1.as_::<Reg>().reg_type(),
362                        op1.as_::<Vec>().element_type(),
363                    );
364                    if !size_op.is_valid() {
365                        self.last_error = Some(AsmError::InvalidInstruction);
366                        return;
367                    }
368                    if !op1.as_::<Vec>().has_element_index() {
369                        self.last_error = Some(AsmError::InvalidInstruction);
370                        return;
371                    }
372                    let x = op0.as_::<Gp>().is_gp64() as u32;
373                    let gp_must_be_x = (size_op.size() >= 3u32 - op_data.is_signed as u32) as u32;
374                    if op_data.is_signed != 0 {
375                        if gp_must_be_x != 0 && x == 0 {
376                            self.last_error = Some(AsmError::InvalidInstruction);
377                            return;
378                        }
379                    } else {
380                        if x != gp_must_be_x {
381                            self.last_error = Some(AsmError::InvalidInstruction);
382                            return;
383                        }
384                    }
385                    let element_index = op1.as_::<Vec>().element_index();
386                    let max_element_index = 15u32 >> size_op.size();
387                    if element_index > max_element_index {
388                        self.last_error = Some(AsmError::InvalidOperand);
389                        return;
390                    }
391                    let imm5 = (1u32 | (element_index << 1)) << size_op.size();
392                    st.opcode.reset((op_data.opcode as u32) << 10);
393                    st.opcode.add_imm(x, 30);
394                    st.opcode.add_imm(imm5, 16);
395                    emit_rd0_rn5!();
396                    return;
397                }
398            };
399        }
400
401        match encoding {
402            Encoding::BaseOp => {
403                let op_data = &BASE_OP[encoding_index];
404                if isign4 == 0 {
405                    st.opcode.reset(op_data.opcode);
406                    emit_op!();
407                }
408            }
409
410            Encoding::BaseOpX16 => {
411                let op_data = &BASE_OP_X16[encoding_index];
412                if isign4 == enc_ops!(Reg) && op0.as_::<Reg>().is_gp64() && op0.id() == 16 {
413                    st.opcode.reset(op_data.opcode);
414                    emit_op!();
415                }
416            }
417
418            Encoding::BaseOpImm => {
419                let op_data = &BASE_OP_IMM[encoding_index];
420                if isign4 == enc_ops!(Imm) {
421                    let imm = op0.as_::<Imm>().value() as u64;
422                    let imm_max = 1u64 << op_data.imm_bits as u32;
423                    if imm >= imm_max {
424                        self.last_error = Some(AsmError::TooLarge);
425                        return;
426                    }
427                    st.opcode.reset(op_data.opcode);
428                    st.opcode.add_imm(imm as u32, op_data.imm_offset as _);
429                    emit_op!();
430                }
431            }
432
433            Encoding::BaseR => {
434                let op_data = &BASE_R[encoding_index];
435                if isign4 == enc_ops!(Reg) {
436                    st.opcode.reset(op_data.opcode);
437                    st.opcode.add_reg(op0.id(), op_data.r_shift);
438                    emit_op!();
439                }
440            }
441
442            Encoding::BaseRR => {
443                let op_data = &BASE_RR[encoding_index];
444                if isign4 == enc_ops!(Reg, Reg) {
445                    let mut x = 0;
446                    if !check_gp_typex(op0, op_data.a_type, &mut x) {
447                        self.last_error = Some(AsmError::InvalidOperand);
448                        return;
449                    }
450                    if !check_gp_type(op1, op_data.b_type) {
451                        self.last_error = Some(AsmError::InvalidOperand);
452                        return;
453                    }
454
455                    if op_data.uniform != 0 && !check_signature!(op0, op1) {
456                        self.last_error = Some(AsmError::InvalidOperand);
457                        return;
458                    }
459
460                    if !check_gp_id(op0, op_data.a_hi_id) || !check_gp_id(op1, op_data.b_hi_id) {
461                        self.last_error = Some(AsmError::InvalidOperand);
462                        return;
463                    }
464                    st.opcode.reset(op_data.opcode);
465                    st.opcode.add_imm(x, 31);
466                    st.opcode.add_reg(op1.id(), op_data.b_shift);
467                    st.opcode.add_reg(op0.id(), op_data.a_shift);
468                    emit_op!();
469                }
470            }
471
472            Encoding::BaseRRR => {
473                let op_data = &BASE_RRR[encoding_index];
474                if isign4 == enc_ops!(Reg, Reg, Reg) {
475                    let mut x = 0;
476                    if !check_gp_typex(op0, op_data.a_type, &mut x) {
477                        self.last_error = Some(AsmError::InvalidOperand);
478                        return;
479                    }
480                    if !check_gp_type(op1, op_data.b_type) || !check_gp_type(op2, op_data.c_type) {
481                        self.last_error = Some(AsmError::InvalidOperand);
482                        return;
483                    }
484
485                    if op_data.uniform != 0 && !check_signature!(op0, op1, op2) {
486                        self.last_error = Some(AsmError::InvalidInstruction);
487                        return;
488                    }
489
490                    if !check_gp_id(op0, op_data.a_hi_id)
491                        || !check_gp_id(op1, op_data.b_hi_id)
492                        || !check_gp_id(op2, op_data.c_hi_id)
493                    {
494                        self.last_error = Some(AsmError::InvalidOperand);
495                        return;
496                    }
497                    st.opcode.reset(op_data.opcode());
498                    st.opcode.add_imm(x, 31);
499                    st.opcode.add_reg(op2.id(), 16);
500                    st.opcode.add_reg(op1.id(), 5);
501                    st.opcode.add_reg(op0.id(), 0);
502                    emit_op!();
503                }
504            }
505
506            Encoding::BaseRRRR => {
507                let op_data = &BASE_RRRR[encoding_index];
508                if isign4 == enc_ops!(Reg, Reg, Reg, Reg) {
509                    let mut x = 0;
510                    if !check_gp_typex(op0, op_data.a_type, &mut x) {
511                        self.last_error = Some(AsmError::InvalidOperand);
512                        return;
513                    }
514                    if !check_gp_type(op1, op_data.b_type)
515                        || !check_gp_type(op2, op_data.c_type)
516                        || !check_gp_type(op3, op_data.d_type)
517                    {
518                        self.last_error = Some(AsmError::InvalidOperand);
519                        return;
520                    }
521
522                    if op_data.uniform != 0 && !check_signature!(op0, op1, op2, op3) {
523                        self.last_error = Some(AsmError::InvalidInstruction);
524                        return;
525                    }
526
527                    if !check_gp_id(op0, op_data.a_hi_id)
528                        || !check_gp_id(op1, op_data.b_hi_id)
529                        || !check_gp_id(op2, op_data.c_hi_id)
530                        || !check_gp_id(op3, op_data.d_hi_id)
531                    {
532                        self.last_error = Some(AsmError::InvalidOperand);
533                        return;
534                    }
535                    st.opcode.reset(op_data.opcode());
536                    st.opcode.add_imm(x, 31);
537                    st.opcode.add_reg(op2.id(), 16);
538                    st.opcode.add_reg(op3.id(), 10);
539                    st.opcode.add_reg(op1.id(), 5);
540                    st.opcode.add_reg(op0.id(), 0);
541                    emit_op!();
542                }
543            }
544
545            Encoding::BaseRRII => {
546                let op_data = &BASE_RRII[encoding_index];
547                if isign4 == enc_ops!(Reg, Reg, Imm, Imm) {
548                    let mut x = 0;
549                    if !check_gp_typex(op0, op_data.a_type, &mut x) {
550                        self.last_error = Some(AsmError::InvalidOperand);
551                        return;
552                    }
553                    if !check_gp_type(op1, op_data.b_type) {
554                        self.last_error = Some(AsmError::InvalidOperand);
555                        return;
556                    }
557
558                    if !check_gp_id(op0, op_data.a_hi_id) || !check_gp_id(op1, op_data.b_hi_id) {
559                        self.last_error = Some(AsmError::InvalidOperand);
560                        return;
561                    }
562
563                    let imm2 = op2.as_::<Imm>().value() as u64;
564                    let imm3 = op3.as_::<Imm>().value() as u64;
565
566                    if imm2 >= 1u64 << (op_data.a_imm_size + op_data.a_imm_discard_lsb)
567                        || imm3 >= 1u64 << (op_data.b_imm_size + op_data.b_imm_discard_lsb)
568                    {
569                        self.last_error = Some(AsmError::TooLarge);
570                        return;
571                    }
572
573                    let a_imm = imm2 as u32 >> op_data.a_imm_discard_lsb;
574                    let b_imm = imm3 as u32 >> op_data.b_imm_discard_lsb;
575
576                    if (a_imm << op_data.a_imm_discard_lsb) != imm2 as u32
577                        || (b_imm << op_data.b_imm_discard_lsb) != imm3 as u32
578                    {
579                        self.last_error = Some(AsmError::TooLarge);
580                        return;
581                    }
582
583                    st.opcode.reset(op_data.opcode());
584                    st.opcode.add_imm(a_imm, op_data.a_imm_offset);
585                    st.opcode.add_imm(b_imm, op_data.b_imm_offset);
586                    st.opcode.add_reg(op1.id(), 5);
587                    st.opcode.add_reg(op0.id(), 0);
588                    emit_op!();
589                }
590            }
591
592            Encoding::BaseMov => {
593                let x = (op0.as_::<Reg>().typ() as u32).wrapping_sub(RegType::Gp32 as u32);
594                if x > 1 {
595                    self.last_error = Some(AsmError::InvalidOperand);
596                    return;
597                }
598
599                if isign4 == enc_ops!(Reg, Reg) {
600                    if !op0.as_::<Reg>().is_gp() || !op1.as_::<Reg>().is_gp() {
601                        self.last_error = Some(AsmError::InvalidOperand);
602                        return;
603                    }
604
605                    if !check_signature!(op0, op1) {
606                        self.last_error = Some(AsmError::InvalidInstruction);
607                        return;
608                    }
609
610                    let has_sp = op0.as_::<Reg>().is_sp() || op1.as_::<Reg>().is_sp();
611
612                    if has_sp {
613                        if !check_gp_id2(op0, op1, 31) {
614                            self.last_error = Some(AsmError::InvalidOperand);
615                            return;
616                        }
617                        st.opcode.reset(0b00010001000000000000000000000000);
618                        st.opcode.add_imm(x, 31);
619                        st.opcode.add_reg(op1.id(), 5);
620                        st.opcode.add_reg(op0.id(), 0);
621                        emit_op!();
622                    } else {
623                        if !check_gp_id2(op0, op1, 63) {
624                            self.last_error = Some(AsmError::InvalidOperand);
625                            return;
626                        }
627                        st.opcode.reset(0b00101010000000000000001111100000);
628                        st.opcode.add_imm(x, 31);
629                        st.opcode.add_reg(op1.id(), 16);
630                        st.opcode.add_reg(op0.id(), 0);
631                        emit_op!();
632                    }
633                }
634
635                if isign4 == enc_ops!(Reg, Imm) {
636                    if !op0.as_::<Reg>().is_gp() {
637                        self.last_error = Some(AsmError::InvalidOperand);
638                        return;
639                    }
640
641                    let mut imm_value = op1.as_::<Imm>().value() as u64;
642                    if x == 0 {
643                        imm_value &= 0xFFFFFFFF;
644                    }
645
646                    // Prefer a single MOVN/MOVZ instruction over a logical instruction.
647                    st.multiple_op_count = encode_mov_sequence64(
648                        &mut st.multiple_op_data,
649                        imm_value,
650                        op0.id() & 31,
651                        x,
652                    );
653                    if st.multiple_op_count == 1 && !op0.as_::<Gp>().is_sp() {
654                        st.opcode.reset(st.multiple_op_data[0]);
655                        emit_op!();
656                    }
657
658                    if !op0.as_::<Gp>().is_zr() {
659                        if let Some(logical_imm) =
660                            encode_logical_imm(imm_value, if x != 0 { 64 } else { 32 })
661                        {
662                            st.opcode.reset(0b00110010000000000000001111100000);
663                            st.opcode.add_imm(x, 31);
664                            st.opcode.add_logical_imm(&logical_imm);
665                            st.opcode.add_reg(op0.id(), 0);
666                            emit_op!();
667                        }
668                    }
669
670                    check_features!();
671                    self.emit_handler(Handler::Multi, &mut st);
672                    return;
673                }
674            }
675
676            Encoding::BaseMovKNZ => {
677                let op_data = &BASE_MOV_KNZ[encoding_index];
678
679                let x = (op0.as_::<Reg>().typ() as u32).wrapping_sub(RegType::Gp32 as u32);
680                if x > 1 {
681                    self.last_error = Some(AsmError::InvalidInstruction);
682                    return;
683                }
684
685                if !check_gp_id(op0, 63) {
686                    self.last_error = Some(AsmError::InvalidOperand);
687                    return;
688                }
689
690                st.opcode.reset(op_data.opcode);
691                st.opcode.add_imm(x, 31);
692
693                if isign4 == enc_ops!(Reg, Imm) {
694                    let imm16 = op1.as_::<Imm>().value() as u64;
695                    if imm16 > 0xFFFF {
696                        self.last_error = Some(AsmError::TooLarge);
697                        return;
698                    }
699
700                    st.opcode.add_imm(imm16 as u32, 5);
701                    st.opcode.add_reg(op0.id(), 0);
702                    emit_op!();
703                }
704
705                if isign4 == enc_ops!(Reg, Imm, Imm) {
706                    let imm16 = op1.as_::<Imm>().value() as u64;
707                    let shift_type = op2.as_::<Imm>().predicate();
708                    let shift_value = op2.as_::<Imm>().value() as u64;
709
710                    if imm16 > 0xFFFF || shift_value > 48 || shift_type != ShiftOp::LSL as u32 {
711                        self.last_error = Some(AsmError::TooLarge);
712                        return;
713                    }
714
715                    let hw = (shift_value as u32) >> 4;
716
717                    if hw << 4 != shift_value as u32 {
718                        self.last_error = Some(AsmError::InvalidOperand);
719                        return;
720                    }
721
722                    st.opcode.add_imm(hw, 21);
723                    st.opcode.add_imm(imm16 as u32, 5);
724                    st.opcode.add_reg(op0.id(), 0);
725
726                    if x == 0 && hw > 1 {
727                        self.last_error = Some(AsmError::InvalidOperand);
728                        return;
729                    }
730
731                    emit_op!();
732                }
733            }
734
735            Encoding::BaseAdr => {
736                let op_data = &BASE_ADR[encoding_index];
737                if isign4 == enc_ops!(Reg, Label)
738                    || isign4 == enc_ops!(Reg, Sym)
739                    || isign4 == enc_ops!(Reg, Imm)
740                {
741                    if !op0.as_::<Reg>().is_gp() {
742                        self.last_error = Some(AsmError::InvalidOperand);
743                        return;
744                    }
745
746                    if !check_gp_id(op0, 63) {
747                        self.last_error = Some(AsmError::InvalidOperand);
748                        return;
749                    }
750
751                    st.opcode.reset(op_data.opcode());
752                    st.opcode.add_reg(op0.id(), 0);
753                    st.offset_format.reset_to_imm_type(
754                        OffsetType::try_from(op_data.offset_type).expect("Invalid offset type"),
755                        4,
756                        5,
757                        21,
758                        0,
759                    );
760
761                    if inst_id == InstId::Adrp as u32 {
762                        st.offset_format.imm_discard_lsb = 12;
763                    }
764                    st.rm_rel = *op1;
765                    emit_rel!();
766                }
767            }
768
769            Encoding::BaseAddSub => {
770                let op_data = &BASE_ADD_SUB[encoding_index];
771
772                let mut x = 0;
773                if !check_gp_typex2(op0, op1, 3, &mut x) {
774                    self.last_error = Some(AsmError::InvalidOperand);
775                    return;
776                }
777
778                if isign4 == enc_ops!(Reg, Reg, Imm) || isign4 == enc_ops!(Reg, Reg, Imm, Imm) {
779                    st.opcode.reset((op_data.immediate_op as u32) << 24);
780
781                    // ADD | SUB (immediate) - ZR is not allowed.
782                    // ADDS|SUBS (immediate) - ZR allowed in Rd, SP allowed in Rn.
783                    let a_hi_id = if st.opcode.get() & 1 << 29 != 0 {
784                        63
785                    } else {
786                        31
787                    };
788                    let b_hi_id = 31;
789                    if !check_gp_id(op0, a_hi_id) || !check_gp_id(op1, b_hi_id) {
790                        self.last_error = Some(AsmError::InvalidOperand);
791                        return;
792                    }
793
794                    let mut imm = op2.as_::<Imm>().value() as u64;
795                    let mut shift = 0;
796
797                    if isign4 == enc_ops!(Reg, Reg, Imm, Imm) {
798                        if op3.as_::<Imm>().predicate() != ShiftOp::LSL as u32 {
799                            self.last_error = Some(AsmError::InvalidOperand);
800                            return;
801                        }
802
803                        if op3.as_::<Imm>().value() != 0 && op3.as_::<Imm>().value() != 12 {
804                            self.last_error = Some(AsmError::InvalidOperand);
805                            return;
806                        }
807
808                        shift = (op3.as_::<Imm>().value() != 0) as u32;
809                    }
810
811                    if imm > 0xfff {
812                        if shift != 0 || (imm & !(0xfff << 12)) != 0 {
813                            self.last_error = Some(AsmError::TooLarge);
814                            return;
815                        }
816
817                        shift = 1;
818                        imm >>= 12;
819                    }
820
821                    st.opcode.add_imm(x, 31);
822                    st.opcode.add_imm(shift, 12);
823                    st.opcode.add_imm(imm as u32, 10);
824                    st.opcode.add_reg(op1.id(), 5);
825                    st.opcode.add_reg(op0.id(), 0);
826                    emit_op!();
827                }
828
829                if isign4 == enc_ops!(Reg, Reg, Reg) || isign4 == enc_ops!(Reg, Reg, Reg, Imm) {
830                    let op_size = if x != 0 { 64 } else { 32 };
831                    let mut shift = 0;
832                    let mut shift_type = ShiftOp::LSL as u32;
833
834                    if isign4 == enc_ops!(Reg, Reg, Reg, Imm) {
835                        shift_type = op3.as_::<Imm>().predicate();
836                        shift = op3.as_::<Imm>().value() as u32;
837                    }
838
839                    if !check_gp_id(op2, 63) {
840                        self.last_error = Some(AsmError::InvalidOperand);
841                        return;
842                    }
843
844                    if shift_type <= ShiftOp::ASR as u32 {
845                        let has_sp = op0.as_::<Gp>().is_sp() || op1.as_::<Gp>().is_sp();
846
847                        if !has_sp {
848                            if !check_signature!(op1, op2) {
849                                self.last_error = Some(AsmError::InvalidInstruction);
850                                return;
851                            }
852
853                            if !check_gp_id3(op0, op1, op2, 63) {
854                                self.last_error = Some(AsmError::InvalidOperand);
855                                return;
856                            }
857
858                            if shift >= op_size {
859                                self.last_error = Some(AsmError::InvalidOperand);
860                                return;
861                            }
862
863                            st.opcode.reset((op_data.shifted_op as u32) << 21);
864                            st.opcode.add_imm(x, 31);
865                            st.opcode.add_imm(shift_type, 22);
866                            st.opcode.add_reg(op2.id(), 16);
867                            st.opcode.add_imm(shift, 10);
868                            st.opcode.add_reg(op1.id(), 5);
869                            st.opcode.add_reg(op0.id(), 0);
870                            emit_op!();
871                        }
872
873                        if shift_type != ShiftOp::LSL as u32 {
874                            self.last_error = Some(AsmError::InvalidOperand);
875                            return;
876                        }
877
878                        shift_type = if x != 0 {
879                            ShiftOp::UXTX as u32
880                        } else {
881                            ShiftOp::UXTW as u32
882                        };
883                    }
884
885                    st.opcode.reset((op_data.extended_op as u32) << 21);
886                    shift_type = shift_type.wrapping_sub(ShiftOp::UXTB as u32);
887
888                    if shift_type > 7 || shift > 4 {
889                        self.last_error = Some(AsmError::InvalidOperand);
890                        return;
891                    }
892
893                    if (st.opcode.get() & (1 << 29)) == 0 {
894                        if !check_gp_id2(op0, op1, 31) {
895                            self.last_error = Some(AsmError::InvalidOperand);
896                            return;
897                        }
898                    } else {
899                        if !check_gp_id(op0, 63) || !check_gp_id(op1, 31) {
900                            self.last_error = Some(AsmError::InvalidOperand);
901                            return;
902                        }
903                    }
904
905                    st.opcode.add_imm(x, 31);
906                    st.opcode.add_reg(op2.id(), 16);
907                    st.opcode.add_imm(shift_type, 13);
908                    st.opcode.add_imm(shift, 10);
909                    st.opcode.add_reg(op1.id(), 5);
910                    st.opcode.add_reg(op0.id(), 0);
911                    emit_op!();
912                }
913            }
914
915            Encoding::BaseLogical => {
916                let op_data = &BASE_LOGICAL[encoding_index];
917
918                let mut x = 0;
919                if !check_gp_typex2(op0, op1, 3, &mut x) {
920                    self.last_error = Some(AsmError::InvalidOperand);
921                    return;
922                }
923
924                if !check_signature!(op0, op1) {
925                    self.last_error = Some(AsmError::InvalidInstruction);
926                    return;
927                }
928
929                let op_size = if x != 0 { 64 } else { 32 };
930
931                if isign4 == enc_ops!(Reg, Reg, Imm) && op_data.immediate_op != 0 {
932                    st.opcode.reset((op_data.immediate_op as u32) << 23);
933
934                    let imm_mask = lsb_mask::<u64>(op_size);
935                    let mut imm_value = op2.as_::<Imm>().value() as u64;
936
937                    if op_data.negate_imm != 0 {
938                        imm_value ^= imm_mask;
939                    }
940
941                    let Some(logical_imm) = encode_logical_imm(imm_value, op_size) else {
942                        self.last_error = Some(AsmError::InvalidOperand);
943                        return;
944                    };
945
946                    let op_ands = 0x3 << 29;
947                    let is_ands = (st.opcode.get() & op_ands) == op_ands;
948
949                    if !check_gp_id(op0, if is_ands { 63 } else { 31 }) || !check_gp_id(op1, 63) {
950                        self.last_error = Some(AsmError::InvalidOperand);
951                        return;
952                    }
953
954                    st.opcode.add_imm(x, 31);
955                    st.opcode.add_logical_imm(&logical_imm);
956                    st.opcode.add_reg(op1.id(), 5);
957                    st.opcode.add_reg(op0.id(), 0);
958                    emit_op!();
959                }
960
961                if !check_signature!(op1, op2) {
962                    self.last_error = Some(AsmError::InvalidInstruction);
963                    return;
964                }
965
966                if isign4 == enc_ops!(Reg, Reg, Reg) {
967                    if !check_gp_id3(op0, op1, op2, 63) {
968                        self.last_error = Some(AsmError::InvalidOperand);
969                        return;
970                    }
971
972                    st.opcode.reset((op_data.shifted_op as u32) << 21);
973                    st.opcode.add_imm(x, 31);
974                    st.opcode.add_reg(op2.id(), 16);
975                    st.opcode.add_reg(op1.id(), 5);
976                    st.opcode.add_reg(op0.id(), 0);
977                    emit_op!();
978                }
979
980                if isign4 == enc_ops!(Reg, Reg, Reg, Imm) {
981                    if !check_gp_id3(op0, op1, op2, 63) {
982                        self.last_error = Some(AsmError::InvalidOperand);
983                        return;
984                    }
985
986                    let shift_type = op3.as_::<Imm>().predicate();
987                    let op_shift = op3.as_::<Imm>().value() as u32;
988
989                    if shift_type > 0x3 || op_shift >= op_size {
990                        self.last_error = Some(AsmError::InvalidOperand);
991                        return;
992                    }
993
994                    st.opcode.reset((op_data.shifted_op as u32) << 21);
995                    st.opcode.add_imm(x, 31);
996                    st.opcode.add_imm(shift_type, 22);
997                    st.opcode.add_reg(op2.id(), 16);
998                    st.opcode.add_imm(op_shift, 10);
999                    st.opcode.add_reg(op1.id(), 5);
1000                    st.opcode.add_reg(op0.id(), 0);
1001                    emit_op!();
1002                }
1003            }
1004
1005            Encoding::BaseCmpCmn => {
1006                let op_data = &BASE_CMP_CMN[encoding_index];
1007
1008                let mut x = 0;
1009                if !check_gp_typex(op0, 3, &mut x) {
1010                    self.last_error = Some(AsmError::InvalidOperand);
1011                    return;
1012                }
1013
1014                if isign4 == enc_ops!(Reg, Imm) {
1015                    if !check_gp_id(op0, 31) {
1016                        self.last_error = Some(AsmError::InvalidOperand);
1017                        return;
1018                    }
1019
1020                    let imm12 = op1.as_::<Imm>();
1021                    let mut imm_shift = 0;
1022                    let mut imm_value = imm12.value() as u64;
1023
1024                    if imm_value > 0xfff {
1025                        if (imm_value & !(0xfff << 12)) != 0 {
1026                            self.last_error = Some(AsmError::TooLarge);
1027                            return;
1028                        }
1029                        imm_shift = 1;
1030                        imm_value >>= 12;
1031                    }
1032
1033                    st.opcode.reset((op_data.immediate_op as u32) << 24);
1034                    st.opcode.add_imm(x, 31);
1035                    st.opcode.add_imm(imm_shift, 22);
1036                    st.opcode.add_imm(imm_value as u32, 10);
1037                    st.opcode.add_reg(op0.id(), 5);
1038                    st.opcode.add_reg(63, 0);
1039                    emit_op!();
1040                }
1041
1042                if isign4 == enc_ops!(Reg, Reg) || isign4 == enc_ops!(Reg, Reg, Imm) {
1043                    let op_size = if x != 0 { 64 } else { 32 };
1044                    let mut shift_type = 0;
1045                    let mut shift_value = 0;
1046
1047                    if isign4 == enc_ops!(Reg, Reg, Imm) {
1048                        shift_type = op2.as_::<Imm>().predicate();
1049                        shift_value = op2.as_::<Imm>().value() as u32;
1050                    }
1051
1052                    let has_sp = op0.as_::<Gp>().is_sp() || op1.as_::<Gp>().is_sp();
1053
1054                    if shift_type <= ShiftOp::ASR as u32 {
1055                        if !has_sp {
1056                            if !check_signature!(op0, op1) {
1057                                self.last_error = Some(AsmError::InvalidInstruction);
1058                                return;
1059                            }
1060
1061                            if shift_value >= op_size {
1062                                self.last_error = Some(AsmError::InvalidOperand);
1063                                return;
1064                            }
1065
1066                            st.opcode.reset((op_data.shifted_op as u32) << 21);
1067                            st.opcode.add_imm(x, 31);
1068                            st.opcode.add_imm(shift_type, 22);
1069                            st.opcode.add_reg(op1.id(), 5);
1070                            st.opcode.add_imm(shift_value, 10);
1071                            st.opcode.add_reg(op0.id(), 5);
1072                            st.opcode.add_reg(63, 0);
1073                            emit_op!();
1074                        }
1075
1076                        if shift_type != ShiftOp::LSL as u32 {
1077                            self.last_error = Some(AsmError::InvalidOperand);
1078                            return;
1079                        }
1080
1081                        shift_type = if x != 0 {
1082                            ShiftOp::UXTX as u32
1083                        } else {
1084                            ShiftOp::UXTW as u32
1085                        }
1086                    }
1087
1088                    shift_type = shift_type.wrapping_sub(ShiftOp::UXTB as u32);
1089
1090                    if shift_type > 7 || shift_value > 4 {
1091                        self.last_error = Some(AsmError::InvalidOperand);
1092                        return;
1093                    }
1094
1095                    st.opcode.reset((op_data.extended_op as u32) << 21);
1096                    st.opcode.add_imm(x, 31);
1097                    st.opcode.add_reg(op1.id(), 16);
1098                    st.opcode.add_imm(shift_type, 13);
1099                    st.opcode.add_imm(shift_value, 10);
1100                    st.opcode.add_reg(op0.id(), 5);
1101                    st.opcode.add_reg(63, 0);
1102                    emit_op!();
1103                }
1104            }
1105
1106            Encoding::BaseMvnNeg => {
1107                let op_data = &BASE_MVN_NEG[encoding_index];
1108
1109                let mut x = 0;
1110                if !check_gp_typex2(op0, op1, 3, &mut x) {
1111                    self.last_error = Some(AsmError::InvalidOperand);
1112                    return;
1113                }
1114
1115                st.opcode.reset(op_data.opcode);
1116                st.opcode.add_imm(x, 31);
1117                st.opcode.add_reg(op1.id(), 16);
1118                st.opcode.add_reg(op0.id(), 0);
1119
1120                if isign4 == enc_ops!(Reg, Reg) {
1121                    if !check_gp_id2(op0, op1, 63) {
1122                        self.last_error = Some(AsmError::InvalidOperand);
1123                        return;
1124                    }
1125
1126                    emit_op!();
1127                }
1128
1129                if isign4 == enc_ops!(Reg, Reg, Imm) {
1130                    if !check_gp_id2(op0, op1, 63) {
1131                        self.last_error = Some(AsmError::InvalidOperand);
1132                        return;
1133                    }
1134
1135                    let op_size = if x != 0 { 64 } else { 32 };
1136                    let shift_type = op2.as_::<Imm>().predicate();
1137                    let shift_value = op2.as_::<Imm>().value() as u32;
1138
1139                    if shift_type > ShiftOp::ROR as u32 || shift_value >= op_size {
1140                        self.last_error = Some(AsmError::InvalidOperand);
1141                        return;
1142                    }
1143
1144                    st.opcode.add_imm(shift_type, 22);
1145                    st.opcode.add_imm(shift_value, 10);
1146                    emit_op!();
1147                }
1148            }
1149
1150            Encoding::BaseTst => {
1151                let op_data = &BASE_TST[encoding_index];
1152
1153                let mut x = 0;
1154                if !check_gp_typex(op0, 3, &mut x) {
1155                    self.last_error = Some(AsmError::InvalidOperand);
1156                    return;
1157                }
1158
1159                if isign4 == enc_ops!(Reg, Imm) && op_data.immediate_op != 0 {
1160                    if !check_gp_id(op0, 63) {
1161                        self.last_error = Some(AsmError::InvalidOperand);
1162                        return;
1163                    }
1164                    let op_size = if x != 0 { 64 } else { 32 };
1165                    let imm_mask = lsb_mask::<u64>(op_size);
1166                    let imm_value = op1.as_::<Imm>().value() as u64;
1167
1168                    let Some(logical_imm) = encode_logical_imm(imm_value & imm_mask, op_size)
1169                    else {
1170                        self.last_error = Some(AsmError::InvalidOperand);
1171                        return;
1172                    };
1173
1174                    st.opcode.reset((op_data.immediate_op as u32) << 22);
1175                    st.opcode.add_logical_imm(&logical_imm);
1176                    st.opcode.add_imm(x, 31);
1177                    st.opcode.add_reg(op0.id(), 5);
1178                    st.opcode.add_reg(63, 0);
1179                    emit_op!();
1180                }
1181
1182                st.opcode.reset((op_data.shifted_op as u32) << 21);
1183                st.opcode.add_imm(x, 31);
1184                st.opcode.add_reg(op1.id(), 16);
1185                st.opcode.add_reg(op0.id(), 5);
1186                st.opcode.add_reg(63, 0);
1187
1188                if isign4 == enc_ops!(Reg, Reg) {
1189                    if !check_gp_id2(op0, op1, 63) {
1190                        self.last_error = Some(AsmError::InvalidOperand);
1191                        return;
1192                    }
1193
1194                    emit_op!();
1195                }
1196
1197                if isign4 == enc_ops!(Reg, Reg, Imm) {
1198                    if !check_gp_id2(op0, op1, 63) {
1199                        self.last_error = Some(AsmError::InvalidOperand);
1200                        return;
1201                    }
1202
1203                    let shift_type = op2.as_::<Imm>().predicate();
1204                    let shift_value = op2.as_::<Imm>().value() as u32;
1205
1206                    if shift_type > 0x3 || shift_value >= (if x != 0 { 64 } else { 32 }) {
1207                        self.last_error = Some(AsmError::InvalidOperand);
1208                        return;
1209                    }
1210
1211                    st.opcode.add_imm(shift_type, 22);
1212                    st.opcode.add_imm(shift_value, 10);
1213                    emit_op!();
1214                }
1215            }
1216
1217            Encoding::BaseBfc => {
1218                let op_data = &BASE_BFC[encoding_index];
1219                if isign4 == enc_ops!(Reg, Imm, Imm) {
1220                    let mut x = 0;
1221                    if !check_gp_typex(op0, 3, &mut x) {
1222                        self.last_error = Some(AsmError::InvalidOperand);
1223                        return;
1224                    }
1225
1226                    let lsb = op1.as_::<Imm>().value() as u64;
1227                    let width = op2.as_::<Imm>().value() as u64;
1228                    let op_size = if x != 0 { 64 } else { 32 };
1229
1230                    if lsb >= op_size || width == 0 || width > op_size {
1231                        self.last_error = Some(AsmError::InvalidOperand);
1232                        return;
1233                    }
1234
1235                    let lsb32 = 0u32.wrapping_sub(lsb as u32) & (op_size as u32 - 1);
1236                    let width32 = width as u32 - 1;
1237
1238                    st.opcode.reset(op_data.opcode);
1239                    st.opcode.add_imm(x, 31);
1240                    st.opcode.add_imm(x, 22);
1241                    st.opcode.add_imm(lsb32, 16);
1242                    st.opcode.add_imm(width32, 10);
1243                    st.opcode.add_reg(op0.id(), 0);
1244                    emit_op!();
1245                }
1246            }
1247
1248            Encoding::BaseBfi => {
1249                let op_data = &BASE_BFI[encoding_index];
1250                if isign4 == enc_ops!(Reg, Reg, Imm, Imm) {
1251                    let mut x = 0;
1252                    if !check_gp_typex(op0, 3, &mut x) {
1253                        self.last_error = Some(AsmError::InvalidOperand);
1254                        return;
1255                    }
1256
1257                    if !check_signature!(op0, op1) {
1258                        self.last_error = Some(AsmError::InvalidInstruction);
1259                        return;
1260                    }
1261
1262                    if !check_gp_id2(op0, op1, 63) {
1263                        self.last_error = Some(AsmError::InvalidOperand);
1264                        return;
1265                    }
1266
1267                    let lsb = op2.as_::<Imm>().value() as u64;
1268                    let width = op3.as_::<Imm>().value() as u64;
1269                    let op_size = if x != 0 { 64 } else { 32 };
1270
1271                    if lsb >= op_size as u64 || width == 0 || width > op_size as u64 {
1272                        self.last_error = Some(AsmError::InvalidOperand);
1273                        return;
1274                    }
1275
1276                    let imm_l = 0u32.wrapping_sub(lsb as u32) & (op_size as u32 - 1);
1277                    let imm_w = width as u32 - 1;
1278
1279                    st.opcode.reset(op_data.opcode);
1280                    st.opcode.add_imm(x, 31);
1281                    st.opcode.add_imm(x, 22);
1282                    st.opcode.add_imm(imm_l, 16);
1283                    st.opcode.add_imm(imm_w, 10);
1284                    st.opcode.add_reg(op1.id(), 5);
1285                    st.opcode.add_reg(op0.id(), 0);
1286                    emit_op!();
1287                }
1288            }
1289
1290            Encoding::BaseBfm => {
1291                let op_data = &BASE_BFM[encoding_index];
1292                if isign4 == enc_ops!(Reg, Reg, Imm, Imm) {
1293                    let mut x = 0;
1294                    if !check_gp_typex(op0, 3, &mut x) {
1295                        self.last_error = Some(AsmError::InvalidInstruction);
1296                        return;
1297                    }
1298
1299                    if !check_signature!(op0, op1) {
1300                        self.last_error = Some(AsmError::InvalidInstruction);
1301                        return;
1302                    }
1303
1304                    if !check_gp_id2(op0, op1, 63) {
1305                        self.last_error = Some(AsmError::InvalidOperand);
1306                        return;
1307                    }
1308
1309                    let imm_r = op2.as_::<Imm>().value() as u64;
1310                    let imm_s = op3.as_::<Imm>().value() as u64;
1311                    let op_size = if x != 0 { 64 } else { 32 };
1312
1313                    if (imm_r | imm_s) >= op_size as u64 {
1314                        self.last_error = Some(AsmError::InvalidOperand);
1315                        return;
1316                    }
1317
1318                    st.opcode.reset(op_data.opcode);
1319                    st.opcode.add_imm(x, 31);
1320                    st.opcode.add_imm(x, 22);
1321                    st.opcode.add_imm(imm_r as u32, 16);
1322                    st.opcode.add_imm(imm_s as u32, 10);
1323                    st.opcode.add_reg(op1.id(), 5);
1324                    st.opcode.add_reg(op0.id(), 0);
1325                    emit_op!();
1326                }
1327            }
1328
1329            Encoding::BaseBfx => {
1330                let op_data = &BASE_BFX[encoding_index];
1331                if isign4 == enc_ops!(Reg, Reg, Imm, Imm) {
1332                    let mut x = 0;
1333                    if !check_gp_typex(op0, 3, &mut x) {
1334                        self.last_error = Some(AsmError::InvalidInstruction);
1335                        return;
1336                    }
1337
1338                    if !check_signature!(op0, op1) {
1339                        self.last_error = Some(AsmError::InvalidInstruction);
1340                        return;
1341                    }
1342
1343                    if !check_gp_id2(op0, op1, 63) {
1344                        self.last_error = Some(AsmError::InvalidOperand);
1345                        return;
1346                    }
1347
1348                    let lsb = op2.as_::<Imm>().value() as u64;
1349                    let width = op3.as_::<Imm>().value() as u64;
1350                    let op_size = if x != 0 { 64 } else { 32 };
1351
1352                    if lsb >= op_size as u64 || width == 0 || width > op_size as u64 {
1353                        self.last_error = Some(AsmError::InvalidOperand);
1354                        return;
1355                    }
1356
1357                    let lsb32 = lsb as u32;
1358                    let width32 = lsb32 + width as u32 - 1;
1359
1360                    if width32 >= op_size as u32 {
1361                        self.last_error = Some(AsmError::InvalidOperand);
1362                        return;
1363                    }
1364
1365                    st.opcode.reset(op_data.opcode);
1366                    st.opcode.add_imm(x, 31);
1367                    st.opcode.add_imm(x, 22);
1368                    st.opcode.add_imm(lsb32, 16);
1369                    st.opcode.add_imm(width32, 10);
1370                    st.opcode.add_reg(op1.id(), 5);
1371                    st.opcode.add_reg(op0.id(), 0);
1372                    emit_op!();
1373                }
1374            }
1375
1376            Encoding::BaseExtend => {
1377                let op_data = &BASE_EXTEND[encoding_index];
1378
1379                if isign4 == enc_ops!(Reg, Reg) {
1380                    let mut x = 0;
1381                    if !check_gp_typex(op0, op_data.reg_type, &mut x) {
1382                        self.last_error = Some(AsmError::InvalidOperand);
1383                        return;
1384                    }
1385
1386                    if !op1.as_::<Reg>().is_gp32() {
1387                        self.last_error = Some(AsmError::InvalidOperand);
1388                        return;
1389                    }
1390
1391                    if !check_gp_id2(op0, op1, 63) {
1392                        self.last_error = Some(AsmError::InvalidOperand);
1393                        return;
1394                    }
1395
1396                    st.opcode.reset(op_data.opcode());
1397                    st.opcode.add_imm(x, 31);
1398                    st.opcode.add_imm(x, 22);
1399                    st.opcode.add_reg(op1.id(), 5);
1400                    st.opcode.add_reg(op0.id(), 0);
1401                    emit_op!();
1402                }
1403            }
1404
1405            Encoding::BaseExtract => {
1406                let op_data = &BASE_EXTRACT[encoding_index];
1407
1408                if isign4 == enc_ops!(Reg, Reg, Reg, Imm) {
1409                    let mut x = 0;
1410                    if !check_gp_typex(op0, 3, &mut x) {
1411                        self.last_error = Some(AsmError::InvalidInstruction);
1412                        return;
1413                    }
1414
1415                    if !check_signature!(op0, op1, op2) {
1416                        self.last_error = Some(AsmError::InvalidInstruction);
1417                        return;
1418                    }
1419
1420                    if !check_gp_id3(op0, op1, op2, 63) {
1421                        self.last_error = Some(AsmError::InvalidOperand);
1422                        return;
1423                    }
1424
1425                    let lsb = op3.as_::<Imm>().value() as u64;
1426                    let op_size = if x != 0 { 64 } else { 32 };
1427
1428                    if lsb >= op_size as u64 {
1429                        self.last_error = Some(AsmError::InvalidOperand);
1430                        return;
1431                    }
1432
1433                    st.opcode.reset(op_data.opcode);
1434                    st.opcode.add_imm(x, 31);
1435                    st.opcode.add_imm(x, 22);
1436                    st.opcode.add_reg(op2.id(), 16);
1437                    st.opcode.add_imm(lsb as u32, 10);
1438                    st.opcode.add_reg(op1.id(), 5);
1439                    st.opcode.add_reg(op0.id(), 0);
1440                    emit_op!();
1441                }
1442            }
1443
1444            Encoding::BaseRev => {
1445                if isign4 == enc_ops!(Reg, Reg) {
1446                    let mut x = 0;
1447                    if !check_gp_typex(op0, 3, &mut x) {
1448                        self.last_error = Some(AsmError::InvalidInstruction);
1449                        return;
1450                    }
1451
1452                    if !check_signature!(op0, op1) {
1453                        self.last_error = Some(AsmError::InvalidInstruction);
1454                        return;
1455                    }
1456
1457                    if !check_gp_id2(op0, op1, 63) {
1458                        self.last_error = Some(AsmError::InvalidOperand);
1459                        return;
1460                    }
1461
1462                    st.opcode.reset(0b01011010110000000000100000000000);
1463                    st.opcode.add_imm(x, 31);
1464                    st.opcode.add_imm(x, 10);
1465                    st.opcode.add_reg(op1.id(), 5);
1466                    st.opcode.add_reg(op0.id(), 0);
1467                    emit_op!();
1468                }
1469            }
1470
1471            Encoding::BaseShift => {
1472                let op_data = &BASE_SHIFT[encoding_index];
1473
1474                let mut x = 0;
1475                if !check_gp_typex(op0, 3, &mut x) {
1476                    self.last_error = Some(AsmError::InvalidInstruction);
1477                    return;
1478                }
1479
1480                if isign4 == enc_ops!(Reg, Reg, Reg) {
1481                    if !check_signature!(op0, op1, op2) {
1482                        self.last_error = Some(AsmError::InvalidInstruction);
1483                        return;
1484                    }
1485
1486                    if !check_gp_id3(op0, op1, op2, 63) {
1487                        self.last_error = Some(AsmError::InvalidOperand);
1488                        return;
1489                    }
1490
1491                    st.opcode.reset(op_data.register_op);
1492                    st.opcode.add_imm(x, 31);
1493                    st.opcode.add_reg(op2.id(), 16);
1494                    st.opcode.add_reg(op1.id(), 5);
1495                    st.opcode.add_reg(op0.id(), 0);
1496                    emit_op!();
1497                }
1498
1499                if isign4 == enc_ops!(Reg, Reg, Imm) && op_data.immediate_op != 0 {
1500                    if !check_signature!(op0, op1) {
1501                        self.last_error = Some(AsmError::InvalidInstruction);
1502                        return;
1503                    }
1504
1505                    if !check_gp_id2(op0, op1, 63) {
1506                        self.last_error = Some(AsmError::InvalidOperand);
1507                        return;
1508                    }
1509
1510                    let imm_r = op2.as_::<Imm>().value() as u64;
1511                    let op_size = if x != 0 { 64 } else { 32 };
1512
1513                    if imm_r >= op_size as u64 {
1514                        self.last_error = Some(AsmError::InvalidOperand);
1515                        return;
1516                    }
1517
1518                    st.opcode.reset(op_data.immediate_op);
1519                    st.opcode.add_imm(x, 31);
1520                    st.opcode.add_imm(x, 22);
1521                    st.opcode.add_reg(op1.id(), 5);
1522                    st.opcode.add_reg(op0.id(), 0);
1523
1524                    if st.opcode.get() & (1 << 10) != 0 {
1525                        st.opcode.add_imm(x, 15);
1526                        st.opcode.add_imm(imm_r as u32, 16);
1527                        emit_op!();
1528                    }
1529
1530                    if op_data.ror == 0 {
1531                        let ubfm_imm_r = (0u32).wrapping_sub(imm_r as u32) & (op_size as u32 - 1);
1532                        let ubfm_imm_s = op_size as u32 - 1 - imm_r as u32;
1533
1534                        st.opcode.add_imm(ubfm_imm_r, 16);
1535                        st.opcode.add_imm(ubfm_imm_s, 10);
1536                        emit_op!();
1537                    } else {
1538                        st.opcode.add_imm(imm_r as u32, 10);
1539                        st.opcode.add_reg(op1.id(), 16);
1540                        emit_op!();
1541                    }
1542                }
1543            }
1544
1545            Encoding::BaseCCmp => {
1546                let op_data = &BASE_C_CMP[encoding_index];
1547
1548                if isign4 == enc_ops!(Reg, Reg, Imm, Imm) || isign4 == enc_ops!(Reg, Imm, Imm, Imm)
1549                {
1550                    let mut x = 0;
1551                    if !check_gp_typex(op0, 3, &mut x) {
1552                        self.last_error = Some(AsmError::InvalidOperand);
1553                        return;
1554                    }
1555
1556                    if !check_gp_id(op0, 31) {
1557                        self.last_error = Some(AsmError::InvalidOperand);
1558                        return;
1559                    }
1560
1561                    let nzcv = op2.as_::<Imm>().value() as u64;
1562                    let cond = op3.as_::<Imm>().value() as u64;
1563
1564                    if (nzcv | cond) > 0xF {
1565                        self.last_error = Some(AsmError::TooLarge);
1566                        return;
1567                    }
1568
1569                    st.opcode.reset(op_data.opcode);
1570                    st.opcode.add_imm(x, 31);
1571                    st.opcode
1572                        .add_imm(cond_code_to_opcode_field(cond as u32), 12);
1573                    st.opcode.add_imm(nzcv as u32, 0);
1574
1575                    if isign4 == enc_ops!(Reg, Reg, Imm, Imm) {
1576                        if !check_signature!(op0, op1) {
1577                            self.last_error = Some(AsmError::InvalidInstruction);
1578                            return;
1579                        }
1580
1581                        if !check_gp_id(op1, 31) {
1582                            self.last_error = Some(AsmError::InvalidOperand);
1583                            return;
1584                        }
1585
1586                        st.opcode.add_reg(op1.id(), 16);
1587                        st.opcode.add_reg(op0.id(), 5);
1588                        emit_op!();
1589                    } else {
1590                        let imm5 = op1.as_::<Imm>().value() as u64;
1591                        if imm5 > 0x1F {
1592                            self.last_error = Some(AsmError::TooLarge);
1593                            return;
1594                        }
1595
1596                        st.opcode.add_imm(1, 11);
1597                        st.opcode.add_imm(imm5 as u32, 16);
1598                        st.opcode.add_reg(op0.id(), 5);
1599                        emit_op!();
1600                    }
1601                }
1602            }
1603
1604            Encoding::BaseCInc => {
1605                let op_data = &BASE_C_INC[encoding_index];
1606
1607                if isign4 == enc_ops!(Reg, Reg, Imm) {
1608                    let mut x = 0;
1609                    if !check_gp_typex2(op0, op1, 3, &mut x) {
1610                        self.last_error = Some(AsmError::InvalidInstruction);
1611                        return;
1612                    }
1613
1614                    if !check_gp_id2(op0, op1, 31) {
1615                        self.last_error = Some(AsmError::InvalidOperand);
1616                        return;
1617                    }
1618
1619                    let cond = op2.as_::<Imm>().value() as u64;
1620                    if cond.wrapping_sub(2) > 0xE {
1621                        self.last_error = Some(AsmError::TooLarge);
1622                        return;
1623                    }
1624
1625                    st.opcode.reset(op_data.opcode);
1626                    st.opcode.add_imm(x, 31);
1627                    st.opcode.add_reg(op1.id(), 16);
1628                    st.opcode
1629                        .add_imm(cond_code_to_opcode_field((cond as u32) ^ 1), 12);
1630                    st.opcode.add_reg(op1.id(), 5);
1631                    st.opcode.add_reg(op0.id(), 0);
1632                    emit_op!();
1633                }
1634            }
1635
1636            Encoding::BaseCSel => {
1637                let op_data = &BASE_C_SEL[encoding_index];
1638
1639                if isign4 == enc_ops!(Reg, Reg, Reg, Imm) {
1640                    let mut x = 0;
1641                    if !check_gp_typex(op0, 3, &mut x) {
1642                        self.last_error = Some(AsmError::InvalidInstruction);
1643                        return;
1644                    }
1645
1646                    if !check_signature!(op0, op1, op2) {
1647                        self.last_error = Some(AsmError::InvalidInstruction);
1648                        return;
1649                    }
1650
1651                    if !check_gp_id3(op0, op1, op2, 31) {
1652                        self.last_error = Some(AsmError::InvalidOperand);
1653                        return;
1654                    }
1655
1656                    let cond = op3.as_::<Imm>().value() as u64;
1657                    if cond > 0xF {
1658                        self.last_error = Some(AsmError::TooLarge);
1659                        return;
1660                    }
1661
1662                    st.opcode.reset(op_data.opcode);
1663                    st.opcode.add_imm(x, 31);
1664                    st.opcode.add_reg(op2.id(), 16);
1665                    st.opcode
1666                        .add_imm(cond_code_to_opcode_field(cond as u32), 12);
1667                    st.opcode.add_reg(op1.id(), 5);
1668                    st.opcode.add_reg(op0.id(), 0);
1669                    emit_op!();
1670                }
1671            }
1672
1673            Encoding::BaseCSet => {
1674                let op_data = &BASE_C_SET[encoding_index];
1675
1676                if isign4 == enc_ops!(Reg, Imm) {
1677                    let mut x = 0;
1678                    if !check_gp_typex(op0, 3, &mut x) {
1679                        self.last_error = Some(AsmError::InvalidInstruction);
1680                        return;
1681                    }
1682
1683                    if !check_gp_id(op0, 31) {
1684                        self.last_error = Some(AsmError::InvalidOperand);
1685                        return;
1686                    }
1687
1688                    let cond = op1.as_::<Imm>().value() as u64;
1689                    if cond.wrapping_sub(2) >= 0xE {
1690                        self.last_error = Some(AsmError::TooLarge);
1691                        return;
1692                    }
1693
1694                    st.opcode.reset(op_data.opcode);
1695                    st.opcode.add_imm(x, 31);
1696                    st.opcode
1697                        .add_imm(cond_code_to_opcode_field((cond as u32) ^ 1), 12);
1698                    st.opcode.add_reg(op0.id(), 0);
1699                    emit_op!();
1700                }
1701            }
1702
1703            Encoding::BaseMinMax => {
1704                let op_data = &BASE_MIN_MAX[encoding_index];
1705
1706                if isign4 == enc_ops!(Reg, Reg, Reg) {
1707                    let mut x = 0;
1708                    if !check_gp_typex(op0, 3, &mut x) {
1709                        self.last_error = Some(AsmError::InvalidInstruction);
1710                        return;
1711                    }
1712
1713                    if !check_signature!(op0, op1, op2) {
1714                        self.last_error = Some(AsmError::InvalidInstruction);
1715                        return;
1716                    }
1717
1718                    st.opcode.reset(op_data.register_op);
1719                    st.opcode.add_imm(x, 31);
1720                    st.opcode.add_reg(op2.id(), 16);
1721                    st.opcode.add_reg(op1.id(), 5);
1722                    st.opcode.add_reg(op0.id(), 0);
1723                    emit_op!();
1724                }
1725
1726                if isign4 == enc_ops!(Reg, Reg, Imm) {
1727                    let mut x = 0;
1728                    if !check_gp_typex(op0, 3, &mut x) {
1729                        self.last_error = Some(AsmError::InvalidInstruction);
1730                        return;
1731                    }
1732
1733                    if !check_signature!(op0, op1) {
1734                        self.last_error = Some(AsmError::InvalidInstruction);
1735                        return;
1736                    }
1737
1738                    let imm = op2.as_::<Imm>().value() as u64;
1739
1740                    if (op_data.immediate_op & (1u32 << 18)) != 0 {
1741                        if imm > 0xFF {
1742                            self.last_error = Some(AsmError::TooLarge);
1743                            return;
1744                        }
1745                    } else {
1746                        if (imm as i64) < -128 || (imm as i64) > 127 {
1747                            self.last_error = Some(AsmError::TooLarge);
1748                            return;
1749                        }
1750                    }
1751
1752                    st.opcode.reset(op_data.immediate_op);
1753                    st.opcode.add_imm(x, 31);
1754                    st.opcode.add_imm((imm & 0xFF) as u32, 10);
1755                    st.opcode.add_reg(op1.id(), 5);
1756                    st.opcode.add_reg(op0.id(), 0);
1757                    emit_op!();
1758                }
1759            }
1760
1761            Encoding::BaseAtDcIcTlbi => {
1762                let op_data = &BASE_AT_DC_IC_TLBI[encoding_index];
1763
1764                if isign4 == enc_ops!(Imm) || isign4 == enc_ops!(Imm, Reg) {
1765                    if op_data.mandatory_reg != 0 && isign4 != enc_ops!(Imm, Reg) {
1766                        self.last_error = Some(AsmError::InvalidInstruction);
1767                        return;
1768                    }
1769
1770                    if op0.as_::<Imm>().value() as u64 > 0x7FFF {
1771                        self.last_error = Some(AsmError::TooLarge);
1772                        return;
1773                    }
1774
1775                    let imm = op0.as_::<Imm>().value() as u32;
1776                    if (imm & op_data.imm_verify_mask) != op_data.imm_verify_data {
1777                        self.last_error = Some(AsmError::InvalidOperand);
1778                        return;
1779                    }
1780
1781                    let mut rt = 31;
1782                    if op1.is_reg() {
1783                        if !op1.as_::<Reg>().is_gp64() {
1784                            self.last_error = Some(AsmError::InvalidInstruction);
1785                            return;
1786                        }
1787
1788                        if !check_gp_id(op1, 63) {
1789                            self.last_error = Some(AsmError::InvalidOperand);
1790                            return;
1791                        }
1792
1793                        rt = op1.id() & 31;
1794                    }
1795
1796                    st.opcode.reset(0b11010101000010000000000000000000);
1797                    st.opcode.add_imm(imm, 5);
1798                    st.opcode.add_reg(rt, 0);
1799                    emit_op!();
1800                }
1801            }
1802
1803            Encoding::BaseMrs => {
1804                if isign4 == enc_ops!(Reg, Imm) {
1805                    if !op0.as_::<Reg>().is_gp64() {
1806                        self.last_error = Some(AsmError::InvalidInstruction);
1807                        return;
1808                    }
1809
1810                    if !check_gp_id(op0, 63) {
1811                        self.last_error = Some(AsmError::InvalidOperand);
1812                        return;
1813                    }
1814
1815                    if op1.as_::<Imm>().value() as u64 > 0xFFFF {
1816                        self.last_error = Some(AsmError::TooLarge);
1817                        return;
1818                    }
1819
1820                    let imm = op1.as_::<Imm>().value() as u32;
1821                    if (imm & (1 << 15)) == 0 {
1822                        self.last_error = Some(AsmError::InvalidOperand);
1823                        return;
1824                    }
1825
1826                    st.opcode.reset(0b11010101001100000000000000000000);
1827                    st.opcode.add_imm(imm, 5);
1828                    st.opcode.add_reg(op0.id(), 0);
1829                    emit_op!();
1830                }
1831            }
1832
1833            Encoding::BaseMsr => {
1834                if isign4 == enc_ops!(Imm, Reg) {
1835                    if !op1.as_::<Reg>().is_gp64() {
1836                        self.last_error = Some(AsmError::InvalidInstruction);
1837                        return;
1838                    }
1839
1840                    if op0.as_::<Imm>().value() as u64 > 0xFFFF {
1841                        self.last_error = Some(AsmError::TooLarge);
1842                        return;
1843                    }
1844
1845                    let imm = op0.as_::<Imm>().value() as u32;
1846                    if (imm & (1 << 15)) == 0 {
1847                        self.last_error = Some(AsmError::InvalidOperand);
1848                        return;
1849                    }
1850
1851                    if !check_gp_id(op1, 63) {
1852                        self.last_error = Some(AsmError::InvalidOperand);
1853                        return;
1854                    }
1855
1856                    st.opcode.reset(0b11010101000100000000000000000000);
1857                    st.opcode.add_imm(imm, 5);
1858                    st.opcode.add_reg(op1.id(), 0);
1859                    emit_op!();
1860                }
1861
1862                if isign4 == enc_ops!(Imm, Imm) {
1863                    if op0.as_::<Imm>().value() as u64 > 0x1F {
1864                        self.last_error = Some(AsmError::TooLarge);
1865                        return;
1866                    }
1867
1868                    if op1.as_::<Imm>().value() as u64 > 0xF {
1869                        self.last_error = Some(AsmError::TooLarge);
1870                        return;
1871                    }
1872
1873                    let op = op0.as_::<Imm>().value() as u32;
1874                    let crm = op1.as_::<Imm>().value() as u32;
1875
1876                    let op1_val = op >> 3;
1877                    let op2_val = op & 0x7;
1878
1879                    st.opcode.reset(0b11010101000000000100000000011111);
1880                    st.opcode.add_imm(op1_val, 16);
1881                    st.opcode.add_imm(crm, 8);
1882                    st.opcode.add_imm(op2_val, 5);
1883                    emit_op!();
1884                }
1885            }
1886
1887            Encoding::BaseSys => {
1888                if isign4 == enc_ops!(Imm, Imm, Imm, Imm) {
1889                    if op0.as_::<Imm>().value() as u64 > 0x7
1890                        || op1.as_::<Imm>().value() as u64 > 0xF
1891                        || op2.as_::<Imm>().value() as u64 > 0xF
1892                        || op3.as_::<Imm>().value() as u64 > 0x7
1893                    {
1894                        self.last_error = Some(AsmError::TooLarge);
1895                        return;
1896                    }
1897
1898                    let op1_val = op0.as_::<Imm>().value() as u32;
1899                    let crn = op1.as_::<Imm>().value() as u32;
1900                    let crm = op2.as_::<Imm>().value() as u32;
1901                    let op2_val = op3.as_::<Imm>().value() as u32;
1902                    let mut rt = 31;
1903
1904                    let op4 = *ops.get(4).unwrap_or(&NOREG);
1905                    if op4.is_reg() {
1906                        if !op4.as_::<Reg>().is_gp64() {
1907                            self.last_error = Some(AsmError::InvalidInstruction);
1908                            return;
1909                        }
1910
1911                        if !check_gp_id(op4, 63) {
1912                            self.last_error = Some(AsmError::InvalidOperand);
1913                            return;
1914                        }
1915
1916                        rt = op4.id() & 31;
1917                    } else if !op4.is_none() {
1918                        self.last_error = Some(AsmError::InvalidInstruction);
1919                        return;
1920                    }
1921
1922                    st.opcode.reset(0b11010101000010000000000000000000);
1923                    st.opcode.add_imm(op1_val, 16);
1924                    st.opcode.add_imm(crn, 12);
1925                    st.opcode.add_imm(crm, 8);
1926                    st.opcode.add_imm(op2_val, 5);
1927                    st.opcode.add_reg(rt, 0);
1928                    emit_op!();
1929                }
1930            }
1931
1932            Encoding::BaseBranchReg => {
1933                let op_data = &BASE_BRANCH_REG[encoding_index];
1934                if isign4 == enc_ops!(Reg) {
1935                    if !op0.as_::<Reg>().is_gp64() {
1936                        self.last_error = Some(AsmError::InvalidInstruction);
1937                        return;
1938                    }
1939
1940                    if !check_gp_id(op0, 63) {
1941                        self.last_error = Some(AsmError::InvalidOperand);
1942                        return;
1943                    }
1944
1945                    st.opcode.reset(op_data.opcode);
1946                    st.opcode.add_reg(op0.id(), 5);
1947                    emit_op!();
1948                }
1949            }
1950
1951            Encoding::BaseBranchRel => {
1952                let op_data = &BASE_BRANCH_REL[encoding_index];
1953                if isign4 == enc_ops!(Label) || isign4 == enc_ops!(Imm) {
1954                    st.opcode.reset(op_data.opcode);
1955                    st.rm_rel = *op0;
1956
1957                    if inst_cc as u32 != 0 || (st.opcode.0 & (1 << 30)) != 0 {
1958                        if st.opcode.has_x() {
1959                            self.last_error = Some(AsmError::InvalidInstruction);
1960                            return;
1961                        }
1962
1963                        st.opcode.0 |= 1 << 30;
1964                        st.opcode
1965                            .add_imm(cond_code_to_opcode_field(inst_cc as u32), 0);
1966                        st.offset_format
1967                            .reset_to_imm_type(OffsetType::SignedOffset, 4, 5, 19, 2);
1968                        st.rm_rel = *op0;
1969                        emit_rel!();
1970                    }
1971
1972                    st.offset_format
1973                        .reset_to_imm_type(OffsetType::SignedOffset, 4, 0, 26, 2);
1974                    st.rm_rel = *op0;
1975                    emit_rel!();
1976                }
1977            }
1978
1979            Encoding::BaseBranchCmp => {
1980                let op_data = &BASE_BRANCH_CMP[encoding_index];
1981                if isign4 == enc_ops!(Reg, Label) || isign4 == enc_ops!(Reg, Imm) {
1982                    let mut x = 0;
1983                    if !check_gp_typex(op0, 3, &mut x) {
1984                        self.last_error = Some(AsmError::InvalidInstruction);
1985                        return;
1986                    }
1987
1988                    if !check_gp_id(op0, 31) {
1989                        self.last_error = Some(AsmError::InvalidOperand);
1990                        return;
1991                    }
1992
1993                    st.opcode.reset(op_data.opcode);
1994                    st.opcode.add_imm(x, 31);
1995                    st.opcode.add_reg(op0.id(), 0);
1996                    st.offset_format
1997                        .reset_to_imm_type(OffsetType::SignedOffset, 4, 5, 19, 2);
1998
1999                    st.rm_rel = *op1;
2000                    emit_rel!();
2001                }
2002            }
2003
2004            Encoding::BaseBranchTst => {
2005                let op_data = &BASE_BRANCH_TST[encoding_index];
2006                if isign4 == enc_ops!(Reg, Imm, Label) || isign4 == enc_ops!(Reg, Imm, Imm) {
2007                    let mut x = 0;
2008                    if !check_gp_typex(op0, 3, &mut x) {
2009                        self.last_error = Some(AsmError::InvalidInstruction);
2010                        return;
2011                    }
2012
2013                    if !check_gp_id(op0, 31) {
2014                        self.last_error = Some(AsmError::InvalidOperand);
2015                        return;
2016                    }
2017
2018                    let mut imm = op1.as_::<Imm>().value() as u64;
2019
2020                    st.opcode.reset(op_data.opcode);
2021                    if imm >= 32 {
2022                        if x == 0 {
2023                            self.last_error = Some(AsmError::InvalidOperand);
2024                            return;
2025                        }
2026                        st.opcode.add_imm(x, 31);
2027                        imm &= 0x1F;
2028                    }
2029
2030                    st.opcode.add_reg(op0.id(), 0);
2031                    st.opcode.add_imm(imm as u32, 19);
2032                    st.offset_format
2033                        .reset_to_imm_type(OffsetType::SignedOffset, 4, 5, 14, 2);
2034
2035                    st.rm_rel = *op2;
2036                    emit_rel!();
2037                }
2038            }
2039
2040            Encoding::BasePrfm => {
2041                let op_data = &BASE_PRFM[encoding_index];
2042                if isign4 == enc_ops!(Imm, Mem) {
2043                    let m = op1.as_::<Mem>();
2044                    st.rm_rel = *op1;
2045
2046                    let imm_shift = 3u32;
2047
2048                    if op0.as_::<Imm>().value() as u64 > 0x1F {
2049                        self.last_error = Some(AsmError::TooLarge);
2050                        return;
2051                    }
2052
2053                    let offset = m.offset();
2054                    let prfop = op0.as_::<Imm>().value() as u32;
2055
2056                    if m.has_base_reg() {
2057                        if m.has_index() {
2058                            let opt = SHIFT_OP_TO_LD_ST_OP_MAP[m.shift_op() as usize];
2059                            if opt == 0xFF {
2060                                self.last_error = Some(AsmError::InvalidOperand);
2061                                return;
2062                            }
2063
2064                            let shift = m.shift();
2065                            let s = if shift != 0 { 1 } else { 0 };
2066
2067                            if s != 0 && shift != imm_shift {
2068                                self.last_error = Some(AsmError::InvalidOperand);
2069                                return;
2070                            }
2071
2072                            st.opcode.reset((op_data.register_op as u32) << 21);
2073                            st.opcode.add_imm(opt as u32, 13);
2074                            st.opcode.add_imm(s, 12);
2075                            st.opcode.0 |= 1 << 11;
2076                            st.opcode.add_imm(prfop, 0);
2077                            st.opcode.add_reg(m.base_id(), 5);
2078                            st.opcode.add_reg(m.index_id(), 16);
2079                            emit_op!();
2080                        }
2081
2082                        let offset32 = offset as i32;
2083                        let imm12 = (offset32 as u32) >> imm_shift;
2084
2085                        if imm12 < (1 << 12) && ((imm12 << imm_shift) as i32) == offset32 {
2086                            st.opcode.reset((op_data.s_offset_op as u32) << 22);
2087                            st.opcode.add_imm(imm12, 10);
2088                            st.opcode.add_imm(prfop, 0);
2089                            st.opcode.add_reg(m.base_id(), 5);
2090                            emit_op!();
2091                        }
2092
2093                        if offset32 >= -256 && offset32 < 256 {
2094                            st.opcode.reset((op_data.u_offset_op as u32) << 21);
2095                            st.opcode.add_imm((offset32 as u32) & 0x1FF, 12);
2096                            st.opcode.add_imm(prfop, 0);
2097                            st.opcode.add_reg(m.base_id(), 5);
2098                            emit_op!();
2099                        }
2100
2101                        self.last_error = Some(AsmError::InvalidOperand);
2102                        return;
2103                    } else {
2104                        st.opcode.reset((op_data.literal_op as u32) << 24);
2105                        st.opcode.add_imm(prfop, 0);
2106                        st.offset_format
2107                            .reset_to_imm_type(OffsetType::SignedOffset, 4, 5, 19, 2);
2108                        st.rm_rel = *op1;
2109                        emit_rel!();
2110                    }
2111                }
2112            }
2113
2114            Encoding::BaseLdSt => {
2115                let op_data = &BASE_LD_ST[encoding_index];
2116                if isign4 == enc_ops!(Reg, Mem) {
2117                    let m = op1.as_::<Mem>();
2118                    st.rm_rel = *op1;
2119
2120                    let mut x = 0;
2121                    if !check_gp_typex(op0, op_data.reg_type, &mut x) {
2122                        self.last_error = Some(AsmError::InvalidOperand);
2123                        return;
2124                    }
2125
2126                    if !check_gp_id(op0, 31) {
2127                        self.last_error = Some(AsmError::InvalidOperand);
2128                        return;
2129                    }
2130
2131                    let x_shift_mask = if op_data.u_offset_shift == 2 { 1 } else { 0 };
2132                    let imm_shift = (op_data.u_offset_shift as u32) + (x & x_shift_mask);
2133
2134                    let offset = m.offset();
2135
2136                    if m.has_base_reg() {
2137                        if m.has_index() {
2138                            let opt = SHIFT_OP_TO_LD_ST_OP_MAP[m.shift_op() as usize];
2139                            if opt == 0xFF {
2140                                self.last_error = Some(AsmError::InvalidOperand);
2141                                return;
2142                            }
2143
2144                            let shift = m.shift();
2145                            let s = if shift != 0 { 1 } else { 0 };
2146
2147                            if s != 0 && shift != imm_shift {
2148                                self.last_error = Some(AsmError::InvalidOperand);
2149                                return;
2150                            }
2151
2152                            st.opcode.reset((op_data.register_op as u32) << 21);
2153                            st.opcode.xor_imm(x, op_data.x_offset as u32);
2154                            st.opcode.add_imm(opt as u32, 13);
2155                            st.opcode.add_imm(s, 12);
2156                            st.opcode.0 |= 1 << 11;
2157                            st.opcode.add_reg(op0.id(), 0);
2158                            st.opcode.add_reg(m.base_id(), 5);
2159                            st.opcode.add_reg(m.index_id(), 16);
2160                            emit_op!();
2161                        }
2162
2163                        let offset32 = offset as i32;
2164                        let imm12 = (offset32 as u32) >> imm_shift;
2165
2166                        if imm12 < (1 << 12) && ((imm12 << imm_shift) as i32) == offset32 {
2167                            st.opcode.reset((op_data.u_offset_op as u32) << 22);
2168                            st.opcode.xor_imm(x, op_data.x_offset as u32);
2169                            st.opcode.add_imm(imm12, 10);
2170                            st.opcode.add_reg(op0.id(), 0);
2171                            st.opcode.add_reg(m.base_id(), 5);
2172                            emit_op!();
2173                        }
2174
2175                        if offset32 >= -256 && offset32 < 256 {
2176                            st.opcode.reset((op_data.u_offset_op as u32) << 22);
2177                            st.opcode.xor_imm(x, op_data.x_offset as u32);
2178                            st.opcode.add_imm((offset32 as u32) & 0x1FF, 12);
2179                            st.opcode.add_reg(op0.id(), 0);
2180                            st.opcode.add_reg(m.base_id(), 5);
2181                            emit_op!();
2182                        }
2183
2184                        self.last_error = Some(AsmError::InvalidOperand);
2185                        return;
2186                    } else {
2187                        if op_data.literal_op == 0 {
2188                            self.last_error = Some(AsmError::InvalidInstruction);
2189                            return;
2190                        }
2191
2192                        st.opcode.reset((op_data.literal_op as u32) << 24);
2193                        st.opcode.xor_imm(x, op_data.x_offset);
2194                        st.opcode.add_reg(op0.id(), 0);
2195                        st.offset_format
2196                            .reset_to_imm_type(OffsetType::Ldr, 4, 5, 19, 2);
2197                        emit_rel!();
2198                    }
2199                }
2200            }
2201
2202            Encoding::BaseLdpStp => {
2203                let op_data = &BASE_LDP_STP[encoding_index];
2204                if isign4 == enc_ops!(Reg, Reg, Mem) {
2205                    let m = op2.as_::<Mem>();
2206                    st.rm_rel = *op2;
2207
2208                    let mut x = 0;
2209                    if !check_gp_typex2(op0, op1, op_data.reg_type, &mut x) {
2210                        self.last_error = Some(AsmError::InvalidOperand);
2211                        return;
2212                    }
2213
2214                    if !check_gp_id2(op0, op1, 31) {
2215                        self.last_error = Some(AsmError::InvalidOperand);
2216                        return;
2217                    }
2218
2219                    let offset_shift = op_data.offset_shift as u32 + x;
2220                    let offset32 = (m.offset_lo32() as i32) >> offset_shift;
2221
2222                    if (offset32 as u32) << offset_shift != m.offset_lo32() as u32 {
2223                        self.last_error = Some(AsmError::InvalidOperand);
2224                        return;
2225                    }
2226
2227                    const I7_MAX: i32 = (1 << 6) - 1;
2228                    const I7_MIN: i32 = -(1 << 6);
2229
2230                    if offset32 < I7_MIN || offset32 > I7_MAX {
2231                        self.last_error = Some(AsmError::InvalidOperand);
2232                        return;
2233                    }
2234
2235                    if m.is_pre_or_post() && offset32 != 0 {
2236                        if op_data.pre_post_op == 0 {
2237                            self.last_error = Some(AsmError::InvalidInstruction);
2238                            return;
2239                        }
2240
2241                        st.opcode.reset((op_data.pre_post_op as u32) << 22);
2242                        st.opcode.add_imm(m.is_pre_index() as u32, 24);
2243                    } else {
2244                        st.opcode.reset((op_data.offset_op as u32) << 22);
2245                    }
2246                    st.opcode.add_imm(x, op_data.x_offset as u32);
2247                    st.opcode.add_imm((offset32 as u32) & 0x7F, 15);
2248                    st.opcode.add_reg(op1.id(), 10);
2249                    st.opcode.add_reg(op0.id(), 0);
2250                    st.opcode.add_reg(m.base_id(), 5);
2251                    emit_op!();
2252                }
2253            }
2254
2255            Encoding::BaseStx => {
2256                let op_data = &BASE_STX[encoding_index];
2257                if isign4 == enc_ops!(Reg, Reg, Mem) {
2258                    let m = op2.as_::<Mem>();
2259                    let mut x = 0;
2260                    if !op0.as_::<Reg>().is_gp32() || !check_gp_typex(op1, op_data.reg_type, &mut x)
2261                    {
2262                        self.last_error = Some(AsmError::InvalidOperand);
2263                        return;
2264                    }
2265                    if !check_gp_id2(op0, op1, 31) {
2266                        self.last_error = Some(AsmError::InvalidOperand);
2267                        return;
2268                    }
2269                    st.opcode.reset(op_data.opcode());
2270                    st.opcode.add_imm(x, op_data.x_offset as _);
2271                    st.opcode.add_reg(op0.id(), 16);
2272                    st.opcode.add_reg(op1.id(), 0);
2273                    st.rm_rel = *op2;
2274                    st.opcode.add_reg(m.base_id(), 5);
2275                    emit_op!();
2276                }
2277            }
2278
2279            Encoding::BaseLdxp => {
2280                let op_data = &BASE_LDXP[encoding_index];
2281                if isign4 == enc_ops!(Reg, Reg, Mem) {
2282                    let m = op2.as_::<Mem>();
2283                    let mut x = 0;
2284                    if !check_gp_typex(op0, op_data.reg_type, &mut x) || !check_signature!(op0, op1)
2285                    {
2286                        self.last_error = Some(AsmError::InvalidOperand);
2287                        return;
2288                    }
2289                    if !check_gp_id2(op0, op1, 31) {
2290                        self.last_error = Some(AsmError::InvalidOperand);
2291                        return;
2292                    }
2293                    st.opcode.reset(op_data.opcode());
2294                    st.opcode.add_imm(x, op_data.x_offset as _);
2295                    st.opcode.add_reg(op1.id(), 10);
2296                    st.opcode.add_reg(op0.id(), 0);
2297                    st.rm_rel = *op2;
2298                    st.opcode.add_reg(m.base_id(), 5);
2299                    emit_op!();
2300                }
2301            }
2302
2303            Encoding::BaseStxp => {
2304                let op_data = &BASE_STXP[encoding_index];
2305                if isign4 == enc_ops!(Reg, Reg, Reg, Mem) {
2306                    let m = op3.as_::<Mem>();
2307                    let mut x = 0;
2308                    if !op0.as_::<Reg>().is_gp32()
2309                        || !check_gp_typex(op1, op_data.reg_type, &mut x)
2310                        || !check_signature!(op1, op2)
2311                    {
2312                        self.last_error = Some(AsmError::InvalidOperand);
2313                        return;
2314                    }
2315                    if !check_gp_id3(op0, op1, op2, 31) {
2316                        self.last_error = Some(AsmError::InvalidOperand);
2317                        return;
2318                    }
2319                    st.opcode.reset(op_data.opcode());
2320                    st.opcode.add_imm(x, op_data.x_offset as _);
2321                    st.opcode.add_reg(op0.id(), 16);
2322                    st.opcode.add_reg(op2.id(), 10);
2323                    st.opcode.add_reg(op1.id(), 0);
2324                    st.rm_rel = *op3;
2325                    st.opcode.add_reg(m.base_id(), 5);
2326                    emit_op!();
2327                }
2328            }
2329
2330            Encoding::BaseRMNoImm => {
2331                let op_data = &BASE_RM_NO_IMM[encoding_index];
2332                if isign4 == enc_ops!(Reg, Mem) {
2333                    let m = op1.as_::<Mem>();
2334                    let mut x = 0;
2335                    if !check_gp_typex(op0, op_data.reg_type, &mut x) {
2336                        self.last_error = Some(AsmError::InvalidOperand);
2337                        return;
2338                    }
2339                    if !check_gp_id(op0, op_data.reg_hi_id) {
2340                        self.last_error = Some(AsmError::InvalidOperand);
2341                        return;
2342                    }
2343                    st.opcode.reset(op_data.opcode());
2344                    st.opcode.add_imm(x, op_data.x_offset as _);
2345                    st.opcode.add_reg(op0.id(), 0);
2346                    st.rm_rel = *op1;
2347
2348                    emit_mem_base_no_imm_rn5!();
2349                }
2350            }
2351
2352            Encoding::BaseRMSImm9 => {
2353                let op_data = &BASE_RM_SIMM9[encoding_index];
2354                if isign4 == enc_ops!(Reg, Mem) {
2355                    let m = op1.as_::<Mem>();
2356                    let mut x = 0;
2357                    if !check_gp_typex(op0, op_data.reg_type, &mut x) {
2358                        self.last_error = Some(AsmError::InvalidOperand);
2359                        return;
2360                    }
2361                    if !check_gp_id(op0, op_data.reg_hi_id) {
2362                        self.last_error = Some(AsmError::InvalidOperand);
2363                        return;
2364                    }
2365                    if m.has_base_reg() && !m.has_index() {
2366                        let offset32 = m.offset() as i32 >> op_data.imm_shift;
2367                        if (offset32 << op_data.imm_shift) != m.offset() as i32 {
2368                            self.last_error = Some(AsmError::InvalidOperand);
2369                            return;
2370                        }
2371                        if offset32 < -256 || offset32 > 255 {
2372                            self.last_error = Some(AsmError::InvalidOperand);
2373                            return;
2374                        }
2375                        if m.is_fixed_offset() {
2376                            st.opcode.reset(op_data.offset_op());
2377                        } else {
2378                            st.opcode.reset(op_data.pre_post_op());
2379                            st.opcode.xor_imm(m.is_pre_index() as u32, 11);
2380                        }
2381                        st.opcode.xor_imm(x, op_data.x_offset as u32);
2382                        st.opcode.add_imm((offset32 as u32) & 0x1FF, 12);
2383                        st.opcode.add_reg(op0.id(), 0);
2384                        st.opcode.add_reg(m.base_id(), 5);
2385                        emit_op!();
2386                    }
2387                    self.last_error = Some(AsmError::InvalidOperand);
2388                    return;
2389                }
2390            }
2391
2392            Encoding::BaseRMSImm10 => {
2393                let op_data = &BASE_RM_SIMM10[encoding_index];
2394                if isign4 == enc_ops!(Reg, Mem) {
2395                    let m = op1.as_::<Mem>();
2396                    let mut x = 0;
2397                    if !check_gp_typex(op0, op_data.reg_type, &mut x) {
2398                        self.last_error = Some(AsmError::InvalidOperand);
2399                        return;
2400                    }
2401                    if !check_gp_id(op0, op_data.reg_hi_id) {
2402                        self.last_error = Some(AsmError::InvalidOperand);
2403                        return;
2404                    }
2405                    if m.has_base_reg() && !m.has_index() {
2406                        let offset32 = m.offset() as i32 >> op_data.imm_shift;
2407                        if (offset32 << op_data.imm_shift) != m.offset() as i32 {
2408                            self.last_error = Some(AsmError::InvalidOperand);
2409                            return;
2410                        }
2411                        if offset32 < -512 || offset32 > 511 {
2412                            self.last_error = Some(AsmError::InvalidOperand);
2413                            return;
2414                        }
2415                        let offset32 = (offset32 as u32) & 0x3FF;
2416                        st.opcode.reset(op_data.opcode());
2417                        st.opcode.xor_imm(m.is_pre_index() as u32, 11);
2418                        st.opcode.xor_imm(x, op_data.x_offset as u32);
2419                        st.opcode.add_imm(offset32 >> 9, 22);
2420                        st.opcode.add_imm(offset32, 12);
2421                        st.opcode.add_reg(op0.id(), 0);
2422                        st.opcode.add_reg(m.base_id(), 5);
2423                        emit_op!();
2424                    }
2425                    self.last_error = Some(AsmError::InvalidOperand);
2426                    return;
2427                }
2428            }
2429
2430            Encoding::BaseAtomicOp => {
2431                let op_data = &BASE_ATOMIC_OP[encoding_index];
2432                if isign4 == enc_ops!(Reg, Reg, Mem) {
2433                    let m = op2.as_::<Mem>();
2434                    let mut x = 0;
2435                    if !check_gp_typex(op0, op_data.reg_type, &mut x) || !check_signature!(op0, op1)
2436                    {
2437                        self.last_error = Some(AsmError::InvalidOperand);
2438                        return;
2439                    }
2440                    if !check_gp_id2(op0, op1, 31) {
2441                        self.last_error = Some(AsmError::InvalidOperand);
2442                        return;
2443                    }
2444                    st.opcode.reset(op_data.opcode());
2445                    st.opcode.add_imm(x, op_data.x_offset as _);
2446                    st.opcode.add_reg(op0.id(), 16);
2447                    st.opcode.add_reg(op1.id(), 0);
2448                    st.rm_rel = *op2;
2449                    st.opcode.add_reg(m.base_id(), 5);
2450                    emit_op!();
2451                }
2452            }
2453
2454            Encoding::BaseAtomicSt => {
2455                let op_data = &BASE_ATOMIC_ST[encoding_index];
2456                if isign4 == enc_ops!(Reg, Mem) {
2457                    let m = op1.as_::<Mem>();
2458                    let mut x = 0;
2459                    if !check_gp_typex(op0, op_data.reg_type, &mut x) {
2460                        self.last_error = Some(AsmError::InvalidOperand);
2461                        return;
2462                    }
2463                    if !check_gp_id(op0, 31) {
2464                        self.last_error = Some(AsmError::InvalidOperand);
2465                        return;
2466                    }
2467                    st.opcode.reset(op_data.opcode());
2468                    st.opcode.add_imm(x, op_data.x_offset as _);
2469                    st.opcode.add_reg(op0.id(), 16);
2470                    st.opcode.add_reg(31, 0);
2471                    st.rm_rel = *op1;
2472                    st.opcode.add_reg(m.base_id(), 5);
2473                    emit_op!();
2474                }
2475            }
2476
2477            Encoding::BaseAtomicCasp => {
2478                let op_data = &BASE_ATOMIC_CASP[encoding_index];
2479                if isign4 == enc_ops!(Reg, Reg, Reg, Reg) {
2480                    let op4 = *ops.get(4).unwrap_or(&NOREG);
2481                    if op4.is_mem() {
2482                        let m = op4.as_::<Mem>();
2483                        let mut x = 0;
2484                        if !check_gp_typex(op0, op_data.reg_type, &mut x) {
2485                            self.last_error = Some(AsmError::InvalidOperand);
2486                            return;
2487                        }
2488                        if !check_signature!(op0, op1, op2, op3) {
2489                            self.last_error = Some(AsmError::InvalidOperand);
2490                            return;
2491                        }
2492                        let id0 = op0.id();
2493                        let id2 = op2.id();
2494                        if (id0 & 1) != 0 || (id2 & 1) != 0 || id0 == id2 || id0 > 30 || id2 > 30 {
2495                            self.last_error = Some(AsmError::InvalidOperand);
2496                            return;
2497                        }
2498                        if (id0 + 1) != op1.id() || (id2 + 1) != op3.id() {
2499                            self.last_error = Some(AsmError::InvalidOperand);
2500                            return;
2501                        }
2502                        st.opcode.reset(op_data.opcode());
2503                        st.opcode.add_imm(x, op_data.x_offset as _);
2504                        st.opcode.add_reg(op0.id(), 16);
2505                        st.opcode.add_reg(op2.id(), 0);
2506                        st.rm_rel = *op4;
2507                        emit_mem_base_no_imm_rn5!();
2508                    }
2509                }
2510            }
2511
2512            Encoding::FSimdSV => {
2513                let op_data = &F_SIMD_SV[encoding_index];
2514
2515                if isign4 == enc_ops!(Reg, Reg) {
2516                    let q = op1.as_::<Reg>().typ() as u32;
2517                    let q = if q >= RegType::Vec64 as u32 {
2518                        q - RegType::Vec64 as u32
2519                    } else {
2520                        u32::MAX
2521                    };
2522                    if q > 1 {
2523                        self.last_error = Some(AsmError::InvalidInstruction);
2524                        return;
2525                    }
2526
2527                    if op0.as_::<Vec>().has_element_type() {
2528                        self.last_error = Some(AsmError::InvalidInstruction);
2529                        return;
2530                    }
2531
2532                    let sz = op0.as_::<Reg>().typ() as u32;
2533                    let sz = if sz >= RegType::Vec16 as u32 {
2534                        sz - RegType::Vec16 as u32
2535                    } else {
2536                        u32::MAX
2537                    };
2538                    let element_sz = op1.as_::<Vec>().element_type() as u32;
2539                    let element_sz = if element_sz >= VecElementType::H as u32 {
2540                        element_sz - VecElementType::H as u32
2541                    } else {
2542                        u32::MAX
2543                    };
2544
2545                    if (sz | element_sz) > 1 || sz != element_sz {
2546                        self.last_error = Some(AsmError::InvalidInstruction);
2547                        return;
2548                    }
2549
2550                    if sz != 0 && q == 0 {
2551                        self.last_error = Some(AsmError::InvalidInstruction);
2552                        return;
2553                    }
2554
2555                    st.opcode.reset((op_data.opcode as u32) << 10);
2556                    if sz == 0 {
2557                        st.opcode.0 ^= 1 << 29;
2558                    }
2559                    st.opcode.add_imm(q, 30);
2560                    st.opcode.add_reg(op0.id(), 0);
2561                    st.opcode.add_reg(op1.id(), 5);
2562                    emit_op!();
2563                }
2564            }
2565
2566            Encoding::FSimdVV => {
2567                let op_data = &F_SIMD_VV[encoding_index];
2568
2569                if isign4 == enc_ops!(Reg, Reg) {
2570                    if !match_signature2(op0, op1, inst_flags as u32) {
2571                        self.last_error = Some(AsmError::InvalidInstruction);
2572                        return;
2573                    }
2574
2575                    if let Some(fp_opcode) = pick_fp_opcode(
2576                        op0.as_::<Vec>(),
2577                        op_data.scalar_op(),
2578                        op_data.scalar_hf(),
2579                        op_data.vector_op(),
2580                        op_data.vector_hf(),
2581                        &mut 0,
2582                    ) {
2583                        st.opcode.reset(fp_opcode.0);
2584                        emit_rd0_rn5!();
2585                    }
2586
2587                    self.last_error = Some(AsmError::InvalidInstruction);
2588                    return;
2589                }
2590            }
2591
2592            Encoding::FSimdVVV => {
2593                let op_data = &F_SIMD_VVV[encoding_index];
2594
2595                if isign4 == enc_ops!(Reg, Reg, Reg) {
2596                    if !match_signature3(op0, op1, op2, inst_flags as u32) {
2597                        self.last_error = Some(AsmError::InvalidInstruction);
2598                        return;
2599                    }
2600
2601                    if let Some(fp_opcode) = pick_fp_opcode(
2602                        op0.as_::<Vec>(),
2603                        op_data.scalar_op(),
2604                        op_data.scalar_hf(),
2605                        op_data.vector_op(),
2606                        op_data.vector_hf(),
2607                        &mut 0,
2608                    ) {
2609                        st.opcode.reset(fp_opcode.0);
2610                        emit_rd0_rn5_rm16!();
2611                    }
2612
2613                    self.last_error = Some(AsmError::InvalidInstruction);
2614                    return;
2615                }
2616            }
2617
2618            Encoding::FSimdVVVe => {
2619                let op_data = &F_SIMD_VVVE[encoding_index];
2620
2621                if isign4 == enc_ops!(Reg, Reg, Reg) {
2622                    if !op2.as_::<Vec>().has_element_index() {
2623                        if !match_signature3(op0, op1, op2, inst_flags as u32) {
2624                            self.last_error = Some(AsmError::InvalidInstruction);
2625                            return;
2626                        }
2627
2628                        if let Some(fp_opcode) = pick_fp_opcode(
2629                            op0.as_::<Vec>(),
2630                            op_data.scalar_op(),
2631                            op_data.scalar_hf(),
2632                            op_data.vector_op(),
2633                            op_data.vector_hf(),
2634                            &mut 0,
2635                        ) {
2636                            st.opcode.reset(fp_opcode.0);
2637
2638                            emit_rd0_rn5_rm16!();
2639                        }
2640
2641                        self.last_error = Some(AsmError::InvalidInstruction);
2642                        return;
2643                    } else {
2644                        if !match_signature2(op0, op1, inst_flags as u32) {
2645                            self.last_error = Some(AsmError::InvalidInstruction);
2646                            return;
2647                        }
2648
2649                        let q = op1.as_::<Reg>().is_vec128() as u32;
2650                        let mut sz = 0;
2651                        if let Some((fp_opcode)) = pick_fp_opcode(
2652                            op0.as_::<Vec>(),
2653                            op_data.element_scalar_op(),
2654                            5,
2655                            op_data.element_vector_op(),
2656                            5,
2657                            &mut sz,
2658                        ) {
2659                            if sz == 0 && op2.as_::<Reg>().id() > 15 {
2660                                self.last_error = Some(AsmError::InvalidOperand);
2661                                return;
2662                            }
2663
2664                            let element_index = op2.as_::<Vec>().element_index();
2665                            if element_index > (7u32 >> sz) {
2666                                self.last_error = Some(AsmError::InvalidOperand);
2667                                return;
2668                            }
2669
2670                            let hlm = element_index << sz;
2671                            st.opcode.reset(fp_opcode.0);
2672                            st.opcode.add_imm(q, 30);
2673                            st.opcode.add_imm(hlm & 3, 20);
2674                            st.opcode.add_imm(hlm >> 2, 11);
2675                            emit_rd0_rn5_rm16!();
2676                        }
2677
2678                        self.last_error = Some(AsmError::InvalidInstruction);
2679                        return;
2680                    }
2681                }
2682            }
2683
2684            Encoding::FSimdVVVV => {
2685                let op_data = &F_SIMD_VVVV[encoding_index];
2686
2687                if isign4 == enc_ops!(Reg, Reg, Reg, Reg) {
2688                    if !match_signature4(op0, op1, op2, op3, inst_flags as u32) {
2689                        self.last_error = Some(AsmError::InvalidInstruction);
2690                        return;
2691                    }
2692
2693                    if let Some(fp_opcode) = pick_fp_opcode(
2694                        op0.as_::<Vec>(),
2695                        op_data.scalar_op(),
2696                        op_data.scalar_hf(),
2697                        op_data.vector_op(),
2698                        op_data.vector_hf(),
2699                        &mut 0,
2700                    ) {
2701                        st.opcode.reset(fp_opcode.0);
2702                        emit_rd0_rn5_rm16_ra10!();
2703                    }
2704
2705                    self.last_error = Some(AsmError::InvalidInstruction);
2706                    return;
2707                }
2708            }
2709
2710            Encoding::SimdFcadd => {
2711                let op_data = &SIMD_FCADD[encoding_index];
2712
2713                if isign4 == enc_ops!(Reg, Reg, Reg, Imm) {
2714                    if !check_signature!(op0, op1, op2) || op0.as_::<Vec>().has_element_index() {
2715                        self.last_error = Some(AsmError::InvalidInstruction);
2716                        return;
2717                    }
2718
2719                    let q = (op0.as_::<Reg>().is_vec128() as u32).wrapping_sub(1);
2720                    if q > 1 {
2721                        self.last_error = Some(AsmError::InvalidInstruction);
2722                        return;
2723                    }
2724
2725                    let mut sz = op0.as_::<Vec>().element_type() as u32;
2726                    sz = sz.wrapping_sub(1);
2727                    if sz == 0 || sz > 3 {
2728                        self.last_error = Some(AsmError::InvalidInstruction);
2729                        return;
2730                    }
2731
2732                    let mut rot = 0u32;
2733                    let imm_val = op3.as_::<Imm>().value();
2734                    if imm_val == 270 {
2735                        rot = 1;
2736                    } else if imm_val != 90 {
2737                        self.last_error = Some(AsmError::InvalidOperand);
2738                        return;
2739                    }
2740
2741                    st.opcode.reset(op_data.opcode());
2742                    st.opcode.add_imm(q, 30);
2743                    st.opcode.add_imm(sz, 22);
2744                    st.opcode.add_imm(rot, 12);
2745                    emit_rd0_rn5_rm16!();
2746                }
2747            }
2748
2749            Encoding::SimdFccmpFccmpe => {
2750                let op_data = &SIMD_FCCMP_FCCMPE[encoding_index];
2751
2752                if isign4 == enc_ops!(Reg, Reg, Imm, Imm) {
2753                    let sz = (op0.as_::<Reg>().typ() as u32).wrapping_sub(RegType::Vec16 as u32);
2754                    if sz > 2 {
2755                        self.last_error = Some(AsmError::InvalidInstruction);
2756                        return;
2757                    }
2758
2759                    if !check_signature!(op0, op1) || op0.as_::<Vec>().has_element_type() {
2760                        self.last_error = Some(AsmError::InvalidInstruction);
2761                        return;
2762                    }
2763
2764                    let nzcv = op2.as_::<Imm>().value() as u64;
2765                    let cond = op3.as_::<Imm>().value() as u64;
2766
2767                    if (nzcv | cond) > 0xF {
2768                        self.last_error = Some(AsmError::InvalidOperand);
2769                        return;
2770                    }
2771
2772                    let type_field = sz.wrapping_sub(1) & 0x3;
2773
2774                    st.opcode.reset(op_data.opcode());
2775                    st.opcode.add_imm(type_field, 22);
2776                    st.opcode
2777                        .add_imm(cond_code_to_opcode_field(cond as u32), 12);
2778                    st.opcode.add_imm(nzcv as u32, 0);
2779                    emit_rn5_rm16!();
2780                }
2781            }
2782
2783            Encoding::SimdFcm => {
2784                let op_data = &SIMD_FCM[encoding_index];
2785
2786                if isign4 == enc_ops!(Reg, Reg, Reg) && op_data.has_register_op() {
2787                    if !match_signature3(op0, op1, op2, inst_flags as u32) {
2788                        self.last_error = Some(AsmError::InvalidInstruction);
2789                        return;
2790                    }
2791
2792                    if let Some(fp_opcode) = pick_fp_opcode(
2793                        op0.as_::<Vec>(),
2794                        op_data.register_scalar_op(),
2795                        op_data.register_scalar_hf(),
2796                        op_data.register_vector_op(),
2797                        op_data.register_vector_hf(),
2798                        &mut 0,
2799                    ) {
2800                        st.opcode.reset(fp_opcode.0);
2801                        emit_rd0_rn5_rm16!();
2802                    }
2803
2804                    self.last_error = Some(AsmError::InvalidInstruction);
2805                    return;
2806                }
2807
2808                if isign4 == enc_ops!(Reg, Reg, Imm) && op_data.has_zero_op() {
2809                    if !check_signature!(op0, op1) {
2810                        self.last_error = Some(AsmError::InvalidInstruction);
2811                        return;
2812                    }
2813
2814                    if op2.as_::<Imm>().value() != 0 {
2815                        self.last_error = Some(AsmError::InvalidOperand);
2816                        return;
2817                    }
2818
2819                    if let Some(fp_opcode) = pick_fp_opcode(
2820                        op0.as_::<Vec>(),
2821                        op_data.zero_scalar_op(),
2822                        5,
2823                        op_data.zero_vector_op(),
2824                        5,
2825                        &mut 0,
2826                    ) {
2827                        st.opcode.reset(fp_opcode.0);
2828                        emit_rd0_rn5!();
2829                    }
2830
2831                    self.last_error = Some(AsmError::InvalidInstruction);
2832                    return;
2833                }
2834            }
2835
2836            Encoding::SimdFcmla => {
2837                let op_data = &SIMD_FCMLA[encoding_index];
2838
2839                if isign4 == enc_ops!(Reg, Reg, Reg, Imm) {
2840                    if !check_signature!(op0, op1) {
2841                        self.last_error = Some(AsmError::InvalidInstruction);
2842                        return;
2843                    }
2844
2845                    let q = (op0.as_::<Reg>().is_vec128() as u32).wrapping_sub(1);
2846                    if q > 1 {
2847                        self.last_error = Some(AsmError::InvalidInstruction);
2848                        return;
2849                    }
2850
2851                    let mut sz = op0.as_::<Vec>().element_type() as u32;
2852                    sz = sz.wrapping_sub(1);
2853                    if sz == 0 || sz > 3 {
2854                        self.last_error = Some(AsmError::InvalidInstruction);
2855                        return;
2856                    }
2857
2858                    let mut rot = 0u32;
2859                    match op3.as_::<Imm>().value() {
2860                        0 => rot = 0,
2861                        90 => rot = 1,
2862                        180 => rot = 2,
2863                        270 => rot = 3,
2864                        _ => {
2865                            self.last_error = Some(AsmError::InvalidOperand);
2866                            return;
2867                        }
2868                    }
2869
2870                    if !op2.as_::<Vec>().has_element_index() {
2871                        if !check_signature!(op1, op2) {
2872                            self.last_error = Some(AsmError::InvalidInstruction);
2873                            return;
2874                        }
2875
2876                        st.opcode.reset(op_data.regular_op());
2877                        st.opcode.add_imm(q, 30);
2878                        st.opcode.add_imm(sz, 22);
2879                        st.opcode.add_imm(rot, 11);
2880                        emit_rd0_rn5_rm16!();
2881                    } else {
2882                        if op0.as_::<Vec>().element_type() != op2.as_::<Vec>().element_type() {
2883                            self.last_error = Some(AsmError::InvalidOperand);
2884                            return;
2885                        }
2886
2887                        if !((sz == 1) || (q == 1 && sz == 2)) {
2888                            self.last_error = Some(AsmError::InvalidOperand);
2889                            return;
2890                        }
2891
2892                        let element_index = op2.as_::<Vec>().element_index();
2893                        let hl_field_shift = if sz == 1 { 0u32 } else { 1u32 };
2894                        let max_element_index = if q == 1 && sz == 1 { 3u32 } else { 1u32 };
2895
2896                        if element_index > max_element_index {
2897                            self.last_error = Some(AsmError::InvalidOperand);
2898                            return;
2899                        }
2900
2901                        let hl = element_index << hl_field_shift;
2902
2903                        st.opcode.reset(op_data.element_op());
2904                        st.opcode.add_imm(q, 30);
2905                        st.opcode.add_imm(sz, 22);
2906                        st.opcode.add_imm(hl & 1u32, 21);
2907                        st.opcode.add_imm(hl >> 1, 11);
2908                        st.opcode.add_imm(rot, 13);
2909                        emit_rd0_rn5_rm16!();
2910                    }
2911                }
2912            }
2913
2914            Encoding::SimdFcmpFcmpe => {
2915                let op_data = &SIMD_FCMP_FCMPE[encoding_index];
2916
2917                let sz = (op0.as_::<Reg>().typ() as u32).wrapping_sub(RegType::Vec16 as u32);
2918                let type_field = sz.wrapping_sub(1) & 0x3u32;
2919
2920                if sz > 2 {
2921                    self.last_error = Some(AsmError::InvalidInstruction);
2922                    return;
2923                }
2924
2925                if op0.as_::<Vec>().has_element_type() {
2926                    self.last_error = Some(AsmError::InvalidInstruction);
2927                    return;
2928                }
2929
2930                st.opcode.reset(op_data.opcode());
2931                st.opcode.add_imm(type_field, 22);
2932
2933                if isign4 == enc_ops!(Reg, Reg) {
2934                    if !check_signature!(op0, op1) {
2935                        self.last_error = Some(AsmError::InvalidInstruction);
2936                        return;
2937                    }
2938
2939                    emit_rd0_rn5_rm16!();
2940                } else if isign4 == enc_ops!(Reg, Imm) {
2941                    if op1.as_::<Imm>().value() != 0 {
2942                        self.last_error = Some(AsmError::InvalidOperand);
2943                        return;
2944                    }
2945
2946                    st.opcode.0 |= 0x8;
2947                    emit_rd0_rn5!();
2948                }
2949            }
2950
2951            Encoding::SimdFcsel => {
2952                if isign4 == enc_ops!(Reg, Reg, Reg, Imm) {
2953                    if !check_signature!(op0, op1, op2) {
2954                        self.last_error = Some(AsmError::InvalidInstruction);
2955                        return;
2956                    }
2957
2958                    let sz = (op0.as_::<Reg>().typ() as u32).wrapping_sub(RegType::Vec16 as u32);
2959                    let type_field = sz.wrapping_sub(1) & 0x3u32;
2960
2961                    if sz > 2 || op0.as_::<Vec>().has_element_type() {
2962                        self.last_error = Some(AsmError::InvalidInstruction);
2963                        return;
2964                    }
2965
2966                    let cond = op3.as_::<Imm>().value() as u32;
2967                    if cond > 0xFu32 {
2968                        self.last_error = Some(AsmError::InvalidImmediate);
2969                        return;
2970                    }
2971
2972                    st.opcode.reset(0b00011110001000000000110000000000u32);
2973                    st.opcode.add_imm(type_field, 22);
2974                    st.opcode.add_imm(cond, 12);
2975                    emit_rd0_rn5_rm16!();
2976                }
2977            }
2978
2979            Encoding::SimdFcvt => {
2980                if isign4 == enc_ops!(Reg, Reg) {
2981                    let dst_sz =
2982                        (op0.as_::<Reg>().reg_type() as u32).wrapping_sub(RegType::Vec16 as u32);
2983                    let src_sz =
2984                        (op1.as_::<Reg>().reg_type() as u32).wrapping_sub(RegType::Vec16 as u32);
2985
2986                    if (dst_sz | src_sz) > 3 {
2987                        self.last_error = Some(AsmError::InvalidInstruction);
2988                        return;
2989                    }
2990
2991                    if op0.as_::<Vec>().has_element_type() || op1.as_::<Vec>().has_element_type() {
2992                        self.last_error = Some(AsmError::InvalidInstruction);
2993                        return;
2994                    }
2995
2996                    // Table that provides 'type' and 'opc' according to the dst/src combination.
2997                    let table: [u8; 16] = [
2998                        0xFFu8, // H <- H (Invalid).
2999                        0x03u8, // H <- S (type=00 opc=11).
3000                        0x13u8, // H <- D (type=01 opc=11).
3001                        0xFFu8, // H <- Q (Invalid).
3002                        0x30u8, // S <- H (type=11 opc=00).
3003                        0xFFu8, // S <- S (Invalid).
3004                        0x10u8, // S <- D (type=01 opc=00).
3005                        0xFFu8, // S <- Q (Invalid).
3006                        0x31u8, // D <- H (type=11 opc=01).
3007                        0x01u8, // D <- S (type=00 opc=01).
3008                        0xFFu8, // D <- D (Invalid).
3009                        0xFFu8, // D <- Q (Invalid).
3010                        0xFFu8, // Q <- H (Invalid).
3011                        0xFFu8, // Q <- S (Invalid).
3012                        0xFFu8, // Q <- D (Invalid).
3013                        0xFFu8, // Q <- Q (Invalid).
3014                    ];
3015
3016                    let type_opc = table[((dst_sz << 2) | src_sz) as usize];
3017                    if type_opc == 0xFFu8 {
3018                        self.last_error = Some(AsmError::InvalidInstruction);
3019                        return;
3020                    }
3021
3022                    st.opcode.reset(0b0001111000100010010000 << 10);
3023                    st.opcode.add_imm((type_opc as u32) >> 4, 22);
3024                    st.opcode.add_imm((type_opc as u32) & 15, 15);
3025                    emit_rd0_rn5!();
3026                }
3027            }
3028
3029            Encoding::SimdFcvtLN => {
3030                let op_data = &SIMD_FCVT_LN[encoding_index];
3031
3032                if isign4 == enc_ops!(Reg, Reg) {
3033                    // Scalar form - only FCVTXN.
3034                    if op0.as_::<Vec>().is_vec32() && op1.as_::<Vec>().is_vec64() {
3035                        if op_data.has_scalar() == 0 {
3036                            self.last_error = Some(AsmError::InvalidInstruction);
3037                            return;
3038                        }
3039
3040                        if op0.as_::<Vec>().has_element_type()
3041                            || op1.as_::<Vec>().has_element_type()
3042                        {
3043                            self.last_error = Some(AsmError::InvalidInstruction);
3044                            return;
3045                        }
3046
3047                        st.opcode.reset(op_data.scalar_op());
3048                        st.opcode.0 |= 0x400000; // sz bit must be 1
3049                        emit_rd0_rn5!();
3050                        return;
3051                    }
3052
3053                    st.opcode.reset(op_data.vector_op());
3054
3055                    let is_long = (inst_flags & InstFlag::Long as u16) != 0;
3056                    let (rl, rn) = if is_long {
3057                        (op0.as_::<Vec>(), op1.as_::<Vec>())
3058                    } else {
3059                        (op1.as_::<Vec>(), op0.as_::<Vec>())
3060                    };
3061
3062                    let q = (rn.reg_type() as u32).wrapping_sub(RegType::Vec64 as u32);
3063                    if (st.opcode.has_q() as u32) != q {
3064                        self.last_error = Some(AsmError::InvalidInstruction);
3065                        return;
3066                    }
3067
3068                    if rl.is_vec_s4()
3069                        && rn.element_type() == VecElementType::H
3070                        && op_data.is_cvtxn() == 0
3071                    {
3072                        emit_rd0_rn5!();
3073                        return;
3074                    }
3075
3076                    if rl.is_vec_d2() && rn.element_type() == VecElementType::S {
3077                        st.opcode.0 |= 0x400000;
3078                        emit_rd0_rn5!();
3079                        return;
3080                    }
3081
3082                    self.last_error = Some(AsmError::InvalidInstruction);
3083                    return;
3084                }
3085            }
3086
3087            Encoding::SimdFcvtSV => {
3088                let op_data = &SIMD_FCVT_SV[encoding_index];
3089
3090                // So we can support both IntToFloat and FloatToInt conversions.
3091                let is_float_to_int = op_data.is_float_to_int();
3092                let (op_gp, op_vec) = if is_float_to_int != 0 {
3093                    (&op0, &op1)
3094                } else {
3095                    (&op1, &op0)
3096                };
3097
3098                if isign4 == enc_ops!(Reg, Reg) {
3099                    if op_gp.as_::<Reg>().is_gp() && op_vec.as_::<Reg>().is_vec() {
3100                        let x = op_gp.as_::<Reg>().is_gp64() as u32;
3101                        let type_field = (op_vec.as_::<Reg>().reg_type() as u32)
3102                            .wrapping_sub(RegType::Vec16 as u32);
3103
3104                        if type_field > 2u32 {
3105                            self.last_error = Some(AsmError::InvalidInstruction);
3106                            return;
3107                        }
3108
3109                        let type_val = (type_field - 1u32) & 0x3;
3110                        st.opcode.reset(op_data.general_op());
3111                        st.opcode.add_imm(type_val, 22);
3112                        st.opcode.add_imm(x, 31);
3113                        emit_rd0_rn5!();
3114                    } else if op0.as_::<Reg>().is_vec() && op1.as_::<Reg>().is_vec() {
3115                        if !check_signature!(op0, op1) {
3116                            self.last_error = Some(AsmError::InvalidInstruction);
3117                            return;
3118                        }
3119
3120                        if let Some(fp_opcode) = pick_fp_opcode(
3121                            op0.as_::<Vec>(),
3122                            op_data.scalar_int_op(),
3123                            5,
3124                            op_data.vector_int_op(),
3125                            5,
3126                            &mut 0,
3127                        ) {
3128                            st.opcode.reset(fp_opcode.0);
3129                            emit_rd0_rn5!();
3130                        } else {
3131                            self.last_error = Some(AsmError::InvalidInstruction);
3132                            return;
3133                        }
3134                    }
3135                } else if isign4 == enc_ops!(Reg, Reg, Imm) && op_data.is_fixed_point() {
3136                    let scale_val = op2.as_::<Imm>().value() as u32;
3137                    if scale_val >= 64 {
3138                        self.last_error = Some(AsmError::InvalidImmediate);
3139                        return;
3140                    }
3141
3142                    if scale_val == 0 {
3143                        self.last_error = Some(AsmError::InvalidOperand);
3144                        return;
3145                    }
3146
3147                    if op_gp.as_::<Reg>().is_gp() && op_vec.as_::<Reg>().is_vec() {
3148                        let x = op_gp.as_::<Reg>().is_gp64() as u32;
3149                        let type_field = (op_vec.as_::<Reg>().reg_type() as u32)
3150                            .wrapping_sub(RegType::Vec16 as u32);
3151
3152                        let scale_limit = 32u32 << x;
3153                        if scale_val > scale_limit {
3154                            self.last_error = Some(AsmError::InvalidOperand);
3155                            return;
3156                        }
3157
3158                        let type_val = (type_field - 1u32) & 0x3;
3159                        st.opcode.reset(op_data.general_op() ^ 0x200000);
3160                        st.opcode.add_imm(type_val, 22);
3161                        st.opcode.add_imm(x, 31);
3162                        st.opcode.add_imm(64u32 - scale_val, 10);
3163                        emit_rd0_rn5!();
3164                    } else if op0.as_::<Reg>().is_vec() && op1.as_::<Reg>().is_vec() {
3165                        if !check_signature!(op0, op1) {
3166                            self.last_error = Some(AsmError::InvalidInstruction);
3167                            return;
3168                        }
3169
3170                        let mut sz = 0u32;
3171                        if let Some(fp_opcode) = pick_fp_opcode(
3172                            op0.as_::<Vec>(),
3173                            op_data.scalar_fp_op(),
3174                            5,
3175                            op_data.vector_fp_op(),
3176                            5,
3177                            &mut sz,
3178                        ) {
3179                            let scale_limit = 16u32 << sz;
3180                            if scale_val > scale_limit {
3181                                self.last_error = Some(AsmError::InvalidOperand);
3182                                return;
3183                            }
3184
3185                            let imm = (!(scale_val) + 1) & ((1u32 << (sz + 4 + 1)) - 1);
3186                            st.opcode.reset(fp_opcode.0);
3187                            st.opcode.add_imm(imm, 16);
3188                            emit_rd0_rn5!();
3189                        } else {
3190                            self.last_error = Some(AsmError::InvalidInstruction);
3191                            return;
3192                        }
3193                    }
3194                }
3195            }
3196
3197            Encoding::SimdFmlal => {
3198                let op_data = &SIMD_FMLAL[encoding_index];
3199
3200                if isign4 == enc_ops!(Reg, Reg, Reg) {
3201                    let mut q =
3202                        (op0.as_::<Reg>().reg_type() as u32).wrapping_sub(RegType::Vec64 as u32);
3203                    let q_is_optional = op_data.optional_q() != 0;
3204
3205                    if q_is_optional {
3206                        if q > 1 {
3207                            self.last_error = Some(AsmError::InvalidInstruction);
3208                            return;
3209                        }
3210                    } else {
3211                        if q != 1 {
3212                            self.last_error = Some(AsmError::InvalidInstruction);
3213                            return;
3214                        }
3215
3216                        q = 0;
3217                    }
3218
3219                    if (op0.as_::<Reg>().reg_type() as u32)
3220                        != (op1.as_::<Reg>().reg_type() as u32) + if q_is_optional { 1 } else { 0 }
3221                        || (op0.as_::<Vec>().element_type() as u32) != op_data.ta as u32
3222                        || (op1.as_::<Vec>().element_type() as u32) != op_data.tb as u32
3223                    {
3224                        self.last_error = Some(AsmError::InvalidInstruction);
3225                        return;
3226                    }
3227
3228                    if !op2.as_::<Vec>().has_element_index() {
3229                        if !check_signature!(&op1, &op2) {
3230                            self.last_error = Some(AsmError::InvalidInstruction);
3231                            return;
3232                        }
3233
3234                        st.opcode.reset(op_data.vector_op());
3235                        st.opcode.add_imm(q, 30);
3236                        emit_rd0_rn5_rm16!();
3237                    } else {
3238                        if (op2.as_::<Vec>().element_type() as u32) != op_data.t_element as u32 {
3239                            self.last_error = Some(AsmError::InvalidInstruction);
3240                            return;
3241                        }
3242
3243                        if op2.as_::<Reg>().id() > 15 {
3244                            self.last_error = Some(AsmError::InvalidOperand);
3245                            return;
3246                        }
3247
3248                        let element_index = op2.as_::<Vec>().element_index();
3249                        if element_index > 7u32 {
3250                            self.last_error = Some(AsmError::InvalidOperand);
3251                            return;
3252                        }
3253
3254                        st.opcode.reset(op_data.element_op());
3255                        st.opcode.add_imm(q, 30);
3256                        st.opcode.add_imm(element_index & 3u32, 20);
3257                        st.opcode.add_imm(element_index >> 2, 11);
3258                        emit_rd0_rn5_rm16!();
3259                    }
3260                }
3261            }
3262
3263            Encoding::SimdFmov => {
3264                if isign4 == enc_ops!(Reg, Reg) {
3265                    // FMOV Gp <-> Vec st.opcode:
3266                    st.opcode.reset(0b00011110001001100000000000000000);
3267
3268                    if (op0.as_::<Reg>().is_gp() && op1.as_::<Reg>().is_vec()) {
3269                        // FMOV Wd, Hn      (sf=0 type=11 rmode=00 op=110)
3270                        // FMOV Xd, Hn      (sf=1 type=11 rmode=00 op=110)
3271                        // FMOV Wd, Sn      (sf=0 type=00 rmode=00 op=110)
3272                        // FMOV Xd, Dn      (sf=1 type=11 rmode=00 op=110)
3273                        // FMOV Xd, Vn.d[1] (sf=1 type=10 rmode=01 op=110)
3274                        let x = op0.as_::<Reg>().is_gp64();
3275                        let sz = (op1.as_::<Reg>().reg_type() as u32)
3276                            .wrapping_sub(RegType::Vec16 as u32);
3277
3278                        let mut typ = sz.wrapping_sub(1) & 0x3;
3279                        let mut r_mode_op = 0b00110;
3280
3281                        if (op1.as_::<Vec>().has_element_index()) {
3282                            // Special case.
3283                            if (!x
3284                                || !op1.as_::<Vec>().is_vec_d2()
3285                                || op1.as_::<Vec>().element_index() != 1)
3286                            {
3287                                self.last_error = Some(AsmError::InvalidInstruction);
3288                                return;
3289                            }
3290                            typ = 0b10;
3291                            r_mode_op = 0b01110;
3292                        } else {
3293                            // Must be scalar.
3294                            if (sz > 2) {
3295                                self.last_error = Some(AsmError::InvalidOperand);
3296                                return;
3297                            }
3298
3299                            if (op1.as_::<Vec>().has_element_type()) {
3300                                self.last_error = Some(AsmError::InvalidInstruction);
3301                                return;
3302                            }
3303
3304                            if (op1.as_::<Vec>().is_vec32() && x) {
3305                                self.last_error = Some(AsmError::InvalidInstruction);
3306                                return;
3307                            }
3308
3309                            if (op1.as_::<Vec>().is_vec64() && !x) {
3310                                self.last_error = Some(AsmError::InvalidInstruction);
3311                                return;
3312                            }
3313                        }
3314
3315                        st.opcode.add_imm(x as u32, 31);
3316                        st.opcode.add_imm(typ, 22);
3317                        st.opcode.add_imm(r_mode_op, 16);
3318
3319                        emit_rd0_rn5!();
3320                    }
3321
3322                    if (op0.as_::<Reg>().is_vec() && op1.as_::<Reg>().is_gp()) {
3323                        // FMOV Hd, Wn      (sf=0 type=11 rmode=00 op=111)
3324                        // FMOV Hd, Xn      (sf=1 type=11 rmode=00 op=111)
3325                        // FMOV Sd, Wn      (sf=0 type=00 rmode=00 op=111)
3326                        // FMOV Dd, Xn      (sf=1 type=11 rmode=00 op=111)
3327                        // FMOV Vd.d[1], Xn (sf=1 type=10 rmode=01 op=111)
3328                        let x = op1.as_::<Reg>().is_gp64();
3329                        let sz = (op0.as_::<Reg>().reg_type() as u32)
3330                            .wrapping_sub(RegType::Vec16 as u32);
3331
3332                        let mut typ = sz.wrapping_sub(1) & 0x3;
3333                        let mut r_mode_op = 0b00111;
3334
3335                        if (op0.as_::<Vec>().has_element_index()) {
3336                            // Special case.
3337                            if (!x
3338                                || !op0.as_::<Vec>().is_vec_d2()
3339                                || op0.as_::<Vec>().element_index() != 1)
3340                            {
3341                                self.last_error = Some(AsmError::InvalidInstruction);
3342                                return;
3343                            }
3344                            typ = 0b10;
3345                            r_mode_op = 0b01111;
3346                        } else {
3347                            // Must be scalar.
3348                            if (sz > 2) {
3349                                self.last_error = Some(AsmError::InvalidInstruction);
3350                                return;
3351                            }
3352
3353                            if (op0.as_::<Vec>().has_element_type()) {
3354                                self.last_error = Some(AsmError::InvalidInstruction);
3355                                return;
3356                            }
3357
3358                            if (op0.as_::<Vec>().is_vec32() && x) {
3359                                self.last_error = Some(AsmError::InvalidInstruction);
3360                                return;
3361                            }
3362
3363                            if (op0.as_::<Vec>().is_vec64() && !x) {
3364                                self.last_error = Some(AsmError::InvalidInstruction);
3365                                return;
3366                            }
3367                        }
3368
3369                        st.opcode.add_imm(x as u32, 31);
3370                        st.opcode.add_imm(typ, 22);
3371                        st.opcode.add_imm(r_mode_op, 16);
3372                        emit_rd0_rn5!();
3373                    }
3374
3375                    if check_signature!(op0, op1) {
3376                        let sz = (op0.as_::<Reg>().reg_type() as u32)
3377                            .wrapping_sub(RegType::Vec16 as u32);
3378                        if sz > 2 {
3379                            self.last_error = Some(AsmError::InvalidInstruction);
3380                            return;
3381                        }
3382
3383                        if op0.as_::<Vec>().has_element_type() {
3384                            self.last_error = Some(AsmError::InvalidInstruction);
3385                            return;
3386                        }
3387
3388                        let typ = sz.wrapping_sub(1) & 0x3;
3389                        st.opcode.reset(0b00011110001000000100000000000000);
3390                        st.opcode.add_imm(typ, 22);
3391                        emit_rd0_rn5!();
3392                    }
3393                }
3394
3395                if isign4 == enc_ops!(Reg, Imm) {
3396                    if op0.as_::<Reg>().is_vec() {
3397                        let fp_value = if op1.as_::<Imm>().is_double() {
3398                            op1.as_::<Imm>().value_f64()
3399                        } else if op1.as_::<Imm>().is_int32() {
3400                            op1.as_::<Imm>().value_as::<i32>() as f64
3401                        } else {
3402                            self.last_error = Some(AsmError::InvalidOperand);
3403                            return;
3404                        };
3405
3406                        if !is_fp64_imm8(fp_value.to_bits()) {
3407                            self.last_error = Some(AsmError::InvalidOperand);
3408                            return;
3409                        }
3410
3411                        let imm8 = encode_fp64_to_imm8(fp_value.to_bits());
3412
3413                        if !op0.as_::<Vec>().has_element_type() {
3414                            let sz = (op0.as_::<Reg>().reg_type() as u32)
3415                                .wrapping_sub(RegType::Vec16 as u32);
3416                            let typ = sz.wrapping_sub(1) & 0x3;
3417                            if sz > 2 {
3418                                self.last_error = Some(AsmError::InvalidInstruction);
3419                                return;
3420                            }
3421
3422                            st.opcode.reset(0b00011110001000000001000000000000);
3423                            st.opcode.add_imm(typ, 22);
3424                            st.opcode.add_imm(imm8, 13);
3425                            emit_rd0!();
3426                        } else {
3427                            let q = (op0.as_::<Reg>().reg_type() as u32)
3428                                .wrapping_sub(RegType::Vec64 as u32);
3429                            let sz = (op0.as_::<Vec>().element_type() as u32)
3430                                .wrapping_sub(VecElementType::H as u32);
3431
3432                            if q > 1 || sz > 2 {
3433                                self.last_error = Some(AsmError::InvalidInstruction);
3434                                return;
3435                            }
3436
3437                            const SZ_BITS_TABLE: [u32; 3] = [1 << 11, 0, 1 << 29];
3438                            st.opcode.reset(0b00001111000000001111010000000000);
3439                            st.opcode ^= SZ_BITS_TABLE[sz as usize];
3440                            st.opcode.add_imm(q, 30);
3441                            st.opcode.add_imm(imm8 >> 5, 16);
3442                            st.opcode.add_imm(imm8 & 31, 5);
3443                            emit_rd0!();
3444                        }
3445                    }
3446                }
3447            }
3448
3449            Encoding::FSimdPair => {
3450                let op_data = &F_SIMD_PAIR[encoding_index];
3451
3452                if isign4 == enc_ops!(Reg, Reg) {
3453                    // This operation is only defined for:
3454                    //   hD, vS.2h (16-bit)
3455                    //   sD, vS.2s (32-bit)
3456                    //   dD, vS.2d (64-bit)
3457                    let sz =
3458                        (op0.as_::<Reg>().reg_type() as u32).wrapping_sub(RegType::Vec16 as u32);
3459                    if sz > 2 {
3460                        self.last_error = Some(AsmError::InvalidInstruction);
3461                        return;
3462                    }
3463
3464                    const SZ_SIGNATURES: [u32; 3] = [
3465                        A64VecS::SIGNATURE | (Vec::SIGNATURE_ELEMENT_H as u32),
3466                        A64VecD::SIGNATURE | (Vec::SIGNATURE_ELEMENT_S as u32),
3467                        A64VecQ::SIGNATURE | (Vec::SIGNATURE_ELEMENT_D as u32),
3468                    ];
3469
3470                    if op0.signature().bits() != SZ_SIGNATURES[sz as usize] {
3471                        self.last_error = Some(AsmError::InvalidInstruction);
3472                        return;
3473                    }
3474
3475                    const SZ_BITS_TABLE: [u32; 3] = [1 << 29, 0, 1 << 22];
3476
3477                    st.opcode.reset(op_data.scalar_op());
3478                    st.opcode ^= SZ_BITS_TABLE[sz as usize];
3479                    emit_rd0_rn5!();
3480                }
3481
3482                if isign4 == enc_ops!(Reg, Reg, Reg) {
3483                    if !check_signature!(op0, op1, op2) {
3484                        self.last_error = Some(AsmError::InvalidInstruction);
3485                        return;
3486                    }
3487
3488                    let q =
3489                        (op0.as_::<Reg>().reg_type() as u32).wrapping_sub(RegType::Vec64 as u32);
3490                    if q > 1 {
3491                        self.last_error = Some(AsmError::InvalidInstruction);
3492                        return;
3493                    }
3494
3495                    const SZ_BITS_TABLE: [u32; 3] =
3496                        [(1 << 22) | (1 << 21) | (1 << 15) | (1 << 14), 0, 1 << 22];
3497                    st.opcode.reset(op_data.scalar_op());
3498                    st.opcode ^= SZ_BITS_TABLE[q as usize];
3499                    st.opcode.add_imm(q, 30);
3500                    emit_rd0_rn5_rm16!();
3501                }
3502            }
3503
3504            Encoding::ISimdSV => {
3505                let op_data = &I_SIMD_SV[encoding_index];
3506
3507                if isign4 == enc_ops!(Reg, Reg) {
3508                    let l = (inst_flags & InstFlag::Long as u16) != 0;
3509                    if (op0.as_::<Vec>().reg_type() as u32).wrapping_sub(RegType::Vec8 as u32)
3510                        != (op1.as_::<Vec>().element_type() as u32)
3511                            .wrapping_sub(VecElementType::B as u32)
3512                            .wrapping_add(l as u32)
3513                    {
3514                        self.last_error = Some(AsmError::InvalidInstruction);
3515                        return;
3516                    }
3517                    let size_op = element_type_to_size_op(
3518                        op_data.vec_op_type,
3519                        op1.as_::<Reg>().reg_type(),
3520                        op1.as_::<Vec>().element_type(),
3521                    );
3522
3523                    if !size_op.is_valid() {
3524                        self.last_error = Some(AsmError::InvalidInstruction);
3525                        return;
3526                    }
3527
3528                    st.opcode.reset(op_data.opcode());
3529                    st.opcode.add_imm(size_op.q(), 30);
3530                    st.opcode.add_imm(size_op.size(), 22);
3531                    emit_rd0_rn5!();
3532                }
3533            }
3534
3535            Encoding::ISimdVV => {
3536                let op_data = &I_SIMD_VV[encoding_index];
3537
3538                if isign4 == enc_ops!(Reg, Reg) {
3539                    let sop = significant_simd_op(op0, op1, inst_flags as u32);
3540                    if !match_signature2(op0, op1, inst_flags as u32) {
3541                        self.last_error = Some(AsmError::InvalidInstruction);
3542                        return;
3543                    }
3544
3545                    let size_op = element_type_to_size_op(
3546                        op_data.vec_op_type,
3547                        sop.as_::<Reg>().reg_type(),
3548                        sop.as_::<Vec>().element_type(),
3549                    );
3550                    if !size_op.is_valid() {
3551                        self.last_error = Some(AsmError::InvalidInstruction);
3552                        return;
3553                    }
3554
3555                    st.opcode.reset(op_data.opcode());
3556                    st.opcode.add_imm(size_op.qs(), 30);
3557                    st.opcode.add_imm(size_op.scalar(), 28);
3558                    st.opcode.add_imm(size_op.size(), 22);
3559                    emit_rd0_rn5!();
3560                }
3561            }
3562
3563            Encoding::ISimdVVx => {
3564                let op_data = &I_SIMD_VVX[encoding_index];
3565                if isign4 == enc_ops!(Reg, Reg) {
3566                    if op0.signature().bits() != op_data.op0_signature
3567                        || op1.signature().bits() != op_data.op1_signature
3568                    {
3569                        self.last_error = Some(AsmError::InvalidInstruction);
3570                        return;
3571                    }
3572                    st.opcode.reset(op_data.opcode());
3573                    emit_rd0_rn5!();
3574                }
3575            }
3576
3577            Encoding::ISimdVVV => {
3578                let op_data = &I_SIMD_VVV[encoding_index];
3579
3580                if isign4 == enc_ops!(Reg, Reg, Reg) {
3581                    let sop = significant_simd_op(op0, op1, inst_flags as u32);
3582                    if !match_signature3(op0, op1, op2, inst_flags as u32) {
3583                        self.last_error = Some(AsmError::InvalidInstruction);
3584                        return;
3585                    }
3586
3587                    let size_op = element_type_to_size_op(
3588                        op_data.vec_op_type,
3589                        sop.as_::<Reg>().reg_type(),
3590                        sop.as_::<Vec>().element_type(),
3591                    );
3592                    if !size_op.is_valid() {
3593                        self.last_error = Some(AsmError::InvalidInstruction);
3594                        return;
3595                    }
3596
3597                    st.opcode.reset(op_data.opcode());
3598                    st.opcode.add_imm(size_op.qs(), 30);
3599                    st.opcode.add_imm(size_op.scalar(), 28);
3600                    st.opcode.add_imm(size_op.size(), 22);
3601                    emit_rd0_rn5_rm16!();
3602                }
3603            }
3604
3605            Encoding::ISimdVVVx => {
3606                let op_data = &I_SIMD_VVVX[encoding_index];
3607
3608                if isign4 == enc_ops!(Reg, Reg, Reg) {
3609                    if op0.signature().bits() != op_data.op0_signature
3610                        || op1.signature().bits() != op_data.op1_signature
3611                        || op2.signature().bits() != op_data.op2_signature
3612                    {
3613                        self.last_error = Some(AsmError::InvalidInstruction);
3614                        return;
3615                    }
3616
3617                    st.opcode.reset(op_data.opcode());
3618                    emit_rd0_rn5_rm16!();
3619                }
3620            }
3621
3622            Encoding::ISimdWWV => {
3623                let op_data = &I_SIMD_WWV[encoding_index];
3624                if isign4 == enc_ops!(Reg, Reg, Reg) {
3625                    let size_op = element_type_to_size_op(
3626                        op_data.vec_op_type,
3627                        op2.as_::<Reg>().reg_type(),
3628                        op2.as_::<Vec>().element_type(),
3629                    );
3630                    if !size_op.is_valid() {
3631                        self.last_error = Some(AsmError::InvalidInstruction);
3632                        return;
3633                    }
3634                    if !check_signature!(op0, op1)
3635                        || !op0.as_::<Reg>().is_vec128()
3636                        || (op0.as_::<Vec>().element_type() as u32)
3637                            != (op2.as_::<Vec>().element_type() as u32 + 1)
3638                    {
3639                        self.last_error = Some(AsmError::InvalidInstruction);
3640                        return;
3641                    }
3642                    st.opcode.reset(op_data.opcode());
3643                    st.opcode.add_imm(size_op.qs(), 30);
3644                    st.opcode.add_imm(size_op.scalar(), 28);
3645                    st.opcode.add_imm(size_op.size(), 22);
3646                    emit_rd0_rn5_rm16!();
3647                }
3648            }
3649
3650            Encoding::ISimdVVVe => {
3651                let op_data = &I_SIMD_VVVE[encoding_index];
3652                if isign4 == enc_ops!(Reg, Reg, Reg) {
3653                    let sop = significant_simd_op(op0, op1, inst_flags as u32);
3654                    if !match_signature2(op0, op1, inst_flags as u32) {
3655                        self.last_error = Some(AsmError::InvalidInstruction);
3656                        return;
3657                    }
3658                    if !op2.as_::<Vec>().has_element_index() {
3659                        let size_op = element_type_to_size_op(
3660                            op_data.regular_vec_type,
3661                            sop.as_::<Reg>().reg_type(),
3662                            sop.as_::<Vec>().element_type(),
3663                        );
3664                        if !size_op.is_valid() {
3665                            self.last_error = Some(AsmError::InvalidInstruction);
3666                            return;
3667                        }
3668                        if !check_signature!(op1, op2) {
3669                            self.last_error = Some(AsmError::InvalidInstruction);
3670                            return;
3671                        }
3672                        st.opcode.reset((op_data.regular_op as u32) << 10);
3673                        st.opcode.add_imm(size_op.qs(), 30);
3674                        st.opcode.add_imm(size_op.scalar(), 28);
3675                        st.opcode.add_imm(size_op.size(), 22);
3676                        emit_rd0_rn5_rm16!();
3677                    } else {
3678                        let size_op = element_type_to_size_op(
3679                            op_data.element_vec_type,
3680                            sop.as_::<Reg>().reg_type(),
3681                            sop.as_::<Vec>().element_type(),
3682                        );
3683                        if !size_op.is_valid() {
3684                            self.last_error = Some(AsmError::InvalidInstruction);
3685                            return;
3686                        }
3687                        let element_index = op2.as_::<Vec>().element_index();
3688                        let mut lmh = LMHImm {
3689                            lm: 0,
3690                            h: 0,
3691                            max_rm_id: 0,
3692                        };
3693                        if !encode_lmh(size_op.size(), element_index, &mut lmh) {
3694                            self.last_error = Some(AsmError::InvalidOperand);
3695                            return;
3696                        }
3697                        if op2.as_::<Reg>().id() > lmh.max_rm_id {
3698                            self.last_error = Some(AsmError::InvalidOperand);
3699                            return;
3700                        }
3701                        st.opcode.reset((op_data.element_op as u32) << 10);
3702                        st.opcode.add_imm(size_op.q(), 30);
3703                        st.opcode.add_imm(size_op.size(), 22);
3704                        st.opcode.add_imm(lmh.lm, 20);
3705                        st.opcode.add_imm(lmh.h, 11);
3706                        emit_rd0_rn5_rm16!();
3707                    }
3708                }
3709            }
3710
3711            Encoding::ISimdVVVI => {
3712                let op_data = &I_SIMD_VVVI[encoding_index];
3713                if isign4 == enc_ops!(Reg, Reg, Reg, Imm) {
3714                    let sop = significant_simd_op(op0, op1, inst_flags as u32);
3715                    if !match_signature3(op0, op1, op2, inst_flags as u32) {
3716                        self.last_error = Some(AsmError::InvalidInstruction);
3717                        return;
3718                    }
3719                    let size_op = element_type_to_size_op(
3720                        op_data.vec_op_type,
3721                        sop.as_::<Reg>().reg_type(),
3722                        sop.as_::<Vec>().element_type(),
3723                    );
3724                    if !size_op.is_valid() {
3725                        self.last_error = Some(AsmError::InvalidInstruction);
3726                        return;
3727                    }
3728                    let imm_value = op3.as_::<Imm>().value() as u64;
3729                    let mut imm_size = op_data.imm_size;
3730                    if op_data.imm64_has_one_bit_less != 0 && size_op.q() == 0 {
3731                        imm_size -= 1;
3732                    }
3733                    let imm_max = 1u64 << imm_size;
3734                    if imm_value >= imm_max {
3735                        self.last_error = Some(AsmError::InvalidImmediate);
3736                        return;
3737                    }
3738                    st.opcode.reset(op_data.opcode());
3739                    st.opcode.add_imm(size_op.qs(), 30);
3740                    st.opcode.add_imm(size_op.scalar(), 28);
3741                    st.opcode.add_imm(size_op.size(), 22);
3742                    st.opcode.add_imm(imm_value as u32, op_data.imm_shift);
3743                    emit_rd0_rn5_rm16!();
3744                }
3745            }
3746
3747            Encoding::ISimdVVVV => {
3748                let op_data = &I_SIMD_VVVV[encoding_index];
3749                if isign4 == enc_ops!(Reg, Reg, Reg, Reg) {
3750                    let sop = significant_simd_op(op0, op1, inst_flags as u32);
3751                    if !match_signature4(op0, op1, op2, op3, inst_flags as u32) {
3752                        self.last_error = Some(AsmError::InvalidInstruction);
3753                        return;
3754                    }
3755                    let size_op = element_type_to_size_op(
3756                        op_data.vec_op_type,
3757                        sop.as_::<Reg>().reg_type(),
3758                        sop.as_::<Vec>().element_type(),
3759                    );
3760                    if !size_op.is_valid() {
3761                        self.last_error = Some(AsmError::InvalidInstruction);
3762                        return;
3763                    }
3764                    st.opcode.reset((op_data.opcode as u32) << 10);
3765                    st.opcode.add_imm(size_op.qs(), 30);
3766                    st.opcode.add_imm(size_op.scalar(), 28);
3767                    st.opcode.add_imm(size_op.size(), 22);
3768                    emit_rd0_rn5_rm16_ra10!();
3769                }
3770            }
3771
3772            Encoding::ISimdVVVVx => {
3773                let op_data = &I_SIMD_VVVVX[encoding_index];
3774                if isign4 == enc_ops!(Reg, Reg, Reg, Reg) {
3775                    if op0.signature().bits() != op_data.op0_signature
3776                        || op1.signature().bits() != op_data.op1_signature
3777                        || op2.signature().bits() != op_data.op2_signature
3778                        || op3.signature().bits() != op_data.op3_signature
3779                    {
3780                        self.last_error = Some(AsmError::InvalidInstruction);
3781                        return;
3782                    }
3783                    st.opcode.reset((op_data.opcode as u32) << 10);
3784                    emit_rd0_rn5_rm16_ra10!();
3785                }
3786            }
3787
3788            Encoding::ISimdPair => {
3789                let op_data = &I_SIMD_PAIR[encoding_index];
3790                if isign4 == enc_ops!(Reg, Reg) && op_data.opcode2 != 0 {
3791                    if op0.as_::<Vec>().is_vec_d1() && op1.as_::<Vec>().is_vec_d2() {
3792                        st.opcode.reset((op_data.opcode2 as u32) << 10);
3793                        st.opcode.add_imm(0x3, 22);
3794                        emit_rd0_rn5!();
3795                    }
3796                }
3797                if isign4 == enc_ops!(Reg, Reg, Reg) {
3798                    if !match_signature3(op0, op1, op2, inst_flags as u32) {
3799                        self.last_error = Some(AsmError::InvalidInstruction);
3800                        return;
3801                    }
3802                    let size_op = element_type_to_size_op(
3803                        op_data.op_type3,
3804                        op0.as_::<Reg>().reg_type(),
3805                        op0.as_::<Vec>().element_type(),
3806                    );
3807                    if !size_op.is_valid() {
3808                        self.last_error = Some(AsmError::InvalidInstruction);
3809                        return;
3810                    }
3811                    st.opcode.reset((op_data.opcode3 as u32) << 10);
3812                    st.opcode.add_imm(size_op.qs(), 30);
3813                    st.opcode.add_imm(size_op.scalar(), 28);
3814                    st.opcode.add_imm(size_op.size(), 22);
3815                    emit_rd0_rn5_rm16!();
3816                }
3817            }
3818
3819            Encoding::SimdBicOrr => {
3820                let op_data = &SIMD_BIC_ORR[encoding_index];
3821                if isign4 == enc_ops!(Reg, Reg, Reg) {
3822                    if !match_signature3(op0, op1, op2, inst_flags as u32) {
3823                        self.last_error = Some(AsmError::InvalidInstruction);
3824                        return;
3825                    }
3826                    let size_op = element_type_to_size_op(
3827                        0, // kVO_V_B
3828                        op0.as_::<Reg>().reg_type(),
3829                        op0.as_::<Vec>().element_type(),
3830                    );
3831                    if !size_op.is_valid() {
3832                        self.last_error = Some(AsmError::InvalidInstruction);
3833                        return;
3834                    }
3835                    st.opcode.reset((op_data.register_op as u32) << 10);
3836                    st.opcode.add_imm(size_op.q(), 30);
3837                    emit_rd0_rn5_rm16!();
3838                }
3839                if isign4 == enc_ops!(Reg, Imm) || isign4 == enc_ops!(Reg, Imm, Imm) {
3840                    let size_op = element_type_to_size_op(
3841                        5, // kVO_V_HS
3842                        op0.as_::<Reg>().reg_type(),
3843                        op0.as_::<Vec>().element_type(),
3844                    );
3845                    if !size_op.is_valid() {
3846                        self.last_error = Some(AsmError::InvalidInstruction);
3847                        return;
3848                    }
3849                    if op1.as_::<Imm>().value() as u64 > 0xFFFFFFFF {
3850                        self.last_error = Some(AsmError::InvalidImmediate);
3851                        return;
3852                    }
3853                    let mut imm = op1.as_::<Imm>().value() as u32;
3854                    let mut shift = 0u32;
3855                    let max_shift = (8u32 << size_op.size()) - 8u32;
3856                    if isign4 == enc_ops!(Reg, Imm, Imm) {
3857                        if op2.as_::<Imm>().predicate() != ShiftOp::LSL as u32 {
3858                            self.last_error = Some(AsmError::InvalidImmediate);
3859                            return;
3860                        }
3861                        if imm > 0xFF || op2.as_::<Imm>().value() as u64 > max_shift as u64 {
3862                            self.last_error = Some(AsmError::InvalidImmediate);
3863                            return;
3864                        }
3865                        shift = op2.as_::<Imm>().value() as u32;
3866                        if (shift & 0x7) != 0 {
3867                            self.last_error = Some(AsmError::InvalidImmediate);
3868                            return;
3869                        }
3870                    } else if imm != 0 {
3871                        shift = imm.trailing_zeros() & !0x7;
3872                        imm >>= shift;
3873                        if imm > 0xFF || shift > max_shift {
3874                            self.last_error = Some(AsmError::InvalidImmediate);
3875                            return;
3876                        }
3877                    }
3878                    let mut cmode = 0x1 | ((shift / 8) << 1);
3879                    if size_op.size() == 1 {
3880                        cmode |= 1 << 3;
3881                    }
3882                    let abc = (imm >> 5) & 0x7;
3883                    let defgh = imm & 0x1F;
3884                    st.opcode.reset((op_data.immediate_op as u32) << 10);
3885                    st.opcode.add_imm(size_op.q(), 30);
3886                    st.opcode.add_imm(abc, 16);
3887                    st.opcode.add_imm(cmode, 12);
3888                    st.opcode.add_imm(defgh, 5);
3889                    emit_rd0!();
3890                }
3891            }
3892
3893            Encoding::SimdCmp => {
3894                let op_data = &SIMD_CMP[encoding_index];
3895
3896                if isign4 == enc_ops!(Reg, Reg, Reg) && op_data.register_op != 0 {
3897                    if !match_signature3(op0, op1, op2, inst_flags as u32) {
3898                        self.last_error = Some(AsmError::InvalidInstruction);
3899                        return;
3900                    }
3901
3902                    let size_op = element_type_to_size_op(
3903                        op_data.vec_op_type,
3904                        op0.as_::<Reg>().reg_type(),
3905                        op0.as_::<Vec>().element_type(),
3906                    );
3907                    if !size_op.is_valid() {
3908                        self.last_error = Some(AsmError::InvalidInstruction);
3909                        return;
3910                    }
3911
3912                    st.opcode.reset((op_data.register_op as u32) << 10);
3913                    st.opcode.add_imm(size_op.qs(), 30);
3914                    st.opcode.add_imm(size_op.scalar(), 28);
3915                    st.opcode.add_imm(size_op.size(), 22);
3916                    emit_rd0_rn5_rm16!();
3917                }
3918
3919                if isign4 == enc_ops!(Reg, Reg, Imm) && op_data.zero_op != 0 {
3920                    if !match_signature2(op0, op1, inst_flags as u32) {
3921                        self.last_error = Some(AsmError::InvalidInstruction);
3922                        return;
3923                    }
3924
3925                    if op2.as_::<Imm>().value() != 0 {
3926                        self.last_error = Some(AsmError::InvalidImmediate);
3927                        return;
3928                    }
3929
3930                    let size_op = element_type_to_size_op(
3931                        op_data.vec_op_type,
3932                        op0.as_::<Reg>().reg_type(),
3933                        op0.as_::<Vec>().element_type(),
3934                    );
3935                    if !size_op.is_valid() {
3936                        self.last_error = Some(AsmError::InvalidInstruction);
3937                        return;
3938                    }
3939
3940                    st.opcode.reset((op_data.zero_op as u32) << 10);
3941                    st.opcode.add_imm(size_op.qs(), 30);
3942                    st.opcode.add_imm(size_op.scalar(), 28);
3943                    st.opcode.add_imm(size_op.size(), 22);
3944                    emit_rd0_rn5!();
3945                }
3946            }
3947
3948            Encoding::SimdDot => {
3949                let op_data = &SIMD_DOT[encoding_index];
3950
3951                if isign4 == enc_ops!(Reg, Reg, Reg) {
3952                    let q =
3953                        (op0.as_::<Reg>().reg_type() as u32).wrapping_sub(RegType::Vec64 as u32);
3954                    let size = 2u32;
3955
3956                    if q > 1 {
3957                        self.last_error = Some(AsmError::InvalidInstruction);
3958                        return;
3959                    }
3960
3961                    if !op2.as_::<Vec>().has_element_index() {
3962                        if op_data.vector_op == 0 {
3963                            self.last_error = Some(AsmError::InvalidInstruction);
3964                            return;
3965                        }
3966
3967                        if op0.as_::<Reg>().reg_type() != op1.as_::<Reg>().reg_type()
3968                            || op1.as_::<Reg>().reg_type() != op2.as_::<Reg>().reg_type()
3969                        {
3970                            self.last_error = Some(AsmError::InvalidInstruction);
3971                            return;
3972                        }
3973
3974                        if op0.as_::<Vec>().element_type() as u32 != op_data.ta as u32
3975                            || op1.as_::<Vec>().element_type() as u32 != op_data.tb as u32
3976                            || op2.as_::<Vec>().element_type() as u32 != op_data.tb as u32
3977                        {
3978                            self.last_error = Some(AsmError::InvalidInstruction);
3979                            return;
3980                        }
3981
3982                        st.opcode.reset((op_data.vector_op as u32) << 10);
3983                        st.opcode.add_imm(q, 30);
3984                        emit_rd0_rn5_rm16!();
3985                    } else {
3986                        if op_data.element_op == 0 {
3987                            self.last_error = Some(AsmError::InvalidInstruction);
3988                            return;
3989                        }
3990
3991                        if op0.as_::<Reg>().reg_type() != op1.as_::<Reg>().reg_type()
3992                            || !op2.as_::<Reg>().is_vec128()
3993                        {
3994                            self.last_error = Some(AsmError::InvalidInstruction);
3995                            return;
3996                        }
3997
3998                        if op0.as_::<Vec>().element_type() as u32 != op_data.ta as u32
3999                            || op1.as_::<Vec>().element_type() as u32 != op_data.tb as u32
4000                            || op2.as_::<Vec>().element_type() as u32 != op_data.t_element as u32
4001                        {
4002                            self.last_error = Some(AsmError::InvalidInstruction);
4003                            return;
4004                        }
4005
4006                        let element_index = op2.as_::<Vec>().element_index();
4007                        let mut lmh = LMHImm {
4008                            lm: 0,
4009                            h: 0,
4010                            max_rm_id: 0,
4011                        };
4012                        if !encode_lmh(size, element_index, &mut lmh) {
4013                            self.last_error = Some(AsmError::InvalidOperand);
4014                            return;
4015                        }
4016
4017                        if op2.as_::<Reg>().id() > lmh.max_rm_id {
4018                            self.last_error = Some(AsmError::InvalidOperand);
4019                            return;
4020                        }
4021
4022                        st.opcode.reset((op_data.element_op as u32) << 10);
4023                        st.opcode.add_imm(q, 30);
4024                        st.opcode.add_imm(lmh.lm, 20);
4025                        st.opcode.add_imm(lmh.h, 11);
4026                        emit_rd0_rn5_rm16!();
4027                    }
4028                }
4029            }
4030
4031            Encoding::SimdDup => {
4032                simd_dup!();
4033            }
4034
4035            Encoding::SimdIns => {
4036                simd_insn!();
4037            }
4038
4039            Encoding::SimdMov => {
4040                if isign4 == enc_ops!(Reg, Reg) {
4041                    if op0.as_::<Reg>().is_vec() && op1.as_::<Reg>().is_vec() {
4042                        // INS v.x[index], v.x[index].
4043                        if op0.as_::<Vec>().has_element_index()
4044                            && op1.as_::<Vec>().has_element_index()
4045                        {
4046                            // SimdIns encoding.
4047
4048                            encoding = Encoding::SimdIns;
4049                            // Recurse to SimdIns.
4050                            simd_insn!();
4051                            return;
4052                        }
4053                        // DUP {b|h|s|d}, v.{b|h|s|d}[index].
4054                        if op1.as_::<Vec>().has_element_index() {
4055                            encoding = Encoding::SimdDup;
4056                            simd_dup!();
4057                            return;
4058                        }
4059                        if !check_signature!(op0, op1) {
4060                            self.last_error = Some(AsmError::InvalidInstruction);
4061                            return;
4062                        }
4063                        let q = (op0.as_::<Reg>().reg_type() as u32)
4064                            .wrapping_sub(RegType::Vec64 as u32);
4065                        if q > 1 {
4066                            self.last_error = Some(AsmError::InvalidInstruction);
4067                            return;
4068                        }
4069                        st.opcode.reset(0b0000111010100000000111 << 10);
4070                        st.opcode.add_imm(q, 30);
4071                        st.opcode.add_reg(op1.id(), 16);
4072                        emit_rd0_rn5!();
4073                        return;
4074                    }
4075                    if op0.as_::<Reg>().is_vec() && op1.as_::<Reg>().is_gp() {
4076                        // INS v.x[index], Rn.
4077                        if op0.as_::<Vec>().has_element_index() {
4078                            encoding = Encoding::SimdIns;
4079                            simd_insn!();
4080                            return;
4081                        }
4082                        self.last_error = Some(AsmError::InvalidInstruction);
4083                        return;
4084                    }
4085                    if op0.as_::<Reg>().is_gp() && op1.as_::<Reg>().is_vec() {
4086                        // UMOV Rd, V.{s|d}[index].
4087                        encoding_index = 1;
4088                        encoding = Encoding::SimdSmovUmov;
4089                        simd_umov!();
4090                        return;
4091                    }
4092                }
4093            }
4094
4095            Encoding::SimdMoviMvni => {
4096                let op_data = &SIMD_MOVI_MVNI[encoding_index];
4097                if isign4 == enc_ops!(Reg, Imm) || isign4 == enc_ops!(Reg, Imm, Imm) {
4098                    let mut size_op = element_type_to_size_op(
4099                        20,
4100                        op0.as_::<Reg>().reg_type(),
4101                        op0.as_::<Vec>().element_type(),
4102                    );
4103                    if !size_op.is_valid() {
4104                        self.last_error = Some(AsmError::InvalidInstruction);
4105                        return;
4106                    }
4107                    let mut imm64 = op1.as_::<Imm>().value() as u64;
4108                    let mut imm8 = 0u32;
4109                    let mut cmode = 0u32;
4110                    let inverted = op_data.inverted;
4111                    let mut op = 0u32;
4112                    let mut shift = 0u32;
4113                    let mut shift_op = ShiftOp::LSL as u32;
4114                    if size_op.size() == 3 {
4115                        if op2.is_imm() && op2.as_::<Imm>().value() != 0 {
4116                            self.last_error = Some(AsmError::InvalidImmediate);
4117                            return;
4118                        }
4119                        if is_byte_mask_imm(imm64) {
4120                            imm8 = encode_imm64_byte_mask_to_imm8(imm64);
4121                        } else {
4122                            if (imm64 >> 32) == (imm64 & 0xFFFFFFFF) {
4123                                imm64 &= 0xFFFFFFFF;
4124                                size_op.decrement_size();
4125                            } else {
4126                                self.last_error = Some(AsmError::InvalidImmediate);
4127                                return;
4128                            }
4129                        }
4130                    }
4131                    if size_op.size() < 3 {
4132                        if imm64 > 0xFFFFFFFF {
4133                            self.last_error = Some(AsmError::InvalidImmediate);
4134                            return;
4135                        }
4136                        imm8 = imm64 as u32;
4137                        if size_op.size() == 2 {
4138                            if (imm8 >> 16) == (imm8 & 0xFFFF) {
4139                                imm8 >>= 16;
4140                                size_op.decrement_size();
4141                            }
4142                        }
4143                        if size_op.size() == 1 {
4144                            if imm8 > 0xFFFF {
4145                                self.last_error = Some(AsmError::InvalidImmediate);
4146                                return;
4147                            }
4148                            if (imm8 >> 8) == (imm8 & 0xFF) {
4149                                imm8 >>= 8;
4150                                size_op.decrement_size();
4151                            }
4152                        }
4153                        let max_shift = (8u32 << size_op.size()) - 8u32;
4154                        if op2.is_imm() {
4155                            if imm8 > 0xFF || op2.as_::<Imm>().value() as u64 > max_shift as u64 {
4156                                self.last_error = Some(AsmError::InvalidImmediate);
4157                                return;
4158                            }
4159                            shift = op2.as_::<Imm>().value() as u32;
4160                            shift_op = op2.as_::<Imm>().predicate();
4161                        } else if imm8 != 0 {
4162                            shift = imm8.trailing_zeros() & !0x7;
4163                            imm8 >>= shift;
4164                            if imm8 > 0xFF || shift > max_shift {
4165                                self.last_error = Some(AsmError::InvalidImmediate);
4166                                return;
4167                            }
4168                        }
4169                        if (shift & 0x7) != 0 {
4170                            self.last_error = Some(AsmError::InvalidImmediate);
4171                            return;
4172                        }
4173                    }
4174                    shift /= 8;
4175                    match size_op.size() {
4176                        0 => {
4177                            if shift_op != ShiftOp::LSL as u32 {
4178                                self.last_error = Some(AsmError::InvalidImmediate);
4179                                return;
4180                            }
4181                            if inverted != 0 {
4182                                imm8 = !imm8 & 0xFF;
4183                            }
4184                            cmode = B!(3) | B!(2) | B!(1);
4185                        }
4186                        1 => {
4187                            if shift_op != ShiftOp::LSL as u32 {
4188                                self.last_error = Some(AsmError::InvalidImmediate);
4189                                return;
4190                            }
4191                            cmode = B!(3) | (shift << 1);
4192                            op = inverted;
4193                        }
4194                        2 => {
4195                            if shift_op == ShiftOp::LSL as u32 {
4196                                cmode = shift << 1;
4197                            } else if shift_op == ShiftOp::MSL as u32 {
4198                                if shift == 0 || shift > 2 {
4199                                    self.last_error = Some(AsmError::InvalidImmediate);
4200                                    return;
4201                                }
4202                                cmode = B!(3) | B!(2) | (shift - 1);
4203                            } else {
4204                                self.last_error = Some(AsmError::InvalidImmediate);
4205                                return;
4206                            }
4207                            op = inverted;
4208                        }
4209                        3 => {
4210                            if inverted != 0 {
4211                                imm8 = !imm8 & 0xFF;
4212                            }
4213                            op = 1;
4214                            cmode = B!(3) | B!(2) | B!(1);
4215                        }
4216                        _ => {}
4217                    }
4218                    let abc = (imm8 >> 5) & 0x7;
4219                    let defgh = imm8 & 0x1F;
4220                    st.opcode.reset((op_data.opcode as u32) << 10);
4221                    st.opcode.add_imm(size_op.q(), 30);
4222                    st.opcode.add_imm(op, 29);
4223                    st.opcode.add_imm(abc, 16);
4224                    st.opcode.add_imm(cmode, 12);
4225                    st.opcode.add_imm(defgh, 5);
4226                    emit_rd0!();
4227                    return;
4228                }
4229            }
4230
4231            Encoding::SimdShift => {
4232                let op_data = &SIMD_SHIFT[encoding_index];
4233                let sop = significant_simd_op(op0, op1, inst_flags as u32);
4234                let size_op = element_type_to_size_op(
4235                    op_data.vec_op_type,
4236                    sop.as_::<Reg>().reg_type(),
4237                    sop.as_::<Vec>().element_type(),
4238                );
4239                if !size_op.is_valid() {
4240                    self.last_error = Some(AsmError::InvalidInstruction);
4241                    return;
4242                }
4243                if isign4 == enc_ops!(Reg, Reg, Imm) && op_data.immediate_op != 0 {
4244                    if !match_signature2(op0, op1, inst_flags as u32) {
4245                        self.last_error = Some(AsmError::InvalidInstruction);
4246                        return;
4247                    }
4248                    if op2.as_::<Imm>().value() as u64 > 63 {
4249                        self.last_error = Some(AsmError::InvalidImmediate);
4250                        return;
4251                    }
4252                    let lsb_shift = size_op.size() + 3;
4253                    let lsb_mask = (1u32 << lsb_shift) - 1;
4254                    let mut imm = op2.as_::<Imm>().value() as u32;
4255                    if op_data.inverted_imm != 0 {
4256                        if imm == 0 || imm > (1u32 << lsb_shift) {
4257                            self.last_error = Some(AsmError::InvalidImmediate);
4258                            return;
4259                        }
4260                        imm = (!imm + 1) & lsb_mask;
4261                    }
4262                    if imm > lsb_mask {
4263                        self.last_error = Some(AsmError::InvalidImmediate);
4264                        return;
4265                    }
4266                    imm |= 1u32 << lsb_shift;
4267                    st.opcode.reset((op_data.immediate_op as u32) << 10);
4268                    st.opcode.add_imm(size_op.qs(), 30);
4269                    st.opcode.add_imm(size_op.scalar(), 28);
4270                    st.opcode.add_imm(imm, 16);
4271                    emit_rd0_rn5!();
4272                    return;
4273                }
4274                if isign4 == enc_ops!(Reg, Reg, Reg) && op_data.register_op != 0 {
4275                    if !match_signature3(op0, op1, op2, inst_flags as u32) {
4276                        self.last_error = Some(AsmError::InvalidInstruction);
4277                        return;
4278                    }
4279                    st.opcode.reset((op_data.register_op as u32) << 10);
4280                    st.opcode.add_imm(size_op.qs(), 30);
4281                    st.opcode.add_imm(size_op.scalar(), 28);
4282                    st.opcode.add_imm(size_op.size(), 22);
4283                    emit_rd0_rn5_rm16!();
4284                    return;
4285                }
4286            }
4287
4288            Encoding::SimdShiftES => {
4289                let op_data = &SIMD_SHIFT_ES[encoding_index];
4290                if isign4 == enc_ops!(Reg, Reg, Imm) {
4291                    let size_op = element_type_to_size_op(
4292                        op_data.vec_op_type,
4293                        op1.as_::<Reg>().reg_type(),
4294                        op1.as_::<Vec>().element_type(),
4295                    );
4296                    if !size_op.is_valid() {
4297                        self.last_error = Some(AsmError::InvalidInstruction);
4298                        return;
4299                    }
4300                    if !match_signature2(op0, op1, inst_flags as u32) {
4301                        self.last_error = Some(AsmError::InvalidInstruction);
4302                        return;
4303                    }
4304                    let shift = op2.as_::<Imm>().value() as u64;
4305                    let shift_op = op2.as_::<Imm>().predicate();
4306                    if shift != (8u64 << size_op.size()) || shift_op != ShiftOp::LSL as u32 {
4307                        self.last_error = Some(AsmError::InvalidImmediate);
4308                        return;
4309                    }
4310                    st.opcode.reset((op_data.opcode as u32) << 10);
4311                    st.opcode.add_imm(size_op.q(), 30);
4312                    st.opcode.add_imm(size_op.size(), 22);
4313                    emit_rd0_rn5!();
4314                    return;
4315                }
4316            }
4317
4318            Encoding::SimdSm3tt => {
4319                let op_data = &SIMD_SM3TT[encoding_index];
4320                if isign4 == enc_ops!(Reg, Reg, Reg) {
4321                    if op0.as_::<Vec>().is_vec_s4()
4322                        && op1.as_::<Vec>().is_vec_s4()
4323                        && op2.as_::<Vec>().is_vec_s4()
4324                        && op2.as_::<Vec>().has_element_index()
4325                    {
4326                        let imm2 = op2.as_::<Vec>().element_index();
4327                        if imm2 > 3 {
4328                            self.last_error = Some(AsmError::InvalidOperand);
4329                            return;
4330                        }
4331                        st.opcode.reset((op_data.opcode as u32) << 10);
4332                        st.opcode.add_imm(imm2, 12);
4333                        emit_rd0_rn5_rm16!();
4334                        return;
4335                    }
4336                }
4337            }
4338
4339            Encoding::SimdSmovUmov => {
4340                simd_umov!();
4341            }
4342
4343            Encoding::SimdSxtlUxtl => {
4344                let op_data = &SIMD_SXTL_UXTL[encoding_index];
4345                if isign4 == enc_ops!(Reg, Reg) {
4346                    let size_op = element_type_to_size_op(
4347                        op_data.vec_op_type,
4348                        op1.as_::<Reg>().reg_type(),
4349                        op1.as_::<Vec>().element_type(),
4350                    );
4351                    if !size_op.is_valid() {
4352                        self.last_error = Some(AsmError::InvalidInstruction);
4353                        return;
4354                    }
4355                    if !match_signature2(op0, op1, inst_flags as u32) {
4356                        self.last_error = Some(AsmError::InvalidInstruction);
4357                        return;
4358                    }
4359                    st.opcode.reset((op_data.opcode as u32) << 10);
4360                    st.opcode.add_imm(size_op.q(), 30);
4361                    st.opcode.add_imm(1u32, size_op.size() + 19);
4362                    emit_rd0_rn5!();
4363                    return;
4364                }
4365            }
4366
4367            Encoding::SimdTblTbx => {
4368                let op_data = &SIMD_TBL_TBX[encoding_index];
4369                if isign4 == enc_ops!(Reg, Reg, Reg) || isign4 == enc_ops!(Reg, Reg, Reg, Reg) {
4370                    st.opcode.reset((op_data.opcode as u32) << 10);
4371
4372                    let q =
4373                        (op0.as_::<Reg>().reg_type() as u32).wrapping_sub(RegType::Vec64 as u32);
4374                    if q > 1 || op0.as_::<Vec>().has_element_index() {
4375                        self.last_error = Some(AsmError::InvalidInstruction);
4376                        return;
4377                    }
4378                    if !op1.as_::<Vec>().is_vec_b16() || op1.as_::<Vec>().has_element_index() {
4379                        self.last_error = Some(AsmError::InvalidInstruction);
4380                        return;
4381                    }
4382                    let len =
4383                        (!op3.is_none() as u32) + (!op4.is_none() as u32) + (!op5.is_none() as u32);
4384                    st.opcode.add_imm(q, 30);
4385                    st.opcode.add_imm(len, 13);
4386
4387                    match len {
4388                        0 => {
4389                            if !check_signature!(op0, op2) {
4390                                self.last_error = Some(AsmError::InvalidInstruction);
4391                                return;
4392                            }
4393                            if op2.id() > 31 {
4394                                self.last_error = Some(AsmError::InvalidOperand);
4395                                return;
4396                            }
4397                            st.opcode.add_reg(op2.id(), 16);
4398                            emit_rd0_rn5!();
4399                            return;
4400                        }
4401                        1 => {
4402                            if !check_signature!(op0, op3) {
4403                                self.last_error = Some(AsmError::InvalidInstruction);
4404                                return;
4405                            }
4406                            if op3.id() > 31 {
4407                                self.last_error = Some(AsmError::InvalidOperand);
4408                                return;
4409                            }
4410                            st.opcode.add_reg(op3.id(), 16);
4411                            emit_rd0_rn5!();
4412                            return;
4413                        }
4414                        2 => {
4415                            if !check_signature!(op0, op4) {
4416                                self.last_error = Some(AsmError::InvalidInstruction);
4417                                return;
4418                            }
4419                            if op4.id() > 31 {
4420                                self.last_error = Some(AsmError::InvalidOperand);
4421                                return;
4422                            }
4423                            st.opcode.add_reg(op4.id(), 16);
4424                            emit_rd0_rn5!();
4425                            return;
4426                        }
4427                        3 => {
4428                            if !check_signature!(op0, op5) {
4429                                self.last_error = Some(AsmError::InvalidInstruction);
4430                                return;
4431                            }
4432                            if op5.id() > 31 {
4433                                self.last_error = Some(AsmError::InvalidOperand);
4434                                return;
4435                            }
4436                            st.opcode.add_reg(op5.id(), 16);
4437                            emit_rd0_rn5!();
4438                            return;
4439                        }
4440                        _ => {
4441                            self.last_error = Some(AsmError::InvalidInstruction);
4442                            return;
4443                        }
4444                    }
4445                }
4446            }
4447
4448            Encoding::SimdLdSt => {
4449                let op_data = &SIMD_LD_ST[encoding_index];
4450                if isign4 == enc_ops!(Reg, Mem) {
4451                    let m = op1.as_::<Mem>();
4452                    st.rm_rel = *op1;
4453
4454                    let xsz =
4455                        (op0.as_::<Reg>().reg_type() as u32).wrapping_sub(RegType::Vec8 as u32);
4456                    if xsz > 4 || op0.as_::<Vec>().has_element_index() {
4457                        self.last_error = Some(AsmError::InvalidOperand);
4458                        return;
4459                    }
4460
4461                    if !check_vec_id(op0) {
4462                        self.last_error = Some(AsmError::InvalidOperand);
4463                        return;
4464                    }
4465
4466                    // TODO: check_mem_base_index_rel(m)
4467                    let offset = m.offset();
4468                    if m.has_base_reg() {
4469                        if m.has_index() {
4470                            let opt = SHIFT_OP_TO_LD_ST_OP_MAP[m.shift_op() as usize];
4471                            if opt == 0xFF {
4472                                self.last_error = Some(AsmError::InvalidOperand);
4473                                return;
4474                            }
4475                            let shift = m.shift();
4476                            let s = if shift != 0 { 1 } else { 0 };
4477                            if s != 0 && shift != xsz {
4478                                self.last_error = Some(AsmError::InvalidOperand);
4479                                return;
4480                            }
4481                            st.opcode.reset((op_data.register_op as u32) << 21);
4482                            st.opcode.add_imm(xsz & 3, 30);
4483                            st.opcode.add_imm(xsz >> 2, 23);
4484                            st.opcode.add_imm(opt as u32, 13);
4485                            st.opcode.add_imm(s, 12);
4486                            st.opcode.0 |= 1 << 11;
4487                            st.opcode.add_reg(op0.id(), 0);
4488                            // Emit mem base index
4489                            st.opcode.add_reg(m.base_id(), 5);
4490                            st.opcode.add_reg(m.index_id(), 16);
4491                            emit_op!();
4492                        }
4493
4494                        let offset32 = offset as i32;
4495                        if m.is_pre_or_post() {
4496                            if offset32 < -256 || offset32 > 255 {
4497                                self.last_error = Some(AsmError::InvalidOperand);
4498                                return;
4499                            }
4500                            st.opcode.reset((op_data.pre_post_op as u32) << 21);
4501                            st.opcode.add_imm(xsz & 3, 30);
4502                            st.opcode.add_imm(xsz >> 2, 23);
4503                            st.opcode.add_imm((offset32 as u32) & 0x1FF, 12);
4504                            st.opcode.add_imm(m.is_pre_index() as u32, 11);
4505                            st.opcode.0 |= 1 << 10;
4506                            st.opcode.add_reg(op0.id(), 0);
4507                            st.opcode.add_reg(m.base_id(), 5);
4508                            emit_op!();
4509                        } else {
4510                            let imm12 = (offset32 as u32) >> xsz;
4511                            if imm12 >= (1 << 12) || ((imm12 << xsz) as i32) != offset32 {
4512                                // Fallback to SimdLdurStur
4513                                let op_data_ldur = &SIMD_LDUR_STUR[encoding_index];
4514                                if m.has_base_reg() && !m.has_index() && !m.is_pre_or_post() {
4515                                    if offset32 < -256 || offset32 > 255 {
4516                                        self.last_error = Some(AsmError::InvalidOperand);
4517                                        return;
4518                                    }
4519                                    st.opcode.reset((op_data_ldur.opcode as u32) << 10);
4520                                    st.opcode.add_imm(xsz & 3, 30);
4521                                    st.opcode.add_imm(xsz >> 2, 23);
4522                                    st.opcode.add_imm((offset32 as u32) & 0x1FF, 12);
4523                                    st.opcode.add_reg(op0.id(), 0);
4524                                    st.opcode.add_reg(m.base_id(), 5);
4525                                    emit_op!();
4526                                }
4527                                self.last_error = Some(AsmError::InvalidOperand);
4528                                return;
4529                            }
4530                            st.opcode.reset((op_data.u_offset_op as u32) << 22);
4531                            st.opcode.add_imm(xsz & 3, 30);
4532                            st.opcode.add_imm(xsz >> 2, 23);
4533                            st.opcode.add_imm(imm12, 10);
4534                            st.opcode.add_reg(op0.id(), 0);
4535                            st.opcode.add_reg(m.base_id(), 5);
4536                            emit_op!();
4537                        }
4538                    } else {
4539                        if op_data.literal_op == 0 {
4540                            self.last_error = Some(AsmError::InvalidOperand);
4541                            return;
4542                        }
4543                        if xsz < 2 {
4544                            self.last_error = Some(AsmError::InvalidOperand);
4545                            return;
4546                        }
4547                        let opc = xsz - 2;
4548                        st.opcode.reset((op_data.literal_op as u32) << 24);
4549                        st.opcode.add_imm(opc, 30);
4550                        st.opcode.add_reg(op0.id(), 0);
4551                        st.offset_format
4552                            .reset_to_imm_type(OffsetType::SignedOffset, 4, 5, 19, 2);
4553                        st.rm_rel = *op1;
4554                        emit_rel!();
4555                    }
4556                }
4557            }
4558
4559            Encoding::SimdLdpStp => {
4560                let op_data = &SIMD_LDP_STP[encoding_index];
4561                if isign4 == enc_ops!(Reg, Reg, Mem) {
4562                    let m = op2.as_::<Mem>();
4563                    st.rm_rel = *op2;
4564
4565                    let opc =
4566                        (op0.as_::<Reg>().reg_type() as u32).wrapping_sub(RegType::Vec32 as u32);
4567                    if opc > 2
4568                        || op0.as_::<Vec>().has_element_type()
4569                        || op0.as_::<Vec>().has_element_index()
4570                    {
4571                        self.last_error = Some(AsmError::InvalidInstruction);
4572                        return;
4573                    }
4574                    if !check_signature!(op0, op1) {
4575                        self.last_error = Some(AsmError::InvalidInstruction);
4576                        return;
4577                    }
4578                    if !check_vec_id2(op0, op1) {
4579                        self.last_error = Some(AsmError::InvalidOperand);
4580                        return;
4581                    }
4582                    if m.base_type() != RegType::Gp64 || m.has_index() {
4583                        self.last_error = Some(AsmError::InvalidOperand);
4584                        return;
4585                    }
4586                    let offset_shift = 2 + opc;
4587                    let offset32 = m.offset() as i32 >> offset_shift;
4588                    if ((offset32 << offset_shift) as i32) != m.offset() as i32 {
4589                        self.last_error = Some(AsmError::InvalidOperand);
4590                        return;
4591                    }
4592                    if offset32 < -64 || offset32 > 63 {
4593                        self.last_error = Some(AsmError::InvalidOperand);
4594                        return;
4595                    }
4596                    if m.is_pre_or_post() && offset32 != 0 {
4597                        if op_data.pre_post_op == 0 {
4598                            self.last_error = Some(AsmError::InvalidOperand);
4599                            return;
4600                        }
4601                        st.opcode.reset((op_data.pre_post_op as u32) << 22);
4602                        st.opcode.add_imm(m.is_pre_index() as u32, 24);
4603                    } else {
4604                        st.opcode.reset((op_data.offset_op as u32) << 22);
4605                    }
4606                    st.opcode.add_imm(opc, 30);
4607                    st.opcode.add_imm((offset32 as u32) & 0x7F, 15);
4608                    st.opcode.add_reg(op1.id(), 10);
4609                    st.opcode.add_reg(op0.id(), 0);
4610                    st.opcode.add_reg(m.base_id(), 5);
4611                    emit_op!();
4612                }
4613            }
4614
4615            Encoding::SimdLdurStur => {
4616                let op_data = &SIMD_LDUR_STUR[encoding_index];
4617                if isign4 == enc_ops!(Reg, Mem) {
4618                    let m = op1.as_::<Mem>();
4619                    st.rm_rel = *op1;
4620
4621                    let sz =
4622                        (op0.as_::<Reg>().reg_type() as u32).wrapping_sub(RegType::Vec8 as u32);
4623                    if sz > 4
4624                        || op0.as_::<Vec>().has_element_type()
4625                        || op0.as_::<Vec>().has_element_index()
4626                    {
4627                        self.last_error = Some(AsmError::InvalidInstruction);
4628                        return;
4629                    }
4630                    if !check_vec_id(op0) {
4631                        self.last_error = Some(AsmError::InvalidOperand);
4632                        return;
4633                    }
4634                    if m.has_base_reg() && !m.has_index() && !m.is_pre_or_post() {
4635                        let offset32 = m.offset() as i32;
4636                        if offset32 < -256 || offset32 > 255 {
4637                            self.last_error = Some(AsmError::InvalidOperand);
4638                            return;
4639                        }
4640                        st.opcode.reset((op_data.opcode as u32) << 10);
4641                        st.opcode.add_imm(sz & 3, 30);
4642                        st.opcode.add_imm(sz >> 2, 23);
4643                        st.opcode.add_imm((offset32 as u32) & 0x1FF, 12);
4644                        st.opcode.add_reg(op0.id(), 0);
4645                        st.opcode.add_reg(m.base_id(), 5);
4646                        emit_op!();
4647                    }
4648                    self.last_error = Some(AsmError::InvalidOperand);
4649                    return;
4650                }
4651            }
4652
4653            Encoding::SimdLdNStN => {
4654                let op_data = &SIMD_LD_N_ST_N[encoding_index];
4655                let o4 = *ops.get(4).unwrap_or(&NOREG);
4656
4657                let mut n = 1;
4658
4659                if isign4 == enc_ops!(Reg, Mem) {
4660                    if op_data.n != 1 {
4661                        self.last_error = Some(AsmError::InvalidInstruction);
4662                        return;
4663                    }
4664                    st.rm_rel = *op1;
4665                } else if isign4 == enc_ops!(Reg, Reg, Mem) {
4666                    if op_data.n != 1 && op_data.n != 2 {
4667                        self.last_error = Some(AsmError::InvalidInstruction);
4668                        return;
4669                    }
4670                    if !check_signature!(op0, op1) || op0.id() + 1 != op1.id() {
4671                        self.last_error = Some(AsmError::InvalidInstruction);
4672                        return;
4673                    }
4674                    n = 2;
4675                    st.rm_rel = *op2;
4676                } else if isign4 == enc_ops!(Reg, Reg, Reg, Mem) && o4.is_none() {
4677                    if op_data.n != 1 && op_data.n != 3 {
4678                        self.last_error = Some(AsmError::InvalidInstruction);
4679                        return;
4680                    }
4681                    if !check_signature!(op0, op1, op2)
4682                        || op0.id() + 1 != op1.id()
4683                        || op1.id() + 1 != op2.id()
4684                    {
4685                        self.last_error = Some(AsmError::InvalidInstruction);
4686                        return;
4687                    }
4688                    n = 3;
4689                    st.rm_rel = *op3;
4690                } else if isign4 == enc_ops!(Reg, Reg, Reg, Reg) && o4.is_mem() {
4691                    if op_data.n != 1 && op_data.n != 4 {
4692                        self.last_error = Some(AsmError::InvalidInstruction);
4693                        return;
4694                    }
4695                    if !check_signature!(op0, op1, op2, op3)
4696                        || op0.id() + 1 != op1.id()
4697                        || op1.id() + 1 != op2.id()
4698                        || op2.id() + 1 != op3.id()
4699                    {
4700                        self.last_error = Some(AsmError::InvalidInstruction);
4701                        return;
4702                    }
4703                    n = 4;
4704                    st.rm_rel = *o4;
4705                } else {
4706                    self.last_error = Some(AsmError::InvalidInstruction);
4707                    return;
4708                }
4709
4710                let v = op0.as_::<Vec>();
4711                let m = st.rm_rel.as_::<Mem>();
4712
4713                let mut q = 0u32;
4714                let mut rm = 0u32;
4715                let mut rn = m.base_id();
4716                let sz = (v.element_type() as u32).wrapping_sub(VecElementType::B as u32);
4717                let mut opc_s_size = sz;
4718                let mut offset_possibility = 0u32;
4719
4720                if sz > 3 {
4721                    self.last_error = Some(AsmError::InvalidInstruction);
4722                    return;
4723                }
4724
4725                if m.base_type() != RegType::Gp64 {
4726                    self.last_error = Some(AsmError::InvalidOperand);
4727                    return;
4728                }
4729
4730                if rn > 30 && rn != Gp::ID_SP {
4731                    self.last_error = Some(AsmError::InvalidOperand);
4732                    return;
4733                }
4734
4735                rn &= 31;
4736
4737                if op_data.replicate != 0 {
4738                    if n != op_data.n {
4739                        self.last_error = Some(AsmError::InvalidInstruction);
4740                        return;
4741                    }
4742                    if v.has_element_index() {
4743                        self.last_error = Some(AsmError::InvalidInstruction);
4744                        return;
4745                    }
4746                    q = (v.reg_type() as u32).wrapping_sub(RegType::Vec64 as u32);
4747                    if q > 1 {
4748                        self.last_error = Some(AsmError::InvalidInstruction);
4749                        return;
4750                    }
4751                    st.opcode.reset((op_data.single_op as u32) << 10);
4752                    offset_possibility = (1u32 << sz) * n;
4753                } else if v.has_element_index() {
4754                    if n != op_data.n {
4755                        self.last_error = Some(AsmError::InvalidInstruction);
4756                        return;
4757                    }
4758                    const OPC_S_SIZE_BY_SZ_TABLE: [u32; 4] =
4759                        [0u32 << 3, 2u32 << 3, 4u32 << 3, (4u32 << 3) | 1u32];
4760                    st.opcode.reset((op_data.single_op as u32) << 10);
4761                    opc_s_size = OPC_S_SIZE_BY_SZ_TABLE[sz as usize];
4762                    offset_possibility = (1u32 << sz) * op_data.n;
4763                    let element_index = v.element_index();
4764                    let max_element_index = 15u32 >> sz;
4765                    if element_index > max_element_index {
4766                        self.last_error = Some(AsmError::InvalidOperand);
4767                        return;
4768                    }
4769                    let element_index_shifted = element_index << sz;
4770                    q = element_index_shifted >> 3;
4771                    opc_s_size |= element_index_shifted & 0x7;
4772                } else {
4773                    const OPC_S_SIZE_BY_N_TABLE: [u32; 5] =
4774                        [0u32, 0x7u32 << 2, 0xAu32 << 2, 0x6u32 << 2, 0x2u32 << 2];
4775                    q = (v.reg_type() as u32).wrapping_sub(RegType::Vec64 as u32);
4776                    if q > 1 {
4777                        self.last_error = Some(AsmError::InvalidInstruction);
4778                        return;
4779                    }
4780                    if op_data.n == 1 {
4781                        opc_s_size |= OPC_S_SIZE_BY_N_TABLE[n as usize];
4782                    }
4783                    st.opcode.reset((op_data.multiple_op as u32) << 10);
4784                    offset_possibility = (8u32 << q) * n;
4785                }
4786
4787                if m.has_index() {
4788                    if m.has_offset() || !m.is_post_index() {
4789                        self.last_error = Some(AsmError::InvalidOperand);
4790                        return;
4791                    }
4792                    rm = m.index_id();
4793                    if rm > 30 {
4794                        self.last_error = Some(AsmError::InvalidOperand);
4795                        return;
4796                    }
4797                    st.opcode.0 |= 1 << 23;
4798                } else {
4799                    if m.has_offset() {
4800                        if m.offset() != offset_possibility as i64 || !m.is_post_index() {
4801                            self.last_error = Some(AsmError::InvalidOperand);
4802                            return;
4803                        }
4804                        rm = 31;
4805                        st.opcode.0 |= 1 << 23;
4806                    }
4807                }
4808
4809                st.opcode.add_imm(q, 30);
4810                st.opcode.add_imm(rm, 16);
4811                st.opcode.add_imm(opc_s_size, 10);
4812                st.opcode.add_imm(rn, 5);
4813
4814                st.opcode.add_reg(op0.id(), 0);
4815                emit_op!();
4816            }
4817
4818            Encoding::None | Encoding::Count => (),
4819        }
4820
4821        self.last_error = Some(AsmError::UnsupportedInstruction {
4822            reason: "Unsupported instruction encoding or operand types",
4823        });
4824    }
4825}
4826
4827// @generated AArch64 target features begin
4828/// AArch64 architectural features present in the pinned AsmJit ISA metadata.
4829#[derive(Clone, Copy, Debug, PartialEq, Eq, PartialOrd, Ord)]
4830#[repr(u8)]
4831pub enum CpuFeature {
4832    Aes,
4833    Asimd,
4834    Bf16,
4835    Bti,
4836    Chk,
4837    Clrbhb,
4838    Crc32,
4839    Cssc,
4840    Dgh,
4841    Dotprod,
4842    Fcma,
4843    Fhm,
4844    Flagm,
4845    Flagm2,
4846    Fp16,
4847    Fp8,
4848    Frintts,
4849    I8Mm,
4850    Jscvt,
4851    Lor,
4852    Lse,
4853    Mte,
4854    Mte2,
4855    Pauth,
4856    Ras,
4857    Rdm,
4858    Sha1,
4859    Sha256,
4860    Sha3,
4861    Sha512,
4862    Sm3,
4863    Sm4,
4864}
4865
4866pub const CPU_FEATURE_COUNT: usize = 32;
4867pub const CPU_FEATURE_NAMES: [&str; CPU_FEATURE_COUNT] = [
4868    "AES", "ASIMD", "BF16", "BTI", "CHK", "CLRBHB", "CRC32", "CSSC", "DGH", "DOTPROD", "FCMA",
4869    "FHM", "FLAGM", "FLAGM2", "FP16", "FP8", "FRINTTS", "I8MM", "JSCVT", "LOR", "LSE", "MTE",
4870    "MTE2", "PAUTH", "RAS", "RDM", "SHA1", "SHA256", "SHA3", "SHA512", "SM3", "SM4",
4871];
4872
4873pub const ALL_CPU_FEATURES: [CpuFeature; CPU_FEATURE_COUNT] = [
4874    CpuFeature::Aes,
4875    CpuFeature::Asimd,
4876    CpuFeature::Bf16,
4877    CpuFeature::Bti,
4878    CpuFeature::Chk,
4879    CpuFeature::Clrbhb,
4880    CpuFeature::Crc32,
4881    CpuFeature::Cssc,
4882    CpuFeature::Dgh,
4883    CpuFeature::Dotprod,
4884    CpuFeature::Fcma,
4885    CpuFeature::Fhm,
4886    CpuFeature::Flagm,
4887    CpuFeature::Flagm2,
4888    CpuFeature::Fp16,
4889    CpuFeature::Fp8,
4890    CpuFeature::Frintts,
4891    CpuFeature::I8Mm,
4892    CpuFeature::Jscvt,
4893    CpuFeature::Lor,
4894    CpuFeature::Lse,
4895    CpuFeature::Mte,
4896    CpuFeature::Mte2,
4897    CpuFeature::Pauth,
4898    CpuFeature::Ras,
4899    CpuFeature::Rdm,
4900    CpuFeature::Sha1,
4901    CpuFeature::Sha256,
4902    CpuFeature::Sha3,
4903    CpuFeature::Sha512,
4904    CpuFeature::Sm3,
4905    CpuFeature::Sm4,
4906];
4907
4908impl CpuFeature {
4909    pub const fn name(self) -> &'static str {
4910        CPU_FEATURE_NAMES[self as usize]
4911    }
4912}
4913
4914const FEATURE_FORM_SIGNATURE_MASK: u32 = OperandSignature::OP_TYPE_MASK
4915    | OperandSignature::REG_TYPE_MASK
4916    | Vec::SIGNATURE_REG_ELEMENT_TYPE_MASK
4917    | Vec::SIGNATURE_REG_ELEMENT_FLAG_MASK;
4918
4919const fn feature_reg_signature(
4920    reg_type: RegType,
4921    element_type: VecElementType,
4922    element_access: bool,
4923) -> u32 {
4924    OperandType::Reg as u32
4925        | (reg_type as u32) << OperandSignature::REG_TYPE_SHIFT
4926        | (element_type as u32) << Vec::SIGNATURE_REG_ELEMENT_TYPE_SHIFT
4927        | (element_access as u32) << Vec::SIGNATURE_REG_ELEMENT_FLAG_SHIFT
4928}
4929
4930struct InstFeatureForm {
4931    opcode_mask: u32,
4932    opcode_value: u32,
4933    operand_signatures: [u32; 6],
4934    required: u64,
4935    context: &'static str,
4936}
4937
4938impl InstFeatureForm {
4939    fn matches(&self, opcode: u32, ops: &[&Operand]) -> bool {
4940        if opcode & self.opcode_mask != self.opcode_value {
4941            return false;
4942        }
4943        self.operand_signatures
4944            .iter()
4945            .enumerate()
4946            .all(|(index, expected)| {
4947                let actual = ops.get(index).map_or(0, |op| op.signature.bits());
4948                actual & FEATURE_FORM_SIGNATURE_MASK == *expected
4949            })
4950    }
4951}
4952
4953/// Conservative required-feature masks, indexed by `InstId as usize`.
4954pub static INST_FEATURE_MASKS: [u64; InstId::_Count as usize] = [
4955    0x0000000000000000, // None
4956    0x0000000000000080, // Abs
4957    0x0000000000000000, // Adc
4958    0x0000000000000000, // Adcs
4959    0x0000000000000000, // Add
4960    0x0000000000200000, // Addg
4961    0x0000000000000000, // Adds
4962    0x0000000000000000, // Adr
4963    0x0000000000000000, // Adrp
4964    0x0000000000000000, // And
4965    0x0000000000000000, // Ands
4966    0x0000000000000000, // Asr
4967    0x0000000000000000, // Asrv
4968    0x0000000000000000, // At
4969    0x0000000000800000, // Autda
4970    0x0000000000800000, // Autdza
4971    0x0000000000800000, // Autdb
4972    0x0000000000800000, // Autdzb
4973    0x0000000000800000, // Autia
4974    0x0000000000800000, // Autia1716
4975    0x0000000000800000, // Autiasp
4976    0x0000000000800000, // Autiaz
4977    0x0000000000800000, // Autib
4978    0x0000000000800000, // Autib1716
4979    0x0000000000800000, // Autibsp
4980    0x0000000000800000, // Autibz
4981    0x0000000000800000, // Autiza
4982    0x0000000000800000, // Autizb
4983    0x0000000000002000, // Axflag
4984    0x0000000000000000, // B
4985    0x0000000000000000, // Bc
4986    0x0000000000000000, // Bfc
4987    0x0000000000000000, // Bfi
4988    0x0000000000000000, // Bfm
4989    0x0000000000000000, // Bfxil
4990    0x0000000000000000, // Bic
4991    0x0000000000000000, // Bics
4992    0x0000000000000000, // Bl
4993    0x0000000000000000, // Blr
4994    0x0000000000000000, // Br
4995    0x0000000000000000, // Brk
4996    0x0000000000000008, // Bti
4997    0x0000000000100000, // Cas
4998    0x0000000000100000, // Casa
4999    0x0000000000100000, // Casab
5000    0x0000000000100000, // Casah
5001    0x0000000000100000, // Casal
5002    0x0000000000100000, // Casalb
5003    0x0000000000100000, // Casalh
5004    0x0000000000100000, // Casb
5005    0x0000000000100000, // Cash
5006    0x0000000000100000, // Casl
5007    0x0000000000100000, // Caslb
5008    0x0000000000100000, // Caslh
5009    0x0000000000100000, // Casp
5010    0x0000000000100000, // Caspa
5011    0x0000000000100000, // Caspal
5012    0x0000000000100000, // Caspl
5013    0x0000000000000000, // Cbnz
5014    0x0000000000000000, // Cbz
5015    0x0000000000000000, // Ccmn
5016    0x0000000000000000, // Ccmp
5017    0x0000000000001000, // Cfinv
5018    0x0000000000000010, // Chkfeat
5019    0x0000000000000000, // Cinc
5020    0x0000000000000000, // Cinv
5021    0x0000000000000020, // Clrbhb
5022    0x0000000000000000, // Clrex
5023    0x0000000000000000, // Cls
5024    0x0000000000000000, // Clz
5025    0x0000000000000000, // Cmn
5026    0x0000000000000000, // Cmp
5027    0x0000000000200000, // Cmpp
5028    0x0000000000000000, // Cneg
5029    0x0000000000000080, // Cnt
5030    0x0000000000000040, // Crc32b
5031    0x0000000000000040, // Crc32cb
5032    0x0000000000000040, // Crc32ch
5033    0x0000000000000040, // Crc32cw
5034    0x0000000000000040, // Crc32cx
5035    0x0000000000000040, // Crc32h
5036    0x0000000000000040, // Crc32w
5037    0x0000000000000040, // Crc32x
5038    0x0000000000000000, // Csdb
5039    0x0000000000000000, // Csel
5040    0x0000000000000000, // Cset
5041    0x0000000000000000, // Csetm
5042    0x0000000000000000, // Csinc
5043    0x0000000000000000, // Csinv
5044    0x0000000000000000, // Csneg
5045    0x0000000000000080, // Ctz
5046    0x0000000000000000, // Dc
5047    0x0000000000000000, // Dcps1
5048    0x0000000000000000, // Dcps2
5049    0x0000000000000000, // Dcps3
5050    0x0000000000000100, // Dgh
5051    0x0000000000000000, // Dmb
5052    0x0000000000000000, // Drps
5053    0x0000000000000000, // Dsb
5054    0x0000000000000000, // Eon
5055    0x0000000000000000, // Eor
5056    0x0000000001000000, // Esb
5057    0x0000000000000000, // Extr
5058    0x0000000000000000, // Eret
5059    0x0000000000200000, // Gmi
5060    0x0000000000000000, // Hint
5061    0x0000000000000000, // Hlt
5062    0x0000000000000000, // Hvc
5063    0x0000000000000000, // Ic
5064    0x0000000000000000, // Isb
5065    0x0000000000100000, // Ldadd
5066    0x0000000000100000, // Ldadda
5067    0x0000000000100000, // Ldaddab
5068    0x0000000000100000, // Ldaddah
5069    0x0000000000100000, // Ldaddal
5070    0x0000000000100000, // Ldaddalb
5071    0x0000000000100000, // Ldaddalh
5072    0x0000000000100000, // Ldaddb
5073    0x0000000000100000, // Ldaddh
5074    0x0000000000100000, // Ldaddl
5075    0x0000000000100000, // Ldaddlb
5076    0x0000000000100000, // Ldaddlh
5077    0x0000000000000000, // Ldar
5078    0x0000000000000000, // Ldarb
5079    0x0000000000000000, // Ldarh
5080    0x0000000000000000, // Ldaxp
5081    0x0000000000000000, // Ldaxr
5082    0x0000000000000000, // Ldaxrb
5083    0x0000000000000000, // Ldaxrh
5084    0x0000000000100000, // Ldclr
5085    0x0000000000100000, // Ldclra
5086    0x0000000000100000, // Ldclrab
5087    0x0000000000100000, // Ldclrah
5088    0x0000000000100000, // Ldclral
5089    0x0000000000100000, // Ldclralb
5090    0x0000000000100000, // Ldclralh
5091    0x0000000000100000, // Ldclrb
5092    0x0000000000100000, // Ldclrh
5093    0x0000000000100000, // Ldclrl
5094    0x0000000000100000, // Ldclrlb
5095    0x0000000000100000, // Ldclrlh
5096    0x0000000000100000, // Ldeor
5097    0x0000000000100000, // Ldeora
5098    0x0000000000100000, // Ldeorab
5099    0x0000000000100000, // Ldeorah
5100    0x0000000000100000, // Ldeoral
5101    0x0000000000100000, // Ldeoralb
5102    0x0000000000100000, // Ldeoralh
5103    0x0000000000100000, // Ldeorb
5104    0x0000000000100000, // Ldeorh
5105    0x0000000000100000, // Ldeorl
5106    0x0000000000100000, // Ldeorlb
5107    0x0000000000100000, // Ldeorlh
5108    0x0000000000200000, // Ldg
5109    0x0000000000400000, // Ldgm
5110    0x0000000000080000, // Ldlar
5111    0x0000000000080000, // Ldlarb
5112    0x0000000000080000, // Ldlarh
5113    0x0000000000000000, // Ldnp
5114    0x0000000000000000, // Ldp
5115    0x0000000000000000, // Ldpsw
5116    0x0000000000000000, // Ldr
5117    0x0000000000800000, // Ldraa
5118    0x0000000000800000, // Ldrab
5119    0x0000000000000000, // Ldrb
5120    0x0000000000000000, // Ldrh
5121    0x0000000000000000, // Ldrsb
5122    0x0000000000000000, // Ldrsh
5123    0x0000000000000000, // Ldrsw
5124    0x0000000000100000, // Ldset
5125    0x0000000000100000, // Ldseta
5126    0x0000000000100000, // Ldsetab
5127    0x0000000000100000, // Ldsetah
5128    0x0000000000100000, // Ldsetal
5129    0x0000000000100000, // Ldsetalb
5130    0x0000000000100000, // Ldsetalh
5131    0x0000000000100000, // Ldsetb
5132    0x0000000000100000, // Ldseth
5133    0x0000000000100000, // Ldsetl
5134    0x0000000000100000, // Ldsetlb
5135    0x0000000000100000, // Ldsetlh
5136    0x0000000000100000, // Ldsmax
5137    0x0000000000100000, // Ldsmaxa
5138    0x0000000000100000, // Ldsmaxab
5139    0x0000000000100000, // Ldsmaxah
5140    0x0000000000100000, // Ldsmaxal
5141    0x0000000000100000, // Ldsmaxalb
5142    0x0000000000100000, // Ldsmaxalh
5143    0x0000000000100000, // Ldsmaxb
5144    0x0000000000100000, // Ldsmaxh
5145    0x0000000000100000, // Ldsmaxl
5146    0x0000000000100000, // Ldsmaxlb
5147    0x0000000000100000, // Ldsmaxlh
5148    0x0000000000100000, // Ldsmin
5149    0x0000000000100000, // Ldsmina
5150    0x0000000000100000, // Ldsminab
5151    0x0000000000100000, // Ldsminah
5152    0x0000000000100000, // Ldsminal
5153    0x0000000000100000, // Ldsminalb
5154    0x0000000000100000, // Ldsminalh
5155    0x0000000000100000, // Ldsminb
5156    0x0000000000100000, // Ldsminh
5157    0x0000000000100000, // Ldsminl
5158    0x0000000000100000, // Ldsminlb
5159    0x0000000000100000, // Ldsminlh
5160    0x0000000000000000, // Ldtr
5161    0x0000000000000000, // Ldtrb
5162    0x0000000000000000, // Ldtrh
5163    0x0000000000000000, // Ldtrsb
5164    0x0000000000000000, // Ldtrsh
5165    0x0000000000000000, // Ldtrsw
5166    0x0000000000100000, // Ldumax
5167    0x0000000000100000, // Ldumaxa
5168    0x0000000000100000, // Ldumaxab
5169    0x0000000000100000, // Ldumaxah
5170    0x0000000000100000, // Ldumaxal
5171    0x0000000000100000, // Ldumaxalb
5172    0x0000000000100000, // Ldumaxalh
5173    0x0000000000100000, // Ldumaxb
5174    0x0000000000100000, // Ldumaxh
5175    0x0000000000100000, // Ldumaxl
5176    0x0000000000100000, // Ldumaxlb
5177    0x0000000000100000, // Ldumaxlh
5178    0x0000000000100000, // Ldumin
5179    0x0000000000100000, // Ldumina
5180    0x0000000000100000, // Lduminab
5181    0x0000000000100000, // Lduminah
5182    0x0000000000100000, // Lduminal
5183    0x0000000000100000, // Lduminalb
5184    0x0000000000100000, // Lduminalh
5185    0x0000000000100000, // Lduminb
5186    0x0000000000100000, // Lduminh
5187    0x0000000000100000, // Lduminl
5188    0x0000000000100000, // Lduminlb
5189    0x0000000000100000, // Lduminlh
5190    0x0000000000000000, // Ldur
5191    0x0000000000000000, // Ldurb
5192    0x0000000000000000, // Ldurh
5193    0x0000000000000000, // Ldursb
5194    0x0000000000000000, // Ldursh
5195    0x0000000000000000, // Ldursw
5196    0x0000000000000000, // Ldxp
5197    0x0000000000000000, // Ldxr
5198    0x0000000000000000, // Ldxrb
5199    0x0000000000000000, // Ldxrh
5200    0x0000000000000000, // Lsl
5201    0x0000000000000000, // Lslv
5202    0x0000000000000000, // Lsr
5203    0x0000000000000000, // Lsrv
5204    0x0000000000000000, // Madd
5205    0x0000000000000000, // Mneg
5206    0x0000000000000000, // Mov
5207    0x0000000000000000, // Movk
5208    0x0000000000000000, // Movn
5209    0x0000000000000000, // Movz
5210    0x0000000000000000, // Mrs
5211    0x0000000000000000, // Msr
5212    0x0000000000000000, // Msub
5213    0x0000000000000000, // Mul
5214    0x0000000000000000, // Mvn
5215    0x0000000000000000, // Neg
5216    0x0000000000000000, // Negs
5217    0x0000000000000000, // Ngc
5218    0x0000000000000000, // Ngcs
5219    0x0000000000000000, // Nop
5220    0x0000000000000000, // Orn
5221    0x0000000000000000, // Orr
5222    0x0000000000800000, // Pacda
5223    0x0000000000800000, // Pacdb
5224    0x0000000000800000, // Pacdza
5225    0x0000000000800000, // Pacdzb
5226    0x0000000000800000, // Pacga
5227    0x0000000000000000, // Prfm
5228    0x0000000000000000, // Pssbb
5229    0x0000000000000000, // Rbit
5230    0x0000000000000000, // Ret
5231    0x0000000000000000, // Rev
5232    0x0000000000000000, // Rev16
5233    0x0000000000000000, // Rev32
5234    0x0000000000000000, // Rev64
5235    0x0000000000000000, // Ror
5236    0x0000000000000000, // Rorv
5237    0x0000000000000000, // Sbc
5238    0x0000000000000000, // Sbcs
5239    0x0000000000000000, // Sbfiz
5240    0x0000000000000000, // Sbfm
5241    0x0000000000000000, // Sbfx
5242    0x0000000000000000, // Sdiv
5243    0x0000000000001000, // Setf8
5244    0x0000000000001000, // Setf16
5245    0x0000000000000000, // Sev
5246    0x0000000000000000, // Sevl
5247    0x0000000000000000, // Smaddl
5248    0x0000000000000080, // Smax
5249    0x0000000000000000, // Smc
5250    0x0000000000000080, // Smin
5251    0x0000000000000000, // Smnegl
5252    0x0000000000000000, // Smsubl
5253    0x0000000000000000, // Smulh
5254    0x0000000000000000, // Smull
5255    0x0000000000000000, // Ssbb
5256    0x0000000000200000, // St2g
5257    0x0000000000100000, // Stadd
5258    0x0000000000100000, // Staddl
5259    0x0000000000100000, // Staddb
5260    0x0000000000100000, // Staddlb
5261    0x0000000000100000, // Staddh
5262    0x0000000000100000, // Staddlh
5263    0x0000000000100000, // Stclr
5264    0x0000000000100000, // Stclrl
5265    0x0000000000100000, // Stclrb
5266    0x0000000000100000, // Stclrlb
5267    0x0000000000100000, // Stclrh
5268    0x0000000000100000, // Stclrlh
5269    0x0000000000100000, // Steor
5270    0x0000000000100000, // Steorl
5271    0x0000000000100000, // Steorb
5272    0x0000000000100000, // Steorlb
5273    0x0000000000100000, // Steorh
5274    0x0000000000100000, // Steorlh
5275    0x0000000000200000, // Stg
5276    0x0000000000400000, // Stgm
5277    0x0000000000200000, // Stgp
5278    0x0000000000080000, // Stllr
5279    0x0000000000080000, // Stllrb
5280    0x0000000000080000, // Stllrh
5281    0x0000000000000000, // Stlr
5282    0x0000000000000000, // Stlrb
5283    0x0000000000000000, // Stlrh
5284    0x0000000000000000, // Stlxp
5285    0x0000000000000000, // Stlxr
5286    0x0000000000000000, // Stlxrb
5287    0x0000000000000000, // Stlxrh
5288    0x0000000000000000, // Stnp
5289    0x0000000000000000, // Stp
5290    0x0000000000000000, // Str
5291    0x0000000000000000, // Strb
5292    0x0000000000000000, // Strh
5293    0x0000000000100000, // Stset
5294    0x0000000000100000, // Stsetl
5295    0x0000000000100000, // Stsetb
5296    0x0000000000100000, // Stsetlb
5297    0x0000000000100000, // Stseth
5298    0x0000000000100000, // Stsetlh
5299    0x0000000000100000, // Stsmax
5300    0x0000000000100000, // Stsmaxl
5301    0x0000000000100000, // Stsmaxb
5302    0x0000000000100000, // Stsmaxlb
5303    0x0000000000100000, // Stsmaxh
5304    0x0000000000100000, // Stsmaxlh
5305    0x0000000000100000, // Stsmin
5306    0x0000000000100000, // Stsminl
5307    0x0000000000100000, // Stsminb
5308    0x0000000000100000, // Stsminlb
5309    0x0000000000100000, // Stsminh
5310    0x0000000000100000, // Stsminlh
5311    0x0000000000000000, // Sttr
5312    0x0000000000000000, // Sttrb
5313    0x0000000000000000, // Sttrh
5314    0x0000000000100000, // Stumax
5315    0x0000000000100000, // Stumaxl
5316    0x0000000000100000, // Stumaxb
5317    0x0000000000100000, // Stumaxlb
5318    0x0000000000100000, // Stumaxh
5319    0x0000000000100000, // Stumaxlh
5320    0x0000000000100000, // Stumin
5321    0x0000000000100000, // Stuminl
5322    0x0000000000100000, // Stuminb
5323    0x0000000000100000, // Stuminlb
5324    0x0000000000100000, // Stuminh
5325    0x0000000000100000, // Stuminlh
5326    0x0000000000000000, // Stur
5327    0x0000000000000000, // Sturb
5328    0x0000000000000000, // Sturh
5329    0x0000000000000000, // Stxp
5330    0x0000000000000000, // Stxr
5331    0x0000000000000000, // Stxrb
5332    0x0000000000000000, // Stxrh
5333    0x0000000000200000, // Stz2g
5334    0x0000000000200000, // Stzg
5335    0x0000000000400000, // Stzgm
5336    0x0000000000000000, // Sub
5337    0x0000000000200000, // Subg
5338    0x0000000000200000, // Subp
5339    0x0000000000200000, // Subps
5340    0x0000000000000000, // Subs
5341    0x0000000000000000, // Svc
5342    0x0000000000100000, // Swp
5343    0x0000000000100000, // Swpa
5344    0x0000000000100000, // Swpab
5345    0x0000000000100000, // Swpah
5346    0x0000000000100000, // Swpal
5347    0x0000000000100000, // Swpalb
5348    0x0000000000100000, // Swpalh
5349    0x0000000000100000, // Swpb
5350    0x0000000000100000, // Swph
5351    0x0000000000100000, // Swpl
5352    0x0000000000100000, // Swplb
5353    0x0000000000100000, // Swplh
5354    0x0000000000000000, // Sxtb
5355    0x0000000000000000, // Sxth
5356    0x0000000000000000, // Sxtw
5357    0x0000000000000000, // Sys
5358    0x0000000000000000, // Tlbi
5359    0x0000000000000000, // Tst
5360    0x0000000000000000, // Tbnz
5361    0x0000000000000000, // Tbz
5362    0x0000000000000000, // Ubfiz
5363    0x0000000000000000, // Ubfm
5364    0x0000000000000000, // Ubfx
5365    0x0000000000000000, // Udf
5366    0x0000000000000000, // Udiv
5367    0x0000000000000000, // Umaddl
5368    0x0000000000000080, // Umax
5369    0x0000000000000080, // Umin
5370    0x0000000000000000, // Umnegl
5371    0x0000000000000000, // Umull
5372    0x0000000000000000, // Umulh
5373    0x0000000000000000, // Umsubl
5374    0x0000000000000000, // Uxtb
5375    0x0000000000000000, // Uxth
5376    0x0000000000000000, // Wfe
5377    0x0000000000000000, // Wfi
5378    0x0000000000002000, // Xaflag
5379    0x0000000000800000, // Xpacd
5380    0x0000000000800000, // Xpaci
5381    0x0000000000800000, // Xpaclri
5382    0x0000000000000000, // Yield
5383    0x0000000000000002, // Abs_v
5384    0x0000000000000002, // Add_v
5385    0x0000000000000002, // Addhn_v
5386    0x0000000000000002, // Addhn2_v
5387    0x0000000000000002, // Addp_v
5388    0x0000000000000002, // Addv_v
5389    0x0000000000000003, // Aesd_v
5390    0x0000000000000003, // Aese_v
5391    0x0000000000000003, // Aesimc_v
5392    0x0000000000000003, // Aesmc_v
5393    0x0000000000000002, // And_v
5394    0x0000000010000002, // Bcax_v
5395    0x0000000000000006, // Bfcvt_v
5396    0x0000000000000006, // Bfcvtn_v
5397    0x0000000000000006, // Bfcvtn2_v
5398    0x0000000000000006, // Bfdot_v
5399    0x0000000000000006, // Bfmlalb_v
5400    0x0000000000000006, // Bfmlalt_v
5401    0x0000000000000006, // Bfmmla_v
5402    0x0000000000000002, // Bic_v
5403    0x0000000000000002, // Bif_v
5404    0x0000000000000002, // Bit_v
5405    0x0000000000000002, // Bsl_v
5406    0x0000000000000002, // Cls_v
5407    0x0000000000000002, // Clz_v
5408    0x0000000000000002, // Cmeq_v
5409    0x0000000000000002, // Cmge_v
5410    0x0000000000000002, // Cmgt_v
5411    0x0000000000000002, // Cmhi_v
5412    0x0000000000000002, // Cmhs_v
5413    0x0000000000000002, // Cmle_v
5414    0x0000000000000002, // Cmlt_v
5415    0x0000000000000002, // Cmtst_v
5416    0x0000000000000002, // Cnt_v
5417    0x0000000000000002, // Dup_v
5418    0x0000000000000002, // Eor_v
5419    0x0000000010000002, // Eor3_v
5420    0x0000000000000002, // Ext_v
5421    0x0000000000004002, // Fabd_v
5422    0x0000000000004002, // Fabs_v
5423    0x0000000000004002, // Facge_v
5424    0x0000000000004002, // Facgt_v
5425    0x0000000000004002, // Fadd_v
5426    0x0000000000004002, // Faddp_v
5427    0x0000000000000402, // Fcadd_v
5428    0x0000000000004002, // Fccmp_v
5429    0x0000000000004002, // Fccmpe_v
5430    0x0000000000004002, // Fcmeq_v
5431    0x0000000000004002, // Fcmge_v
5432    0x0000000000004002, // Fcmgt_v
5433    0x0000000000000402, // Fcmla_v
5434    0x0000000000004002, // Fcmle_v
5435    0x0000000000004002, // Fcmlt_v
5436    0x0000000000004002, // Fcmp_v
5437    0x0000000000004002, // Fcmpe_v
5438    0x0000000000004002, // Fcsel_v
5439    0x0000000000000002, // Fcvt_v
5440    0x0000000000004002, // Fcvtas_v
5441    0x0000000000004002, // Fcvtau_v
5442    0x0000000000000002, // Fcvtl_v
5443    0x0000000000000002, // Fcvtl2_v
5444    0x0000000000004002, // Fcvtms_v
5445    0x0000000000004002, // Fcvtmu_v
5446    0x0000000000008002, // Fcvtn_v
5447    0x0000000000008002, // Fcvtn2_v
5448    0x0000000000004002, // Fcvtns_v
5449    0x0000000000004002, // Fcvtnu_v
5450    0x0000000000004002, // Fcvtps_v
5451    0x0000000000004002, // Fcvtpu_v
5452    0x0000000000000000, // Fcvtxn_v
5453    0x0000000000000000, // Fcvtxn2_v
5454    0x0000000000004002, // Fcvtzs_v
5455    0x0000000000004002, // Fcvtzu_v
5456    0x0000000000004002, // Fdiv_v
5457    0x0000000000040002, // Fjcvtzs_v
5458    0x0000000000004002, // Fmadd_v
5459    0x0000000000004002, // Fmax_v
5460    0x0000000000004002, // Fmaxnm_v
5461    0x0000000000004002, // Fmaxnmp_v
5462    0x0000000000004002, // Fmaxnmv_v
5463    0x0000000000004002, // Fmaxp_v
5464    0x0000000000004002, // Fmaxv_v
5465    0x0000000000004002, // Fmin_v
5466    0x0000000000004002, // Fminnm_v
5467    0x0000000000004002, // Fminnmp_v
5468    0x0000000000004002, // Fminnmv_v
5469    0x0000000000004002, // Fminp_v
5470    0x0000000000004002, // Fminv_v
5471    0x0000000000004002, // Fmla_v
5472    0x0000000000000802, // Fmlal_v
5473    0x0000000000000802, // Fmlal2_v
5474    0x0000000000004002, // Fmls_v
5475    0x0000000000000802, // Fmlsl_v
5476    0x0000000000000802, // Fmlsl2_v
5477    0x0000000000004002, // Fmov_v
5478    0x0000000000004002, // Fmsub_v
5479    0x0000000000004002, // Fmul_v
5480    0x0000000000004002, // Fmulx_v
5481    0x0000000000004002, // Fneg_v
5482    0x0000000000004002, // Fnmadd_v
5483    0x0000000000004002, // Fnmsub_v
5484    0x0000000000004002, // Fnmul_v
5485    0x0000000000004002, // Frecpe_v
5486    0x0000000000004002, // Frecps_v
5487    0x0000000000004002, // Frecpx_v
5488    0x0000000000010002, // Frint32x_v
5489    0x0000000000010002, // Frint32z_v
5490    0x0000000000010002, // Frint64x_v
5491    0x0000000000010002, // Frint64z_v
5492    0x0000000000004002, // Frinta_v
5493    0x0000000000004002, // Frinti_v
5494    0x0000000000004002, // Frintm_v
5495    0x0000000000004002, // Frintn_v
5496    0x0000000000004002, // Frintp_v
5497    0x0000000000004002, // Frintx_v
5498    0x0000000000004002, // Frintz_v
5499    0x0000000000004002, // Frsqrte_v
5500    0x0000000000004002, // Frsqrts_v
5501    0x0000000000004002, // Fsqrt_v
5502    0x0000000000004002, // Fsub_v
5503    0x0000000000000002, // Ins_v
5504    0x0000000000000002, // Ld1_v
5505    0x0000000000000002, // Ld1r_v
5506    0x0000000000000002, // Ld2_v
5507    0x0000000000000002, // Ld2r_v
5508    0x0000000000000002, // Ld3_v
5509    0x0000000000000002, // Ld3r_v
5510    0x0000000000000002, // Ld4_v
5511    0x0000000000000002, // Ld4r_v
5512    0x0000000000000002, // Ldnp_v
5513    0x0000000000000002, // Ldp_v
5514    0x0000000000000002, // Ldr_v
5515    0x0000000000000002, // Ldur_v
5516    0x0000000000000002, // Mla_v
5517    0x0000000000000002, // Mls_v
5518    0x0000000000000002, // Mov_v
5519    0x0000000000000002, // Movi_v
5520    0x0000000000000002, // Mul_v
5521    0x0000000000000002, // Mvn_v
5522    0x0000000000000002, // Mvni_v
5523    0x0000000000000002, // Neg_v
5524    0x0000000000000002, // Not_v
5525    0x0000000000000002, // Orn_v
5526    0x0000000000000002, // Orr_v
5527    0x0000000000000002, // Pmul_v
5528    0x0000000000000002, // Pmull_v
5529    0x0000000000000002, // Pmull2_v
5530    0x0000000000000002, // Raddhn_v
5531    0x0000000000000002, // Raddhn2_v
5532    0x0000000010000002, // Rax1_v
5533    0x0000000000000002, // Rbit_v
5534    0x0000000000000002, // Rev16_v
5535    0x0000000000000002, // Rev32_v
5536    0x0000000000000002, // Rev64_v
5537    0x0000000000000002, // Rshrn_v
5538    0x0000000000000002, // Rshrn2_v
5539    0x0000000000000002, // Rsubhn_v
5540    0x0000000000000002, // Rsubhn2_v
5541    0x0000000000000002, // Saba_v
5542    0x0000000000000002, // Sabal_v
5543    0x0000000000000002, // Sabal2_v
5544    0x0000000000000002, // Sabd_v
5545    0x0000000000000002, // Sabdl_v
5546    0x0000000000000002, // Sabdl2_v
5547    0x0000000000000002, // Sadalp_v
5548    0x0000000000000002, // Saddl_v
5549    0x0000000000000002, // Saddl2_v
5550    0x0000000000000002, // Saddlp_v
5551    0x0000000000000002, // Saddlv_v
5552    0x0000000000000002, // Saddw_v
5553    0x0000000000000002, // Saddw2_v
5554    0x0000000000004002, // Scvtf_v
5555    0x0000000000000202, // Sdot_v
5556    0x0000000004000002, // Sha1c_v
5557    0x0000000004000002, // Sha1h_v
5558    0x0000000004000002, // Sha1m_v
5559    0x0000000004000002, // Sha1p_v
5560    0x0000000004000002, // Sha1su0_v
5561    0x0000000004000002, // Sha1su1_v
5562    0x0000000008000002, // Sha256h_v
5563    0x0000000008000002, // Sha256h2_v
5564    0x0000000008000002, // Sha256su0_v
5565    0x0000000008000002, // Sha256su1_v
5566    0x0000000020000002, // Sha512h_v
5567    0x0000000020000002, // Sha512h2_v
5568    0x0000000020000002, // Sha512su0_v
5569    0x0000000020000002, // Sha512su1_v
5570    0x0000000000000002, // Shadd_v
5571    0x0000000000000002, // Shl_v
5572    0x0000000000000002, // Shll_v
5573    0x0000000000000002, // Shll2_v
5574    0x0000000000000002, // Shrn_v
5575    0x0000000000000002, // Shrn2_v
5576    0x0000000000000002, // Shsub_v
5577    0x0000000000000002, // Sli_v
5578    0x0000000040000002, // Sm3partw1_v
5579    0x0000000040000002, // Sm3partw2_v
5580    0x0000000040000002, // Sm3ss1_v
5581    0x0000000040000002, // Sm3tt1a_v
5582    0x0000000040000002, // Sm3tt1b_v
5583    0x0000000040000002, // Sm3tt2a_v
5584    0x0000000040000002, // Sm3tt2b_v
5585    0x0000000080000002, // Sm4e_v
5586    0x0000000080000002, // Sm4ekey_v
5587    0x0000000000000002, // Smax_v
5588    0x0000000000000002, // Smaxp_v
5589    0x0000000000000002, // Smaxv_v
5590    0x0000000000000002, // Smin_v
5591    0x0000000000000002, // Sminp_v
5592    0x0000000000000002, // Sminv_v
5593    0x0000000000000002, // Smlal_v
5594    0x0000000000000002, // Smlal2_v
5595    0x0000000000000002, // Smlsl_v
5596    0x0000000000000002, // Smlsl2_v
5597    0x0000000000020002, // Smmla_v
5598    0x0000000000000002, // Smov_v
5599    0x0000000000000002, // Smull_v
5600    0x0000000000000002, // Smull2_v
5601    0x0000000000000002, // Sqabs_v
5602    0x0000000000000002, // Sqadd_v
5603    0x0000000000000002, // Sqdmlal_v
5604    0x0000000000000002, // Sqdmlal2_v
5605    0x0000000000000002, // Sqdmlsl_v
5606    0x0000000000000002, // Sqdmlsl2_v
5607    0x0000000000000002, // Sqdmulh_v
5608    0x0000000000000002, // Sqdmull_v
5609    0x0000000000000002, // Sqdmull2_v
5610    0x0000000000000002, // Sqneg_v
5611    0x0000000002000002, // Sqrdmlah_v
5612    0x0000000002000002, // Sqrdmlsh_v
5613    0x0000000000000002, // Sqrdmulh_v
5614    0x0000000000000002, // Sqrshl_v
5615    0x0000000000000002, // Sqrshrn_v
5616    0x0000000000000002, // Sqrshrn2_v
5617    0x0000000000000002, // Sqrshrun_v
5618    0x0000000000000002, // Sqrshrun2_v
5619    0x0000000000000002, // Sqshl_v
5620    0x0000000000000002, // Sqshlu_v
5621    0x0000000000000002, // Sqshrn_v
5622    0x0000000000000002, // Sqshrn2_v
5623    0x0000000000000002, // Sqshrun_v
5624    0x0000000000000002, // Sqshrun2_v
5625    0x0000000000000002, // Sqsub_v
5626    0x0000000000000002, // Sqxtn_v
5627    0x0000000000000002, // Sqxtn2_v
5628    0x0000000000000002, // Sqxtun_v
5629    0x0000000000000002, // Sqxtun2_v
5630    0x0000000000000002, // Srhadd_v
5631    0x0000000000000002, // Sri_v
5632    0x0000000000000002, // Srshl_v
5633    0x0000000000000002, // Srshr_v
5634    0x0000000000000002, // Srsra_v
5635    0x0000000000000002, // Sshl_v
5636    0x0000000000000002, // Sshll_v
5637    0x0000000000000002, // Sshll2_v
5638    0x0000000000000002, // Sshr_v
5639    0x0000000000000002, // Ssra_v
5640    0x0000000000000002, // Ssubl_v
5641    0x0000000000000002, // Ssubl2_v
5642    0x0000000000000002, // Ssubw_v
5643    0x0000000000000002, // Ssubw2_v
5644    0x0000000000000002, // St1_v
5645    0x0000000000000002, // St2_v
5646    0x0000000000000002, // St3_v
5647    0x0000000000000002, // St4_v
5648    0x0000000000000002, // Stnp_v
5649    0x0000000000000002, // Stp_v
5650    0x0000000000000002, // Str_v
5651    0x0000000000000002, // Stur_v
5652    0x0000000000000002, // Sub_v
5653    0x0000000000000002, // Subhn_v
5654    0x0000000000000002, // Subhn2_v
5655    0x0000000000020002, // Sudot_v
5656    0x0000000000000002, // Suqadd_v
5657    0x0000000000000002, // Sxtl_v
5658    0x0000000000000002, // Sxtl2_v
5659    0x0000000000000002, // Tbl_v
5660    0x0000000000000002, // Tbx_v
5661    0x0000000000000002, // Trn1_v
5662    0x0000000000000002, // Trn2_v
5663    0x0000000000000002, // Uaba_v
5664    0x0000000000000002, // Uabal_v
5665    0x0000000000000002, // Uabal2_v
5666    0x0000000000000002, // Uabd_v
5667    0x0000000000000002, // Uabdl_v
5668    0x0000000000000002, // Uabdl2_v
5669    0x0000000000000002, // Uadalp_v
5670    0x0000000000000002, // Uaddl_v
5671    0x0000000000000002, // Uaddl2_v
5672    0x0000000000000002, // Uaddlp_v
5673    0x0000000000000002, // Uaddlv_v
5674    0x0000000000000002, // Uaddw_v
5675    0x0000000000000002, // Uaddw2_v
5676    0x0000000000004002, // Ucvtf_v
5677    0x0000000000000202, // Udot_v
5678    0x0000000000000002, // Uhadd_v
5679    0x0000000000000002, // Uhsub_v
5680    0x0000000000000002, // Umax_v
5681    0x0000000000000002, // Umaxp_v
5682    0x0000000000000002, // Umaxv_v
5683    0x0000000000000002, // Umin_v
5684    0x0000000000000002, // Uminp_v
5685    0x0000000000000002, // Uminv_v
5686    0x0000000000000002, // Umlal_v
5687    0x0000000000000002, // Umlal2_v
5688    0x0000000000000002, // Umlsl_v
5689    0x0000000000000002, // Umlsl2_v
5690    0x0000000000020002, // Ummla_v
5691    0x0000000000000002, // Umov_v
5692    0x0000000000000002, // Umull_v
5693    0x0000000000000002, // Umull2_v
5694    0x0000000000000002, // Uqadd_v
5695    0x0000000000000002, // Uqrshl_v
5696    0x0000000000000002, // Uqrshrn_v
5697    0x0000000000000002, // Uqrshrn2_v
5698    0x0000000000000002, // Uqshl_v
5699    0x0000000000000002, // Uqshrn_v
5700    0x0000000000000002, // Uqshrn2_v
5701    0x0000000000000002, // Uqsub_v
5702    0x0000000000000002, // Uqxtn_v
5703    0x0000000000000002, // Uqxtn2_v
5704    0x0000000000000002, // Urecpe_v
5705    0x0000000000000002, // Urhadd_v
5706    0x0000000000000002, // Urshl_v
5707    0x0000000000000002, // Urshr_v
5708    0x0000000000000002, // Ursqrte_v
5709    0x0000000000000002, // Ursra_v
5710    0x0000000000020002, // Usdot_v
5711    0x0000000000000002, // Ushl_v
5712    0x0000000000000002, // Ushll_v
5713    0x0000000000000002, // Ushll2_v
5714    0x0000000000000002, // Ushr_v
5715    0x0000000000020002, // Usmmla_v
5716    0x0000000000000002, // Usqadd_v
5717    0x0000000000000002, // Usra_v
5718    0x0000000000000002, // Usubl_v
5719    0x0000000000000002, // Usubl2_v
5720    0x0000000000000002, // Usubw_v
5721    0x0000000000000002, // Usubw2_v
5722    0x0000000000000002, // Uxtl_v
5723    0x0000000000000002, // Uxtl2_v
5724    0x0000000000000002, // Uzp1_v
5725    0x0000000000000002, // Uzp2_v
5726    0x0000000010000002, // Xar_v
5727    0x0000000000000002, // Xtn_v
5728    0x0000000000000002, // Xtn2_v
5729    0x0000000000000002, // Zip1_v
5730    0x0000000000000002, // Zip2_v
5731];
5732
5733/// Requirements common to every form, indexed by `InstId as usize`.
5734static INST_BASE_FEATURE_MASKS: [u64; InstId::_Count as usize] = [
5735    0x0000000000000000, // None
5736    0x0000000000000080, // Abs
5737    0x0000000000000000, // Adc
5738    0x0000000000000000, // Adcs
5739    0x0000000000000000, // Add
5740    0x0000000000200000, // Addg
5741    0x0000000000000000, // Adds
5742    0x0000000000000000, // Adr
5743    0x0000000000000000, // Adrp
5744    0x0000000000000000, // And
5745    0x0000000000000000, // Ands
5746    0x0000000000000000, // Asr
5747    0x0000000000000000, // Asrv
5748    0x0000000000000000, // At
5749    0x0000000000800000, // Autda
5750    0x0000000000800000, // Autdza
5751    0x0000000000800000, // Autdb
5752    0x0000000000800000, // Autdzb
5753    0x0000000000800000, // Autia
5754    0x0000000000800000, // Autia1716
5755    0x0000000000800000, // Autiasp
5756    0x0000000000800000, // Autiaz
5757    0x0000000000800000, // Autib
5758    0x0000000000800000, // Autib1716
5759    0x0000000000800000, // Autibsp
5760    0x0000000000800000, // Autibz
5761    0x0000000000800000, // Autiza
5762    0x0000000000800000, // Autizb
5763    0x0000000000002000, // Axflag
5764    0x0000000000000000, // B
5765    0x0000000000000000, // Bc
5766    0x0000000000000000, // Bfc
5767    0x0000000000000000, // Bfi
5768    0x0000000000000000, // Bfm
5769    0x0000000000000000, // Bfxil
5770    0x0000000000000000, // Bic
5771    0x0000000000000000, // Bics
5772    0x0000000000000000, // Bl
5773    0x0000000000000000, // Blr
5774    0x0000000000000000, // Br
5775    0x0000000000000000, // Brk
5776    0x0000000000000008, // Bti
5777    0x0000000000100000, // Cas
5778    0x0000000000100000, // Casa
5779    0x0000000000100000, // Casab
5780    0x0000000000100000, // Casah
5781    0x0000000000100000, // Casal
5782    0x0000000000100000, // Casalb
5783    0x0000000000100000, // Casalh
5784    0x0000000000100000, // Casb
5785    0x0000000000100000, // Cash
5786    0x0000000000100000, // Casl
5787    0x0000000000100000, // Caslb
5788    0x0000000000100000, // Caslh
5789    0x0000000000100000, // Casp
5790    0x0000000000100000, // Caspa
5791    0x0000000000100000, // Caspal
5792    0x0000000000100000, // Caspl
5793    0x0000000000000000, // Cbnz
5794    0x0000000000000000, // Cbz
5795    0x0000000000000000, // Ccmn
5796    0x0000000000000000, // Ccmp
5797    0x0000000000001000, // Cfinv
5798    0x0000000000000010, // Chkfeat
5799    0x0000000000000000, // Cinc
5800    0x0000000000000000, // Cinv
5801    0x0000000000000020, // Clrbhb
5802    0x0000000000000000, // Clrex
5803    0x0000000000000000, // Cls
5804    0x0000000000000000, // Clz
5805    0x0000000000000000, // Cmn
5806    0x0000000000000000, // Cmp
5807    0x0000000000200000, // Cmpp
5808    0x0000000000000000, // Cneg
5809    0x0000000000000080, // Cnt
5810    0x0000000000000040, // Crc32b
5811    0x0000000000000040, // Crc32cb
5812    0x0000000000000040, // Crc32ch
5813    0x0000000000000040, // Crc32cw
5814    0x0000000000000040, // Crc32cx
5815    0x0000000000000040, // Crc32h
5816    0x0000000000000040, // Crc32w
5817    0x0000000000000040, // Crc32x
5818    0x0000000000000000, // Csdb
5819    0x0000000000000000, // Csel
5820    0x0000000000000000, // Cset
5821    0x0000000000000000, // Csetm
5822    0x0000000000000000, // Csinc
5823    0x0000000000000000, // Csinv
5824    0x0000000000000000, // Csneg
5825    0x0000000000000080, // Ctz
5826    0x0000000000000000, // Dc
5827    0x0000000000000000, // Dcps1
5828    0x0000000000000000, // Dcps2
5829    0x0000000000000000, // Dcps3
5830    0x0000000000000100, // Dgh
5831    0x0000000000000000, // Dmb
5832    0x0000000000000000, // Drps
5833    0x0000000000000000, // Dsb
5834    0x0000000000000000, // Eon
5835    0x0000000000000000, // Eor
5836    0x0000000001000000, // Esb
5837    0x0000000000000000, // Extr
5838    0x0000000000000000, // Eret
5839    0x0000000000200000, // Gmi
5840    0x0000000000000000, // Hint
5841    0x0000000000000000, // Hlt
5842    0x0000000000000000, // Hvc
5843    0x0000000000000000, // Ic
5844    0x0000000000000000, // Isb
5845    0x0000000000100000, // Ldadd
5846    0x0000000000100000, // Ldadda
5847    0x0000000000100000, // Ldaddab
5848    0x0000000000100000, // Ldaddah
5849    0x0000000000100000, // Ldaddal
5850    0x0000000000100000, // Ldaddalb
5851    0x0000000000100000, // Ldaddalh
5852    0x0000000000100000, // Ldaddb
5853    0x0000000000100000, // Ldaddh
5854    0x0000000000100000, // Ldaddl
5855    0x0000000000100000, // Ldaddlb
5856    0x0000000000100000, // Ldaddlh
5857    0x0000000000000000, // Ldar
5858    0x0000000000000000, // Ldarb
5859    0x0000000000000000, // Ldarh
5860    0x0000000000000000, // Ldaxp
5861    0x0000000000000000, // Ldaxr
5862    0x0000000000000000, // Ldaxrb
5863    0x0000000000000000, // Ldaxrh
5864    0x0000000000100000, // Ldclr
5865    0x0000000000100000, // Ldclra
5866    0x0000000000100000, // Ldclrab
5867    0x0000000000100000, // Ldclrah
5868    0x0000000000100000, // Ldclral
5869    0x0000000000100000, // Ldclralb
5870    0x0000000000100000, // Ldclralh
5871    0x0000000000100000, // Ldclrb
5872    0x0000000000100000, // Ldclrh
5873    0x0000000000100000, // Ldclrl
5874    0x0000000000100000, // Ldclrlb
5875    0x0000000000100000, // Ldclrlh
5876    0x0000000000100000, // Ldeor
5877    0x0000000000100000, // Ldeora
5878    0x0000000000100000, // Ldeorab
5879    0x0000000000100000, // Ldeorah
5880    0x0000000000100000, // Ldeoral
5881    0x0000000000100000, // Ldeoralb
5882    0x0000000000100000, // Ldeoralh
5883    0x0000000000100000, // Ldeorb
5884    0x0000000000100000, // Ldeorh
5885    0x0000000000100000, // Ldeorl
5886    0x0000000000100000, // Ldeorlb
5887    0x0000000000100000, // Ldeorlh
5888    0x0000000000200000, // Ldg
5889    0x0000000000400000, // Ldgm
5890    0x0000000000080000, // Ldlar
5891    0x0000000000080000, // Ldlarb
5892    0x0000000000080000, // Ldlarh
5893    0x0000000000000000, // Ldnp
5894    0x0000000000000000, // Ldp
5895    0x0000000000000000, // Ldpsw
5896    0x0000000000000000, // Ldr
5897    0x0000000000800000, // Ldraa
5898    0x0000000000800000, // Ldrab
5899    0x0000000000000000, // Ldrb
5900    0x0000000000000000, // Ldrh
5901    0x0000000000000000, // Ldrsb
5902    0x0000000000000000, // Ldrsh
5903    0x0000000000000000, // Ldrsw
5904    0x0000000000100000, // Ldset
5905    0x0000000000100000, // Ldseta
5906    0x0000000000100000, // Ldsetab
5907    0x0000000000100000, // Ldsetah
5908    0x0000000000100000, // Ldsetal
5909    0x0000000000100000, // Ldsetalb
5910    0x0000000000100000, // Ldsetalh
5911    0x0000000000100000, // Ldsetb
5912    0x0000000000100000, // Ldseth
5913    0x0000000000100000, // Ldsetl
5914    0x0000000000100000, // Ldsetlb
5915    0x0000000000100000, // Ldsetlh
5916    0x0000000000100000, // Ldsmax
5917    0x0000000000100000, // Ldsmaxa
5918    0x0000000000100000, // Ldsmaxab
5919    0x0000000000100000, // Ldsmaxah
5920    0x0000000000100000, // Ldsmaxal
5921    0x0000000000100000, // Ldsmaxalb
5922    0x0000000000100000, // Ldsmaxalh
5923    0x0000000000100000, // Ldsmaxb
5924    0x0000000000100000, // Ldsmaxh
5925    0x0000000000100000, // Ldsmaxl
5926    0x0000000000100000, // Ldsmaxlb
5927    0x0000000000100000, // Ldsmaxlh
5928    0x0000000000100000, // Ldsmin
5929    0x0000000000100000, // Ldsmina
5930    0x0000000000100000, // Ldsminab
5931    0x0000000000100000, // Ldsminah
5932    0x0000000000100000, // Ldsminal
5933    0x0000000000100000, // Ldsminalb
5934    0x0000000000100000, // Ldsminalh
5935    0x0000000000100000, // Ldsminb
5936    0x0000000000100000, // Ldsminh
5937    0x0000000000100000, // Ldsminl
5938    0x0000000000100000, // Ldsminlb
5939    0x0000000000100000, // Ldsminlh
5940    0x0000000000000000, // Ldtr
5941    0x0000000000000000, // Ldtrb
5942    0x0000000000000000, // Ldtrh
5943    0x0000000000000000, // Ldtrsb
5944    0x0000000000000000, // Ldtrsh
5945    0x0000000000000000, // Ldtrsw
5946    0x0000000000100000, // Ldumax
5947    0x0000000000100000, // Ldumaxa
5948    0x0000000000100000, // Ldumaxab
5949    0x0000000000100000, // Ldumaxah
5950    0x0000000000100000, // Ldumaxal
5951    0x0000000000100000, // Ldumaxalb
5952    0x0000000000100000, // Ldumaxalh
5953    0x0000000000100000, // Ldumaxb
5954    0x0000000000100000, // Ldumaxh
5955    0x0000000000100000, // Ldumaxl
5956    0x0000000000100000, // Ldumaxlb
5957    0x0000000000100000, // Ldumaxlh
5958    0x0000000000100000, // Ldumin
5959    0x0000000000100000, // Ldumina
5960    0x0000000000100000, // Lduminab
5961    0x0000000000100000, // Lduminah
5962    0x0000000000100000, // Lduminal
5963    0x0000000000100000, // Lduminalb
5964    0x0000000000100000, // Lduminalh
5965    0x0000000000100000, // Lduminb
5966    0x0000000000100000, // Lduminh
5967    0x0000000000100000, // Lduminl
5968    0x0000000000100000, // Lduminlb
5969    0x0000000000100000, // Lduminlh
5970    0x0000000000000000, // Ldur
5971    0x0000000000000000, // Ldurb
5972    0x0000000000000000, // Ldurh
5973    0x0000000000000000, // Ldursb
5974    0x0000000000000000, // Ldursh
5975    0x0000000000000000, // Ldursw
5976    0x0000000000000000, // Ldxp
5977    0x0000000000000000, // Ldxr
5978    0x0000000000000000, // Ldxrb
5979    0x0000000000000000, // Ldxrh
5980    0x0000000000000000, // Lsl
5981    0x0000000000000000, // Lslv
5982    0x0000000000000000, // Lsr
5983    0x0000000000000000, // Lsrv
5984    0x0000000000000000, // Madd
5985    0x0000000000000000, // Mneg
5986    0x0000000000000000, // Mov
5987    0x0000000000000000, // Movk
5988    0x0000000000000000, // Movn
5989    0x0000000000000000, // Movz
5990    0x0000000000000000, // Mrs
5991    0x0000000000000000, // Msr
5992    0x0000000000000000, // Msub
5993    0x0000000000000000, // Mul
5994    0x0000000000000000, // Mvn
5995    0x0000000000000000, // Neg
5996    0x0000000000000000, // Negs
5997    0x0000000000000000, // Ngc
5998    0x0000000000000000, // Ngcs
5999    0x0000000000000000, // Nop
6000    0x0000000000000000, // Orn
6001    0x0000000000000000, // Orr
6002    0x0000000000800000, // Pacda
6003    0x0000000000800000, // Pacdb
6004    0x0000000000800000, // Pacdza
6005    0x0000000000800000, // Pacdzb
6006    0x0000000000800000, // Pacga
6007    0x0000000000000000, // Prfm
6008    0x0000000000000000, // Pssbb
6009    0x0000000000000000, // Rbit
6010    0x0000000000000000, // Ret
6011    0x0000000000000000, // Rev
6012    0x0000000000000000, // Rev16
6013    0x0000000000000000, // Rev32
6014    0x0000000000000000, // Rev64
6015    0x0000000000000000, // Ror
6016    0x0000000000000000, // Rorv
6017    0x0000000000000000, // Sbc
6018    0x0000000000000000, // Sbcs
6019    0x0000000000000000, // Sbfiz
6020    0x0000000000000000, // Sbfm
6021    0x0000000000000000, // Sbfx
6022    0x0000000000000000, // Sdiv
6023    0x0000000000001000, // Setf8
6024    0x0000000000001000, // Setf16
6025    0x0000000000000000, // Sev
6026    0x0000000000000000, // Sevl
6027    0x0000000000000000, // Smaddl
6028    0x0000000000000080, // Smax
6029    0x0000000000000000, // Smc
6030    0x0000000000000080, // Smin
6031    0x0000000000000000, // Smnegl
6032    0x0000000000000000, // Smsubl
6033    0x0000000000000000, // Smulh
6034    0x0000000000000000, // Smull
6035    0x0000000000000000, // Ssbb
6036    0x0000000000200000, // St2g
6037    0x0000000000100000, // Stadd
6038    0x0000000000100000, // Staddl
6039    0x0000000000100000, // Staddb
6040    0x0000000000100000, // Staddlb
6041    0x0000000000100000, // Staddh
6042    0x0000000000100000, // Staddlh
6043    0x0000000000100000, // Stclr
6044    0x0000000000100000, // Stclrl
6045    0x0000000000100000, // Stclrb
6046    0x0000000000100000, // Stclrlb
6047    0x0000000000100000, // Stclrh
6048    0x0000000000100000, // Stclrlh
6049    0x0000000000100000, // Steor
6050    0x0000000000100000, // Steorl
6051    0x0000000000100000, // Steorb
6052    0x0000000000100000, // Steorlb
6053    0x0000000000100000, // Steorh
6054    0x0000000000100000, // Steorlh
6055    0x0000000000200000, // Stg
6056    0x0000000000400000, // Stgm
6057    0x0000000000200000, // Stgp
6058    0x0000000000080000, // Stllr
6059    0x0000000000080000, // Stllrb
6060    0x0000000000080000, // Stllrh
6061    0x0000000000000000, // Stlr
6062    0x0000000000000000, // Stlrb
6063    0x0000000000000000, // Stlrh
6064    0x0000000000000000, // Stlxp
6065    0x0000000000000000, // Stlxr
6066    0x0000000000000000, // Stlxrb
6067    0x0000000000000000, // Stlxrh
6068    0x0000000000000000, // Stnp
6069    0x0000000000000000, // Stp
6070    0x0000000000000000, // Str
6071    0x0000000000000000, // Strb
6072    0x0000000000000000, // Strh
6073    0x0000000000100000, // Stset
6074    0x0000000000100000, // Stsetl
6075    0x0000000000100000, // Stsetb
6076    0x0000000000100000, // Stsetlb
6077    0x0000000000100000, // Stseth
6078    0x0000000000100000, // Stsetlh
6079    0x0000000000100000, // Stsmax
6080    0x0000000000100000, // Stsmaxl
6081    0x0000000000100000, // Stsmaxb
6082    0x0000000000100000, // Stsmaxlb
6083    0x0000000000100000, // Stsmaxh
6084    0x0000000000100000, // Stsmaxlh
6085    0x0000000000100000, // Stsmin
6086    0x0000000000100000, // Stsminl
6087    0x0000000000100000, // Stsminb
6088    0x0000000000100000, // Stsminlb
6089    0x0000000000100000, // Stsminh
6090    0x0000000000100000, // Stsminlh
6091    0x0000000000000000, // Sttr
6092    0x0000000000000000, // Sttrb
6093    0x0000000000000000, // Sttrh
6094    0x0000000000100000, // Stumax
6095    0x0000000000100000, // Stumaxl
6096    0x0000000000100000, // Stumaxb
6097    0x0000000000100000, // Stumaxlb
6098    0x0000000000100000, // Stumaxh
6099    0x0000000000100000, // Stumaxlh
6100    0x0000000000100000, // Stumin
6101    0x0000000000100000, // Stuminl
6102    0x0000000000100000, // Stuminb
6103    0x0000000000100000, // Stuminlb
6104    0x0000000000100000, // Stuminh
6105    0x0000000000100000, // Stuminlh
6106    0x0000000000000000, // Stur
6107    0x0000000000000000, // Sturb
6108    0x0000000000000000, // Sturh
6109    0x0000000000000000, // Stxp
6110    0x0000000000000000, // Stxr
6111    0x0000000000000000, // Stxrb
6112    0x0000000000000000, // Stxrh
6113    0x0000000000200000, // Stz2g
6114    0x0000000000200000, // Stzg
6115    0x0000000000400000, // Stzgm
6116    0x0000000000000000, // Sub
6117    0x0000000000200000, // Subg
6118    0x0000000000200000, // Subp
6119    0x0000000000200000, // Subps
6120    0x0000000000000000, // Subs
6121    0x0000000000000000, // Svc
6122    0x0000000000100000, // Swp
6123    0x0000000000100000, // Swpa
6124    0x0000000000100000, // Swpab
6125    0x0000000000100000, // Swpah
6126    0x0000000000100000, // Swpal
6127    0x0000000000100000, // Swpalb
6128    0x0000000000100000, // Swpalh
6129    0x0000000000100000, // Swpb
6130    0x0000000000100000, // Swph
6131    0x0000000000100000, // Swpl
6132    0x0000000000100000, // Swplb
6133    0x0000000000100000, // Swplh
6134    0x0000000000000000, // Sxtb
6135    0x0000000000000000, // Sxth
6136    0x0000000000000000, // Sxtw
6137    0x0000000000000000, // Sys
6138    0x0000000000000000, // Tlbi
6139    0x0000000000000000, // Tst
6140    0x0000000000000000, // Tbnz
6141    0x0000000000000000, // Tbz
6142    0x0000000000000000, // Ubfiz
6143    0x0000000000000000, // Ubfm
6144    0x0000000000000000, // Ubfx
6145    0x0000000000000000, // Udf
6146    0x0000000000000000, // Udiv
6147    0x0000000000000000, // Umaddl
6148    0x0000000000000080, // Umax
6149    0x0000000000000080, // Umin
6150    0x0000000000000000, // Umnegl
6151    0x0000000000000000, // Umull
6152    0x0000000000000000, // Umulh
6153    0x0000000000000000, // Umsubl
6154    0x0000000000000000, // Uxtb
6155    0x0000000000000000, // Uxth
6156    0x0000000000000000, // Wfe
6157    0x0000000000000000, // Wfi
6158    0x0000000000002000, // Xaflag
6159    0x0000000000800000, // Xpacd
6160    0x0000000000800000, // Xpaci
6161    0x0000000000800000, // Xpaclri
6162    0x0000000000000000, // Yield
6163    0x0000000000000002, // Abs_v
6164    0x0000000000000002, // Add_v
6165    0x0000000000000002, // Addhn_v
6166    0x0000000000000002, // Addhn2_v
6167    0x0000000000000002, // Addp_v
6168    0x0000000000000002, // Addv_v
6169    0x0000000000000003, // Aesd_v
6170    0x0000000000000003, // Aese_v
6171    0x0000000000000003, // Aesimc_v
6172    0x0000000000000003, // Aesmc_v
6173    0x0000000000000002, // And_v
6174    0x0000000010000002, // Bcax_v
6175    0x0000000000000006, // Bfcvt_v
6176    0x0000000000000006, // Bfcvtn_v
6177    0x0000000000000006, // Bfcvtn2_v
6178    0x0000000000000006, // Bfdot_v
6179    0x0000000000000006, // Bfmlalb_v
6180    0x0000000000000006, // Bfmlalt_v
6181    0x0000000000000006, // Bfmmla_v
6182    0x0000000000000002, // Bic_v
6183    0x0000000000000002, // Bif_v
6184    0x0000000000000002, // Bit_v
6185    0x0000000000000002, // Bsl_v
6186    0x0000000000000002, // Cls_v
6187    0x0000000000000002, // Clz_v
6188    0x0000000000000002, // Cmeq_v
6189    0x0000000000000002, // Cmge_v
6190    0x0000000000000002, // Cmgt_v
6191    0x0000000000000002, // Cmhi_v
6192    0x0000000000000002, // Cmhs_v
6193    0x0000000000000002, // Cmle_v
6194    0x0000000000000002, // Cmlt_v
6195    0x0000000000000002, // Cmtst_v
6196    0x0000000000000002, // Cnt_v
6197    0x0000000000000002, // Dup_v
6198    0x0000000000000002, // Eor_v
6199    0x0000000010000002, // Eor3_v
6200    0x0000000000000002, // Ext_v
6201    0x0000000000000002, // Fabd_v
6202    0x0000000000000002, // Fabs_v
6203    0x0000000000000002, // Facge_v
6204    0x0000000000000002, // Facgt_v
6205    0x0000000000000002, // Fadd_v
6206    0x0000000000000002, // Faddp_v
6207    0x0000000000000402, // Fcadd_v
6208    0x0000000000000002, // Fccmp_v
6209    0x0000000000000002, // Fccmpe_v
6210    0x0000000000000002, // Fcmeq_v
6211    0x0000000000000002, // Fcmge_v
6212    0x0000000000000002, // Fcmgt_v
6213    0x0000000000000402, // Fcmla_v
6214    0x0000000000000002, // Fcmle_v
6215    0x0000000000000002, // Fcmlt_v
6216    0x0000000000000002, // Fcmp_v
6217    0x0000000000000002, // Fcmpe_v
6218    0x0000000000000002, // Fcsel_v
6219    0x0000000000000002, // Fcvt_v
6220    0x0000000000000002, // Fcvtas_v
6221    0x0000000000000002, // Fcvtau_v
6222    0x0000000000000002, // Fcvtl_v
6223    0x0000000000000002, // Fcvtl2_v
6224    0x0000000000000002, // Fcvtms_v
6225    0x0000000000000002, // Fcvtmu_v
6226    0x0000000000000002, // Fcvtn_v
6227    0x0000000000000002, // Fcvtn2_v
6228    0x0000000000000002, // Fcvtns_v
6229    0x0000000000000002, // Fcvtnu_v
6230    0x0000000000000002, // Fcvtps_v
6231    0x0000000000000002, // Fcvtpu_v
6232    0x0000000000000000, // Fcvtxn_v
6233    0x0000000000000000, // Fcvtxn2_v
6234    0x0000000000000002, // Fcvtzs_v
6235    0x0000000000000002, // Fcvtzu_v
6236    0x0000000000000002, // Fdiv_v
6237    0x0000000000040002, // Fjcvtzs_v
6238    0x0000000000000002, // Fmadd_v
6239    0x0000000000000002, // Fmax_v
6240    0x0000000000000002, // Fmaxnm_v
6241    0x0000000000000002, // Fmaxnmp_v
6242    0x0000000000000002, // Fmaxnmv_v
6243    0x0000000000000002, // Fmaxp_v
6244    0x0000000000000002, // Fmaxv_v
6245    0x0000000000000002, // Fmin_v
6246    0x0000000000000002, // Fminnm_v
6247    0x0000000000000002, // Fminnmp_v
6248    0x0000000000000002, // Fminnmv_v
6249    0x0000000000000002, // Fminp_v
6250    0x0000000000000002, // Fminv_v
6251    0x0000000000000002, // Fmla_v
6252    0x0000000000000802, // Fmlal_v
6253    0x0000000000000802, // Fmlal2_v
6254    0x0000000000000002, // Fmls_v
6255    0x0000000000000802, // Fmlsl_v
6256    0x0000000000000802, // Fmlsl2_v
6257    0x0000000000000002, // Fmov_v
6258    0x0000000000000002, // Fmsub_v
6259    0x0000000000000002, // Fmul_v
6260    0x0000000000000002, // Fmulx_v
6261    0x0000000000000002, // Fneg_v
6262    0x0000000000000002, // Fnmadd_v
6263    0x0000000000000002, // Fnmsub_v
6264    0x0000000000000002, // Fnmul_v
6265    0x0000000000000002, // Frecpe_v
6266    0x0000000000000002, // Frecps_v
6267    0x0000000000000002, // Frecpx_v
6268    0x0000000000010002, // Frint32x_v
6269    0x0000000000010002, // Frint32z_v
6270    0x0000000000010002, // Frint64x_v
6271    0x0000000000010002, // Frint64z_v
6272    0x0000000000000002, // Frinta_v
6273    0x0000000000000002, // Frinti_v
6274    0x0000000000000002, // Frintm_v
6275    0x0000000000000002, // Frintn_v
6276    0x0000000000000002, // Frintp_v
6277    0x0000000000000002, // Frintx_v
6278    0x0000000000000002, // Frintz_v
6279    0x0000000000000002, // Frsqrte_v
6280    0x0000000000000002, // Frsqrts_v
6281    0x0000000000000002, // Fsqrt_v
6282    0x0000000000000002, // Fsub_v
6283    0x0000000000000002, // Ins_v
6284    0x0000000000000002, // Ld1_v
6285    0x0000000000000002, // Ld1r_v
6286    0x0000000000000002, // Ld2_v
6287    0x0000000000000002, // Ld2r_v
6288    0x0000000000000002, // Ld3_v
6289    0x0000000000000002, // Ld3r_v
6290    0x0000000000000002, // Ld4_v
6291    0x0000000000000002, // Ld4r_v
6292    0x0000000000000002, // Ldnp_v
6293    0x0000000000000002, // Ldp_v
6294    0x0000000000000002, // Ldr_v
6295    0x0000000000000002, // Ldur_v
6296    0x0000000000000002, // Mla_v
6297    0x0000000000000002, // Mls_v
6298    0x0000000000000002, // Mov_v
6299    0x0000000000000002, // Movi_v
6300    0x0000000000000002, // Mul_v
6301    0x0000000000000002, // Mvn_v
6302    0x0000000000000002, // Mvni_v
6303    0x0000000000000002, // Neg_v
6304    0x0000000000000002, // Not_v
6305    0x0000000000000002, // Orn_v
6306    0x0000000000000002, // Orr_v
6307    0x0000000000000002, // Pmul_v
6308    0x0000000000000002, // Pmull_v
6309    0x0000000000000002, // Pmull2_v
6310    0x0000000000000002, // Raddhn_v
6311    0x0000000000000002, // Raddhn2_v
6312    0x0000000010000002, // Rax1_v
6313    0x0000000000000002, // Rbit_v
6314    0x0000000000000002, // Rev16_v
6315    0x0000000000000002, // Rev32_v
6316    0x0000000000000002, // Rev64_v
6317    0x0000000000000002, // Rshrn_v
6318    0x0000000000000002, // Rshrn2_v
6319    0x0000000000000002, // Rsubhn_v
6320    0x0000000000000002, // Rsubhn2_v
6321    0x0000000000000002, // Saba_v
6322    0x0000000000000002, // Sabal_v
6323    0x0000000000000002, // Sabal2_v
6324    0x0000000000000002, // Sabd_v
6325    0x0000000000000002, // Sabdl_v
6326    0x0000000000000002, // Sabdl2_v
6327    0x0000000000000002, // Sadalp_v
6328    0x0000000000000002, // Saddl_v
6329    0x0000000000000002, // Saddl2_v
6330    0x0000000000000002, // Saddlp_v
6331    0x0000000000000002, // Saddlv_v
6332    0x0000000000000002, // Saddw_v
6333    0x0000000000000002, // Saddw2_v
6334    0x0000000000000002, // Scvtf_v
6335    0x0000000000000202, // Sdot_v
6336    0x0000000004000002, // Sha1c_v
6337    0x0000000004000002, // Sha1h_v
6338    0x0000000004000002, // Sha1m_v
6339    0x0000000004000002, // Sha1p_v
6340    0x0000000004000002, // Sha1su0_v
6341    0x0000000004000002, // Sha1su1_v
6342    0x0000000008000002, // Sha256h_v
6343    0x0000000008000002, // Sha256h2_v
6344    0x0000000008000002, // Sha256su0_v
6345    0x0000000008000002, // Sha256su1_v
6346    0x0000000020000002, // Sha512h_v
6347    0x0000000020000002, // Sha512h2_v
6348    0x0000000020000002, // Sha512su0_v
6349    0x0000000020000002, // Sha512su1_v
6350    0x0000000000000002, // Shadd_v
6351    0x0000000000000002, // Shl_v
6352    0x0000000000000002, // Shll_v
6353    0x0000000000000002, // Shll2_v
6354    0x0000000000000002, // Shrn_v
6355    0x0000000000000002, // Shrn2_v
6356    0x0000000000000002, // Shsub_v
6357    0x0000000000000002, // Sli_v
6358    0x0000000040000002, // Sm3partw1_v
6359    0x0000000040000002, // Sm3partw2_v
6360    0x0000000040000002, // Sm3ss1_v
6361    0x0000000040000002, // Sm3tt1a_v
6362    0x0000000040000002, // Sm3tt1b_v
6363    0x0000000040000002, // Sm3tt2a_v
6364    0x0000000040000002, // Sm3tt2b_v
6365    0x0000000080000002, // Sm4e_v
6366    0x0000000080000002, // Sm4ekey_v
6367    0x0000000000000002, // Smax_v
6368    0x0000000000000002, // Smaxp_v
6369    0x0000000000000002, // Smaxv_v
6370    0x0000000000000002, // Smin_v
6371    0x0000000000000002, // Sminp_v
6372    0x0000000000000002, // Sminv_v
6373    0x0000000000000002, // Smlal_v
6374    0x0000000000000002, // Smlal2_v
6375    0x0000000000000002, // Smlsl_v
6376    0x0000000000000002, // Smlsl2_v
6377    0x0000000000020002, // Smmla_v
6378    0x0000000000000002, // Smov_v
6379    0x0000000000000002, // Smull_v
6380    0x0000000000000002, // Smull2_v
6381    0x0000000000000002, // Sqabs_v
6382    0x0000000000000002, // Sqadd_v
6383    0x0000000000000002, // Sqdmlal_v
6384    0x0000000000000002, // Sqdmlal2_v
6385    0x0000000000000002, // Sqdmlsl_v
6386    0x0000000000000002, // Sqdmlsl2_v
6387    0x0000000000000002, // Sqdmulh_v
6388    0x0000000000000002, // Sqdmull_v
6389    0x0000000000000002, // Sqdmull2_v
6390    0x0000000000000002, // Sqneg_v
6391    0x0000000002000002, // Sqrdmlah_v
6392    0x0000000002000002, // Sqrdmlsh_v
6393    0x0000000000000002, // Sqrdmulh_v
6394    0x0000000000000002, // Sqrshl_v
6395    0x0000000000000002, // Sqrshrn_v
6396    0x0000000000000002, // Sqrshrn2_v
6397    0x0000000000000002, // Sqrshrun_v
6398    0x0000000000000002, // Sqrshrun2_v
6399    0x0000000000000002, // Sqshl_v
6400    0x0000000000000002, // Sqshlu_v
6401    0x0000000000000002, // Sqshrn_v
6402    0x0000000000000002, // Sqshrn2_v
6403    0x0000000000000002, // Sqshrun_v
6404    0x0000000000000002, // Sqshrun2_v
6405    0x0000000000000002, // Sqsub_v
6406    0x0000000000000002, // Sqxtn_v
6407    0x0000000000000002, // Sqxtn2_v
6408    0x0000000000000002, // Sqxtun_v
6409    0x0000000000000002, // Sqxtun2_v
6410    0x0000000000000002, // Srhadd_v
6411    0x0000000000000002, // Sri_v
6412    0x0000000000000002, // Srshl_v
6413    0x0000000000000002, // Srshr_v
6414    0x0000000000000002, // Srsra_v
6415    0x0000000000000002, // Sshl_v
6416    0x0000000000000002, // Sshll_v
6417    0x0000000000000002, // Sshll2_v
6418    0x0000000000000002, // Sshr_v
6419    0x0000000000000002, // Ssra_v
6420    0x0000000000000002, // Ssubl_v
6421    0x0000000000000002, // Ssubl2_v
6422    0x0000000000000002, // Ssubw_v
6423    0x0000000000000002, // Ssubw2_v
6424    0x0000000000000002, // St1_v
6425    0x0000000000000002, // St2_v
6426    0x0000000000000002, // St3_v
6427    0x0000000000000002, // St4_v
6428    0x0000000000000002, // Stnp_v
6429    0x0000000000000002, // Stp_v
6430    0x0000000000000002, // Str_v
6431    0x0000000000000002, // Stur_v
6432    0x0000000000000002, // Sub_v
6433    0x0000000000000002, // Subhn_v
6434    0x0000000000000002, // Subhn2_v
6435    0x0000000000020002, // Sudot_v
6436    0x0000000000000002, // Suqadd_v
6437    0x0000000000000002, // Sxtl_v
6438    0x0000000000000002, // Sxtl2_v
6439    0x0000000000000002, // Tbl_v
6440    0x0000000000000002, // Tbx_v
6441    0x0000000000000002, // Trn1_v
6442    0x0000000000000002, // Trn2_v
6443    0x0000000000000002, // Uaba_v
6444    0x0000000000000002, // Uabal_v
6445    0x0000000000000002, // Uabal2_v
6446    0x0000000000000002, // Uabd_v
6447    0x0000000000000002, // Uabdl_v
6448    0x0000000000000002, // Uabdl2_v
6449    0x0000000000000002, // Uadalp_v
6450    0x0000000000000002, // Uaddl_v
6451    0x0000000000000002, // Uaddl2_v
6452    0x0000000000000002, // Uaddlp_v
6453    0x0000000000000002, // Uaddlv_v
6454    0x0000000000000002, // Uaddw_v
6455    0x0000000000000002, // Uaddw2_v
6456    0x0000000000000002, // Ucvtf_v
6457    0x0000000000000202, // Udot_v
6458    0x0000000000000002, // Uhadd_v
6459    0x0000000000000002, // Uhsub_v
6460    0x0000000000000002, // Umax_v
6461    0x0000000000000002, // Umaxp_v
6462    0x0000000000000002, // Umaxv_v
6463    0x0000000000000002, // Umin_v
6464    0x0000000000000002, // Uminp_v
6465    0x0000000000000002, // Uminv_v
6466    0x0000000000000002, // Umlal_v
6467    0x0000000000000002, // Umlal2_v
6468    0x0000000000000002, // Umlsl_v
6469    0x0000000000000002, // Umlsl2_v
6470    0x0000000000020002, // Ummla_v
6471    0x0000000000000002, // Umov_v
6472    0x0000000000000002, // Umull_v
6473    0x0000000000000002, // Umull2_v
6474    0x0000000000000002, // Uqadd_v
6475    0x0000000000000002, // Uqrshl_v
6476    0x0000000000000002, // Uqrshrn_v
6477    0x0000000000000002, // Uqrshrn2_v
6478    0x0000000000000002, // Uqshl_v
6479    0x0000000000000002, // Uqshrn_v
6480    0x0000000000000002, // Uqshrn2_v
6481    0x0000000000000002, // Uqsub_v
6482    0x0000000000000002, // Uqxtn_v
6483    0x0000000000000002, // Uqxtn2_v
6484    0x0000000000000002, // Urecpe_v
6485    0x0000000000000002, // Urhadd_v
6486    0x0000000000000002, // Urshl_v
6487    0x0000000000000002, // Urshr_v
6488    0x0000000000000002, // Ursqrte_v
6489    0x0000000000000002, // Ursra_v
6490    0x0000000000020002, // Usdot_v
6491    0x0000000000000002, // Ushl_v
6492    0x0000000000000002, // Ushll_v
6493    0x0000000000000002, // Ushll2_v
6494    0x0000000000000002, // Ushr_v
6495    0x0000000000020002, // Usmmla_v
6496    0x0000000000000002, // Usqadd_v
6497    0x0000000000000002, // Usra_v
6498    0x0000000000000002, // Usubl_v
6499    0x0000000000000002, // Usubl2_v
6500    0x0000000000000002, // Usubw_v
6501    0x0000000000000002, // Usubw2_v
6502    0x0000000000000002, // Uxtl_v
6503    0x0000000000000002, // Uxtl2_v
6504    0x0000000000000002, // Uzp1_v
6505    0x0000000000000002, // Uzp2_v
6506    0x0000000010000002, // Xar_v
6507    0x0000000000000002, // Xtn_v
6508    0x0000000000000002, // Xtn2_v
6509    0x0000000000000002, // Zip1_v
6510    0x0000000000000002, // Zip2_v
6511];
6512
6513static INST_BASE_FEATURE_CONTEXT: [&str; InstId::_Count as usize] = [
6514    "",
6515    "abs requires: CSSC",
6516    "",
6517    "",
6518    "",
6519    "addg requires: MTE",
6520    "",
6521    "",
6522    "",
6523    "",
6524    "",
6525    "",
6526    "",
6527    "",
6528    "autda requires: PAUTH",
6529    "autdza requires: PAUTH",
6530    "autdb requires: PAUTH",
6531    "autdzb requires: PAUTH",
6532    "autia requires: PAUTH",
6533    "autia1716 requires: PAUTH",
6534    "autiasp requires: PAUTH",
6535    "autiaz requires: PAUTH",
6536    "autib requires: PAUTH",
6537    "autib1716 requires: PAUTH",
6538    "autibsp requires: PAUTH",
6539    "autibz requires: PAUTH",
6540    "autiza requires: PAUTH",
6541    "autizb requires: PAUTH",
6542    "axflag requires: FLAGM2",
6543    "",
6544    "",
6545    "",
6546    "",
6547    "",
6548    "",
6549    "",
6550    "",
6551    "",
6552    "",
6553    "",
6554    "",
6555    "bti requires: BTI",
6556    "cas requires: LSE",
6557    "casa requires: LSE",
6558    "casab requires: LSE",
6559    "casah requires: LSE",
6560    "casal requires: LSE",
6561    "casalb requires: LSE",
6562    "casalh requires: LSE",
6563    "casb requires: LSE",
6564    "cash requires: LSE",
6565    "casl requires: LSE",
6566    "caslb requires: LSE",
6567    "caslh requires: LSE",
6568    "casp requires: LSE",
6569    "caspa requires: LSE",
6570    "caspal requires: LSE",
6571    "caspl requires: LSE",
6572    "",
6573    "",
6574    "",
6575    "",
6576    "cfinv requires: FLAGM",
6577    "chkfeat requires: CHK",
6578    "",
6579    "",
6580    "clrbhb requires: CLRBHB",
6581    "",
6582    "",
6583    "",
6584    "",
6585    "",
6586    "cmpp requires: MTE",
6587    "",
6588    "cnt requires: CSSC",
6589    "crc32b requires: CRC32",
6590    "crc32cb requires: CRC32",
6591    "crc32ch requires: CRC32",
6592    "crc32cw requires: CRC32",
6593    "crc32cx requires: CRC32",
6594    "crc32h requires: CRC32",
6595    "crc32w requires: CRC32",
6596    "crc32x requires: CRC32",
6597    "",
6598    "",
6599    "",
6600    "",
6601    "",
6602    "",
6603    "",
6604    "ctz requires: CSSC",
6605    "",
6606    "",
6607    "",
6608    "",
6609    "dgh requires: DGH",
6610    "",
6611    "",
6612    "",
6613    "",
6614    "",
6615    "esb requires: RAS",
6616    "",
6617    "",
6618    "gmi requires: MTE",
6619    "",
6620    "",
6621    "",
6622    "",
6623    "",
6624    "ldadd requires: LSE",
6625    "ldadda requires: LSE",
6626    "ldaddab requires: LSE",
6627    "ldaddah requires: LSE",
6628    "ldaddal requires: LSE",
6629    "ldaddalb requires: LSE",
6630    "ldaddalh requires: LSE",
6631    "ldaddb requires: LSE",
6632    "ldaddh requires: LSE",
6633    "ldaddl requires: LSE",
6634    "ldaddlb requires: LSE",
6635    "ldaddlh requires: LSE",
6636    "",
6637    "",
6638    "",
6639    "",
6640    "",
6641    "",
6642    "",
6643    "ldclr requires: LSE",
6644    "ldclra requires: LSE",
6645    "ldclrab requires: LSE",
6646    "ldclrah requires: LSE",
6647    "ldclral requires: LSE",
6648    "ldclralb requires: LSE",
6649    "ldclralh requires: LSE",
6650    "ldclrb requires: LSE",
6651    "ldclrh requires: LSE",
6652    "ldclrl requires: LSE",
6653    "ldclrlb requires: LSE",
6654    "ldclrlh requires: LSE",
6655    "ldeor requires: LSE",
6656    "ldeora requires: LSE",
6657    "ldeorab requires: LSE",
6658    "ldeorah requires: LSE",
6659    "ldeoral requires: LSE",
6660    "ldeoralb requires: LSE",
6661    "ldeoralh requires: LSE",
6662    "ldeorb requires: LSE",
6663    "ldeorh requires: LSE",
6664    "ldeorl requires: LSE",
6665    "ldeorlb requires: LSE",
6666    "ldeorlh requires: LSE",
6667    "ldg requires: MTE",
6668    "ldgm requires: MTE2",
6669    "ldlar requires: LOR",
6670    "ldlarb requires: LOR",
6671    "ldlarh requires: LOR",
6672    "",
6673    "",
6674    "",
6675    "",
6676    "ldraa requires: PAUTH",
6677    "ldrab requires: PAUTH",
6678    "",
6679    "",
6680    "",
6681    "",
6682    "",
6683    "ldset requires: LSE",
6684    "ldseta requires: LSE",
6685    "ldsetab requires: LSE",
6686    "ldsetah requires: LSE",
6687    "ldsetal requires: LSE",
6688    "ldsetalb requires: LSE",
6689    "ldsetalh requires: LSE",
6690    "ldsetb requires: LSE",
6691    "ldseth requires: LSE",
6692    "ldsetl requires: LSE",
6693    "ldsetlb requires: LSE",
6694    "ldsetlh requires: LSE",
6695    "ldsmax requires: LSE",
6696    "ldsmaxa requires: LSE",
6697    "ldsmaxab requires: LSE",
6698    "ldsmaxah requires: LSE",
6699    "ldsmaxal requires: LSE",
6700    "ldsmaxalb requires: LSE",
6701    "ldsmaxalh requires: LSE",
6702    "ldsmaxb requires: LSE",
6703    "ldsmaxh requires: LSE",
6704    "ldsmaxl requires: LSE",
6705    "ldsmaxlb requires: LSE",
6706    "ldsmaxlh requires: LSE",
6707    "ldsmin requires: LSE",
6708    "ldsmina requires: LSE",
6709    "ldsminab requires: LSE",
6710    "ldsminah requires: LSE",
6711    "ldsminal requires: LSE",
6712    "ldsminalb requires: LSE",
6713    "ldsminalh requires: LSE",
6714    "ldsminb requires: LSE",
6715    "ldsminh requires: LSE",
6716    "ldsminl requires: LSE",
6717    "ldsminlb requires: LSE",
6718    "ldsminlh requires: LSE",
6719    "",
6720    "",
6721    "",
6722    "",
6723    "",
6724    "",
6725    "ldumax requires: LSE",
6726    "ldumaxa requires: LSE",
6727    "ldumaxab requires: LSE",
6728    "ldumaxah requires: LSE",
6729    "ldumaxal requires: LSE",
6730    "ldumaxalb requires: LSE",
6731    "ldumaxalh requires: LSE",
6732    "ldumaxb requires: LSE",
6733    "ldumaxh requires: LSE",
6734    "ldumaxl requires: LSE",
6735    "ldumaxlb requires: LSE",
6736    "ldumaxlh requires: LSE",
6737    "ldumin requires: LSE",
6738    "ldumina requires: LSE",
6739    "lduminab requires: LSE",
6740    "lduminah requires: LSE",
6741    "lduminal requires: LSE",
6742    "lduminalb requires: LSE",
6743    "lduminalh requires: LSE",
6744    "lduminb requires: LSE",
6745    "lduminh requires: LSE",
6746    "lduminl requires: LSE",
6747    "lduminlb requires: LSE",
6748    "lduminlh requires: LSE",
6749    "",
6750    "",
6751    "",
6752    "",
6753    "",
6754    "",
6755    "",
6756    "",
6757    "",
6758    "",
6759    "",
6760    "",
6761    "",
6762    "",
6763    "",
6764    "",
6765    "",
6766    "",
6767    "",
6768    "",
6769    "",
6770    "",
6771    "",
6772    "",
6773    "",
6774    "",
6775    "",
6776    "",
6777    "",
6778    "",
6779    "",
6780    "",
6781    "pacda requires: PAUTH",
6782    "pacdb requires: PAUTH",
6783    "pacdza requires: PAUTH",
6784    "pacdzb requires: PAUTH",
6785    "pacga requires: PAUTH",
6786    "",
6787    "",
6788    "",
6789    "",
6790    "",
6791    "",
6792    "",
6793    "",
6794    "",
6795    "",
6796    "",
6797    "",
6798    "",
6799    "",
6800    "",
6801    "",
6802    "setf8 requires: FLAGM",
6803    "setf16 requires: FLAGM",
6804    "",
6805    "",
6806    "",
6807    "smax requires: CSSC",
6808    "",
6809    "smin requires: CSSC",
6810    "",
6811    "",
6812    "",
6813    "",
6814    "",
6815    "st2g requires: MTE",
6816    "stadd requires: LSE",
6817    "staddl requires: LSE",
6818    "staddb requires: LSE",
6819    "staddlb requires: LSE",
6820    "staddh requires: LSE",
6821    "staddlh requires: LSE",
6822    "stclr requires: LSE",
6823    "stclrl requires: LSE",
6824    "stclrb requires: LSE",
6825    "stclrlb requires: LSE",
6826    "stclrh requires: LSE",
6827    "stclrlh requires: LSE",
6828    "steor requires: LSE",
6829    "steorl requires: LSE",
6830    "steorb requires: LSE",
6831    "steorlb requires: LSE",
6832    "steorh requires: LSE",
6833    "steorlh requires: LSE",
6834    "stg requires: MTE",
6835    "stgm requires: MTE2",
6836    "stgp requires: MTE",
6837    "stllr requires: LOR",
6838    "stllrb requires: LOR",
6839    "stllrh requires: LOR",
6840    "",
6841    "",
6842    "",
6843    "",
6844    "",
6845    "",
6846    "",
6847    "",
6848    "",
6849    "",
6850    "",
6851    "",
6852    "stset requires: LSE",
6853    "stsetl requires: LSE",
6854    "stsetb requires: LSE",
6855    "stsetlb requires: LSE",
6856    "stseth requires: LSE",
6857    "stsetlh requires: LSE",
6858    "stsmax requires: LSE",
6859    "stsmaxl requires: LSE",
6860    "stsmaxb requires: LSE",
6861    "stsmaxlb requires: LSE",
6862    "stsmaxh requires: LSE",
6863    "stsmaxlh requires: LSE",
6864    "stsmin requires: LSE",
6865    "stsminl requires: LSE",
6866    "stsminb requires: LSE",
6867    "stsminlb requires: LSE",
6868    "stsminh requires: LSE",
6869    "stsminlh requires: LSE",
6870    "",
6871    "",
6872    "",
6873    "stumax requires: LSE",
6874    "stumaxl requires: LSE",
6875    "stumaxb requires: LSE",
6876    "stumaxlb requires: LSE",
6877    "stumaxh requires: LSE",
6878    "stumaxlh requires: LSE",
6879    "stumin requires: LSE",
6880    "stuminl requires: LSE",
6881    "stuminb requires: LSE",
6882    "stuminlb requires: LSE",
6883    "stuminh requires: LSE",
6884    "stuminlh requires: LSE",
6885    "",
6886    "",
6887    "",
6888    "",
6889    "",
6890    "",
6891    "",
6892    "stz2g requires: MTE",
6893    "stzg requires: MTE",
6894    "stzgm requires: MTE2",
6895    "",
6896    "subg requires: MTE",
6897    "subp requires: MTE",
6898    "subps requires: MTE",
6899    "",
6900    "",
6901    "swp requires: LSE",
6902    "swpa requires: LSE",
6903    "swpab requires: LSE",
6904    "swpah requires: LSE",
6905    "swpal requires: LSE",
6906    "swpalb requires: LSE",
6907    "swpalh requires: LSE",
6908    "swpb requires: LSE",
6909    "swph requires: LSE",
6910    "swpl requires: LSE",
6911    "swplb requires: LSE",
6912    "swplh requires: LSE",
6913    "",
6914    "",
6915    "",
6916    "",
6917    "",
6918    "",
6919    "",
6920    "",
6921    "",
6922    "",
6923    "",
6924    "",
6925    "",
6926    "",
6927    "umax requires: CSSC",
6928    "umin requires: CSSC",
6929    "",
6930    "",
6931    "",
6932    "",
6933    "",
6934    "",
6935    "",
6936    "",
6937    "xaflag requires: FLAGM2",
6938    "xpacd requires: PAUTH",
6939    "xpaci requires: PAUTH",
6940    "xpaclri requires: PAUTH",
6941    "",
6942    "abs requires: ASIMD",
6943    "add requires: ASIMD",
6944    "addhn requires: ASIMD",
6945    "addhn2 requires: ASIMD",
6946    "addp requires: ASIMD",
6947    "addv requires: ASIMD",
6948    "aesd requires: AES, ASIMD",
6949    "aese requires: AES, ASIMD",
6950    "aesimc requires: AES, ASIMD",
6951    "aesmc requires: AES, ASIMD",
6952    "and requires: ASIMD",
6953    "bcax requires: ASIMD, SHA3",
6954    "bfcvt requires: ASIMD, BF16",
6955    "bfcvtn requires: ASIMD, BF16",
6956    "bfcvtn2 requires: ASIMD, BF16",
6957    "bfdot requires: ASIMD, BF16",
6958    "bfmlalb requires: ASIMD, BF16",
6959    "bfmlalt requires: ASIMD, BF16",
6960    "bfmmla requires: ASIMD, BF16",
6961    "bic requires: ASIMD",
6962    "bif requires: ASIMD",
6963    "bit requires: ASIMD",
6964    "bsl requires: ASIMD",
6965    "cls requires: ASIMD",
6966    "clz requires: ASIMD",
6967    "cmeq requires: ASIMD",
6968    "cmge requires: ASIMD",
6969    "cmgt requires: ASIMD",
6970    "cmhi requires: ASIMD",
6971    "cmhs requires: ASIMD",
6972    "cmle requires: ASIMD",
6973    "cmlt requires: ASIMD",
6974    "cmtst requires: ASIMD",
6975    "cnt requires: ASIMD",
6976    "dup requires: ASIMD",
6977    "eor requires: ASIMD",
6978    "eor3 requires: ASIMD, SHA3",
6979    "ext requires: ASIMD",
6980    "fabd requires: ASIMD",
6981    "fabs requires: ASIMD",
6982    "facge requires: ASIMD",
6983    "facgt requires: ASIMD",
6984    "fadd requires: ASIMD",
6985    "faddp requires: ASIMD",
6986    "fcadd requires: ASIMD, FCMA",
6987    "fccmp requires: ASIMD",
6988    "fccmpe requires: ASIMD",
6989    "fcmeq requires: ASIMD",
6990    "fcmge requires: ASIMD",
6991    "fcmgt requires: ASIMD",
6992    "fcmla requires: ASIMD, FCMA",
6993    "fcmle requires: ASIMD",
6994    "fcmlt requires: ASIMD",
6995    "fcmp requires: ASIMD",
6996    "fcmpe requires: ASIMD",
6997    "fcsel requires: ASIMD",
6998    "fcvt requires: ASIMD",
6999    "fcvtas requires: ASIMD",
7000    "fcvtau requires: ASIMD",
7001    "fcvtl requires: ASIMD",
7002    "fcvtl2 requires: ASIMD",
7003    "fcvtms requires: ASIMD",
7004    "fcvtmu requires: ASIMD",
7005    "fcvtn requires: ASIMD",
7006    "fcvtn2 requires: ASIMD",
7007    "fcvtns requires: ASIMD",
7008    "fcvtnu requires: ASIMD",
7009    "fcvtps requires: ASIMD",
7010    "fcvtpu requires: ASIMD",
7011    "",
7012    "",
7013    "fcvtzs requires: ASIMD",
7014    "fcvtzu requires: ASIMD",
7015    "fdiv requires: ASIMD",
7016    "fjcvtzs requires: ASIMD, JSCVT",
7017    "fmadd requires: ASIMD",
7018    "fmax requires: ASIMD",
7019    "fmaxnm requires: ASIMD",
7020    "fmaxnmp requires: ASIMD",
7021    "fmaxnmv requires: ASIMD",
7022    "fmaxp requires: ASIMD",
7023    "fmaxv requires: ASIMD",
7024    "fmin requires: ASIMD",
7025    "fminnm requires: ASIMD",
7026    "fminnmp requires: ASIMD",
7027    "fminnmv requires: ASIMD",
7028    "fminp requires: ASIMD",
7029    "fminv requires: ASIMD",
7030    "fmla requires: ASIMD",
7031    "fmlal requires: ASIMD, FHM",
7032    "fmlal2 requires: ASIMD, FHM",
7033    "fmls requires: ASIMD",
7034    "fmlsl requires: ASIMD, FHM",
7035    "fmlsl2 requires: ASIMD, FHM",
7036    "fmov requires: ASIMD",
7037    "fmsub requires: ASIMD",
7038    "fmul requires: ASIMD",
7039    "fmulx requires: ASIMD",
7040    "fneg requires: ASIMD",
7041    "fnmadd requires: ASIMD",
7042    "fnmsub requires: ASIMD",
7043    "fnmul requires: ASIMD",
7044    "frecpe requires: ASIMD",
7045    "frecps requires: ASIMD",
7046    "frecpx requires: ASIMD",
7047    "frint32x requires: ASIMD, FRINTTS",
7048    "frint32z requires: ASIMD, FRINTTS",
7049    "frint64x requires: ASIMD, FRINTTS",
7050    "frint64z requires: ASIMD, FRINTTS",
7051    "frinta requires: ASIMD",
7052    "frinti requires: ASIMD",
7053    "frintm requires: ASIMD",
7054    "frintn requires: ASIMD",
7055    "frintp requires: ASIMD",
7056    "frintx requires: ASIMD",
7057    "frintz requires: ASIMD",
7058    "frsqrte requires: ASIMD",
7059    "frsqrts requires: ASIMD",
7060    "fsqrt requires: ASIMD",
7061    "fsub requires: ASIMD",
7062    "ins requires: ASIMD",
7063    "ld1 requires: ASIMD",
7064    "ld1r requires: ASIMD",
7065    "ld2 requires: ASIMD",
7066    "ld2r requires: ASIMD",
7067    "ld3 requires: ASIMD",
7068    "ld3r requires: ASIMD",
7069    "ld4 requires: ASIMD",
7070    "ld4r requires: ASIMD",
7071    "ldnp requires: ASIMD",
7072    "ldp requires: ASIMD",
7073    "ldr requires: ASIMD",
7074    "ldur requires: ASIMD",
7075    "mla requires: ASIMD",
7076    "mls requires: ASIMD",
7077    "mov requires: ASIMD",
7078    "movi requires: ASIMD",
7079    "mul requires: ASIMD",
7080    "mvn requires: ASIMD",
7081    "mvni requires: ASIMD",
7082    "neg requires: ASIMD",
7083    "not requires: ASIMD",
7084    "orn requires: ASIMD",
7085    "orr requires: ASIMD",
7086    "pmul requires: ASIMD",
7087    "pmull requires: ASIMD",
7088    "pmull2 requires: ASIMD",
7089    "raddhn requires: ASIMD",
7090    "raddhn2 requires: ASIMD",
7091    "rax1 requires: ASIMD, SHA3",
7092    "rbit requires: ASIMD",
7093    "rev16 requires: ASIMD",
7094    "rev32 requires: ASIMD",
7095    "rev64 requires: ASIMD",
7096    "rshrn requires: ASIMD",
7097    "rshrn2 requires: ASIMD",
7098    "rsubhn requires: ASIMD",
7099    "rsubhn2 requires: ASIMD",
7100    "saba requires: ASIMD",
7101    "sabal requires: ASIMD",
7102    "sabal2 requires: ASIMD",
7103    "sabd requires: ASIMD",
7104    "sabdl requires: ASIMD",
7105    "sabdl2 requires: ASIMD",
7106    "sadalp requires: ASIMD",
7107    "saddl requires: ASIMD",
7108    "saddl2 requires: ASIMD",
7109    "saddlp requires: ASIMD",
7110    "saddlv requires: ASIMD",
7111    "saddw requires: ASIMD",
7112    "saddw2 requires: ASIMD",
7113    "scvtf requires: ASIMD",
7114    "sdot requires: ASIMD, DOTPROD",
7115    "sha1c requires: ASIMD, SHA1",
7116    "sha1h requires: ASIMD, SHA1",
7117    "sha1m requires: ASIMD, SHA1",
7118    "sha1p requires: ASIMD, SHA1",
7119    "sha1su0 requires: ASIMD, SHA1",
7120    "sha1su1 requires: ASIMD, SHA1",
7121    "sha256h requires: ASIMD, SHA256",
7122    "sha256h2 requires: ASIMD, SHA256",
7123    "sha256su0 requires: ASIMD, SHA256",
7124    "sha256su1 requires: ASIMD, SHA256",
7125    "sha512h requires: ASIMD, SHA512",
7126    "sha512h2 requires: ASIMD, SHA512",
7127    "sha512su0 requires: ASIMD, SHA512",
7128    "sha512su1 requires: ASIMD, SHA512",
7129    "shadd requires: ASIMD",
7130    "shl requires: ASIMD",
7131    "shll requires: ASIMD",
7132    "shll2 requires: ASIMD",
7133    "shrn requires: ASIMD",
7134    "shrn2 requires: ASIMD",
7135    "shsub requires: ASIMD",
7136    "sli requires: ASIMD",
7137    "sm3partw1 requires: ASIMD, SM3",
7138    "sm3partw2 requires: ASIMD, SM3",
7139    "sm3ss1 requires: ASIMD, SM3",
7140    "sm3tt1a requires: ASIMD, SM3",
7141    "sm3tt1b requires: ASIMD, SM3",
7142    "sm3tt2a requires: ASIMD, SM3",
7143    "sm3tt2b requires: ASIMD, SM3",
7144    "sm4e requires: ASIMD, SM4",
7145    "sm4ekey requires: ASIMD, SM4",
7146    "smax requires: ASIMD",
7147    "smaxp requires: ASIMD",
7148    "smaxv requires: ASIMD",
7149    "smin requires: ASIMD",
7150    "sminp requires: ASIMD",
7151    "sminv requires: ASIMD",
7152    "smlal requires: ASIMD",
7153    "smlal2 requires: ASIMD",
7154    "smlsl requires: ASIMD",
7155    "smlsl2 requires: ASIMD",
7156    "smmla requires: ASIMD, I8MM",
7157    "smov requires: ASIMD",
7158    "smull requires: ASIMD",
7159    "smull2 requires: ASIMD",
7160    "sqabs requires: ASIMD",
7161    "sqadd requires: ASIMD",
7162    "sqdmlal requires: ASIMD",
7163    "sqdmlal2 requires: ASIMD",
7164    "sqdmlsl requires: ASIMD",
7165    "sqdmlsl2 requires: ASIMD",
7166    "sqdmulh requires: ASIMD",
7167    "sqdmull requires: ASIMD",
7168    "sqdmull2 requires: ASIMD",
7169    "sqneg requires: ASIMD",
7170    "sqrdmlah requires: ASIMD, RDM",
7171    "sqrdmlsh requires: ASIMD, RDM",
7172    "sqrdmulh requires: ASIMD",
7173    "sqrshl requires: ASIMD",
7174    "sqrshrn requires: ASIMD",
7175    "sqrshrn2 requires: ASIMD",
7176    "sqrshrun requires: ASIMD",
7177    "sqrshrun2 requires: ASIMD",
7178    "sqshl requires: ASIMD",
7179    "sqshlu requires: ASIMD",
7180    "sqshrn requires: ASIMD",
7181    "sqshrn2 requires: ASIMD",
7182    "sqshrun requires: ASIMD",
7183    "sqshrun2 requires: ASIMD",
7184    "sqsub requires: ASIMD",
7185    "sqxtn requires: ASIMD",
7186    "sqxtn2 requires: ASIMD",
7187    "sqxtun requires: ASIMD",
7188    "sqxtun2 requires: ASIMD",
7189    "srhadd requires: ASIMD",
7190    "sri requires: ASIMD",
7191    "srshl requires: ASIMD",
7192    "srshr requires: ASIMD",
7193    "srsra requires: ASIMD",
7194    "sshl requires: ASIMD",
7195    "sshll requires: ASIMD",
7196    "sshll2 requires: ASIMD",
7197    "sshr requires: ASIMD",
7198    "ssra requires: ASIMD",
7199    "ssubl requires: ASIMD",
7200    "ssubl2 requires: ASIMD",
7201    "ssubw requires: ASIMD",
7202    "ssubw2 requires: ASIMD",
7203    "st1 requires: ASIMD",
7204    "st2 requires: ASIMD",
7205    "st3 requires: ASIMD",
7206    "st4 requires: ASIMD",
7207    "stnp requires: ASIMD",
7208    "stp requires: ASIMD",
7209    "str requires: ASIMD",
7210    "stur requires: ASIMD",
7211    "sub requires: ASIMD",
7212    "subhn requires: ASIMD",
7213    "subhn2 requires: ASIMD",
7214    "sudot requires: ASIMD, I8MM",
7215    "suqadd requires: ASIMD",
7216    "sxtl requires: ASIMD",
7217    "sxtl2 requires: ASIMD",
7218    "tbl requires: ASIMD",
7219    "tbx requires: ASIMD",
7220    "trn1 requires: ASIMD",
7221    "trn2 requires: ASIMD",
7222    "uaba requires: ASIMD",
7223    "uabal requires: ASIMD",
7224    "uabal2 requires: ASIMD",
7225    "uabd requires: ASIMD",
7226    "uabdl requires: ASIMD",
7227    "uabdl2 requires: ASIMD",
7228    "uadalp requires: ASIMD",
7229    "uaddl requires: ASIMD",
7230    "uaddl2 requires: ASIMD",
7231    "uaddlp requires: ASIMD",
7232    "uaddlv requires: ASIMD",
7233    "uaddw requires: ASIMD",
7234    "uaddw2 requires: ASIMD",
7235    "ucvtf requires: ASIMD",
7236    "udot requires: ASIMD, DOTPROD",
7237    "uhadd requires: ASIMD",
7238    "uhsub requires: ASIMD",
7239    "umax requires: ASIMD",
7240    "umaxp requires: ASIMD",
7241    "umaxv requires: ASIMD",
7242    "umin requires: ASIMD",
7243    "uminp requires: ASIMD",
7244    "uminv requires: ASIMD",
7245    "umlal requires: ASIMD",
7246    "umlal2 requires: ASIMD",
7247    "umlsl requires: ASIMD",
7248    "umlsl2 requires: ASIMD",
7249    "ummla requires: ASIMD, I8MM",
7250    "umov requires: ASIMD",
7251    "umull requires: ASIMD",
7252    "umull2 requires: ASIMD",
7253    "uqadd requires: ASIMD",
7254    "uqrshl requires: ASIMD",
7255    "uqrshrn requires: ASIMD",
7256    "uqrshrn2 requires: ASIMD",
7257    "uqshl requires: ASIMD",
7258    "uqshrn requires: ASIMD",
7259    "uqshrn2 requires: ASIMD",
7260    "uqsub requires: ASIMD",
7261    "uqxtn requires: ASIMD",
7262    "uqxtn2 requires: ASIMD",
7263    "urecpe requires: ASIMD",
7264    "urhadd requires: ASIMD",
7265    "urshl requires: ASIMD",
7266    "urshr requires: ASIMD",
7267    "ursqrte requires: ASIMD",
7268    "ursra requires: ASIMD",
7269    "usdot requires: ASIMD, I8MM",
7270    "ushl requires: ASIMD",
7271    "ushll requires: ASIMD",
7272    "ushll2 requires: ASIMD",
7273    "ushr requires: ASIMD",
7274    "usmmla requires: ASIMD, I8MM",
7275    "usqadd requires: ASIMD",
7276    "usra requires: ASIMD",
7277    "usubl requires: ASIMD",
7278    "usubl2 requires: ASIMD",
7279    "usubw requires: ASIMD",
7280    "usubw2 requires: ASIMD",
7281    "uxtl requires: ASIMD",
7282    "uxtl2 requires: ASIMD",
7283    "uzp1 requires: ASIMD",
7284    "uzp2 requires: ASIMD",
7285    "xar requires: ASIMD, SHA3",
7286    "xtn requires: ASIMD",
7287    "xtn2 requires: ASIMD",
7288    "zip1 requires: ASIMD",
7289    "zip2 requires: ASIMD",
7290];
7291
7292static INST_FEATURE_FORM_OFFSETS: [u16; InstId::_Count as usize + 1] = [
7293    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
7294    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
7295    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
7296    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
7297    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
7298    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
7299    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
7300    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
7301    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
7302    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
7303    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
7304    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
7305    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
7306    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
7307    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 6, 9, 12, 15, 18, 18, 19, 20, 26,
7308    32, 38, 38, 41, 44, 46, 48, 49, 49, 54, 59, 59, 59, 64, 69, 72, 73, 78, 83, 88, 93, 93, 93,
7309    103, 113, 116, 116, 117, 120, 123, 126, 128, 131, 133, 136, 139, 142, 144, 147, 149, 154, 154,
7310    154, 159, 159, 159, 167, 168, 174, 180, 183, 184, 185, 186, 189, 192, 193, 193, 193, 193, 193,
7311    196, 199, 202, 205, 208, 211, 214, 217, 220, 223, 226, 226, 226, 226, 226, 226, 226, 226, 226,
7312    226, 226, 226, 226, 226, 226, 226, 226, 226, 226, 226, 226, 226, 226, 226, 226, 226, 226, 226,
7313    226, 226, 226, 226, 226, 226, 226, 226, 226, 226, 226, 226, 226, 226, 226, 226, 226, 226, 226,
7314    226, 226, 226, 226, 226, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236,
7315    236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236,
7316    236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236,
7317    236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236,
7318    236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236,
7319    236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236,
7320    236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 246, 246, 246, 246, 246, 246,
7321    246, 246, 246, 246, 246, 246, 246, 246, 246, 246, 246, 246, 246, 246, 246, 246, 246, 246, 246,
7322    246, 246, 246, 246, 246, 246, 246, 246, 246, 246, 246, 246, 246, 246, 246, 246, 246, 246, 246,
7323    246, 246, 246, 246, 246, 246, 246, 246, 246, 246, 246,
7324];
7325
7326static INST_FEATURE_FORMS: [InstFeatureForm; 246] = [
7327    InstFeatureForm {
7328        opcode_mask: 0xffe0fc00,
7329        opcode_value: 0x7ec01400,
7330        operand_signatures: [
7331            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7332            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7333            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7334            0,
7335            0,
7336            0,
7337        ],
7338        required: 0x0000000000004002,
7339        context: "fabd Hd, Hn, Hm requires: ASIMD, FP16",
7340    },
7341    InstFeatureForm {
7342        opcode_mask: 0xffe0fc00,
7343        opcode_value: 0x2ec01400,
7344        operand_signatures: [
7345            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7346            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7347            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7348            0,
7349            0,
7350            0,
7351        ],
7352        required: 0x0000000000004002,
7353        context: "fabd Vd.4H, Vn.4H, Vm.4H requires: ASIMD, FP16",
7354    },
7355    InstFeatureForm {
7356        opcode_mask: 0xffe0fc00,
7357        opcode_value: 0x6ec01400,
7358        operand_signatures: [
7359            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7360            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7361            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7362            0,
7363            0,
7364            0,
7365        ],
7366        required: 0x0000000000004002,
7367        context: "fabd Vd.8H, Vn.8H, Vm.8H requires: ASIMD, FP16",
7368    },
7369    InstFeatureForm {
7370        opcode_mask: 0xfffffc00,
7371        opcode_value: 0x1ee0c000,
7372        operand_signatures: [
7373            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7374            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7375            0,
7376            0,
7377            0,
7378            0,
7379        ],
7380        required: 0x0000000000004002,
7381        context: "fabs Hd, Hn requires: ASIMD, FP16",
7382    },
7383    InstFeatureForm {
7384        opcode_mask: 0xfffffc00,
7385        opcode_value: 0x0ef8f800,
7386        operand_signatures: [
7387            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7388            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7389            0,
7390            0,
7391            0,
7392            0,
7393        ],
7394        required: 0x0000000000004002,
7395        context: "fabs Vd.4H, Vn.4H requires: ASIMD, FP16",
7396    },
7397    InstFeatureForm {
7398        opcode_mask: 0xfffffc00,
7399        opcode_value: 0x4ef8f800,
7400        operand_signatures: [
7401            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7402            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7403            0,
7404            0,
7405            0,
7406            0,
7407        ],
7408        required: 0x0000000000004002,
7409        context: "fabs Vd.8H, Vn.8H requires: ASIMD, FP16",
7410    },
7411    InstFeatureForm {
7412        opcode_mask: 0xffe0fc00,
7413        opcode_value: 0x7e402c00,
7414        operand_signatures: [
7415            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7416            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7417            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7418            0,
7419            0,
7420            0,
7421        ],
7422        required: 0x0000000000004002,
7423        context: "facge Hd, Hn, Hm requires: ASIMD, FP16",
7424    },
7425    InstFeatureForm {
7426        opcode_mask: 0xffe0fc00,
7427        opcode_value: 0x2e402c00,
7428        operand_signatures: [
7429            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7430            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7431            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7432            0,
7433            0,
7434            0,
7435        ],
7436        required: 0x0000000000004002,
7437        context: "facge Vd.4H, Vn.4H, Vm.4H requires: ASIMD, FP16",
7438    },
7439    InstFeatureForm {
7440        opcode_mask: 0xffe0fc00,
7441        opcode_value: 0x6e402c00,
7442        operand_signatures: [
7443            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7444            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7445            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7446            0,
7447            0,
7448            0,
7449        ],
7450        required: 0x0000000000004002,
7451        context: "facge Vd.8H, Vn.8H, Vm.8H requires: ASIMD, FP16",
7452    },
7453    InstFeatureForm {
7454        opcode_mask: 0xffe0fc00,
7455        opcode_value: 0x7ec02c00,
7456        operand_signatures: [
7457            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7458            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7459            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7460            0,
7461            0,
7462            0,
7463        ],
7464        required: 0x0000000000004002,
7465        context: "facgt Hd, Hn, Hm requires: ASIMD, FP16",
7466    },
7467    InstFeatureForm {
7468        opcode_mask: 0xffe0fc00,
7469        opcode_value: 0x2ec02c00,
7470        operand_signatures: [
7471            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7472            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7473            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7474            0,
7475            0,
7476            0,
7477        ],
7478        required: 0x0000000000004002,
7479        context: "facgt Vd.4H, Vn.4H, Vm.4H requires: ASIMD, FP16",
7480    },
7481    InstFeatureForm {
7482        opcode_mask: 0xffe0fc00,
7483        opcode_value: 0x6ec02c00,
7484        operand_signatures: [
7485            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7486            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7487            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7488            0,
7489            0,
7490            0,
7491        ],
7492        required: 0x0000000000004002,
7493        context: "facgt Vd.8H, Vn.8H, Vm.8H requires: ASIMD, FP16",
7494    },
7495    InstFeatureForm {
7496        opcode_mask: 0xffe0fc00,
7497        opcode_value: 0x1ee02800,
7498        operand_signatures: [
7499            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7500            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7501            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7502            0,
7503            0,
7504            0,
7505        ],
7506        required: 0x0000000000004002,
7507        context: "fadd Hd, Hn, Hm requires: ASIMD, FP16",
7508    },
7509    InstFeatureForm {
7510        opcode_mask: 0xffe0fc00,
7511        opcode_value: 0x0e401400,
7512        operand_signatures: [
7513            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7514            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7515            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7516            0,
7517            0,
7518            0,
7519        ],
7520        required: 0x0000000000004002,
7521        context: "fadd Vd.4H, Vn.4H, Vm.4H requires: ASIMD, FP16",
7522    },
7523    InstFeatureForm {
7524        opcode_mask: 0xffe0fc00,
7525        opcode_value: 0x4e401400,
7526        operand_signatures: [
7527            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7528            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7529            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7530            0,
7531            0,
7532            0,
7533        ],
7534        required: 0x0000000000004002,
7535        context: "fadd Vd.8H, Vn.8H, Vm.8H requires: ASIMD, FP16",
7536    },
7537    InstFeatureForm {
7538        opcode_mask: 0xfffffc00,
7539        opcode_value: 0x5e30d800,
7540        operand_signatures: [
7541            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7542            feature_reg_signature(RegType::Vec32, VecElementType::H, false),
7543            0,
7544            0,
7545            0,
7546            0,
7547        ],
7548        required: 0x0000000000004002,
7549        context: "faddp Hd, Vn.2H requires: ASIMD, FP16",
7550    },
7551    InstFeatureForm {
7552        opcode_mask: 0xffe0fc00,
7553        opcode_value: 0x2e401400,
7554        operand_signatures: [
7555            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7556            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7557            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7558            0,
7559            0,
7560            0,
7561        ],
7562        required: 0x0000000000004002,
7563        context: "faddp Vd.4H, Vn.4H, Vm.4H requires: ASIMD, FP16",
7564    },
7565    InstFeatureForm {
7566        opcode_mask: 0xffe0fc00,
7567        opcode_value: 0x6e401400,
7568        operand_signatures: [
7569            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7570            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7571            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7572            0,
7573            0,
7574            0,
7575        ],
7576        required: 0x0000000000004002,
7577        context: "faddp Vd.8H, Vn.8H, Vm.8H requires: ASIMD, FP16",
7578    },
7579    InstFeatureForm {
7580        opcode_mask: 0xffe00c10,
7581        opcode_value: 0x1ee00400,
7582        operand_signatures: [
7583            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7584            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7585            OperandType::Imm as u32,
7586            OperandType::Imm as u32,
7587            0,
7588            0,
7589        ],
7590        required: 0x0000000000004002,
7591        context: "fccmp Hn, Hm, #nzcv, #cond requires: ASIMD, FP16",
7592    },
7593    InstFeatureForm {
7594        opcode_mask: 0xffe00c10,
7595        opcode_value: 0x1ee00410,
7596        operand_signatures: [
7597            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7598            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7599            OperandType::Imm as u32,
7600            OperandType::Imm as u32,
7601            0,
7602            0,
7603        ],
7604        required: 0x0000000000004002,
7605        context: "fccmpe Hn, Hm, #nzcv, #cond requires: ASIMD, FP16",
7606    },
7607    InstFeatureForm {
7608        opcode_mask: 0xfffffc00,
7609        opcode_value: 0x5ef8d800,
7610        operand_signatures: [
7611            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7612            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7613            OperandType::Imm as u32,
7614            0,
7615            0,
7616            0,
7617        ],
7618        required: 0x0000000000004002,
7619        context: "fcmeq Hd, Hn, #0 requires: ASIMD, FP16",
7620    },
7621    InstFeatureForm {
7622        opcode_mask: 0xfffffc00,
7623        opcode_value: 0x0ef8d800,
7624        operand_signatures: [
7625            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7626            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7627            OperandType::Imm as u32,
7628            0,
7629            0,
7630            0,
7631        ],
7632        required: 0x0000000000004002,
7633        context: "fcmeq Vd.4H, Vn.4H, #0 requires: ASIMD, FP16",
7634    },
7635    InstFeatureForm {
7636        opcode_mask: 0xfffffc00,
7637        opcode_value: 0x4ef8d800,
7638        operand_signatures: [
7639            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7640            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7641            OperandType::Imm as u32,
7642            0,
7643            0,
7644            0,
7645        ],
7646        required: 0x0000000000004002,
7647        context: "fcmeq Vd.8H, Vn.8H, #0 requires: ASIMD, FP16",
7648    },
7649    InstFeatureForm {
7650        opcode_mask: 0xffe0fc00,
7651        opcode_value: 0x5e402400,
7652        operand_signatures: [
7653            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7654            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7655            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7656            0,
7657            0,
7658            0,
7659        ],
7660        required: 0x0000000000004002,
7661        context: "fcmeq Hd, Hn, Hm requires: ASIMD, FP16",
7662    },
7663    InstFeatureForm {
7664        opcode_mask: 0xffe0fc00,
7665        opcode_value: 0x0e402400,
7666        operand_signatures: [
7667            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7668            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7669            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7670            0,
7671            0,
7672            0,
7673        ],
7674        required: 0x0000000000004002,
7675        context: "fcmeq Vd.4H, Vn.4H, Vm.4H requires: ASIMD, FP16",
7676    },
7677    InstFeatureForm {
7678        opcode_mask: 0xffe0fc00,
7679        opcode_value: 0x4e402400,
7680        operand_signatures: [
7681            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7682            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7683            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7684            0,
7685            0,
7686            0,
7687        ],
7688        required: 0x0000000000004002,
7689        context: "fcmeq Vd.8H, Vn.8H, Vm.8H requires: ASIMD, FP16",
7690    },
7691    InstFeatureForm {
7692        opcode_mask: 0xfffffc00,
7693        opcode_value: 0x7ef8c800,
7694        operand_signatures: [
7695            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7696            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7697            OperandType::Imm as u32,
7698            0,
7699            0,
7700            0,
7701        ],
7702        required: 0x0000000000004002,
7703        context: "fcmge Hd, Hn, #0 requires: ASIMD, FP16",
7704    },
7705    InstFeatureForm {
7706        opcode_mask: 0xfffffc00,
7707        opcode_value: 0x2ef8c800,
7708        operand_signatures: [
7709            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7710            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7711            OperandType::Imm as u32,
7712            0,
7713            0,
7714            0,
7715        ],
7716        required: 0x0000000000004002,
7717        context: "fcmge Vd.4H, Vn.4H, #0 requires: ASIMD, FP16",
7718    },
7719    InstFeatureForm {
7720        opcode_mask: 0xfffffc00,
7721        opcode_value: 0x6ef8c800,
7722        operand_signatures: [
7723            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7724            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7725            OperandType::Imm as u32,
7726            0,
7727            0,
7728            0,
7729        ],
7730        required: 0x0000000000004002,
7731        context: "fcmge Vd.8H, Vn.8H, #0 requires: ASIMD, FP16",
7732    },
7733    InstFeatureForm {
7734        opcode_mask: 0xffe0fc00,
7735        opcode_value: 0x7e402400,
7736        operand_signatures: [
7737            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7738            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7739            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7740            0,
7741            0,
7742            0,
7743        ],
7744        required: 0x0000000000004002,
7745        context: "fcmge Hd, Hn, Hm requires: ASIMD, FP16",
7746    },
7747    InstFeatureForm {
7748        opcode_mask: 0xffe0fc00,
7749        opcode_value: 0x2e402400,
7750        operand_signatures: [
7751            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7752            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7753            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7754            0,
7755            0,
7756            0,
7757        ],
7758        required: 0x0000000000004002,
7759        context: "fcmge Vd.4H, Vn.4H, Vm.4H requires: ASIMD, FP16",
7760    },
7761    InstFeatureForm {
7762        opcode_mask: 0xffe0fc00,
7763        opcode_value: 0x6e402400,
7764        operand_signatures: [
7765            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7766            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7767            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7768            0,
7769            0,
7770            0,
7771        ],
7772        required: 0x0000000000004002,
7773        context: "fcmge Vd.8H, Vn.8H, Vm.8H requires: ASIMD, FP16",
7774    },
7775    InstFeatureForm {
7776        opcode_mask: 0xfffffc00,
7777        opcode_value: 0x5ef8c800,
7778        operand_signatures: [
7779            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7780            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7781            OperandType::Imm as u32,
7782            0,
7783            0,
7784            0,
7785        ],
7786        required: 0x0000000000004002,
7787        context: "fcmgt Hd, Hn, #0 requires: ASIMD, FP16",
7788    },
7789    InstFeatureForm {
7790        opcode_mask: 0xfffffc00,
7791        opcode_value: 0x0ef8c800,
7792        operand_signatures: [
7793            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7794            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7795            OperandType::Imm as u32,
7796            0,
7797            0,
7798            0,
7799        ],
7800        required: 0x0000000000004002,
7801        context: "fcmgt Vd.4H, Vn.4H, #0 requires: ASIMD, FP16",
7802    },
7803    InstFeatureForm {
7804        opcode_mask: 0xfffffc00,
7805        opcode_value: 0x4ef8c800,
7806        operand_signatures: [
7807            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7808            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7809            OperandType::Imm as u32,
7810            0,
7811            0,
7812            0,
7813        ],
7814        required: 0x0000000000004002,
7815        context: "fcmgt Vd.8H, Vn.8H, #0 requires: ASIMD, FP16",
7816    },
7817    InstFeatureForm {
7818        opcode_mask: 0xffe0fc00,
7819        opcode_value: 0x7ec02400,
7820        operand_signatures: [
7821            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7822            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7823            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7824            0,
7825            0,
7826            0,
7827        ],
7828        required: 0x0000000000004002,
7829        context: "fcmgt Hd, Hn, Hm requires: ASIMD, FP16",
7830    },
7831    InstFeatureForm {
7832        opcode_mask: 0xffe0fc00,
7833        opcode_value: 0x2ec02400,
7834        operand_signatures: [
7835            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7836            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7837            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7838            0,
7839            0,
7840            0,
7841        ],
7842        required: 0x0000000000004002,
7843        context: "fcmgt Vd.4H, Vn.4H, Vm.4H requires: ASIMD, FP16",
7844    },
7845    InstFeatureForm {
7846        opcode_mask: 0xffe0fc00,
7847        opcode_value: 0x6ec02400,
7848        operand_signatures: [
7849            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7850            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7851            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7852            0,
7853            0,
7854            0,
7855        ],
7856        required: 0x0000000000004002,
7857        context: "fcmgt Vd.8H, Vn.8H, Vm.8H requires: ASIMD, FP16",
7858    },
7859    InstFeatureForm {
7860        opcode_mask: 0xfffffc00,
7861        opcode_value: 0x7ef8d800,
7862        operand_signatures: [
7863            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7864            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7865            OperandType::Imm as u32,
7866            0,
7867            0,
7868            0,
7869        ],
7870        required: 0x0000000000004002,
7871        context: "fcmle Hd, Hn, #0 requires: ASIMD, FP16",
7872    },
7873    InstFeatureForm {
7874        opcode_mask: 0xfffffc00,
7875        opcode_value: 0x2ef8d800,
7876        operand_signatures: [
7877            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7878            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7879            OperandType::Imm as u32,
7880            0,
7881            0,
7882            0,
7883        ],
7884        required: 0x0000000000004002,
7885        context: "fcmle Vd.4H, Vn.4H, #0 requires: ASIMD, FP16",
7886    },
7887    InstFeatureForm {
7888        opcode_mask: 0xfffffc00,
7889        opcode_value: 0x6ef8d800,
7890        operand_signatures: [
7891            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7892            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7893            OperandType::Imm as u32,
7894            0,
7895            0,
7896            0,
7897        ],
7898        required: 0x0000000000004002,
7899        context: "fcmle Vd.8H, Vn.8H, #0 requires: ASIMD, FP16",
7900    },
7901    InstFeatureForm {
7902        opcode_mask: 0xfffffc00,
7903        opcode_value: 0x5ef8e800,
7904        operand_signatures: [
7905            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7906            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7907            OperandType::Imm as u32,
7908            0,
7909            0,
7910            0,
7911        ],
7912        required: 0x0000000000004002,
7913        context: "fcmlt Hd, Hn, #0 requires: ASIMD, FP16",
7914    },
7915    InstFeatureForm {
7916        opcode_mask: 0xfffffc00,
7917        opcode_value: 0x0ef8e800,
7918        operand_signatures: [
7919            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7920            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7921            OperandType::Imm as u32,
7922            0,
7923            0,
7924            0,
7925        ],
7926        required: 0x0000000000004002,
7927        context: "fcmlt Vd.4H, Vn.4H, #0 requires: ASIMD, FP16",
7928    },
7929    InstFeatureForm {
7930        opcode_mask: 0xfffffc00,
7931        opcode_value: 0x4ef8e800,
7932        operand_signatures: [
7933            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7934            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7935            OperandType::Imm as u32,
7936            0,
7937            0,
7938            0,
7939        ],
7940        required: 0x0000000000004002,
7941        context: "fcmlt Vd.8H, Vn.8H, #0 requires: ASIMD, FP16",
7942    },
7943    InstFeatureForm {
7944        opcode_mask: 0xfffffc1f,
7945        opcode_value: 0x1ee02008,
7946        operand_signatures: [
7947            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7948            OperandType::Imm as u32,
7949            0,
7950            0,
7951            0,
7952            0,
7953        ],
7954        required: 0x0000000000004002,
7955        context: "fcmp Hn, #0 requires: ASIMD, FP16",
7956    },
7957    InstFeatureForm {
7958        opcode_mask: 0xffe0fc1f,
7959        opcode_value: 0x1ee02000,
7960        operand_signatures: [
7961            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7962            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7963            0,
7964            0,
7965            0,
7966            0,
7967        ],
7968        required: 0x0000000000004002,
7969        context: "fcmp Hn, Hm requires: ASIMD, FP16",
7970    },
7971    InstFeatureForm {
7972        opcode_mask: 0xfffffc1f,
7973        opcode_value: 0x1ee02018,
7974        operand_signatures: [
7975            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7976            OperandType::Imm as u32,
7977            0,
7978            0,
7979            0,
7980            0,
7981        ],
7982        required: 0x0000000000004002,
7983        context: "fcmpe Hn, #0 requires: ASIMD, FP16",
7984    },
7985    InstFeatureForm {
7986        opcode_mask: 0xffe0fc1f,
7987        opcode_value: 0x1ee02010,
7988        operand_signatures: [
7989            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7990            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7991            0,
7992            0,
7993            0,
7994            0,
7995        ],
7996        required: 0x0000000000004002,
7997        context: "fcmpe Hn, Hm requires: ASIMD, FP16",
7998    },
7999    InstFeatureForm {
8000        opcode_mask: 0xffe00c00,
8001        opcode_value: 0x1ee00c00,
8002        operand_signatures: [
8003            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8004            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8005            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8006            OperandType::Imm as u32,
8007            0,
8008            0,
8009        ],
8010        required: 0x0000000000004002,
8011        context: "fcsel Hd, Hn, Hm, #cond requires: ASIMD, FP16",
8012    },
8013    InstFeatureForm {
8014        opcode_mask: 0xfffffc00,
8015        opcode_value: 0x1ee40000,
8016        operand_signatures: [
8017            feature_reg_signature(RegType::Gp32, VecElementType::None, false),
8018            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8019            0,
8020            0,
8021            0,
8022            0,
8023        ],
8024        required: 0x0000000000004002,
8025        context: "fcvtas Wd, Hn requires: ASIMD, FP16",
8026    },
8027    InstFeatureForm {
8028        opcode_mask: 0xfffffc00,
8029        opcode_value: 0x9ee40000,
8030        operand_signatures: [
8031            feature_reg_signature(RegType::Gp64, VecElementType::None, false),
8032            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8033            0,
8034            0,
8035            0,
8036            0,
8037        ],
8038        required: 0x0000000000004002,
8039        context: "fcvtas Xd, Hn requires: ASIMD, FP16",
8040    },
8041    InstFeatureForm {
8042        opcode_mask: 0xfffffc00,
8043        opcode_value: 0x5e79c800,
8044        operand_signatures: [
8045            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8046            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8047            0,
8048            0,
8049            0,
8050            0,
8051        ],
8052        required: 0x0000000000004002,
8053        context: "fcvtas Hd, Hn requires: ASIMD, FP16",
8054    },
8055    InstFeatureForm {
8056        opcode_mask: 0xfffffc00,
8057        opcode_value: 0x0e79c800,
8058        operand_signatures: [
8059            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
8060            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
8061            0,
8062            0,
8063            0,
8064            0,
8065        ],
8066        required: 0x0000000000004002,
8067        context: "fcvtas Vd.4H, Vn.4H requires: ASIMD, FP16",
8068    },
8069    InstFeatureForm {
8070        opcode_mask: 0xfffffc00,
8071        opcode_value: 0x4e79c800,
8072        operand_signatures: [
8073            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
8074            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
8075            0,
8076            0,
8077            0,
8078            0,
8079        ],
8080        required: 0x0000000000004002,
8081        context: "fcvtas Vd.8H, Vn.8H requires: ASIMD, FP16",
8082    },
8083    InstFeatureForm {
8084        opcode_mask: 0xfffffc00,
8085        opcode_value: 0x1ee50000,
8086        operand_signatures: [
8087            feature_reg_signature(RegType::Gp32, VecElementType::None, false),
8088            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8089            0,
8090            0,
8091            0,
8092            0,
8093        ],
8094        required: 0x0000000000004002,
8095        context: "fcvtau Wd, Hn requires: ASIMD, FP16",
8096    },
8097    InstFeatureForm {
8098        opcode_mask: 0xfffffc00,
8099        opcode_value: 0x9ee50000,
8100        operand_signatures: [
8101            feature_reg_signature(RegType::Gp64, VecElementType::None, false),
8102            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8103            0,
8104            0,
8105            0,
8106            0,
8107        ],
8108        required: 0x0000000000004002,
8109        context: "fcvtau Xd, Hn requires: ASIMD, FP16",
8110    },
8111    InstFeatureForm {
8112        opcode_mask: 0xfffffc00,
8113        opcode_value: 0x7e79c800,
8114        operand_signatures: [
8115            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8116            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8117            0,
8118            0,
8119            0,
8120            0,
8121        ],
8122        required: 0x0000000000004002,
8123        context: "fcvtau Hd, Hn requires: ASIMD, FP16",
8124    },
8125    InstFeatureForm {
8126        opcode_mask: 0xfffffc00,
8127        opcode_value: 0x2e79c800,
8128        operand_signatures: [
8129            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
8130            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
8131            0,
8132            0,
8133            0,
8134            0,
8135        ],
8136        required: 0x0000000000004002,
8137        context: "fcvtau Vd.4H, Vn.4H requires: ASIMD, FP16",
8138    },
8139    InstFeatureForm {
8140        opcode_mask: 0xfffffc00,
8141        opcode_value: 0x6e79c800,
8142        operand_signatures: [
8143            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
8144            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
8145            0,
8146            0,
8147            0,
8148            0,
8149        ],
8150        required: 0x0000000000004002,
8151        context: "fcvtau Vd.8H, Vn.8H requires: ASIMD, FP16",
8152    },
8153    InstFeatureForm {
8154        opcode_mask: 0xfffffc00,
8155        opcode_value: 0x1ef00000,
8156        operand_signatures: [
8157            feature_reg_signature(RegType::Gp32, VecElementType::None, false),
8158            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8159            0,
8160            0,
8161            0,
8162            0,
8163        ],
8164        required: 0x0000000000004002,
8165        context: "fcvtms Wd, Hn requires: ASIMD, FP16",
8166    },
8167    InstFeatureForm {
8168        opcode_mask: 0xfffffc00,
8169        opcode_value: 0x9ef00000,
8170        operand_signatures: [
8171            feature_reg_signature(RegType::Gp64, VecElementType::None, false),
8172            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8173            0,
8174            0,
8175            0,
8176            0,
8177        ],
8178        required: 0x0000000000004002,
8179        context: "fcvtms Xd, Hn requires: ASIMD, FP16",
8180    },
8181    InstFeatureForm {
8182        opcode_mask: 0xfffffc00,
8183        opcode_value: 0x5e79b800,
8184        operand_signatures: [
8185            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8186            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8187            0,
8188            0,
8189            0,
8190            0,
8191        ],
8192        required: 0x0000000000004002,
8193        context: "fcvtms Hd, Hn requires: ASIMD, FP16",
8194    },
8195    InstFeatureForm {
8196        opcode_mask: 0xfffffc00,
8197        opcode_value: 0x0e79b800,
8198        operand_signatures: [
8199            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
8200            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
8201            0,
8202            0,
8203            0,
8204            0,
8205        ],
8206        required: 0x0000000000004002,
8207        context: "fcvtms Vd.4H, Vn.4H requires: ASIMD, FP16",
8208    },
8209    InstFeatureForm {
8210        opcode_mask: 0xfffffc00,
8211        opcode_value: 0x4e79b800,
8212        operand_signatures: [
8213            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
8214            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
8215            0,
8216            0,
8217            0,
8218            0,
8219        ],
8220        required: 0x0000000000004002,
8221        context: "fcvtms Vd.8H, Vn.8H requires: ASIMD, FP16",
8222    },
8223    InstFeatureForm {
8224        opcode_mask: 0xfffffc00,
8225        opcode_value: 0x1ef10000,
8226        operand_signatures: [
8227            feature_reg_signature(RegType::Gp32, VecElementType::None, false),
8228            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8229            0,
8230            0,
8231            0,
8232            0,
8233        ],
8234        required: 0x0000000000004002,
8235        context: "fcvtmu Wd, Hn requires: ASIMD, FP16",
8236    },
8237    InstFeatureForm {
8238        opcode_mask: 0xfffffc00,
8239        opcode_value: 0x9ef10000,
8240        operand_signatures: [
8241            feature_reg_signature(RegType::Gp64, VecElementType::None, false),
8242            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8243            0,
8244            0,
8245            0,
8246            0,
8247        ],
8248        required: 0x0000000000004002,
8249        context: "fcvtmu Xd, Hn requires: ASIMD, FP16",
8250    },
8251    InstFeatureForm {
8252        opcode_mask: 0xfffffc00,
8253        opcode_value: 0x7e79b800,
8254        operand_signatures: [
8255            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8256            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8257            0,
8258            0,
8259            0,
8260            0,
8261        ],
8262        required: 0x0000000000004002,
8263        context: "fcvtmu Hd, Hn requires: ASIMD, FP16",
8264    },
8265    InstFeatureForm {
8266        opcode_mask: 0xfffffc00,
8267        opcode_value: 0x2e79b800,
8268        operand_signatures: [
8269            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
8270            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
8271            0,
8272            0,
8273            0,
8274            0,
8275        ],
8276        required: 0x0000000000004002,
8277        context: "fcvtmu Vd.4H, Vn.4H requires: ASIMD, FP16",
8278    },
8279    InstFeatureForm {
8280        opcode_mask: 0xfffffc00,
8281        opcode_value: 0x6e79b800,
8282        operand_signatures: [
8283            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
8284            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
8285            0,
8286            0,
8287            0,
8288            0,
8289        ],
8290        required: 0x0000000000004002,
8291        context: "fcvtmu Vd.8H, Vn.8H requires: ASIMD, FP16",
8292    },
8293    InstFeatureForm {
8294        opcode_mask: 0xffe0fc00,
8295        opcode_value: 0x0e40f400,
8296        operand_signatures: [
8297            feature_reg_signature(RegType::Vec64, VecElementType::B, false),
8298            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
8299            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
8300            0,
8301            0,
8302            0,
8303        ],
8304        required: 0x0000000000008002,
8305        context: "fcvtn Vd.8B, Vn.4H, Vm.4H requires: ASIMD, FP8",
8306    },
8307    InstFeatureForm {
8308        opcode_mask: 0xffe0fc00,
8309        opcode_value: 0x4e40f400,
8310        operand_signatures: [
8311            feature_reg_signature(RegType::Vec128, VecElementType::B, false),
8312            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
8313            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
8314            0,
8315            0,
8316            0,
8317        ],
8318        required: 0x0000000000008002,
8319        context: "fcvtn Vd.16B, Vn.8H, Vm.8H requires: ASIMD, FP8",
8320    },
8321    InstFeatureForm {
8322        opcode_mask: 0xffe0fc00,
8323        opcode_value: 0x0e00f400,
8324        operand_signatures: [
8325            feature_reg_signature(RegType::Vec64, VecElementType::B, false),
8326            feature_reg_signature(RegType::Vec128, VecElementType::S, false),
8327            feature_reg_signature(RegType::Vec128, VecElementType::S, false),
8328            0,
8329            0,
8330            0,
8331        ],
8332        required: 0x0000000000008002,
8333        context: "fcvtn Vd.8B, Vn.4S, Vm.4S requires: ASIMD, FP8",
8334    },
8335    InstFeatureForm {
8336        opcode_mask: 0xffe0fc00,
8337        opcode_value: 0x4e00f400,
8338        operand_signatures: [
8339            feature_reg_signature(RegType::Vec128, VecElementType::B, false),
8340            feature_reg_signature(RegType::Vec128, VecElementType::S, false),
8341            feature_reg_signature(RegType::Vec128, VecElementType::S, false),
8342            0,
8343            0,
8344            0,
8345        ],
8346        required: 0x0000000000008002,
8347        context: "fcvtn2 Vx.16B, Vn.4S, Vm.4S requires: ASIMD, FP8",
8348    },
8349    InstFeatureForm {
8350        opcode_mask: 0xfffffc00,
8351        opcode_value: 0x1ee00000,
8352        operand_signatures: [
8353            feature_reg_signature(RegType::Gp32, VecElementType::None, false),
8354            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8355            0,
8356            0,
8357            0,
8358            0,
8359        ],
8360        required: 0x0000000000004002,
8361        context: "fcvtns Wd, Hn requires: ASIMD, FP16",
8362    },
8363    InstFeatureForm {
8364        opcode_mask: 0xfffffc00,
8365        opcode_value: 0x9ee00000,
8366        operand_signatures: [
8367            feature_reg_signature(RegType::Gp64, VecElementType::None, false),
8368            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8369            0,
8370            0,
8371            0,
8372            0,
8373        ],
8374        required: 0x0000000000004002,
8375        context: "fcvtns Xd, Hn requires: ASIMD, FP16",
8376    },
8377    InstFeatureForm {
8378        opcode_mask: 0xfffffc00,
8379        opcode_value: 0x5e79a800,
8380        operand_signatures: [
8381            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8382            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8383            0,
8384            0,
8385            0,
8386            0,
8387        ],
8388        required: 0x0000000000004002,
8389        context: "fcvtns Hd, Hn requires: ASIMD, FP16",
8390    },
8391    InstFeatureForm {
8392        opcode_mask: 0xfffffc00,
8393        opcode_value: 0x0e79a800,
8394        operand_signatures: [
8395            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
8396            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
8397            0,
8398            0,
8399            0,
8400            0,
8401        ],
8402        required: 0x0000000000004002,
8403        context: "fcvtns Vd.4H, Vn.4H requires: ASIMD, FP16",
8404    },
8405    InstFeatureForm {
8406        opcode_mask: 0xfffffc00,
8407        opcode_value: 0x4e79a800,
8408        operand_signatures: [
8409            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
8410            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
8411            0,
8412            0,
8413            0,
8414            0,
8415        ],
8416        required: 0x0000000000004002,
8417        context: "fcvtns Vd.8H, Vn.8H requires: ASIMD, FP16",
8418    },
8419    InstFeatureForm {
8420        opcode_mask: 0xfffffc00,
8421        opcode_value: 0x1ee10000,
8422        operand_signatures: [
8423            feature_reg_signature(RegType::Gp32, VecElementType::None, false),
8424            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8425            0,
8426            0,
8427            0,
8428            0,
8429        ],
8430        required: 0x0000000000004002,
8431        context: "fcvtnu Wd, Hn requires: ASIMD, FP16",
8432    },
8433    InstFeatureForm {
8434        opcode_mask: 0xfffffc00,
8435        opcode_value: 0x9ee10000,
8436        operand_signatures: [
8437            feature_reg_signature(RegType::Gp64, VecElementType::None, false),
8438            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8439            0,
8440            0,
8441            0,
8442            0,
8443        ],
8444        required: 0x0000000000004002,
8445        context: "fcvtnu Xd, Hn requires: ASIMD, FP16",
8446    },
8447    InstFeatureForm {
8448        opcode_mask: 0xfffffc00,
8449        opcode_value: 0x7e79a800,
8450        operand_signatures: [
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8453            0,
8454            0,
8455            0,
8456            0,
8457        ],
8458        required: 0x0000000000004002,
8459        context: "fcvtnu Hd, Hn requires: ASIMD, FP16",
8460    },
8461    InstFeatureForm {
8462        opcode_mask: 0xfffffc00,
8463        opcode_value: 0x2e79a800,
8464        operand_signatures: [
8465            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
8466            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
8467            0,
8468            0,
8469            0,
8470            0,
8471        ],
8472        required: 0x0000000000004002,
8473        context: "fcvtnu Vd.4H, Vn.4H requires: ASIMD, FP16",
8474    },
8475    InstFeatureForm {
8476        opcode_mask: 0xfffffc00,
8477        opcode_value: 0x6e79a800,
8478        operand_signatures: [
8479            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
8480            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
8481            0,
8482            0,
8483            0,
8484            0,
8485        ],
8486        required: 0x0000000000004002,
8487        context: "fcvtnu Vd.8H, Vn.8H requires: ASIMD, FP16",
8488    },
8489    InstFeatureForm {
8490        opcode_mask: 0xfffffc00,
8491        opcode_value: 0x1ee80000,
8492        operand_signatures: [
8493            feature_reg_signature(RegType::Gp32, VecElementType::None, false),
8494            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8495            0,
8496            0,
8497            0,
8498            0,
8499        ],
8500        required: 0x0000000000004002,
8501        context: "fcvtps Wd, Hn requires: ASIMD, FP16",
8502    },
8503    InstFeatureForm {
8504        opcode_mask: 0xfffffc00,
8505        opcode_value: 0x9ee80000,
8506        operand_signatures: [
8507            feature_reg_signature(RegType::Gp64, VecElementType::None, false),
8508            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8509            0,
8510            0,
8511            0,
8512            0,
8513        ],
8514        required: 0x0000000000004002,
8515        context: "fcvtps Xd, Hn requires: ASIMD, FP16",
8516    },
8517    InstFeatureForm {
8518        opcode_mask: 0xfffffc00,
8519        opcode_value: 0x5ef9a800,
8520        operand_signatures: [
8521            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8522            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8523            0,
8524            0,
8525            0,
8526            0,
8527        ],
8528        required: 0x0000000000004002,
8529        context: "fcvtps Hd, Hn requires: ASIMD, FP16",
8530    },
8531    InstFeatureForm {
8532        opcode_mask: 0xfffffc00,
8533        opcode_value: 0x0ef9a800,
8534        operand_signatures: [
8535            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
8536            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
8537            0,
8538            0,
8539            0,
8540            0,
8541        ],
8542        required: 0x0000000000004002,
8543        context: "fcvtps Vd.4H, Vn.4H requires: ASIMD, FP16",
8544    },
8545    InstFeatureForm {
8546        opcode_mask: 0xfffffc00,
8547        opcode_value: 0x4ef9a800,
8548        operand_signatures: [
8549            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
8550            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
8551            0,
8552            0,
8553            0,
8554            0,
8555        ],
8556        required: 0x0000000000004002,
8557        context: "fcvtps Vd.8H, Vn.8H requires: ASIMD, FP16",
8558    },
8559    InstFeatureForm {
8560        opcode_mask: 0xfffffc00,
8561        opcode_value: 0x1ee90000,
8562        operand_signatures: [
8563            feature_reg_signature(RegType::Gp32, VecElementType::None, false),
8564            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8565            0,
8566            0,
8567            0,
8568            0,
8569        ],
8570        required: 0x0000000000004002,
8571        context: "fcvtpu Wd, Hn requires: ASIMD, FP16",
8572    },
8573    InstFeatureForm {
8574        opcode_mask: 0xfffffc00,
8575        opcode_value: 0x9ee90000,
8576        operand_signatures: [
8577            feature_reg_signature(RegType::Gp64, VecElementType::None, false),
8578            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8579            0,
8580            0,
8581            0,
8582            0,
8583        ],
8584        required: 0x0000000000004002,
8585        context: "fcvtpu Xd, Hn requires: ASIMD, FP16",
8586    },
8587    InstFeatureForm {
8588        opcode_mask: 0xfffffc00,
8589        opcode_value: 0x7ef9a800,
8590        operand_signatures: [
8591            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8592            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8593            0,
8594            0,
8595            0,
8596            0,
8597        ],
8598        required: 0x0000000000004002,
8599        context: "fcvtpu Hd, Hn requires: ASIMD, FP16",
8600    },
8601    InstFeatureForm {
8602        opcode_mask: 0xfffffc00,
8603        opcode_value: 0x2ef9a800,
8604        operand_signatures: [
8605            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
8606            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
8607            0,
8608            0,
8609            0,
8610            0,
8611        ],
8612        required: 0x0000000000004002,
8613        context: "fcvtpu Vd.4H, Vn.4H requires: ASIMD, FP16",
8614    },
8615    InstFeatureForm {
8616        opcode_mask: 0xfffffc00,
8617        opcode_value: 0x6ef9a800,
8618        operand_signatures: [
8619            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
8620            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
8621            0,
8622            0,
8623            0,
8624            0,
8625        ],
8626        required: 0x0000000000004002,
8627        context: "fcvtpu Vd.8H, Vn.8H requires: ASIMD, FP16",
8628    },
8629    InstFeatureForm {
8630        opcode_mask: 0xfffffc00,
8631        opcode_value: 0x1ef80000,
8632        operand_signatures: [
8633            feature_reg_signature(RegType::Gp32, VecElementType::None, false),
8634            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8635            0,
8636            0,
8637            0,
8638            0,
8639        ],
8640        required: 0x0000000000004002,
8641        context: "fcvtzs Wd, Hn requires: ASIMD, FP16",
8642    },
8643    InstFeatureForm {
8644        opcode_mask: 0xfffffc00,
8645        opcode_value: 0x9ef80000,
8646        operand_signatures: [
8647            feature_reg_signature(RegType::Gp64, VecElementType::None, false),
8648            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8649            0,
8650            0,
8651            0,
8652            0,
8653        ],
8654        required: 0x0000000000004002,
8655        context: "fcvtzs Xd, Hn requires: ASIMD, FP16",
8656    },
8657    InstFeatureForm {
8658        opcode_mask: 0xfffffc00,
8659        opcode_value: 0x5ef9b800,
8660        operand_signatures: [
8661            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8662            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8663            0,
8664            0,
8665            0,
8666            0,
8667        ],
8668        required: 0x0000000000004002,
8669        context: "fcvtzs Hd, Hn requires: ASIMD, FP16",
8670    },
8671    InstFeatureForm {
8672        opcode_mask: 0xfffffc00,
8673        opcode_value: 0x0ef9b800,
8674        operand_signatures: [
8675            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
8676            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
8677            0,
8678            0,
8679            0,
8680            0,
8681        ],
8682        required: 0x0000000000004002,
8683        context: "fcvtzs Vd.4H, Vn.4H requires: ASIMD, FP16",
8684    },
8685    InstFeatureForm {
8686        opcode_mask: 0xfffffc00,
8687        opcode_value: 0x4ef9b800,
8688        operand_signatures: [
8689            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
8690            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
8691            0,
8692            0,
8693            0,
8694            0,
8695        ],
8696        required: 0x0000000000004002,
8697        context: "fcvtzs Vd.8H, Vn.8H requires: ASIMD, FP16",
8698    },
8699    InstFeatureForm {
8700        opcode_mask: 0xffff0000,
8701        opcode_value: 0x1ed80000,
8702        operand_signatures: [
8703            feature_reg_signature(RegType::Gp32, VecElementType::None, false),
8704            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8705            OperandType::Imm as u32,
8706            0,
8707            0,
8708            0,
8709        ],
8710        required: 0x0000000000004002,
8711        context: "fcvtzs Wd, Hn, #fbits requires: ASIMD, FP16",
8712    },
8713    InstFeatureForm {
8714        opcode_mask: 0xffff0000,
8715        opcode_value: 0x9ed80000,
8716        operand_signatures: [
8717            feature_reg_signature(RegType::Gp64, VecElementType::None, false),
8718            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8719            OperandType::Imm as u32,
8720            0,
8721            0,
8722            0,
8723        ],
8724        required: 0x0000000000004002,
8725        context: "fcvtzs Xd, Hn, #fbits requires: ASIMD, FP16",
8726    },
8727    InstFeatureForm {
8728        opcode_mask: 0xff80fc00,
8729        opcode_value: 0x5f00fc00,
8730        operand_signatures: [
8731            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8732            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8733            OperandType::Imm as u32,
8734            0,
8735            0,
8736            0,
8737        ],
8738        required: 0x0000000000004002,
8739        context: "fcvtzs Hd, Hn, #fbits requires: ASIMD, FP16",
8740    },
8741    InstFeatureForm {
8742        opcode_mask: 0xff80fc00,
8743        opcode_value: 0x0f00fc00,
8744        operand_signatures: [
8745            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
8746            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
8747            OperandType::Imm as u32,
8748            0,
8749            0,
8750            0,
8751        ],
8752        required: 0x0000000000004002,
8753        context: "fcvtzs Vd.4H, Vn.4H, #fbits requires: ASIMD, FP16",
8754    },
8755    InstFeatureForm {
8756        opcode_mask: 0xff80fc00,
8757        opcode_value: 0x4f00fc00,
8758        operand_signatures: [
8759            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
8760            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
8761            OperandType::Imm as u32,
8762            0,
8763            0,
8764            0,
8765        ],
8766        required: 0x0000000000004002,
8767        context: "fcvtzs Vd.8H, Vn.8H, #fbits requires: ASIMD, FP16",
8768    },
8769    InstFeatureForm {
8770        opcode_mask: 0xfffffc00,
8771        opcode_value: 0x1ef90000,
8772        operand_signatures: [
8773            feature_reg_signature(RegType::Gp32, VecElementType::None, false),
8774            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8775            0,
8776            0,
8777            0,
8778            0,
8779        ],
8780        required: 0x0000000000004002,
8781        context: "fcvtzu Wd, Hn requires: ASIMD, FP16",
8782    },
8783    InstFeatureForm {
8784        opcode_mask: 0xfffffc00,
8785        opcode_value: 0x9ef90000,
8786        operand_signatures: [
8787            feature_reg_signature(RegType::Gp64, VecElementType::None, false),
8788            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8789            0,
8790            0,
8791            0,
8792            0,
8793        ],
8794        required: 0x0000000000004002,
8795        context: "fcvtzu Xd, Hn requires: ASIMD, FP16",
8796    },
8797    InstFeatureForm {
8798        opcode_mask: 0xfffffc00,
8799        opcode_value: 0x7ef9b800,
8800        operand_signatures: [
8801            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8802            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8803            0,
8804            0,
8805            0,
8806            0,
8807        ],
8808        required: 0x0000000000004002,
8809        context: "fcvtzu Hd, Hn requires: ASIMD, FP16",
8810    },
8811    InstFeatureForm {
8812        opcode_mask: 0xfffffc00,
8813        opcode_value: 0x2ef9b800,
8814        operand_signatures: [
8815            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
8816            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
8817            0,
8818            0,
8819            0,
8820            0,
8821        ],
8822        required: 0x0000000000004002,
8823        context: "fcvtzu Vd.4H, Vn.4H requires: ASIMD, FP16",
8824    },
8825    InstFeatureForm {
8826        opcode_mask: 0xfffffc00,
8827        opcode_value: 0x6ef9b800,
8828        operand_signatures: [
8829            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
8830            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
8831            0,
8832            0,
8833            0,
8834            0,
8835        ],
8836        required: 0x0000000000004002,
8837        context: "fcvtzu Vd.8H, Vn.8H requires: ASIMD, FP16",
8838    },
8839    InstFeatureForm {
8840        opcode_mask: 0xffff0000,
8841        opcode_value: 0x1ed90000,
8842        operand_signatures: [
8843            feature_reg_signature(RegType::Gp32, VecElementType::None, false),
8844            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8845            OperandType::Imm as u32,
8846            0,
8847            0,
8848            0,
8849        ],
8850        required: 0x0000000000004002,
8851        context: "fcvtzu Wd, Hn, #fbits requires: ASIMD, FP16",
8852    },
8853    InstFeatureForm {
8854        opcode_mask: 0xffff0000,
8855        opcode_value: 0x9ed90000,
8856        operand_signatures: [
8857            feature_reg_signature(RegType::Gp64, VecElementType::None, false),
8858            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8859            OperandType::Imm as u32,
8860            0,
8861            0,
8862            0,
8863        ],
8864        required: 0x0000000000004002,
8865        context: "fcvtzu Xd, Hn, #fbits requires: ASIMD, FP16",
8866    },
8867    InstFeatureForm {
8868        opcode_mask: 0xff80fc00,
8869        opcode_value: 0x7f00fc00,
8870        operand_signatures: [
8871            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8872            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8873            OperandType::Imm as u32,
8874            0,
8875            0,
8876            0,
8877        ],
8878        required: 0x0000000000004002,
8879        context: "fcvtzu Hd, Hn, #fbits requires: ASIMD, FP16",
8880    },
8881    InstFeatureForm {
8882        opcode_mask: 0xff80fc00,
8883        opcode_value: 0x2f00fc00,
8884        operand_signatures: [
8885            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
8886            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
8887            OperandType::Imm as u32,
8888            0,
8889            0,
8890            0,
8891        ],
8892        required: 0x0000000000004002,
8893        context: "fcvtzu Vd.4H, Vn.4H, #fbits requires: ASIMD, FP16",
8894    },
8895    InstFeatureForm {
8896        opcode_mask: 0xff80fc00,
8897        opcode_value: 0x6f00fc00,
8898        operand_signatures: [
8899            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
8900            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
8901            OperandType::Imm as u32,
8902            0,
8903            0,
8904            0,
8905        ],
8906        required: 0x0000000000004002,
8907        context: "fcvtzu Vd.8H, Vn.8H, #fbits requires: ASIMD, FP16",
8908    },
8909    InstFeatureForm {
8910        opcode_mask: 0xffe0fc00,
8911        opcode_value: 0x1ee01800,
8912        operand_signatures: [
8913            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8914            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8915            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8916            0,
8917            0,
8918            0,
8919        ],
8920        required: 0x0000000000004002,
8921        context: "fdiv Hd, Hn, Hm requires: ASIMD, FP16",
8922    },
8923    InstFeatureForm {
8924        opcode_mask: 0xffe0fc00,
8925        opcode_value: 0x2e403c00,
8926        operand_signatures: [
8927            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
8928            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
8929            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
8930            0,
8931            0,
8932            0,
8933        ],
8934        required: 0x0000000000004002,
8935        context: "fdiv Vd.4H, Vn.4H, Vm.4H requires: ASIMD, FP16",
8936    },
8937    InstFeatureForm {
8938        opcode_mask: 0xffe0fc00,
8939        opcode_value: 0x6e403c00,
8940        operand_signatures: [
8941            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
8942            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
8943            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
8944            0,
8945            0,
8946            0,
8947        ],
8948        required: 0x0000000000004002,
8949        context: "fdiv Vd.8H, Vn.8H, Vm.8H requires: ASIMD, FP16",
8950    },
8951    InstFeatureForm {
8952        opcode_mask: 0xffe08000,
8953        opcode_value: 0x1fc00000,
8954        operand_signatures: [
8955            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8956            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8957            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8958            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8959            0,
8960            0,
8961        ],
8962        required: 0x0000000000004002,
8963        context: "fmadd Hd, Hn, Hm, Ha requires: ASIMD, FP16",
8964    },
8965    InstFeatureForm {
8966        opcode_mask: 0xffe0fc00,
8967        opcode_value: 0x1ee04800,
8968        operand_signatures: [
8969            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8970            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8971            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8972            0,
8973            0,
8974            0,
8975        ],
8976        required: 0x0000000000004002,
8977        context: "fmax Hd, Hn, Hm requires: ASIMD, FP16",
8978    },
8979    InstFeatureForm {
8980        opcode_mask: 0xffe0fc00,
8981        opcode_value: 0x0e403400,
8982        operand_signatures: [
8983            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
8984            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
8985            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
8986            0,
8987            0,
8988            0,
8989        ],
8990        required: 0x0000000000004002,
8991        context: "fmax Vd.4H, Vn.4H, Vm.4H requires: ASIMD, FP16",
8992    },
8993    InstFeatureForm {
8994        opcode_mask: 0xffe0fc00,
8995        opcode_value: 0x4e403400,
8996        operand_signatures: [
8997            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
8998            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
8999            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9000            0,
9001            0,
9002            0,
9003        ],
9004        required: 0x0000000000004002,
9005        context: "fmax Vd.8H, Vn.8H, Vm.8H requires: ASIMD, FP16",
9006    },
9007    InstFeatureForm {
9008        opcode_mask: 0xffe0fc00,
9009        opcode_value: 0x1ee06800,
9010        operand_signatures: [
9011            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9012            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9013            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9014            0,
9015            0,
9016            0,
9017        ],
9018        required: 0x0000000000004002,
9019        context: "fmaxnm Hd, Hn, Hm requires: ASIMD, FP16",
9020    },
9021    InstFeatureForm {
9022        opcode_mask: 0xffe0fc00,
9023        opcode_value: 0x0e400400,
9024        operand_signatures: [
9025            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9026            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9027            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9028            0,
9029            0,
9030            0,
9031        ],
9032        required: 0x0000000000004002,
9033        context: "fmaxnm Vd.4H, Vn.4H, Vm.4H requires: ASIMD, FP16",
9034    },
9035    InstFeatureForm {
9036        opcode_mask: 0xffe0fc00,
9037        opcode_value: 0x4e400400,
9038        operand_signatures: [
9039            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9040            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9041            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9042            0,
9043            0,
9044            0,
9045        ],
9046        required: 0x0000000000004002,
9047        context: "fmaxnm Vd.8H, Vn.8H, Vm.8H requires: ASIMD, FP16",
9048    },
9049    InstFeatureForm {
9050        opcode_mask: 0xfffffc00,
9051        opcode_value: 0x5e30c800,
9052        operand_signatures: [
9053            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9054            feature_reg_signature(RegType::Vec32, VecElementType::H, false),
9055            0,
9056            0,
9057            0,
9058            0,
9059        ],
9060        required: 0x0000000000004002,
9061        context: "fmaxnmp Hd, Vn.2H requires: ASIMD, FP16",
9062    },
9063    InstFeatureForm {
9064        opcode_mask: 0xffe0fc00,
9065        opcode_value: 0x2e400400,
9066        operand_signatures: [
9067            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9068            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9069            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9070            0,
9071            0,
9072            0,
9073        ],
9074        required: 0x0000000000004002,
9075        context: "fmaxnmp Vd.4H, Vn.4H, Vm.4H requires: ASIMD, FP16",
9076    },
9077    InstFeatureForm {
9078        opcode_mask: 0xffe0fc00,
9079        opcode_value: 0x6e400400,
9080        operand_signatures: [
9081            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9082            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9083            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9084            0,
9085            0,
9086            0,
9087        ],
9088        required: 0x0000000000004002,
9089        context: "fmaxnmp Vd.8H, Vn.8H, Vm.8H requires: ASIMD, FP16",
9090    },
9091    InstFeatureForm {
9092        opcode_mask: 0xfffffc00,
9093        opcode_value: 0x0e30c800,
9094        operand_signatures: [
9095            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9096            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9097            0,
9098            0,
9099            0,
9100            0,
9101        ],
9102        required: 0x0000000000004002,
9103        context: "fmaxnmv Hd, Vn.4H requires: ASIMD, FP16",
9104    },
9105    InstFeatureForm {
9106        opcode_mask: 0xfffffc00,
9107        opcode_value: 0x4e30c800,
9108        operand_signatures: [
9109            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9110            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9111            0,
9112            0,
9113            0,
9114            0,
9115        ],
9116        required: 0x0000000000004002,
9117        context: "fmaxnmv Hd, Vn.8H requires: ASIMD, FP16",
9118    },
9119    InstFeatureForm {
9120        opcode_mask: 0xfffffc00,
9121        opcode_value: 0x5e30f800,
9122        operand_signatures: [
9123            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9124            feature_reg_signature(RegType::Vec32, VecElementType::H, false),
9125            0,
9126            0,
9127            0,
9128            0,
9129        ],
9130        required: 0x0000000000004002,
9131        context: "fmaxp Hd, Vn.2H requires: ASIMD, FP16",
9132    },
9133    InstFeatureForm {
9134        opcode_mask: 0xffe0fc00,
9135        opcode_value: 0x2e403400,
9136        operand_signatures: [
9137            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9138            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9139            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9140            0,
9141            0,
9142            0,
9143        ],
9144        required: 0x0000000000004002,
9145        context: "fmaxp Vd.4H, Vn.4H, Vm.4H requires: ASIMD, FP16",
9146    },
9147    InstFeatureForm {
9148        opcode_mask: 0xffe0fc00,
9149        opcode_value: 0x6e403400,
9150        operand_signatures: [
9151            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9152            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9153            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9154            0,
9155            0,
9156            0,
9157        ],
9158        required: 0x0000000000004002,
9159        context: "fmaxp Vd.8H, Vn.8H, Vm.8H requires: ASIMD, FP16",
9160    },
9161    InstFeatureForm {
9162        opcode_mask: 0xfffffc00,
9163        opcode_value: 0x0e30f800,
9164        operand_signatures: [
9165            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9166            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9167            0,
9168            0,
9169            0,
9170            0,
9171        ],
9172        required: 0x0000000000004002,
9173        context: "fmaxv Hd, Vn.4H requires: ASIMD, FP16",
9174    },
9175    InstFeatureForm {
9176        opcode_mask: 0xfffffc00,
9177        opcode_value: 0x4e30f800,
9178        operand_signatures: [
9179            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9180            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9181            0,
9182            0,
9183            0,
9184            0,
9185        ],
9186        required: 0x0000000000004002,
9187        context: "fmaxv Hd, Vn.8H requires: ASIMD, FP16",
9188    },
9189    InstFeatureForm {
9190        opcode_mask: 0xffe0fc00,
9191        opcode_value: 0x1ee05800,
9192        operand_signatures: [
9193            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9194            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9195            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9196            0,
9197            0,
9198            0,
9199        ],
9200        required: 0x0000000000004002,
9201        context: "fmin Hd, Hn, Hm requires: ASIMD, FP16",
9202    },
9203    InstFeatureForm {
9204        opcode_mask: 0xffe0fc00,
9205        opcode_value: 0x0ec03400,
9206        operand_signatures: [
9207            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9208            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9209            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9210            0,
9211            0,
9212            0,
9213        ],
9214        required: 0x0000000000004002,
9215        context: "fmin Vd.4H, Vn.4H, Vm.4H requires: ASIMD, FP16",
9216    },
9217    InstFeatureForm {
9218        opcode_mask: 0xffe0fc00,
9219        opcode_value: 0x4ec03400,
9220        operand_signatures: [
9221            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9222            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9223            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9224            0,
9225            0,
9226            0,
9227        ],
9228        required: 0x0000000000004002,
9229        context: "fmin Vd.8H, Vn.8H, Vm.8H requires: ASIMD, FP16",
9230    },
9231    InstFeatureForm {
9232        opcode_mask: 0xffe0fc00,
9233        opcode_value: 0x1ee07800,
9234        operand_signatures: [
9235            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9236            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9237            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9238            0,
9239            0,
9240            0,
9241        ],
9242        required: 0x0000000000004002,
9243        context: "fminnm Hd, Hn, Hm requires: ASIMD, FP16",
9244    },
9245    InstFeatureForm {
9246        opcode_mask: 0xffe0fc00,
9247        opcode_value: 0x0ec00400,
9248        operand_signatures: [
9249            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9250            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9251            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9252            0,
9253            0,
9254            0,
9255        ],
9256        required: 0x0000000000004002,
9257        context: "fminnm Vd.4H, Vn.4H, Vm.4H requires: ASIMD, FP16",
9258    },
9259    InstFeatureForm {
9260        opcode_mask: 0xffe0fc00,
9261        opcode_value: 0x4ec00400,
9262        operand_signatures: [
9263            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9264            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9265            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9266            0,
9267            0,
9268            0,
9269        ],
9270        required: 0x0000000000004002,
9271        context: "fminnm Vd.8H, Vn.8H, Vm.8H requires: ASIMD, FP16",
9272    },
9273    InstFeatureForm {
9274        opcode_mask: 0xfffffc00,
9275        opcode_value: 0x5eb0c800,
9276        operand_signatures: [
9277            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9278            feature_reg_signature(RegType::Vec32, VecElementType::H, false),
9279            0,
9280            0,
9281            0,
9282            0,
9283        ],
9284        required: 0x0000000000004002,
9285        context: "fminnmp Hd, Vn.2H requires: ASIMD, FP16",
9286    },
9287    InstFeatureForm {
9288        opcode_mask: 0xffe0fc00,
9289        opcode_value: 0x2ec00400,
9290        operand_signatures: [
9291            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9292            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9293            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9294            0,
9295            0,
9296            0,
9297        ],
9298        required: 0x0000000000004002,
9299        context: "fminnmp Vd.4H, Vn.4H, Vm.4H requires: ASIMD, FP16",
9300    },
9301    InstFeatureForm {
9302        opcode_mask: 0xffe0fc00,
9303        opcode_value: 0x6ec00400,
9304        operand_signatures: [
9305            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9306            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9307            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9308            0,
9309            0,
9310            0,
9311        ],
9312        required: 0x0000000000004002,
9313        context: "fminnmp Vd.8H, Vn.8H, Vm.8H requires: ASIMD, FP16",
9314    },
9315    InstFeatureForm {
9316        opcode_mask: 0xfffffc00,
9317        opcode_value: 0x0eb0c800,
9318        operand_signatures: [
9319            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9320            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9321            0,
9322            0,
9323            0,
9324            0,
9325        ],
9326        required: 0x0000000000004002,
9327        context: "fminnmv Hd, Vn.4H requires: ASIMD, FP16",
9328    },
9329    InstFeatureForm {
9330        opcode_mask: 0xfffffc00,
9331        opcode_value: 0x4eb0c800,
9332        operand_signatures: [
9333            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9334            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9335            0,
9336            0,
9337            0,
9338            0,
9339        ],
9340        required: 0x0000000000004002,
9341        context: "fminnmv Hd, Vn.8H requires: ASIMD, FP16",
9342    },
9343    InstFeatureForm {
9344        opcode_mask: 0xfffffc00,
9345        opcode_value: 0x5eb0f800,
9346        operand_signatures: [
9347            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9348            feature_reg_signature(RegType::Vec32, VecElementType::H, false),
9349            0,
9350            0,
9351            0,
9352            0,
9353        ],
9354        required: 0x0000000000004002,
9355        context: "fminp Hd, Vn.2H requires: ASIMD, FP16",
9356    },
9357    InstFeatureForm {
9358        opcode_mask: 0xffe0fc00,
9359        opcode_value: 0x2ec03400,
9360        operand_signatures: [
9361            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9362            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9363            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9364            0,
9365            0,
9366            0,
9367        ],
9368        required: 0x0000000000004002,
9369        context: "fminp Vd.4H, Vn.4H, Vm.4H requires: ASIMD, FP16",
9370    },
9371    InstFeatureForm {
9372        opcode_mask: 0xffe0fc00,
9373        opcode_value: 0x6ec03400,
9374        operand_signatures: [
9375            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9376            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9377            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9378            0,
9379            0,
9380            0,
9381        ],
9382        required: 0x0000000000004002,
9383        context: "fminp Vd.8H, Vn.8H, Vm.8H requires: ASIMD, FP16",
9384    },
9385    InstFeatureForm {
9386        opcode_mask: 0xfffffc00,
9387        opcode_value: 0x0eb0f800,
9388        operand_signatures: [
9389            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9390            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9391            0,
9392            0,
9393            0,
9394            0,
9395        ],
9396        required: 0x0000000000004002,
9397        context: "fminv Hd, Vn.4H requires: ASIMD, FP16",
9398    },
9399    InstFeatureForm {
9400        opcode_mask: 0xfffffc00,
9401        opcode_value: 0x4eb0f800,
9402        operand_signatures: [
9403            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9404            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9405            0,
9406            0,
9407            0,
9408            0,
9409        ],
9410        required: 0x0000000000004002,
9411        context: "fminv Hd, Vn.8H requires: ASIMD, FP16",
9412    },
9413    InstFeatureForm {
9414        opcode_mask: 0xffe0fc00,
9415        opcode_value: 0x0e400c00,
9416        operand_signatures: [
9417            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9418            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9419            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9420            0,
9421            0,
9422            0,
9423        ],
9424        required: 0x0000000000004002,
9425        context: "fmla Vx.4H, Vn.4H, Vm.4H requires: ASIMD, FP16",
9426    },
9427    InstFeatureForm {
9428        opcode_mask: 0xffe0fc00,
9429        opcode_value: 0x4e400c00,
9430        operand_signatures: [
9431            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9432            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9433            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9434            0,
9435            0,
9436            0,
9437        ],
9438        required: 0x0000000000004002,
9439        context: "fmla Vx.8H, Vn.8H, Vm.8H requires: ASIMD, FP16",
9440    },
9441    InstFeatureForm {
9442        opcode_mask: 0xffc0f400,
9443        opcode_value: 0x5f001000,
9444        operand_signatures: [
9445            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9446            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9447            feature_reg_signature(RegType::Vec128, VecElementType::H, true),
9448            0,
9449            0,
9450            0,
9451        ],
9452        required: 0x0000000000004002,
9453        context: "fmla Hx, Hn, Vm.H[#idx] requires: ASIMD, FP16",
9454    },
9455    InstFeatureForm {
9456        opcode_mask: 0xffc0f400,
9457        opcode_value: 0x0f001000,
9458        operand_signatures: [
9459            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9460            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9461            feature_reg_signature(RegType::Vec128, VecElementType::H, true),
9462            0,
9463            0,
9464            0,
9465        ],
9466        required: 0x0000000000004002,
9467        context: "fmla Vx.4H, Vn.4H, Vm.H[#idx] requires: ASIMD, FP16",
9468    },
9469    InstFeatureForm {
9470        opcode_mask: 0xffc0f400,
9471        opcode_value: 0x4f001000,
9472        operand_signatures: [
9473            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9474            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9475            feature_reg_signature(RegType::Vec128, VecElementType::H, true),
9476            0,
9477            0,
9478            0,
9479        ],
9480        required: 0x0000000000004002,
9481        context: "fmla Vx.8H, Vn.8H, Vm.H[#idx] requires: ASIMD, FP16",
9482    },
9483    InstFeatureForm {
9484        opcode_mask: 0xffe0fc00,
9485        opcode_value: 0x0ec00c00,
9486        operand_signatures: [
9487            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9488            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9489            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9490            0,
9491            0,
9492            0,
9493        ],
9494        required: 0x0000000000004002,
9495        context: "fmls Vx.4H, Vn.4H, Vm.4H requires: ASIMD, FP16",
9496    },
9497    InstFeatureForm {
9498        opcode_mask: 0xffe0fc00,
9499        opcode_value: 0x4ec00c00,
9500        operand_signatures: [
9501            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9502            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9503            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9504            0,
9505            0,
9506            0,
9507        ],
9508        required: 0x0000000000004002,
9509        context: "fmls Vx.8H, Vn.8H, Vm.8H requires: ASIMD, FP16",
9510    },
9511    InstFeatureForm {
9512        opcode_mask: 0xffc0f400,
9513        opcode_value: 0x5f005000,
9514        operand_signatures: [
9515            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9516            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9517            feature_reg_signature(RegType::Vec128, VecElementType::H, true),
9518            0,
9519            0,
9520            0,
9521        ],
9522        required: 0x0000000000004002,
9523        context: "fmls Hx, Hn, Vm.H[#idx] requires: ASIMD, FP16",
9524    },
9525    InstFeatureForm {
9526        opcode_mask: 0xffc0f400,
9527        opcode_value: 0x0f005000,
9528        operand_signatures: [
9529            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9530            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9531            feature_reg_signature(RegType::Vec128, VecElementType::H, true),
9532            0,
9533            0,
9534            0,
9535        ],
9536        required: 0x0000000000004002,
9537        context: "fmls Vx.4H, Vn.4H, Vm.H[#idx] requires: ASIMD, FP16",
9538    },
9539    InstFeatureForm {
9540        opcode_mask: 0xffc0f400,
9541        opcode_value: 0x4f005000,
9542        operand_signatures: [
9543            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9544            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9545            feature_reg_signature(RegType::Vec128, VecElementType::H, true),
9546            0,
9547            0,
9548            0,
9549        ],
9550        required: 0x0000000000004002,
9551        context: "fmls Vx.8H, Vn.8H, Vm.H[#idx] requires: ASIMD, FP16",
9552    },
9553    InstFeatureForm {
9554        opcode_mask: 0xfffffc00,
9555        opcode_value: 0x1ee60000,
9556        operand_signatures: [
9557            feature_reg_signature(RegType::Gp32, VecElementType::None, false),
9558            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9559            0,
9560            0,
9561            0,
9562            0,
9563        ],
9564        required: 0x0000000000004002,
9565        context: "fmov Wd, Hn requires: ASIMD, FP16",
9566    },
9567    InstFeatureForm {
9568        opcode_mask: 0xfffffc00,
9569        opcode_value: 0x9ee60000,
9570        operand_signatures: [
9571            feature_reg_signature(RegType::Gp64, VecElementType::None, false),
9572            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9573            0,
9574            0,
9575            0,
9576            0,
9577        ],
9578        required: 0x0000000000004002,
9579        context: "fmov Xd, Hn requires: ASIMD, FP16",
9580    },
9581    InstFeatureForm {
9582        opcode_mask: 0xfffffc00,
9583        opcode_value: 0x1ee70000,
9584        operand_signatures: [
9585            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9586            feature_reg_signature(RegType::Gp32, VecElementType::None, false),
9587            0,
9588            0,
9589            0,
9590            0,
9591        ],
9592        required: 0x0000000000004002,
9593        context: "fmov Hd, Wn requires: ASIMD, FP16",
9594    },
9595    InstFeatureForm {
9596        opcode_mask: 0xfffffc00,
9597        opcode_value: 0x9ee70000,
9598        operand_signatures: [
9599            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9600            feature_reg_signature(RegType::Gp64, VecElementType::None, false),
9601            0,
9602            0,
9603            0,
9604            0,
9605        ],
9606        required: 0x0000000000004002,
9607        context: "fmov Hd, Xn requires: ASIMD, FP16",
9608    },
9609    InstFeatureForm {
9610        opcode_mask: 0xfffffc00,
9611        opcode_value: 0x1ee04000,
9612        operand_signatures: [
9613            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9614            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9615            0,
9616            0,
9617            0,
9618            0,
9619        ],
9620        required: 0x0000000000004002,
9621        context: "fmov Hd, Hn requires: ASIMD, FP16",
9622    },
9623    InstFeatureForm {
9624        opcode_mask: 0xffe01fe0,
9625        opcode_value: 0x1ee01000,
9626        operand_signatures: [
9627            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9628            OperandType::Imm as u32,
9629            0,
9630            0,
9631            0,
9632            0,
9633        ],
9634        required: 0x0000000000004002,
9635        context: "fmov Hd, #fimm requires: ASIMD, FP16",
9636    },
9637    InstFeatureForm {
9638        opcode_mask: 0xfff8fc00,
9639        opcode_value: 0x0f00fc00,
9640        operand_signatures: [
9641            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9642            OperandType::Imm as u32,
9643            0,
9644            0,
9645            0,
9646            0,
9647        ],
9648        required: 0x0000000000004002,
9649        context: "fmov Vd.4H, #fimm requires: ASIMD, FP16",
9650    },
9651    InstFeatureForm {
9652        opcode_mask: 0xfff8fc00,
9653        opcode_value: 0x4f00fc00,
9654        operand_signatures: [
9655            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9656            OperandType::Imm as u32,
9657            0,
9658            0,
9659            0,
9660            0,
9661        ],
9662        required: 0x0000000000004002,
9663        context: "fmov Vd.8H, #fimm requires: ASIMD, FP16",
9664    },
9665    InstFeatureForm {
9666        opcode_mask: 0xffe08000,
9667        opcode_value: 0x1fc08000,
9668        operand_signatures: [
9669            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9670            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9671            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9672            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9673            0,
9674            0,
9675        ],
9676        required: 0x0000000000004002,
9677        context: "fmsub Hd, Hn, Hm, Ha requires: ASIMD, FP16",
9678    },
9679    InstFeatureForm {
9680        opcode_mask: 0xffe0fc00,
9681        opcode_value: 0x1ee00800,
9682        operand_signatures: [
9683            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9684            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9685            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9686            0,
9687            0,
9688            0,
9689        ],
9690        required: 0x0000000000004002,
9691        context: "fmul Hd, Hn, Hm requires: ASIMD, FP16",
9692    },
9693    InstFeatureForm {
9694        opcode_mask: 0xffe0fc00,
9695        opcode_value: 0x2e401c00,
9696        operand_signatures: [
9697            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9698            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9699            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9700            0,
9701            0,
9702            0,
9703        ],
9704        required: 0x0000000000004002,
9705        context: "fmul Vd.4H, Vn.4H, Vm.4H requires: ASIMD, FP16",
9706    },
9707    InstFeatureForm {
9708        opcode_mask: 0xffe0fc00,
9709        opcode_value: 0x6e401c00,
9710        operand_signatures: [
9711            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9712            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9713            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9714            0,
9715            0,
9716            0,
9717        ],
9718        required: 0x0000000000004002,
9719        context: "fmul Vd.8H, Vn.8H, Vm.8H requires: ASIMD, FP16",
9720    },
9721    InstFeatureForm {
9722        opcode_mask: 0xffc0f400,
9723        opcode_value: 0x5f009000,
9724        operand_signatures: [
9725            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9726            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9727            feature_reg_signature(RegType::Vec128, VecElementType::H, true),
9728            0,
9729            0,
9730            0,
9731        ],
9732        required: 0x0000000000004002,
9733        context: "fmul Hd, Hn, Vm.H[#idx] requires: ASIMD, FP16",
9734    },
9735    InstFeatureForm {
9736        opcode_mask: 0xffc0f400,
9737        opcode_value: 0x0f009000,
9738        operand_signatures: [
9739            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9740            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9741            feature_reg_signature(RegType::Vec128, VecElementType::H, true),
9742            0,
9743            0,
9744            0,
9745        ],
9746        required: 0x0000000000004002,
9747        context: "fmul Vd.4H, Vn.4H, Vm.H[#idx] requires: ASIMD, FP16",
9748    },
9749    InstFeatureForm {
9750        opcode_mask: 0xffc0f400,
9751        opcode_value: 0x4f009000,
9752        operand_signatures: [
9753            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9754            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9755            feature_reg_signature(RegType::Vec128, VecElementType::H, true),
9756            0,
9757            0,
9758            0,
9759        ],
9760        required: 0x0000000000004002,
9761        context: "fmul Vd.8H, Vn.8H, Vm.H[#idx] requires: ASIMD, FP16",
9762    },
9763    InstFeatureForm {
9764        opcode_mask: 0xffe0fc00,
9765        opcode_value: 0x5e401c00,
9766        operand_signatures: [
9767            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9768            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9769            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9770            0,
9771            0,
9772            0,
9773        ],
9774        required: 0x0000000000004002,
9775        context: "fmulx Hd, Hn, Hm requires: ASIMD, FP16",
9776    },
9777    InstFeatureForm {
9778        opcode_mask: 0xffe0fc00,
9779        opcode_value: 0x0e401c00,
9780        operand_signatures: [
9781            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9782            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9783            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9784            0,
9785            0,
9786            0,
9787        ],
9788        required: 0x0000000000004002,
9789        context: "fmulx Vd.4H, Vn.4H, Vm.4H requires: ASIMD, FP16",
9790    },
9791    InstFeatureForm {
9792        opcode_mask: 0xffe0fc00,
9793        opcode_value: 0x4e401c00,
9794        operand_signatures: [
9795            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9796            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9797            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9798            0,
9799            0,
9800            0,
9801        ],
9802        required: 0x0000000000004002,
9803        context: "fmulx Vd.8H, Vn.8H, Vm.8H requires: ASIMD, FP16",
9804    },
9805    InstFeatureForm {
9806        opcode_mask: 0xffc0f400,
9807        opcode_value: 0x7f009000,
9808        operand_signatures: [
9809            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9810            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9811            feature_reg_signature(RegType::Vec128, VecElementType::H, true),
9812            0,
9813            0,
9814            0,
9815        ],
9816        required: 0x0000000000004002,
9817        context: "fmulx Hd, Hn, Vm.H[#idx] requires: ASIMD, FP16",
9818    },
9819    InstFeatureForm {
9820        opcode_mask: 0xffc0f400,
9821        opcode_value: 0x2f009000,
9822        operand_signatures: [
9823            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9824            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9825            feature_reg_signature(RegType::Vec128, VecElementType::H, true),
9826            0,
9827            0,
9828            0,
9829        ],
9830        required: 0x0000000000004002,
9831        context: "fmulx Vd.4H, Vn.4H, Vm.H[#idx] requires: ASIMD, FP16",
9832    },
9833    InstFeatureForm {
9834        opcode_mask: 0xffc0f400,
9835        opcode_value: 0x6f009000,
9836        operand_signatures: [
9837            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9838            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9839            feature_reg_signature(RegType::Vec128, VecElementType::H, true),
9840            0,
9841            0,
9842            0,
9843        ],
9844        required: 0x0000000000004002,
9845        context: "fmulx Vd.8H, Vn.8H, Vm.H[#idx] requires: ASIMD, FP16",
9846    },
9847    InstFeatureForm {
9848        opcode_mask: 0xfffffc00,
9849        opcode_value: 0x1ee14000,
9850        operand_signatures: [
9851            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9852            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9853            0,
9854            0,
9855            0,
9856            0,
9857        ],
9858        required: 0x0000000000004002,
9859        context: "fneg Hd, Hn requires: ASIMD, FP16",
9860    },
9861    InstFeatureForm {
9862        opcode_mask: 0xfffffc00,
9863        opcode_value: 0x2ef8f800,
9864        operand_signatures: [
9865            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9866            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9867            0,
9868            0,
9869            0,
9870            0,
9871        ],
9872        required: 0x0000000000004002,
9873        context: "fneg Vd.4H, Vn.4H requires: ASIMD, FP16",
9874    },
9875    InstFeatureForm {
9876        opcode_mask: 0xfffffc00,
9877        opcode_value: 0x6ef8f800,
9878        operand_signatures: [
9879            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9880            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9881            0,
9882            0,
9883            0,
9884            0,
9885        ],
9886        required: 0x0000000000004002,
9887        context: "fneg Vd.8H, Vn.8H requires: ASIMD, FP16",
9888    },
9889    InstFeatureForm {
9890        opcode_mask: 0xffe08000,
9891        opcode_value: 0x1fe00000,
9892        operand_signatures: [
9893            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9894            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9895            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9896            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9897            0,
9898            0,
9899        ],
9900        required: 0x0000000000004002,
9901        context: "fnmadd Hd, Hn, Hm, Ha requires: ASIMD, FP16",
9902    },
9903    InstFeatureForm {
9904        opcode_mask: 0xffe08000,
9905        opcode_value: 0x1fe08000,
9906        operand_signatures: [
9907            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9908            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9909            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9910            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9911            0,
9912            0,
9913        ],
9914        required: 0x0000000000004002,
9915        context: "fnmsub Hd, Hn, Hm, Ha requires: ASIMD, FP16",
9916    },
9917    InstFeatureForm {
9918        opcode_mask: 0xffe0fc00,
9919        opcode_value: 0x1ee08800,
9920        operand_signatures: [
9921            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9922            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9923            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9924            0,
9925            0,
9926            0,
9927        ],
9928        required: 0x0000000000004002,
9929        context: "fnmul Hd, Hn, Hm requires: ASIMD, FP16",
9930    },
9931    InstFeatureForm {
9932        opcode_mask: 0xfffffc00,
9933        opcode_value: 0x5ef9d800,
9934        operand_signatures: [
9935            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9936            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9937            0,
9938            0,
9939            0,
9940            0,
9941        ],
9942        required: 0x0000000000004002,
9943        context: "frecpe Hd, Hn requires: ASIMD, FP16",
9944    },
9945    InstFeatureForm {
9946        opcode_mask: 0xfffffc00,
9947        opcode_value: 0x0ef9d800,
9948        operand_signatures: [
9949            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9950            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9951            0,
9952            0,
9953            0,
9954            0,
9955        ],
9956        required: 0x0000000000004002,
9957        context: "frecpe Vd.4H, Vn.4H requires: ASIMD, FP16",
9958    },
9959    InstFeatureForm {
9960        opcode_mask: 0xfffffc00,
9961        opcode_value: 0x4ef9d800,
9962        operand_signatures: [
9963            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9964            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9965            0,
9966            0,
9967            0,
9968            0,
9969        ],
9970        required: 0x0000000000004002,
9971        context: "frecpe Vd.8H, Vn.8H requires: ASIMD, FP16",
9972    },
9973    InstFeatureForm {
9974        opcode_mask: 0xffe0fc00,
9975        opcode_value: 0x5e403c00,
9976        operand_signatures: [
9977            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9978            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9979            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9980            0,
9981            0,
9982            0,
9983        ],
9984        required: 0x0000000000004002,
9985        context: "frecps Hd, Hn, Hm requires: ASIMD, FP16",
9986    },
9987    InstFeatureForm {
9988        opcode_mask: 0xffe0fc00,
9989        opcode_value: 0x0e403c00,
9990        operand_signatures: [
9991            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9992            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9993            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9994            0,
9995            0,
9996            0,
9997        ],
9998        required: 0x0000000000004002,
9999        context: "frecps Vd.4H, Vn.4H, Vm.4H requires: ASIMD, FP16",
10000    },
10001    InstFeatureForm {
10002        opcode_mask: 0xffe0fc00,
10003        opcode_value: 0x4e403c00,
10004        operand_signatures: [
10005            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10006            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10007            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10008            0,
10009            0,
10010            0,
10011        ],
10012        required: 0x0000000000004002,
10013        context: "frecps Vd.8H, Vn.8H, Vm.8H requires: ASIMD, FP16",
10014    },
10015    InstFeatureForm {
10016        opcode_mask: 0xfffffc00,
10017        opcode_value: 0x5ef9f800,
10018        operand_signatures: [
10019            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10020            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10021            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10022            0,
10023            0,
10024            0,
10025        ],
10026        required: 0x0000000000004002,
10027        context: "frecpx Hd, Hn, Hm requires: ASIMD, FP16",
10028    },
10029    InstFeatureForm {
10030        opcode_mask: 0xfffffc00,
10031        opcode_value: 0x1ee64000,
10032        operand_signatures: [
10033            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10034            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10035            0,
10036            0,
10037            0,
10038            0,
10039        ],
10040        required: 0x0000000000004002,
10041        context: "frinta Hd, Hn requires: ASIMD, FP16",
10042    },
10043    InstFeatureForm {
10044        opcode_mask: 0xfffffc00,
10045        opcode_value: 0x2e798800,
10046        operand_signatures: [
10047            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10048            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10049            0,
10050            0,
10051            0,
10052            0,
10053        ],
10054        required: 0x0000000000004002,
10055        context: "frinta Vd.4H, Vn.4H requires: ASIMD, FP16",
10056    },
10057    InstFeatureForm {
10058        opcode_mask: 0xfffffc00,
10059        opcode_value: 0x6e798800,
10060        operand_signatures: [
10061            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10062            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10063            0,
10064            0,
10065            0,
10066            0,
10067        ],
10068        required: 0x0000000000004002,
10069        context: "frinta Vd.8H, Vn.8H requires: ASIMD, FP16",
10070    },
10071    InstFeatureForm {
10072        opcode_mask: 0xfffffc00,
10073        opcode_value: 0x1ee7c000,
10074        operand_signatures: [
10075            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10076            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10077            0,
10078            0,
10079            0,
10080            0,
10081        ],
10082        required: 0x0000000000004002,
10083        context: "frinti Hd, Hn requires: ASIMD, FP16",
10084    },
10085    InstFeatureForm {
10086        opcode_mask: 0xfffffc00,
10087        opcode_value: 0x2ef99800,
10088        operand_signatures: [
10089            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10090            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10091            0,
10092            0,
10093            0,
10094            0,
10095        ],
10096        required: 0x0000000000004002,
10097        context: "frinti Vd.4H, Vn.4H requires: ASIMD, FP16",
10098    },
10099    InstFeatureForm {
10100        opcode_mask: 0xfffffc00,
10101        opcode_value: 0x6ef99800,
10102        operand_signatures: [
10103            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10104            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10105            0,
10106            0,
10107            0,
10108            0,
10109        ],
10110        required: 0x0000000000004002,
10111        context: "frinti Vd.8H, Vn.8H requires: ASIMD, FP16",
10112    },
10113    InstFeatureForm {
10114        opcode_mask: 0xfffffc00,
10115        opcode_value: 0x1ee54000,
10116        operand_signatures: [
10117            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10118            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10119            0,
10120            0,
10121            0,
10122            0,
10123        ],
10124        required: 0x0000000000004002,
10125        context: "frintm Hd, Hn requires: ASIMD, FP16",
10126    },
10127    InstFeatureForm {
10128        opcode_mask: 0xfffffc00,
10129        opcode_value: 0x0e799800,
10130        operand_signatures: [
10131            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10132            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10133            0,
10134            0,
10135            0,
10136            0,
10137        ],
10138        required: 0x0000000000004002,
10139        context: "frintm Vd.4H, Vn.4H requires: ASIMD, FP16",
10140    },
10141    InstFeatureForm {
10142        opcode_mask: 0xfffffc00,
10143        opcode_value: 0x4e799800,
10144        operand_signatures: [
10145            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10146            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10147            0,
10148            0,
10149            0,
10150            0,
10151        ],
10152        required: 0x0000000000004002,
10153        context: "frintm Vd.8H, Vn.8H requires: ASIMD, FP16",
10154    },
10155    InstFeatureForm {
10156        opcode_mask: 0xfffffc00,
10157        opcode_value: 0x1ee44000,
10158        operand_signatures: [
10159            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10160            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10161            0,
10162            0,
10163            0,
10164            0,
10165        ],
10166        required: 0x0000000000004002,
10167        context: "frintn Hd, Hn requires: ASIMD, FP16",
10168    },
10169    InstFeatureForm {
10170        opcode_mask: 0xfffffc00,
10171        opcode_value: 0x0e798800,
10172        operand_signatures: [
10173            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10174            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10175            0,
10176            0,
10177            0,
10178            0,
10179        ],
10180        required: 0x0000000000004002,
10181        context: "frintn Vd.4H, Vn.4H requires: ASIMD, FP16",
10182    },
10183    InstFeatureForm {
10184        opcode_mask: 0xfffffc00,
10185        opcode_value: 0x4e798800,
10186        operand_signatures: [
10187            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10188            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10189            0,
10190            0,
10191            0,
10192            0,
10193        ],
10194        required: 0x0000000000004002,
10195        context: "frintn Vd.8H, Vn.8H requires: ASIMD, FP16",
10196    },
10197    InstFeatureForm {
10198        opcode_mask: 0xfffffc00,
10199        opcode_value: 0x1ee4c000,
10200        operand_signatures: [
10201            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10202            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10203            0,
10204            0,
10205            0,
10206            0,
10207        ],
10208        required: 0x0000000000004002,
10209        context: "frintp Hd, Hn requires: ASIMD, FP16",
10210    },
10211    InstFeatureForm {
10212        opcode_mask: 0xfffffc00,
10213        opcode_value: 0x0ef98800,
10214        operand_signatures: [
10215            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10216            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10217            0,
10218            0,
10219            0,
10220            0,
10221        ],
10222        required: 0x0000000000004002,
10223        context: "frintp Vd.4H, Vn.4H requires: ASIMD, FP16",
10224    },
10225    InstFeatureForm {
10226        opcode_mask: 0xfffffc00,
10227        opcode_value: 0x4ef98800,
10228        operand_signatures: [
10229            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10230            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10231            0,
10232            0,
10233            0,
10234            0,
10235        ],
10236        required: 0x0000000000004002,
10237        context: "frintp Vd.8H, Vn.8H requires: ASIMD, FP16",
10238    },
10239    InstFeatureForm {
10240        opcode_mask: 0xfffffc00,
10241        opcode_value: 0x1ee74000,
10242        operand_signatures: [
10243            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10244            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10245            0,
10246            0,
10247            0,
10248            0,
10249        ],
10250        required: 0x0000000000004002,
10251        context: "frintx Hd, Hn requires: ASIMD, FP16",
10252    },
10253    InstFeatureForm {
10254        opcode_mask: 0xfffffc00,
10255        opcode_value: 0x2e799800,
10256        operand_signatures: [
10257            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10258            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10259            0,
10260            0,
10261            0,
10262            0,
10263        ],
10264        required: 0x0000000000004002,
10265        context: "frintx Vd.4H, Vn.4H requires: ASIMD, FP16",
10266    },
10267    InstFeatureForm {
10268        opcode_mask: 0xfffffc00,
10269        opcode_value: 0x6e799800,
10270        operand_signatures: [
10271            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10272            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10273            0,
10274            0,
10275            0,
10276            0,
10277        ],
10278        required: 0x0000000000004002,
10279        context: "frintx Vd.8H, Vn.8H requires: ASIMD, FP16",
10280    },
10281    InstFeatureForm {
10282        opcode_mask: 0xfffffc00,
10283        opcode_value: 0x1ee5c000,
10284        operand_signatures: [
10285            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10286            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10287            0,
10288            0,
10289            0,
10290            0,
10291        ],
10292        required: 0x0000000000004002,
10293        context: "frintz Hd, Hn requires: ASIMD, FP16",
10294    },
10295    InstFeatureForm {
10296        opcode_mask: 0xfffffc00,
10297        opcode_value: 0x0ef99800,
10298        operand_signatures: [
10299            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10300            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10301            0,
10302            0,
10303            0,
10304            0,
10305        ],
10306        required: 0x0000000000004002,
10307        context: "frintz Vd.4H, Vn.4H requires: ASIMD, FP16",
10308    },
10309    InstFeatureForm {
10310        opcode_mask: 0xfffffc00,
10311        opcode_value: 0x4ef99800,
10312        operand_signatures: [
10313            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10314            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10315            0,
10316            0,
10317            0,
10318            0,
10319        ],
10320        required: 0x0000000000004002,
10321        context: "frintz Vd.8H, Vn.8H requires: ASIMD, FP16",
10322    },
10323    InstFeatureForm {
10324        opcode_mask: 0xfffffc00,
10325        opcode_value: 0x7ef9d800,
10326        operand_signatures: [
10327            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10328            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10329            0,
10330            0,
10331            0,
10332            0,
10333        ],
10334        required: 0x0000000000004002,
10335        context: "frsqrte Hd, Hn requires: ASIMD, FP16",
10336    },
10337    InstFeatureForm {
10338        opcode_mask: 0xfffffc00,
10339        opcode_value: 0x2ef9d800,
10340        operand_signatures: [
10341            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10342            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10343            0,
10344            0,
10345            0,
10346            0,
10347        ],
10348        required: 0x0000000000004002,
10349        context: "frsqrte Vd.4H, Vn.4H requires: ASIMD, FP16",
10350    },
10351    InstFeatureForm {
10352        opcode_mask: 0xfffffc00,
10353        opcode_value: 0x6ef9d800,
10354        operand_signatures: [
10355            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10356            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10357            0,
10358            0,
10359            0,
10360            0,
10361        ],
10362        required: 0x0000000000004002,
10363        context: "frsqrte Vd.8H, Vn.8H requires: ASIMD, FP16",
10364    },
10365    InstFeatureForm {
10366        opcode_mask: 0xffe0fc00,
10367        opcode_value: 0x5ec03c00,
10368        operand_signatures: [
10369            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10370            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10371            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10372            0,
10373            0,
10374            0,
10375        ],
10376        required: 0x0000000000004002,
10377        context: "frsqrts Hd, Hn, Hm requires: ASIMD, FP16",
10378    },
10379    InstFeatureForm {
10380        opcode_mask: 0xffe0fc00,
10381        opcode_value: 0x0ec03c00,
10382        operand_signatures: [
10383            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10384            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10385            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10386            0,
10387            0,
10388            0,
10389        ],
10390        required: 0x0000000000004002,
10391        context: "frsqrts Vd.4H, Vn.4H, Vm.4H requires: ASIMD, FP16",
10392    },
10393    InstFeatureForm {
10394        opcode_mask: 0xffe0fc00,
10395        opcode_value: 0x4ec03c00,
10396        operand_signatures: [
10397            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10398            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10399            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10400            0,
10401            0,
10402            0,
10403        ],
10404        required: 0x0000000000004002,
10405        context: "frsqrts Vd.8H, Vn.8H, Vm.8H requires: ASIMD, FP16",
10406    },
10407    InstFeatureForm {
10408        opcode_mask: 0xfffffc00,
10409        opcode_value: 0x1ee1c000,
10410        operand_signatures: [
10411            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10412            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10413            0,
10414            0,
10415            0,
10416            0,
10417        ],
10418        required: 0x0000000000004002,
10419        context: "fsqrt Hd, Hn requires: ASIMD, FP16",
10420    },
10421    InstFeatureForm {
10422        opcode_mask: 0xfffffc00,
10423        opcode_value: 0x2ef9f800,
10424        operand_signatures: [
10425            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10426            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10427            0,
10428            0,
10429            0,
10430            0,
10431        ],
10432        required: 0x0000000000004002,
10433        context: "fsqrt Vd.4H, Vn.4H requires: ASIMD, FP16",
10434    },
10435    InstFeatureForm {
10436        opcode_mask: 0xfffffc00,
10437        opcode_value: 0x6ef9f800,
10438        operand_signatures: [
10439            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10440            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10441            0,
10442            0,
10443            0,
10444            0,
10445        ],
10446        required: 0x0000000000004002,
10447        context: "fsqrt Vd.8H, Vn.8H requires: ASIMD, FP16",
10448    },
10449    InstFeatureForm {
10450        opcode_mask: 0xffe0fc00,
10451        opcode_value: 0x1ee03800,
10452        operand_signatures: [
10453            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10454            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10455            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10456            0,
10457            0,
10458            0,
10459        ],
10460        required: 0x0000000000004002,
10461        context: "fsub Hd, Hn, Hm requires: ASIMD, FP16",
10462    },
10463    InstFeatureForm {
10464        opcode_mask: 0xffe0fc00,
10465        opcode_value: 0x0ec01400,
10466        operand_signatures: [
10467            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10468            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10469            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10470            0,
10471            0,
10472            0,
10473        ],
10474        required: 0x0000000000004002,
10475        context: "fsub Vd.4H, Vn.4H, Vm.4H requires: ASIMD, FP16",
10476    },
10477    InstFeatureForm {
10478        opcode_mask: 0xffe0fc00,
10479        opcode_value: 0x4ec01400,
10480        operand_signatures: [
10481            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10482            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10483            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10484            0,
10485            0,
10486            0,
10487        ],
10488        required: 0x0000000000004002,
10489        context: "fsub Vd.8H, Vn.8H, Vm.8H requires: ASIMD, FP16",
10490    },
10491    InstFeatureForm {
10492        opcode_mask: 0xfffffc00,
10493        opcode_value: 0x1ee20000,
10494        operand_signatures: [
10495            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10496            feature_reg_signature(RegType::Gp32, VecElementType::None, false),
10497            0,
10498            0,
10499            0,
10500            0,
10501        ],
10502        required: 0x0000000000004002,
10503        context: "scvtf Hd, Wn requires: ASIMD, FP16",
10504    },
10505    InstFeatureForm {
10506        opcode_mask: 0xfffffc00,
10507        opcode_value: 0x9ee20000,
10508        operand_signatures: [
10509            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10510            feature_reg_signature(RegType::Gp64, VecElementType::None, false),
10511            0,
10512            0,
10513            0,
10514            0,
10515        ],
10516        required: 0x0000000000004002,
10517        context: "scvtf Hd, Xn requires: ASIMD, FP16",
10518    },
10519    InstFeatureForm {
10520        opcode_mask: 0xfffffc00,
10521        opcode_value: 0x5e79d800,
10522        operand_signatures: [
10523            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10524            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10525            0,
10526            0,
10527            0,
10528            0,
10529        ],
10530        required: 0x0000000000004002,
10531        context: "scvtf Hd, Hn requires: ASIMD, FP16",
10532    },
10533    InstFeatureForm {
10534        opcode_mask: 0xfffffc00,
10535        opcode_value: 0x0e79d800,
10536        operand_signatures: [
10537            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10538            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10539            0,
10540            0,
10541            0,
10542            0,
10543        ],
10544        required: 0x0000000000004002,
10545        context: "scvtf Vd.4H, Vn.4H requires: ASIMD, FP16",
10546    },
10547    InstFeatureForm {
10548        opcode_mask: 0xfffffc00,
10549        opcode_value: 0x4e79d800,
10550        operand_signatures: [
10551            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10552            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10553            0,
10554            0,
10555            0,
10556            0,
10557        ],
10558        required: 0x0000000000004002,
10559        context: "scvtf Vd.8H, Vn.8H requires: ASIMD, FP16",
10560    },
10561    InstFeatureForm {
10562        opcode_mask: 0xffff0000,
10563        opcode_value: 0x1ec20000,
10564        operand_signatures: [
10565            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10566            feature_reg_signature(RegType::Gp32, VecElementType::None, false),
10567            OperandType::Imm as u32,
10568            0,
10569            0,
10570            0,
10571        ],
10572        required: 0x0000000000004002,
10573        context: "scvtf Hd, Wn, #fbits requires: ASIMD, FP16",
10574    },
10575    InstFeatureForm {
10576        opcode_mask: 0xffff0000,
10577        opcode_value: 0x9ec20000,
10578        operand_signatures: [
10579            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10580            feature_reg_signature(RegType::Gp64, VecElementType::None, false),
10581            OperandType::Imm as u32,
10582            0,
10583            0,
10584            0,
10585        ],
10586        required: 0x0000000000004002,
10587        context: "scvtf Hd, Xn, #fbits requires: ASIMD, FP16",
10588    },
10589    InstFeatureForm {
10590        opcode_mask: 0xff80fc00,
10591        opcode_value: 0x5f00e400,
10592        operand_signatures: [
10593            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10594            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10595            OperandType::Imm as u32,
10596            0,
10597            0,
10598            0,
10599        ],
10600        required: 0x0000000000004002,
10601        context: "scvtf Hd, Hn, #bits requires: ASIMD, FP16",
10602    },
10603    InstFeatureForm {
10604        opcode_mask: 0xff80fc00,
10605        opcode_value: 0x0f00e400,
10606        operand_signatures: [
10607            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10608            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10609            OperandType::Imm as u32,
10610            0,
10611            0,
10612            0,
10613        ],
10614        required: 0x0000000000004002,
10615        context: "scvtf Vd.4H, Vn.4H, #fbits requires: ASIMD, FP16",
10616    },
10617    InstFeatureForm {
10618        opcode_mask: 0xff80fc00,
10619        opcode_value: 0x4f00e400,
10620        operand_signatures: [
10621            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10622            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10623            OperandType::Imm as u32,
10624            0,
10625            0,
10626            0,
10627        ],
10628        required: 0x0000000000004002,
10629        context: "scvtf Vd.8H, Vn.8H, #fbits requires: ASIMD, FP16",
10630    },
10631    InstFeatureForm {
10632        opcode_mask: 0xfffffc00,
10633        opcode_value: 0x1ee30000,
10634        operand_signatures: [
10635            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10636            feature_reg_signature(RegType::Gp32, VecElementType::None, false),
10637            0,
10638            0,
10639            0,
10640            0,
10641        ],
10642        required: 0x0000000000004002,
10643        context: "ucvtf Hd, Wn requires: ASIMD, FP16",
10644    },
10645    InstFeatureForm {
10646        opcode_mask: 0xfffffc00,
10647        opcode_value: 0x9ee30000,
10648        operand_signatures: [
10649            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10650            feature_reg_signature(RegType::Gp64, VecElementType::None, false),
10651            0,
10652            0,
10653            0,
10654            0,
10655        ],
10656        required: 0x0000000000004002,
10657        context: "ucvtf Hd, Xn requires: ASIMD, FP16",
10658    },
10659    InstFeatureForm {
10660        opcode_mask: 0xfffffc00,
10661        opcode_value: 0x7e79d800,
10662        operand_signatures: [
10663            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10664            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10665            0,
10666            0,
10667            0,
10668            0,
10669        ],
10670        required: 0x0000000000004002,
10671        context: "ucvtf Hd, Hn requires: ASIMD, FP16",
10672    },
10673    InstFeatureForm {
10674        opcode_mask: 0xfffffc00,
10675        opcode_value: 0x2e79d800,
10676        operand_signatures: [
10677            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10678            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10679            0,
10680            0,
10681            0,
10682            0,
10683        ],
10684        required: 0x0000000000004002,
10685        context: "ucvtf Vd.4H, Vn.4H requires: ASIMD, FP16",
10686    },
10687    InstFeatureForm {
10688        opcode_mask: 0xfffffc00,
10689        opcode_value: 0x6e79d800,
10690        operand_signatures: [
10691            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10692            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10693            0,
10694            0,
10695            0,
10696            0,
10697        ],
10698        required: 0x0000000000004002,
10699        context: "ucvtf Vd.8H, Vn.8H requires: ASIMD, FP16",
10700    },
10701    InstFeatureForm {
10702        opcode_mask: 0xffff0000,
10703        opcode_value: 0x1ec30000,
10704        operand_signatures: [
10705            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10706            feature_reg_signature(RegType::Gp32, VecElementType::None, false),
10707            OperandType::Imm as u32,
10708            0,
10709            0,
10710            0,
10711        ],
10712        required: 0x0000000000004002,
10713        context: "ucvtf Hd, Wn, #fbits requires: ASIMD, FP16",
10714    },
10715    InstFeatureForm {
10716        opcode_mask: 0xffff0000,
10717        opcode_value: 0x9ec30000,
10718        operand_signatures: [
10719            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10720            feature_reg_signature(RegType::Gp64, VecElementType::None, false),
10721            OperandType::Imm as u32,
10722            0,
10723            0,
10724            0,
10725        ],
10726        required: 0x0000000000004002,
10727        context: "ucvtf Hd, Xn, #fbits requires: ASIMD, FP16",
10728    },
10729    InstFeatureForm {
10730        opcode_mask: 0xff80fc00,
10731        opcode_value: 0x7f00e400,
10732        operand_signatures: [
10733            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10734            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10735            OperandType::Imm as u32,
10736            0,
10737            0,
10738            0,
10739        ],
10740        required: 0x0000000000004002,
10741        context: "ucvtf Hd, Hn, #bits requires: ASIMD, FP16",
10742    },
10743    InstFeatureForm {
10744        opcode_mask: 0xff80fc00,
10745        opcode_value: 0x2f00e400,
10746        operand_signatures: [
10747            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10748            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10749            OperandType::Imm as u32,
10750            0,
10751            0,
10752            0,
10753        ],
10754        required: 0x0000000000004002,
10755        context: "ucvtf Vd.4H, Vn.4H, #fbits requires: ASIMD, FP16",
10756    },
10757    InstFeatureForm {
10758        opcode_mask: 0xff80fc00,
10759        opcode_value: 0x6f00e400,
10760        operand_signatures: [
10761            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10762            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10763            OperandType::Imm as u32,
10764            0,
10765            0,
10766            0,
10767        ],
10768        required: 0x0000000000004002,
10769        context: "ucvtf Vd.8H, Vn.8H, #fbits requires: ASIMD, FP16",
10770    },
10771];
10772
10773fn required_features_for_form(
10774    inst_id: usize,
10775    opcode: u32,
10776    ops: &[&Operand],
10777) -> (u64, &'static str) {
10778    let start = INST_FEATURE_FORM_OFFSETS[inst_id] as usize;
10779    let end = INST_FEATURE_FORM_OFFSETS[inst_id + 1] as usize;
10780    for form in &INST_FEATURE_FORMS[start..end] {
10781        if form.matches(opcode, ops) {
10782            return (form.required, form.context);
10783        }
10784    }
10785    (
10786        INST_BASE_FEATURE_MASKS[inst_id],
10787        INST_BASE_FEATURE_CONTEXT[inst_id],
10788    )
10789}
10790
10791/// One instruction carrying each represented feature.
10792pub static CPU_FEATURE_REPRESENTATIVE: [InstId; CPU_FEATURE_COUNT] = [
10793    InstId::Aesd_v,
10794    InstId::Abs_v,
10795    InstId::Bfcvt_v,
10796    InstId::Bti,
10797    InstId::Chkfeat,
10798    InstId::Clrbhb,
10799    InstId::Crc32b,
10800    InstId::Abs,
10801    InstId::Dgh,
10802    InstId::Sdot_v,
10803    InstId::Fcadd_v,
10804    InstId::Fmlal_v,
10805    InstId::Cfinv,
10806    InstId::Axflag,
10807    InstId::Fabd_v,
10808    InstId::Fcvtn_v,
10809    InstId::Frint32x_v,
10810    InstId::Smmla_v,
10811    InstId::Fjcvtzs_v,
10812    InstId::Ldlar,
10813    InstId::Cas,
10814    InstId::Addg,
10815    InstId::Ldgm,
10816    InstId::Autda,
10817    InstId::Esb,
10818    InstId::Sqrdmlah_v,
10819    InstId::Sha1c_v,
10820    InstId::Sha256h_v,
10821    InstId::Bcax_v,
10822    InstId::Sha512h_v,
10823    InstId::Sm3partw1_v,
10824    InstId::Sm4e_v,
10825];
10826// @generated AArch64 target features end