asmkit/x86/features/
CLWB.rs

1use crate::x86::assembler::*;
2use crate::x86::operands::*;
3use super::super::opcodes::*;
4use crate::core::emitter::*;
5use crate::core::operand::*;
6
7/// A dummy operand that represents no register. Here just for simplicity.
8const NOREG: Operand = Operand::new();
9
10/// `CLWB` (CLWB). 
11/// Writes back to memory the cache line (if modified) that contains the linear address specified with the memory operand from any level of the cache hierarchy in the cache coherence domain. The line may be retained in the cache hierarchy in non-modified state. Retaining the line in the cache hierarchy is a performance optimization (treated as a hint by hardware) to reduce the possibility of cache miss on a subsequent access. Hardware may choose to retain the line at any of the levels in the cache hierarchy, and in some cases, may invalidate the line from the cache hierarchy. The source operand is a byte memory location.
12///
13///
14/// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/CLWB.html).
15///
16/// Supported operand variants:
17///
18/// ```text
19/// +---+----------+
20/// | # | Operands |
21/// +---+----------+
22/// | 1 | Mem      |
23/// +---+----------+
24/// ```
25pub trait ClwbEmitter<A> {
26    fn clwb(&mut self, op0: A);
27}
28
29impl<'a> ClwbEmitter<Mem> for Assembler<'a> {
30    fn clwb(&mut self, op0: Mem) {
31        self.emit(CLWBM, op0.as_operand(), &NOREG, &NOREG, &NOREG);
32    }
33}
34
35
36impl<'a> Assembler<'a> {
37    /// `CLWB` (CLWB). 
38    /// Writes back to memory the cache line (if modified) that contains the linear address specified with the memory operand from any level of the cache hierarchy in the cache coherence domain. The line may be retained in the cache hierarchy in non-modified state. Retaining the line in the cache hierarchy is a performance optimization (treated as a hint by hardware) to reduce the possibility of cache miss on a subsequent access. Hardware may choose to retain the line at any of the levels in the cache hierarchy, and in some cases, may invalidate the line from the cache hierarchy. The source operand is a byte memory location.
39    ///
40    ///
41    /// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/CLWB.html).
42    ///
43    /// Supported operand variants:
44    ///
45    /// ```text
46    /// +---+----------+
47    /// | # | Operands |
48    /// +---+----------+
49    /// | 1 | Mem      |
50    /// +---+----------+
51    /// ```
52    #[inline]
53    pub fn clwb<A>(&mut self, op0: A)
54    where Assembler<'a>: ClwbEmitter<A> {
55        <Self as ClwbEmitter<A>>::clwb(self, op0);
56    }
57}
asmkit/x86/features/CLWB.rs

asmkit/x86/features/
CLWB.rs
