Enum asm_riscv::I

pub enum I {
Show 40 variants    LUI {
        d: Reg,
        im: i32,
    },
    AUIPC {
        d: Reg,
        im: i32,
    },
    JAL {
        d: Reg,
        im: i32,
    },
    JALR {
        d: Reg,
        s: Reg,
        im: i16,
    },
    BEQ {
        s1: Reg,
        s2: Reg,
        im: i16,
    },
    BNE {
        s1: Reg,
        s2: Reg,
        im: i16,
    },
    BLT {
        s1: Reg,
        s2: Reg,
        im: i16,
    },
    BGE {
        s1: Reg,
        s2: Reg,
        im: i16,
    },
    BLTU {
        s1: Reg,
        s2: Reg,
        im: i16,
    },
    BGEU {
        s1: Reg,
        s2: Reg,
        im: i16,
    },
    LB {
        d: Reg,
        s: Reg,
        im: i16,
    },
    LH {
        d: Reg,
        s: Reg,
        im: i16,
    },
    LW {
        d: Reg,
        s: Reg,
        im: i16,
    },
    LBU {
        d: Reg,
        s: Reg,
        im: i16,
    },
    LHU {
        d: Reg,
        s: Reg,
        im: i16,
    },
    SB {
        s1: Reg,
        s2: Reg,
        im: i16,
    },
    SH {
        s1: Reg,
        s2: Reg,
        im: i16,
    },
    SW {
        s1: Reg,
        s2: Reg,
        im: i16,
    },
    ADDI {
        d: Reg,
        s: Reg,
        im: i16,
    },
    SLTI {
        d: Reg,
        s: Reg,
        im: i16,
    },
    SLTUI {
        d: Reg,
        s: Reg,
        im: i16,
    },
    XORI {
        d: Reg,
        s: Reg,
        im: i16,
    },
    ORI {
        d: Reg,
        s: Reg,
        im: i16,
    },
    ANDI {
        d: Reg,
        s: Reg,
        im: i16,
    },
    SLLI {
        d: Reg,
        s: Reg,
        im: i8,
    },
    SRLI {
        d: Reg,
        s: Reg,
        im: i8,
    },
    SRAI {
        d: Reg,
        s: Reg,
        im: i8,
    },
    ADD {
        d: Reg,
        s1: Reg,
        s2: Reg,
    },
    SUB {
        d: Reg,
        s1: Reg,
        s2: Reg,
    },
    SLL {
        d: Reg,
        s1: Reg,
        s2: Reg,
    },
    SLT {
        d: Reg,
        s1: Reg,
        s2: Reg,
    },
    SLTU {
        d: Reg,
        s1: Reg,
        s2: Reg,
    },
    XOR {
        d: Reg,
        s1: Reg,
        s2: Reg,
    },
    SRL {
        d: Reg,
        s1: Reg,
        s2: Reg,
    },
    SRA {
        d: Reg,
        s1: Reg,
        s2: Reg,
    },
    OR {
        d: Reg,
        s1: Reg,
        s2: Reg,
    },
    AND {
        d: Reg,
        s1: Reg,
        s2: Reg,
    },
    ECALL {},
    EBREAK {},
    FENCE {
        im: i16,
    },
}

Expand description

An assembly instruction (im is limited to 12 bits)

Variants§

LUI

Fields

§d: Reg

§im: i32

U: Set upper 20 bits to immediate value

AUIPC

Fields

§d: Reg

§im: i32

U: Add upper 20 bits to immediate value in program counter

JAL

Fields

§d: Reg

§im: i32

UJ: Jump and Link Relative

JALR

Fields

§d: Reg

§s: Reg

§im: i16

I: Jump and Link, Register

BEQ

Fields

§s1: Reg

§s2: Reg

§im: i16

SB: 12-bit immediate offset Branch on Equal

BNE

Fields

§s1: Reg

§s2: Reg

§im: i16

SB: 12-bit immediate offset Branch on Not Equal

BLT

Fields

§s1: Reg

§s2: Reg

§im: i16

SB: 12-bit immediate offset Branch on Less Than

BGE

Fields

§s1: Reg

§s2: Reg

§im: i16

SB: 12-bit immediate offset Branch on Greater Than Or Equal To

BLTU

Fields

§s1: Reg

§s2: Reg

§im: i16

SB: 12-bit immediate offset Branch on Less Than (Unsigned)

BGEU

Fields

§s1: Reg

§s2: Reg

§im: i16

SB: 12-bit immediate offset Branch on Greater Than Or Equal To (Unsigned)

LB

Fields

§d: Reg

§s: Reg

§im: i16

I: Load Byte (R[d]: M[R[s] + im])

LH

Fields

§d: Reg

§s: Reg

§im: i16

I: Load Half-Word (R[d]: M[R[s] + im])

LW

Fields

§d: Reg

§s: Reg

§im: i16

I: Load Word (R[d]: M[R[s] + im])

LBU

Fields

§d: Reg

§s: Reg

§im: i16

I: Load Byte Unsigned (R[d]: M[R[s] + im])

LHU

Fields

§d: Reg

§s: Reg

§im: i16

I: Load Half Unsigned (R[d]: M[R[s] + im])

SB

Fields

§s1: Reg

§s2: Reg

§im: i16

S: Store Byte

SH

Fields

§s1: Reg

§s2: Reg

§im: i16

S: Store Half Word

SW

Fields

§s1: Reg

§s2: Reg

§im: i16

S: Store Word

ADDI

Fields

§d: Reg

§s: Reg

§im: i16

I: Add Immediate (R[d]: R[s] + im)

SLTI

Fields

§d: Reg

§s: Reg

§im: i16

I: Set 1 on Less Than, 0 Otherwise Immediate

SLTUI

Fields

§d: Reg

§s: Reg

§im: i16

I: Set 1 on Less Than, 0 Otherwise Immediate Unsigned

XORI

Fields

§d: Reg

§s: Reg

§im: i16

I: Xor Immediate

ORI

Fields

§d: Reg

§s: Reg

§im: i16

I: Or Immediate

ANDI

Fields

§d: Reg

§s: Reg

§im: i16

I: And Immediate

SLLI

Fields

§d: Reg

§s: Reg

§im: i8

I: Logical Left Shift Immediate

SRLI

Fields

§d: Reg

§s: Reg

§im: i8

I: Logical Right Shift Immediate

SRAI

Fields

§d: Reg

§s: Reg

§im: i8

I: Arithmetic Shift Right Immediate (See SRA).

ADD

Fields

§d: Reg

§s1: Reg

§s2: Reg

R: Add (R[d]: R[s1] + R[s2])

SUB

Fields

§d: Reg

§s1: Reg

§s2: Reg

R: Subtract (R[d]: R[s1] - R[s2])

SLL

Fields

§d: Reg

§s1: Reg

§s2: Reg

R: Logical Left Shift

SLT

Fields

§d: Reg

§s1: Reg

§s2: Reg

R: Set 1 on Less Than, 0 Otherwise

SLTU

Fields

§d: Reg

§s1: Reg

§s2: Reg

R: Set 1 on Less Than, 0 Otherwise Unsigned

XOR

Fields

§d: Reg

§s1: Reg

§s2: Reg

R: Xor

SRL

Fields

§d: Reg

§s1: Reg

§s2: Reg

R: Logical Right Shift

SRA

Fields

§d: Reg

§s1: Reg

§s2: Reg

R: Arithmetic Shift Right (Sign Bit Copied Rather Than Filling In Zeros)

OR

Fields

§d: Reg

§s1: Reg

§s2: Reg

R: Or

AND

Fields

§d: Reg

§s1: Reg

§s2: Reg

R: And

ECALL

Fields

I: Invoke a system call (Registers defined by ABI, not hardware)

EBREAK

Fields

I: Debugger Breakpoint

FENCE

Fields

§im: i16

I: Fence (Immediate Is Made Up Of Ordered High Order To Low Order Bits:)

fm(4), PI(1), PO(1), PR(1), PW(1), SI(1), SO(1), SR(1), SW(1)

Trait Implementations§

impl Clone for I

fn clone(&self) -> I

Returns a copy of the value. Read more

1.0.0 · source§

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source. Read more

impl Debug for I

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter. Read more

impl From<I> for u32

fn from(with: I) -> Self

Converts to this type from the input type.

impl TryFrom<u32> for I

type Error = ConversionError

The type returned in the event of a conversion error.

fn try_from(with: u32) -> Result<Self, Self::Error>

Performs the conversion.

impl Copy for I

Auto Trait Implementations§

impl RefUnwindSafe for I

impl Send for I

impl Sync for I

impl Unpin for I

impl UnwindSafe for I

Blanket Implementations§

impl<T> Any for Twhere T: 'static + ?Sized,

fn type_id(&self) -> TypeId

Gets the TypeId of self. Read more

impl<T> Borrow<T> for Twhere T: ?Sized,

fn borrow(&self) -> &T

Immutably borrows from an owned value. Read more

impl<T> BorrowMut<T> for Twhere T: ?Sized,

fn borrow_mut(&mut self) -> &mut T

Mutably borrows from an owned value. Read more

impl<T> From<T> for T

fn from(t: T) -> T

Returns the argument unchanged.

impl<T, U> Into<U> for Twhere U: From<T>,

fn into(self) -> U

Calls U::from(self).

That is, this conversion is whatever the implementation of From<T> for U chooses to do.

impl<T, U> TryFrom<U> for Twhere U: Into<T>,

type Error = Infallible

The type returned in the event of a conversion error.

fn try_from(value: U) -> Result<T, <T as TryFrom<U>>::Error>

Performs the conversion.

impl<T, U> TryInto<U> for Twhere U: TryFrom<T>,

type Error = <U as TryFrom<T>>::Error

The type returned in the event of a conversion error.

fn try_into(self) -> Result<U, <U as TryFrom<T>>::Error>

Performs the conversion.