armv4t/

operation.rs

use types::{MultiplyFlags, TransferFlags};

descriminant! {
    #[doc = "
Condition codes for controlling execution

Variants, values and conditions are as follows:

| Variant       | Value | Conditions                |
|---------------|-------|---------------------------|
| `Equal`       | `0x0` | `Z == true`               |
| `NotEqual`    | `0x1` | `Z == false`              |
| `UnsignedGTE` | `0x2` | `C == true`               |
| `UnsignedLT`  | `0x3` | `C == false`              |
| `Negative`    | `0x4` | `N == true`               |
| `Positive`    | `0x5` | `N == false`              |
| `Overflow`    | `0x6` | `V == true`               |
| `NoOverflow`  | `0x7` | `V == false`              |
| `UnsignedGT`  | `0x8` | `C == true && Z == false` |
| `UnsignedLTE` | `0x9` | `C == false && Z == true` |
| `SignedGTE`   | `0xa` | `N == V`                  |
| `SignedLT`    | `0xb` | `N != V`                  |
| `SignedGT`    | `0xc` | `Z == false && N == V`    |
| `SignedLTE`   | `0xd` | `Z == true || N != V`     |
| `Always`      | `0xe` | -                         |"]
    #[derive(Clone, Copy, Debug, PartialEq)]
    pub enum Condition<u32> {
        #[doc = "Equal"]
        Equal = 0x0,
        #[doc = "Not equal"]
        NotEqual = 0x1,
        #[doc = "Greater than or equal (unsigned)"]
        UnsignedGTE = 0x2,
        #[doc = "Less than (unsigned)"]
        UnsignedLT = 0x3,
        #[doc = "Negative"]
        Negative = 0x4,
        #[doc = "Positive or zero"]
        Positive = 0x5,
        #[doc = "Overflow"]
        Overflow = 0x6,
        #[doc = "No overflow"]
        NoOverflow = 0x7,
        #[doc = "Greater than (unsigned)"]
        UnsignedGT = 0x8,
        #[doc = "Less than or equal (unsigned)"]
        UnsignedLTE = 0x9,
        #[doc = "Greater than or equal (signed)"]
        SignedGTE = 0xa,
        #[doc = "Less than (signed)"]
        SignedLT = 0xb,
        #[doc = "Greater than (signed)"]
        SignedGT = 0xc,
        #[doc = "Less than or equal (signed)"]
        SignedLTE = 0xd,
        #[doc = "Always"]
        Always = 0xe
    }
}

/// A collection of registers associated with an operation.
#[derive(Clone, Copy, Debug, Default, PartialEq)]
pub struct Registers {
    /// The `d` register
    pub d: u8,
    /// The `h` register
    pub h: u8,
    /// The `l` register
    pub l: u8,
    /// The `m` register
    pub m: u8,
    /// The `n` register
    pub n: u8,
    /// The `s` register
    pub s: u8,
}

/// A wrapper around a boolean that specifies whether to set condition
/// codes.
#[derive(Clone, Copy, Debug, PartialEq)]
pub struct SetFlags(pub bool);

impl From<bool> for SetFlags {
    fn from(flag: bool) -> Self {
        SetFlags(flag)
    }
}

/// A wrapper around a boolean that specifies whether to set r14 on
/// branching.
#[derive(Clone, Copy, Debug, PartialEq)]
pub struct Link(pub bool);

impl From<bool> for Link {
    fn from(flag: bool) -> Self {
        Link(flag)
    }
}

/// Processor operations
///
/// Operations that the processor can perform.
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum Operation {
    /// Data processing
    ///
    /// Perform an arithmetic or logical calculation on data contained
    /// in registers or encoded in the instruction.
    Alu(DataOp, SetFlags, Registers, Shift),
    /// Status register transfer
    ///
    /// Perform a transfer of a value between a register and a status
    /// register.
    ///
    /// __NOTE:__ The u8 member is the mask of the portions of the
    /// status register that should be transferred.
    StatusTransfer(TransferFlags, u8, Registers, Shift),
    /// Multiply
    ///
    /// Perform integer multiplication on data contained in registers.
    Multiply(MultiplyFlags, Registers),
    /// Multiply long
    ///
    /// Perform integer multiplication on data contained in registers,
    /// producing a 64-bit result.
    MultiplyLong(MultiplyFlags, Registers),
    /// Single Data Swap
    ///
    /// Perform a swap between a register and a memory address.
    SingleDataSwap(TransferFlags, Registers),
    /// Branch and Exchange
    ///
    /// Perform a branch by setting the program counter. The instruction
    /// set can also be changed based on the contents of the new PC.
    BranchExchange(Registers),
    /// Halfword and signed data transfer
    ///
    /// Perform a transfer of a halfword, byte, signed halfword, or
    /// signed halfword value between a register and memory.
    HalfwordDataTransfer(TransferFlags, Registers, Shift),
    /// Single data transfer
    ///
    /// Perform a transfer of a word, or byte value between a register
    /// and memory.
    SingleDataTransfer(TransferFlags, Registers, Shift),
    /// Undefined
    ///
    /// Execute the undefined instruction trap.
    Undefined,
    /// Block data transfer
    ///
    /// Perform a transfer of a subset of visible registers between the
    /// register bank and memory.
    BlockDataTransfer(TransferFlags, Registers, u16),
    /// Conditional branch
    ///
    /// Perform a branch by adding an offset to the program counter.
    Branch(Condition, Link, i32),
    /// Coprocessor data transfer
    ///
    /// Perform a transfer between a subset of a coprocessor's registers
    /// and memory.
    ///
    /// __NOTE:__ The u8 member is the coprocessor number and the u32
    /// member is the offset.
    CoprocessorDataTransfer(TransferFlags, u8, Registers, u32),
    /// Coprocessor data operation
    ///
    /// Perform a request for an operation on a coprocessor.
    ///
    /// __NOTE:__ The u8 members are, in order: coprocessor number,
    /// coprocessor opcode, coprocessor information.
    CoprocessorDataOperation(u8, u8, u8, Registers),
    /// Coprocessor register transfer
    ///
    /// Perform a transfer between an ARM register and a coprocessor
    /// register, with an optional transformation.
    ///
    /// __NOTE:__ The u8 members are, in order: coprocessor number,
    /// coprocessor opcode, coprocessor information.
    CoprocessorRegisterTransfer(TransferFlags, u8, u8, u8, Registers),
    /// Software interrupt
    ///
    /// Execute the software interrupt trap.
    SoftwareInterrupt(u32),
}

descriminant! {
    #[doc = "
Arithmetic/logical operations

Variants, values and operations are as follows:

| Variant | Value | Operation & Flags                       |
|---------|-------|-----------------------------------------|
| `And`   | `0x0` | `lhs & rhs` sets N, Z; shift sets C     |
| `Eor`   | `0x1` | `lhs ^ rhs` sets N, Z, shift sets C     |
| `Sub`   | `0x2` | `lhs - rhs` sets N, Z, C, V             |
| `Rsb`   | `0x3` | `rhs - lhs` sets N, Z, C, V             |
| `Add`   | `0x4` | `lhs + rhs` sets N, Z, C, V             |
| `Adc`   | `0x5` | `lhs + rhs + carry` sets N, Z, C, V     |
| `Sbc`   | `0x6` | `lhs - rhs - 1 + carry` sets N, Z, C, V |
| `Rsc`   | `0x7` | `rhs - lhs - 1 + carry` sets N, Z, C, V |
| `Tst`   | `0x8` | `lhs & rhs` sets N, Z; shift sets C     |
| `Teq`   | `0x9` | `lhs ^ rhs` sets N, Z; shift sets C     |
| `Cmp`   | `0xa` | `lhs - rhs` sets N, Z, C, V             |
| `Cmn`   | `0xb` | `lhs + rhs` sets N, Z, C, V             |
| `Orr`   | `0xc` | `lhs | rhs` sets N, Z; shift sets C     |
| `Mov`   | `0xd` | `rhs` sets N, Z; shift sets C           |
| `Bic`   | `0xe` | `lhs & !rhs` sets N, Z; shift sets C    |
| `Mvn`   | `0xf` | `!rhs` sets N, Z; shift sets C          |"]
    #[derive(Clone, Copy, Debug, PartialEq)]
    pub enum DataOp<u32> {
        #[doc = "And"]
        And = 0x0,
        #[doc = "Exclusive or"]
        Eor = 0x1,
        #[doc = "Subtract"]
        Sub = 0x2,
        #[doc = "Reverse subtract"]
        Rsb = 0x3,
        #[doc = "Add"]
        Add = 0x4,
        #[doc = "Add with carry"]
        Adc = 0x5,
        #[doc = "Subtract with carry"]
        Sbc = 0x6,
        #[doc = "Reverse subtract with carry"]
        Rsc = 0x7,
        #[doc = "Test"]
        Tst = 0x8,
        #[doc = "Test equal"]
        Teq = 0x9,
        #[doc = "Compare"]
        Cmp = 0xa,
        #[doc = "Compare negative"]
        Cmn = 0xb,
        #[doc = "Or"]
        Orr = 0xc,
        #[doc = "Move"]
        Mov = 0xd,
        #[doc = "Bit clear"]
        Bic = 0xe,
        #[doc = "Move negative"]
        Mvn = 0xf
    }
}

/// Barrel shift operations
///
/// Shift types are encoded as follows:
///
///  - `0b00`: logical left
///  - `0b01`: logical right
///  - `0b10`: arithmetic right
///  - `0b11`: rotate right
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum Shift {
    /// Immediate value
    ///
    /// The value in the instruction is used unmodified.
    Immediate {
        /// Value
        value: u32,
    },
    /// Immediate shifted register
    ///
    /// The value in register `rm` is shifted by the amount given in the
    /// amount field.
    ImmediateShiftedRegister {
        /// Amount to shift the base value
        amount: u8,
        /// Type of shift to perform
        shift: u8,
        /// Register containing base value
        m: u8
    },
    /// Register shifted register
    ///
    /// The value in register `rm` is shifted by the amount given in
    /// register `rs`.
    RegisterShiftedRegister {
        /// Register containing the amount to shift
        s: u8,
        /// Type of shift to perform
        shift: u8,
        /// Register containing base value
        m: u8
    },
    /// Rotated immediate value
    ///
    /// The immediate value is rotated by twice the amount given in the
    /// rotate field.
    RotatedImmediate {
        /// Amount to rotate divided by two
        rotation: u8,
        /// Value to rotate
        immediate: u8
    },
}