arm_vgic 0.5.5

ARM Virtual Generic Interrupt Controller (VGIC) implementation.
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90

// Copyright 2025 The Axvisor Team
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
//     http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.

use aarch64_cpu::registers::{CNTPCT_EL0, Readable};
use aarch64_sysreg::SystemRegType;
use axdevice_base::{
    AccessWidth, BusAccess, BusKind, BusResponse, Device, DeviceAccess, DeviceError, DeviceResult,
    Resource,
};
use log::debug;

const CNTPCT_EL0_ADDR: u32 = SystemRegType::CNTPCT_EL0 as u32;

impl SysCntpctEl0 {
    /// Reads CNTPCT_EL0.
    pub fn read_register(&self, _width: AccessWidth) -> DeviceResult<usize> {
        Ok(CNTPCT_EL0.get() as usize)
    }

    /// Ignores guest writes to the read-only CNTPCT_EL0 register.
    pub fn write_register(&self, _width: AccessWidth, val: usize) -> DeviceResult {
        debug!("Write to read-only virtual counter register CNTPCT_EL0, value: {val}");
        Ok(())
    }
}

/// System register emulation for CNTPCT_EL0.
///
/// Provides virtualization support for the physical counter register.
pub struct SysCntpctEl0 {
    resources: [Resource; 1],
}

impl SysCntpctEl0 {
    /// Creates a new CNTPCT_EL0 register emulator.
    pub fn new() -> Self {
        Self {
            resources: [Resource::SysReg {
                addr: CNTPCT_EL0_ADDR,
                count: 1,
            }],
        }
    }
}

impl Default for SysCntpctEl0 {
    fn default() -> Self {
        Self::new()
    }
}

impl Device for SysCntpctEl0 {
    fn name(&self) -> &str {
        "aarch64-cntpct-el0"
    }

    fn resources(&self) -> &[Resource] {
        &self.resources
    }

    fn access(
        &self,
        access: &BusAccess,
        _context: &mut dyn DeviceAccess,
    ) -> Result<BusResponse, DeviceError> {
        if access.kind != BusKind::SysReg || access.addr != CNTPCT_EL0_ADDR as u64 {
            return Err(DeviceError::OutOfRange { addr: access.addr });
        }
        if access.is_read {
            self.read_register(access.width)
                .map(|value| BusResponse::Read {
                    value: value as u64,
                })
        } else {
            self.write_register(access.width, access.data as usize)
                .map(|_| BusResponse::Write)
        }
    }
}