arm_sysregs/
lib.rs

1// SPDX-FileCopyrightText: Copyright The arm-sysregs Contributors.
2// SPDX-License-Identifier: MIT OR Apache-2.0
3
4//! Access to Arm CPU system registers.
5
6#![cfg_attr(not(any(test, feature = "fakes")), no_std)]
7
8#[cfg(not(any(test, feature = "fakes")))]
9mod aarch64;
10#[cfg(any(test, feature = "fakes"))]
11pub mod fake;
12mod macros;
13mod manual;
14
15use bitflags::bitflags;
16pub use manual::*;
17#[doc(hidden)]
18pub use paste as _paste;
19
20#[cfg(feature = "el1")]
21bitflags! {
22    /// `APIAKeyHi_EL1` system register value.
23    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
24    #[repr(transparent)]
25    pub struct ApiakeyhiEl1: u64 {
26    }
27}
28
29#[cfg(feature = "el1")]
30impl ApiakeyhiEl1 {
31    /// Offset of the APIAKeyHi field.
32    pub const APIAKEYHI_SHIFT: u32 = 0;
33    /// Mask for the APIAKeyHi field.
34    pub const APIAKEYHI_MASK: u64 =
35        0b1111111111111111111111111111111111111111111111111111111111111111;
36
37    /// Returns the value of the `APIAKeyHi` field.
38    pub const fn apiakeyhi(self) -> u64 {
39        ((self.bits() >> Self::APIAKEYHI_SHIFT)
40            & 0b1111111111111111111111111111111111111111111111111111111111111111) as u64
41    }
42}
43
44#[cfg(feature = "el1")]
45bitflags! {
46    /// `APIAKeyLo_EL1` system register value.
47    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
48    #[repr(transparent)]
49    pub struct ApiakeyloEl1: u64 {
50    }
51}
52
53#[cfg(feature = "el1")]
54impl ApiakeyloEl1 {
55    /// Offset of the APIAKeyLo field.
56    pub const APIAKEYLO_SHIFT: u32 = 0;
57    /// Mask for the APIAKeyLo field.
58    pub const APIAKEYLO_MASK: u64 =
59        0b1111111111111111111111111111111111111111111111111111111111111111;
60
61    /// Returns the value of the `APIAKeyLo` field.
62    pub const fn apiakeylo(self) -> u64 {
63        ((self.bits() >> Self::APIAKEYLO_SHIFT)
64            & 0b1111111111111111111111111111111111111111111111111111111111111111) as u64
65    }
66}
67
68#[cfg(feature = "el1")]
69bitflags! {
70    /// `CCSIDR_EL1` system register value.
71    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
72    #[repr(transparent)]
73    pub struct CcsidrEl1: u64 {
74    }
75}
76
77#[cfg(feature = "el1")]
78impl CcsidrEl1 {
79    /// Offset of the LineSize field.
80    pub const LINESIZE_SHIFT: u32 = 0;
81    /// Mask for the LineSize field.
82    pub const LINESIZE_MASK: u64 = 0b111;
83
84    /// Returns the value of the `LineSize` field.
85    pub const fn linesize(self) -> u8 {
86        ((self.bits() >> Self::LINESIZE_SHIFT) & 0b111) as u8
87    }
88}
89
90#[cfg(feature = "el1")]
91bitflags! {
92    /// `CLIDR_EL1` system register value.
93    ///
94    /// Cache Level ID.
95    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
96    #[repr(transparent)]
97    pub struct ClidrEl1: u64 {
98    }
99}
100
101#[cfg(feature = "el1")]
102impl ClidrEl1 {
103    /// Offset of the Ctype<n> field.
104    pub const CTYPE_SHIFT: u32 = 0;
105    /// Mask for the Ctype<n> field.
106    pub const CTYPE_MASK: u64 = 0b111;
107    /// Offset of the LoUIS field.
108    pub const LOUIS_SHIFT: u32 = 21;
109    /// Mask for the LoUIS field.
110    pub const LOUIS_MASK: u64 = 0b111;
111    /// Offset of the LoC field.
112    pub const LOC_SHIFT: u32 = 24;
113    /// Mask for the LoC field.
114    pub const LOC_MASK: u64 = 0b111;
115    /// Offset of the LoUU field.
116    pub const LOUU_SHIFT: u32 = 27;
117    /// Mask for the LoUU field.
118    pub const LOUU_MASK: u64 = 0b111;
119    /// Offset of the ICB field.
120    pub const ICB_SHIFT: u32 = 30;
121    /// Mask for the ICB field.
122    pub const ICB_MASK: u64 = 0b111;
123    /// Offset of the Ttype<n> field.
124    pub const TTYPE_SHIFT: u32 = 33;
125    /// Mask for the Ttype<n> field.
126    pub const TTYPE_MASK: u64 = 0b11;
127
128    /// Returns the value of the given `Ctype<n>` field.
129    pub fn ctype(self, n: u32) -> crate::manual::CacheType {
130        assert!(n >= 1 && n < 8);
131        crate::manual::CacheType::try_from(
132            ((self.bits() >> (Self::CTYPE_SHIFT + (n - 1) * 3)) & 0b111) as u8,
133        )
134        .unwrap()
135    }
136
137    /// Returns the value of the `LoUIS` field.
138    ///
139    /// Level of Unification Inner Shareable for the cache hierarchy.
140    pub const fn louis(self) -> u8 {
141        ((self.bits() >> Self::LOUIS_SHIFT) & 0b111) as u8
142    }
143
144    /// Returns the value of the `LoC` field.
145    ///
146    /// Level of Coherence for the cache hierarchy.
147    pub const fn loc(self) -> u8 {
148        ((self.bits() >> Self::LOC_SHIFT) & 0b111) as u8
149    }
150
151    /// Returns the value of the `LoUU` field.
152    ///
153    /// Level of Unification Uniprocessor for the cache hierarchy.
154    pub const fn louu(self) -> u8 {
155        ((self.bits() >> Self::LOUU_SHIFT) & 0b111) as u8
156    }
157
158    /// Returns the value of the `ICB` field.
159    ///
160    /// Inner cache boundary level.
161    pub const fn icb(self) -> u8 {
162        ((self.bits() >> Self::ICB_SHIFT) & 0b111) as u8
163    }
164
165    /// Returns the value of the given `Ttype<n>` field.
166    pub const fn ttype(self, n: u32) -> u8 {
167        assert!(n >= 1 && n < 8);
168        ((self.bits() >> (Self::TTYPE_SHIFT + (n - 1) * 2)) & 0b11) as u8
169    }
170}
171
172bitflags! {
173    /// `CNTFRQ_EL0` system register value.
174    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
175    #[repr(transparent)]
176    pub struct CntfrqEl0: u64 {
177    }
178}
179
180impl CntfrqEl0 {
181    /// Offset of the ClockFreq field.
182    pub const CLOCKFREQ_SHIFT: u32 = 0;
183    /// Mask for the ClockFreq field.
184    pub const CLOCKFREQ_MASK: u64 = 0b11111111111111111111111111111111;
185
186    /// Returns the value of the `ClockFreq` field.
187    pub const fn clockfreq(self) -> u32 {
188        ((self.bits() >> Self::CLOCKFREQ_SHIFT) & 0b11111111111111111111111111111111) as u32
189    }
190}
191
192#[cfg(feature = "el2")]
193bitflags! {
194    /// `CNTHCTL_EL2` system register value.
195    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
196    #[repr(transparent)]
197    pub struct CnthctlEl2: u64 {
198        /// `EL0PCTEN` bit.
199        const EL0PCTEN = 1 << 0;
200        /// `EL0VCTEN` bit.
201        const EL0VCTEN = 1 << 1;
202        /// `EL1PCEN` bit.
203        const EL1PCEN = 1 << 1;
204        /// `EVNTEN` bit.
205        const EVNTEN = 1 << 2;
206        /// `EVNTDIR` bit.
207        const EVNTDIR = 1 << 3;
208        /// `EL0VTEN` bit.
209        const EL0VTEN = 1 << 8;
210        /// `EL0PTEN` bit.
211        const EL0PTEN = 1 << 9;
212        /// `EL1PTEN` bit.
213        const EL1PTEN = 1 << 11;
214        /// `ECV` bit.
215        const ECV = 1 << 12;
216        /// `EL1TVT` bit.
217        const EL1TVT = 1 << 13;
218        /// `EL1TVCT` bit.
219        const EL1TVCT = 1 << 14;
220        /// `EL1NVPCT` bit.
221        const EL1NVPCT = 1 << 15;
222        /// `EL1NVVCT` bit.
223        const EL1NVVCT = 1 << 16;
224        /// `EVNTIS` bit.
225        const EVNTIS = 1 << 17;
226        /// `CNTVMASK` bit.
227        const CNTVMASK = 1 << 18;
228        /// `CNTPMASK` bit.
229        const CNTPMASK = 1 << 19;
230    }
231}
232
233#[cfg(feature = "el2")]
234impl CnthctlEl2 {
235    /// Offset of the EL0PCTEN field.
236    pub const EL0PCTEN_SHIFT: u32 = 0;
237    /// Offset of the EL0VCTEN field.
238    pub const EL0VCTEN_SHIFT: u32 = 1;
239    /// Offset of the EL1PCEN field.
240    pub const EL1PCEN_SHIFT: u32 = 1;
241    /// Offset of the EVNTEN field.
242    pub const EVNTEN_SHIFT: u32 = 2;
243    /// Offset of the EVNTDIR field.
244    pub const EVNTDIR_SHIFT: u32 = 3;
245    /// Offset of the EVNTI field.
246    pub const EVNTI_SHIFT: u32 = 4;
247    /// Mask for the EVNTI field.
248    pub const EVNTI_MASK: u64 = 0b1111;
249    /// Offset of the EL0VTEN field.
250    pub const EL0VTEN_SHIFT: u32 = 8;
251    /// Offset of the EL0PTEN field.
252    pub const EL0PTEN_SHIFT: u32 = 9;
253    /// Offset of the EL1PTEN field.
254    pub const EL1PTEN_SHIFT: u32 = 11;
255    /// Offset of the ECV field.
256    pub const ECV_SHIFT: u32 = 12;
257    /// Offset of the EL1TVT field.
258    pub const EL1TVT_SHIFT: u32 = 13;
259    /// Offset of the EL1TVCT field.
260    pub const EL1TVCT_SHIFT: u32 = 14;
261    /// Offset of the EL1NVPCT field.
262    pub const EL1NVPCT_SHIFT: u32 = 15;
263    /// Offset of the EL1NVVCT field.
264    pub const EL1NVVCT_SHIFT: u32 = 16;
265    /// Offset of the EVNTIS field.
266    pub const EVNTIS_SHIFT: u32 = 17;
267    /// Offset of the CNTVMASK field.
268    pub const CNTVMASK_SHIFT: u32 = 18;
269    /// Offset of the CNTPMASK field.
270    pub const CNTPMASK_SHIFT: u32 = 19;
271
272    /// Returns the value of the `EVNTI` field.
273    pub const fn evnti(self) -> u8 {
274        ((self.bits() >> Self::EVNTI_SHIFT) & 0b1111) as u8
275    }
276}
277
278#[cfg(feature = "el2")]
279bitflags! {
280    /// `CNTVOFF_EL2` system register value.
281    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
282    #[repr(transparent)]
283    pub struct CntvoffEl2: u64 {
284    }
285}
286
287#[cfg(feature = "el2")]
288impl CntvoffEl2 {
289    /// Offset of the VOffset field.
290    pub const VOFFSET_SHIFT: u32 = 0;
291    /// Mask for the VOffset field.
292    pub const VOFFSET_MASK: u64 =
293        0b1111111111111111111111111111111111111111111111111111111111111111;
294
295    /// Returns the value of the `VOffset` field.
296    pub const fn voffset(self) -> u64 {
297        ((self.bits() >> Self::VOFFSET_SHIFT)
298            & 0b1111111111111111111111111111111111111111111111111111111111111111) as u64
299    }
300}
301
302#[cfg(feature = "el1")]
303bitflags! {
304    /// `CONTEXTIDR_EL1` system register value.
305    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
306    #[repr(transparent)]
307    pub struct ContextidrEl1: u64 {
308    }
309}
310
311#[cfg(feature = "el1")]
312impl ContextidrEl1 {
313    /// Offset of the PROCID field.
314    pub const PROCID_SHIFT: u32 = 0;
315    /// Mask for the PROCID field.
316    pub const PROCID_MASK: u64 = 0b11111111111111111111111111111111;
317
318    /// Returns the value of the `PROCID` field.
319    pub const fn procid(self) -> u32 {
320        ((self.bits() >> Self::PROCID_SHIFT) & 0b11111111111111111111111111111111) as u32
321    }
322}
323
324#[cfg(feature = "el2")]
325bitflags! {
326    /// `CONTEXTIDR_EL2` system register value.
327    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
328    #[repr(transparent)]
329    pub struct ContextidrEl2: u64 {
330    }
331}
332
333#[cfg(feature = "el2")]
334impl ContextidrEl2 {
335    /// Offset of the PROCID field.
336    pub const PROCID_SHIFT: u32 = 0;
337    /// Mask for the PROCID field.
338    pub const PROCID_MASK: u64 = 0b11111111111111111111111111111111;
339
340    /// Returns the value of the `PROCID` field.
341    pub const fn procid(self) -> u32 {
342        ((self.bits() >> Self::PROCID_SHIFT) & 0b11111111111111111111111111111111) as u32
343    }
344}
345
346#[cfg(feature = "el1")]
347bitflags! {
348    /// `CPACR_EL1` system register value.
349    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
350    #[repr(transparent)]
351    pub struct CpacrEl1: u64 {
352        /// `TTA` bit.
353        const TTA = 1 << 28;
354        /// `E0POE` bit.
355        const E0POE = 1 << 29;
356        /// `TAM` bit.
357        const TAM = 1 << 30;
358        /// `TCPAC` bit.
359        const TCPAC = 1 << 31;
360        /// `E0TP0E` bit.
361        const E0TP0E = 1 << 32;
362        /// `E0TP1E` bit.
363        const E0TP1E = 1 << 33;
364    }
365}
366
367#[cfg(feature = "el1")]
368impl CpacrEl1 {
369    /// Offset of the ZEN field.
370    pub const ZEN_SHIFT: u32 = 16;
371    /// Mask for the ZEN field.
372    pub const ZEN_MASK: u64 = 0b11;
373    /// Offset of the FPEN field.
374    pub const FPEN_SHIFT: u32 = 20;
375    /// Mask for the FPEN field.
376    pub const FPEN_MASK: u64 = 0b11;
377    /// Offset of the SMEN field.
378    pub const SMEN_SHIFT: u32 = 24;
379    /// Mask for the SMEN field.
380    pub const SMEN_MASK: u64 = 0b11;
381    /// Offset of the TTA field.
382    pub const TTA_SHIFT: u32 = 28;
383    /// Offset of the E0POE field.
384    pub const E0POE_SHIFT: u32 = 29;
385    /// Offset of the TAM field.
386    pub const TAM_SHIFT: u32 = 30;
387    /// Offset of the TCPAC field.
388    pub const TCPAC_SHIFT: u32 = 31;
389    /// Offset of the E0TP0E field.
390    pub const E0TP0E_SHIFT: u32 = 32;
391    /// Offset of the E0TP1E field.
392    pub const E0TP1E_SHIFT: u32 = 33;
393
394    /// Returns the value of the `ZEN` field.
395    pub const fn zen(self) -> u8 {
396        ((self.bits() >> Self::ZEN_SHIFT) & 0b11) as u8
397    }
398
399    /// Returns the value of the `FPEN` field.
400    pub const fn fpen(self) -> u8 {
401        ((self.bits() >> Self::FPEN_SHIFT) & 0b11) as u8
402    }
403
404    /// Returns the value of the `SMEN` field.
405    pub const fn smen(self) -> u8 {
406        ((self.bits() >> Self::SMEN_SHIFT) & 0b11) as u8
407    }
408}
409
410#[cfg(feature = "el2")]
411bitflags! {
412    /// `CPTR_EL2` system register value.
413    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
414    #[repr(transparent)]
415    pub struct CptrEl2: u64 {
416        /// RES1 bits in the `CPTR_EL2` register.
417        const RES1 = 0b10001011111111;
418        /// `TZ` bit.
419        const TZ = 1 << 8;
420        /// `TFP` bit.
421        const TFP = 1 << 10;
422        /// `TSM` bit.
423        const TSM = 1 << 12;
424        /// `E0POE` bit.
425        const E0POE = 1 << 29;
426        /// `TAM` bit.
427        const TAM = 1 << 30;
428        /// `TCPAC` bit.
429        const TCPAC = 1 << 31;
430        /// `E0TP0E` bit.
431        const E0TP0E = 1 << 32;
432        /// `E0TP1E` bit.
433        const E0TP1E = 1 << 33;
434    }
435}
436
437#[cfg(feature = "el2")]
438impl CptrEl2 {
439    /// Offset of the TZ field.
440    pub const TZ_SHIFT: u32 = 8;
441    /// Offset of the TFP field.
442    pub const TFP_SHIFT: u32 = 10;
443    /// Offset of the TSM field.
444    pub const TSM_SHIFT: u32 = 12;
445    /// Offset of the ZEN field.
446    pub const ZEN_SHIFT: u32 = 16;
447    /// Mask for the ZEN field.
448    pub const ZEN_MASK: u64 = 0b11;
449    /// Offset of the FPEN field.
450    pub const FPEN_SHIFT: u32 = 20;
451    /// Mask for the FPEN field.
452    pub const FPEN_MASK: u64 = 0b11;
453    /// Offset of the SMEN field.
454    pub const SMEN_SHIFT: u32 = 24;
455    /// Mask for the SMEN field.
456    pub const SMEN_MASK: u64 = 0b11;
457    /// Offset of the E0POE field.
458    pub const E0POE_SHIFT: u32 = 29;
459    /// Offset of the TAM field.
460    pub const TAM_SHIFT: u32 = 30;
461    /// Offset of the TCPAC field.
462    pub const TCPAC_SHIFT: u32 = 31;
463    /// Offset of the E0TP0E field.
464    pub const E0TP0E_SHIFT: u32 = 32;
465    /// Offset of the E0TP1E field.
466    pub const E0TP1E_SHIFT: u32 = 33;
467
468    /// Returns the value of the `ZEN` field.
469    pub const fn zen(self) -> u8 {
470        ((self.bits() >> Self::ZEN_SHIFT) & 0b11) as u8
471    }
472
473    /// Returns the value of the `FPEN` field.
474    pub const fn fpen(self) -> u8 {
475        ((self.bits() >> Self::FPEN_SHIFT) & 0b11) as u8
476    }
477
478    /// Returns the value of the `SMEN` field.
479    pub const fn smen(self) -> u8 {
480        ((self.bits() >> Self::SMEN_SHIFT) & 0b11) as u8
481    }
482}
483
484#[cfg(feature = "el3")]
485bitflags! {
486    /// `CPTR_EL3` system register value.
487    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
488    #[repr(transparent)]
489    pub struct CptrEl3: u64 {
490        /// Do not trap execution of SVE instructions.
491        const EZ = 1 << 8;
492        /// Trap Advanced SIMD instructions execution.
493        const TFP = 1 << 10;
494        /// When FEAT_SME is implemented, do not trap SME instructions and system registers accesses.
495        const ESM = 1 << 12;
496        /// Trap trace system register accesses.
497        const TTA = 1 << 20;
498        /// When FEAT_AMUv1 implemented trap accesses from EL2/EL1/EL0 to AMU registers.
499        const TAM = 1 << 30;
500        /// Trap EL2 accesses to CPTR_EL2/HCPTR, and EL2/EL1 accesses to CPACR_EL1/CPACR.
501        const TCPAC = 1 << 31;
502    }
503}
504
505#[cfg(feature = "el3")]
506impl CptrEl3 {
507    /// Offset of the EZ field.
508    pub const EZ_SHIFT: u32 = 8;
509    /// Offset of the TFP field.
510    pub const TFP_SHIFT: u32 = 10;
511    /// Offset of the ESM field.
512    pub const ESM_SHIFT: u32 = 12;
513    /// Offset of the TTA field.
514    pub const TTA_SHIFT: u32 = 20;
515    /// Offset of the TAM field.
516    pub const TAM_SHIFT: u32 = 30;
517    /// Offset of the TCPAC field.
518    pub const TCPAC_SHIFT: u32 = 31;
519}
520
521#[cfg(feature = "el1")]
522bitflags! {
523    /// `CSSELR_EL1` system register value.
524    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
525    #[repr(transparent)]
526    pub struct CsselrEl1: u64 {
527        /// Instruction not Data bit.
528        const IND = 1 << 0;
529        /// Allocation Tag not Data bit, only valid if FEAT_MTE2 is implemented.
530        const TND = 1 << 4;
531    }
532}
533
534#[cfg(feature = "el1")]
535impl CsselrEl1 {
536    /// Offset of the InD field.
537    pub const IND_SHIFT: u32 = 0;
538    /// Offset of the Level field.
539    pub const LEVEL_SHIFT: u32 = 1;
540    /// Mask for the Level field.
541    pub const LEVEL_MASK: u64 = 0b111;
542    /// Offset of the TnD field.
543    pub const TND_SHIFT: u32 = 4;
544
545    /// Returns the value of the `Level` field.
546    pub const fn level(self) -> u8 {
547        ((self.bits() >> Self::LEVEL_SHIFT) & 0b111) as u8
548    }
549}
550
551bitflags! {
552    /// `CTR_EL0` system register value.
553    ///
554    /// Cache Type Register.
555    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
556    #[repr(transparent)]
557    pub struct CtrEl0: u64 {
558        /// RES1 bits in the `CTR_EL0` register.
559        const RES1 = 0b10000000000000000000000000000000;
560        /// `IDC` bit.
561        const IDC = 1 << 28;
562        /// `DIC` bit.
563        const DIC = 1 << 29;
564    }
565}
566
567impl CtrEl0 {
568    /// Offset of the IminLine field.
569    pub const IMINLINE_SHIFT: u32 = 0;
570    /// Mask for the IminLine field.
571    pub const IMINLINE_MASK: u64 = 0b1111;
572    /// Offset of the L1Ip field.
573    pub const L1IP_SHIFT: u32 = 14;
574    /// Mask for the L1Ip field.
575    pub const L1IP_MASK: u64 = 0b11;
576    /// Offset of the DminLine field.
577    pub const DMINLINE_SHIFT: u32 = 16;
578    /// Mask for the DminLine field.
579    pub const DMINLINE_MASK: u64 = 0b1111;
580    /// Offset of the ERG field.
581    pub const ERG_SHIFT: u32 = 20;
582    /// Mask for the ERG field.
583    pub const ERG_MASK: u64 = 0b1111;
584    /// Offset of the CWG field.
585    pub const CWG_SHIFT: u32 = 24;
586    /// Mask for the CWG field.
587    pub const CWG_MASK: u64 = 0b1111;
588    /// Offset of the IDC field.
589    pub const IDC_SHIFT: u32 = 28;
590    /// Offset of the DIC field.
591    pub const DIC_SHIFT: u32 = 29;
592    /// Offset of the TminLine field.
593    pub const TMINLINE_SHIFT: u32 = 32;
594    /// Mask for the TminLine field.
595    pub const TMINLINE_MASK: u64 = 0b111111;
596
597    /// Returns the value of the `IminLine` field.
598    pub const fn iminline(self) -> u8 {
599        ((self.bits() >> Self::IMINLINE_SHIFT) & 0b1111) as u8
600    }
601
602    /// Returns the value of the `L1Ip` field.
603    pub const fn l1ip(self) -> u8 {
604        ((self.bits() >> Self::L1IP_SHIFT) & 0b11) as u8
605    }
606
607    /// Returns the value of the `DminLine` field.
608    ///
609    /// Log2 of the number of words in the smallest cache line of all the data caches and unified caches that are controlled by the PE.
610    pub const fn dminline(self) -> u8 {
611        ((self.bits() >> Self::DMINLINE_SHIFT) & 0b1111) as u8
612    }
613
614    /// Returns the value of the `ERG` field.
615    pub const fn erg(self) -> u8 {
616        ((self.bits() >> Self::ERG_SHIFT) & 0b1111) as u8
617    }
618
619    /// Returns the value of the `CWG` field.
620    pub const fn cwg(self) -> u8 {
621        ((self.bits() >> Self::CWG_SHIFT) & 0b1111) as u8
622    }
623
624    /// Returns the value of the `TminLine` field.
625    pub const fn tminline(self) -> u8 {
626        ((self.bits() >> Self::TMINLINE_SHIFT) & 0b111111) as u8
627    }
628}
629
630#[cfg(feature = "el1")]
631bitflags! {
632    /// `DISR_EL1` system register value.
633    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
634    #[repr(transparent)]
635    pub struct DisrEl1: u64 {
636        /// `WnR` bit.
637        const WNR = 1 << 6;
638        /// `WnRV` bit.
639        const WNRV = 1 << 7;
640        /// `EA` bit.
641        const EA = 1 << 9;
642        /// `IDS` bit.
643        const IDS = 1 << 24;
644        /// `A` bit.
645        const A = 1 << 31;
646    }
647}
648
649#[cfg(feature = "el1")]
650impl DisrEl1 {
651    /// Offset of the DFSC field.
652    pub const DFSC_SHIFT: u32 = 0;
653    /// Mask for the DFSC field.
654    pub const DFSC_MASK: u64 = 0b111111;
655    /// Offset of the WnR field.
656    pub const WNR_SHIFT: u32 = 6;
657    /// Offset of the WnRV field.
658    pub const WNRV_SHIFT: u32 = 7;
659    /// Offset of the EA field.
660    pub const EA_SHIFT: u32 = 9;
661    /// Offset of the AET field.
662    pub const AET_SHIFT: u32 = 10;
663    /// Mask for the AET field.
664    pub const AET_MASK: u64 = 0b111;
665    /// Offset of the WU field.
666    pub const WU_SHIFT: u32 = 16;
667    /// Mask for the WU field.
668    pub const WU_MASK: u64 = 0b11;
669    /// Offset of the IDS field.
670    pub const IDS_SHIFT: u32 = 24;
671    /// Offset of the A field.
672    pub const A_SHIFT: u32 = 31;
673
674    /// Returns the value of the `DFSC` field.
675    pub const fn dfsc(self) -> u8 {
676        ((self.bits() >> Self::DFSC_SHIFT) & 0b111111) as u8
677    }
678
679    /// Returns the value of the `AET` field.
680    pub const fn aet(self) -> u8 {
681        ((self.bits() >> Self::AET_SHIFT) & 0b111) as u8
682    }
683
684    /// Returns the value of the `WU` field.
685    pub const fn wu(self) -> u8 {
686        ((self.bits() >> Self::WU_SHIFT) & 0b11) as u8
687    }
688}
689
690bitflags! {
691    /// `DIT` system register value.
692    ///
693    /// Data Independent Timing.
694    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
695    #[repr(transparent)]
696    pub struct Dit: u64 {
697        /// Enable data independent timing.
698        const DIT = 1 << 24;
699    }
700}
701
702impl Dit {
703    /// Offset of the DIT field.
704    pub const DIT_SHIFT: u32 = 24;
705}
706
707#[cfg(feature = "el1")]
708bitflags! {
709    /// `ELR_EL1` system register value.
710    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
711    #[repr(transparent)]
712    pub struct ElrEl1: u64 {
713    }
714}
715
716#[cfg(feature = "el1")]
717impl ElrEl1 {
718    /// Offset of the ADDR field.
719    pub const ADDR_SHIFT: u32 = 0;
720    /// Mask for the ADDR field.
721    pub const ADDR_MASK: u64 = 0b1111111111111111111111111111111111111111111111111111111111111111;
722
723    /// Returns the value of the `ADDR` field.
724    pub const fn addr(self) -> u64 {
725        ((self.bits() >> Self::ADDR_SHIFT)
726            & 0b1111111111111111111111111111111111111111111111111111111111111111) as u64
727    }
728}
729
730#[cfg(feature = "el2")]
731bitflags! {
732    /// `ELR_EL2` system register value.
733    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
734    #[repr(transparent)]
735    pub struct ElrEl2: u64 {
736    }
737}
738
739#[cfg(feature = "el2")]
740impl ElrEl2 {
741    /// Offset of the ADDR field.
742    pub const ADDR_SHIFT: u32 = 0;
743    /// Mask for the ADDR field.
744    pub const ADDR_MASK: u64 = 0b1111111111111111111111111111111111111111111111111111111111111111;
745
746    /// Returns the value of the `ADDR` field.
747    pub const fn addr(self) -> u64 {
748        ((self.bits() >> Self::ADDR_SHIFT)
749            & 0b1111111111111111111111111111111111111111111111111111111111111111) as u64
750    }
751}
752
753#[cfg(feature = "el1")]
754bitflags! {
755    /// `ESR_EL1` system register value.
756    #[derive(Clone, Copy, Eq, PartialEq)]
757    #[repr(transparent)]
758    pub struct EsrEl1: u64 {
759        /// `IL` bit.
760        const IL = 1 << 25;
761    }
762}
763
764#[cfg(feature = "el1")]
765impl EsrEl1 {
766    /// Offset of the ISS field.
767    pub const ISS_SHIFT: u32 = 0;
768    /// Mask for the ISS field.
769    pub const ISS_MASK: u64 = 0b1111111111111111111111111;
770    /// Offset of the IL field.
771    pub const IL_SHIFT: u32 = 25;
772    /// Offset of the EC field.
773    pub const EC_SHIFT: u32 = 26;
774    /// Mask for the EC field.
775    pub const EC_MASK: u64 = 0b111111;
776    /// Offset of the ISS2 field.
777    pub const ISS2_SHIFT: u32 = 32;
778    /// Mask for the ISS2 field.
779    pub const ISS2_MASK: u64 = 0b111111111111111111111111;
780
781    /// Returns the value of the `ISS` field.
782    pub const fn iss(self) -> u32 {
783        ((self.bits() >> Self::ISS_SHIFT) & 0b1111111111111111111111111) as u32
784    }
785
786    /// Returns the value of the `EC` field.
787    pub const fn ec(self) -> u8 {
788        ((self.bits() >> Self::EC_SHIFT) & 0b111111) as u8
789    }
790
791    /// Returns the value of the `ISS2` field.
792    pub const fn iss2(self) -> u32 {
793        ((self.bits() >> Self::ISS2_SHIFT) & 0b111111111111111111111111) as u32
794    }
795}
796
797#[cfg(feature = "el2")]
798bitflags! {
799    /// `ESR_EL2` system register value.
800    #[derive(Clone, Copy, Eq, PartialEq)]
801    #[repr(transparent)]
802    pub struct EsrEl2: u64 {
803        /// 32-bit instruction length.
804        const IL = 1 << 25;
805    }
806}
807
808#[cfg(feature = "el2")]
809impl EsrEl2 {
810    /// Offset of the ISS field.
811    pub const ISS_SHIFT: u32 = 0;
812    /// Mask for the ISS field.
813    pub const ISS_MASK: u64 = 0b1111111111111111111111111;
814    /// Offset of the IL field.
815    pub const IL_SHIFT: u32 = 25;
816    /// Offset of the EC field.
817    pub const EC_SHIFT: u32 = 26;
818    /// Mask for the EC field.
819    pub const EC_MASK: u64 = 0b111111;
820    /// Offset of the ISS2 field.
821    pub const ISS2_SHIFT: u32 = 32;
822    /// Mask for the ISS2 field.
823    pub const ISS2_MASK: u64 = 0b111111111111111111111111;
824
825    /// Returns the value of the `ISS` field.
826    pub const fn iss(self) -> u32 {
827        ((self.bits() >> Self::ISS_SHIFT) & 0b1111111111111111111111111) as u32
828    }
829
830    /// Returns the value of the `EC` field.
831    pub const fn ec(self) -> u8 {
832        ((self.bits() >> Self::EC_SHIFT) & 0b111111) as u8
833    }
834
835    /// Returns the value of the `ISS2` field.
836    pub const fn iss2(self) -> u32 {
837        ((self.bits() >> Self::ISS2_SHIFT) & 0b111111111111111111111111) as u32
838    }
839}
840
841#[cfg(feature = "el3")]
842bitflags! {
843    /// `ESR_EL3` system register value.
844    #[derive(Clone, Copy, Eq, PartialEq)]
845    #[repr(transparent)]
846    pub struct EsrEl3: u64 {
847        /// 32-bit instruction length.
848        const IL = 1 << 25;
849    }
850}
851
852#[cfg(feature = "el3")]
853impl EsrEl3 {
854    /// Offset of the ISS field.
855    pub const ISS_SHIFT: u32 = 0;
856    /// Mask for the ISS field.
857    pub const ISS_MASK: u64 = 0b1111111111111111111111111;
858    /// Offset of the IL field.
859    pub const IL_SHIFT: u32 = 25;
860    /// Offset of the EC field.
861    pub const EC_SHIFT: u32 = 26;
862    /// Mask for the EC field.
863    pub const EC_MASK: u64 = 0b111111;
864    /// Offset of the ISS2 field.
865    pub const ISS2_SHIFT: u32 = 32;
866    /// Mask for the ISS2 field.
867    pub const ISS2_MASK: u64 = 0b111111111111111111111111;
868
869    /// Returns the value of the `ISS` field.
870    pub const fn iss(self) -> u32 {
871        ((self.bits() >> Self::ISS_SHIFT) & 0b1111111111111111111111111) as u32
872    }
873
874    /// Returns the value of the `EC` field.
875    pub const fn ec(self) -> u8 {
876        ((self.bits() >> Self::EC_SHIFT) & 0b111111) as u8
877    }
878
879    /// Returns the value of the `ISS2` field.
880    pub const fn iss2(self) -> u32 {
881        ((self.bits() >> Self::ISS2_SHIFT) & 0b111111111111111111111111) as u32
882    }
883}
884
885#[cfg(feature = "el1")]
886bitflags! {
887    /// `FAR_EL1` system register value.
888    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
889    #[repr(transparent)]
890    pub struct FarEl1: u64 {
891    }
892}
893
894#[cfg(feature = "el1")]
895impl FarEl1 {
896    /// Offset of the VA field.
897    pub const VA_SHIFT: u32 = 0;
898    /// Mask for the VA field.
899    pub const VA_MASK: u64 = 0b1111111111111111111111111111111111111111111111111111111111111111;
900
901    /// Returns the value of the `VA` field.
902    pub const fn va(self) -> u64 {
903        ((self.bits() >> Self::VA_SHIFT)
904            & 0b1111111111111111111111111111111111111111111111111111111111111111) as u64
905    }
906}
907
908#[cfg(feature = "el2")]
909bitflags! {
910    /// `FAR_EL2` system register value.
911    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
912    #[repr(transparent)]
913    pub struct FarEl2: u64 {
914    }
915}
916
917#[cfg(feature = "el2")]
918impl FarEl2 {
919    /// Offset of the VA field.
920    pub const VA_SHIFT: u32 = 0;
921    /// Mask for the VA field.
922    pub const VA_MASK: u64 = 0b1111111111111111111111111111111111111111111111111111111111111111;
923
924    /// Returns the value of the `VA` field.
925    pub const fn va(self) -> u64 {
926        ((self.bits() >> Self::VA_SHIFT)
927            & 0b1111111111111111111111111111111111111111111111111111111111111111) as u64
928    }
929}
930
931#[cfg(feature = "el1")]
932bitflags! {
933    /// `GCR_EL1` system register value.
934    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
935    #[repr(transparent)]
936    pub struct GcrEl1: u64 {
937        /// `RRND` bit.
938        const RRND = 1 << 16;
939    }
940}
941
942#[cfg(feature = "el1")]
943impl GcrEl1 {
944    /// Offset of the Exclude field.
945    pub const EXCLUDE_SHIFT: u32 = 0;
946    /// Mask for the Exclude field.
947    pub const EXCLUDE_MASK: u64 = 0b1111111111111111;
948    /// Offset of the RRND field.
949    pub const RRND_SHIFT: u32 = 16;
950
951    /// Returns the value of the `Exclude` field.
952    pub const fn exclude(self) -> u16 {
953        ((self.bits() >> Self::EXCLUDE_SHIFT) & 0b1111111111111111) as u16
954    }
955}
956
957#[cfg(feature = "el1")]
958bitflags! {
959    /// `GCSCR_EL1` system register value.
960    ///
961    /// Guarded Control Stack Control register.
962    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
963    #[repr(transparent)]
964    pub struct GcscrEl1: u64 {
965        /// `PCRSEL` bit.
966        const PCRSEL = 1 << 0;
967        /// `RVCHKEN` bit.
968        const RVCHKEN = 1 << 5;
969        /// Exception state lock enable.
970        const EXLOCKEN = 1 << 6;
971        /// `PUSHMEn` bit.
972        const PUSHMEN = 1 << 8;
973        /// `STREn` bit.
974        const STREN = 1 << 9;
975    }
976}
977
978#[cfg(feature = "el1")]
979impl GcscrEl1 {
980    /// Offset of the PCRSEL field.
981    pub const PCRSEL_SHIFT: u32 = 0;
982    /// Offset of the RVCHKEN field.
983    pub const RVCHKEN_SHIFT: u32 = 5;
984    /// Offset of the EXLOCKEN field.
985    pub const EXLOCKEN_SHIFT: u32 = 6;
986    /// Offset of the PUSHMEn field.
987    pub const PUSHMEN_SHIFT: u32 = 8;
988    /// Offset of the STREn field.
989    pub const STREN_SHIFT: u32 = 9;
990}
991
992#[cfg(feature = "el2")]
993bitflags! {
994    /// `GCSCR_EL2` system register value.
995    ///
996    /// Guarded Control Stack Control register.
997    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
998    #[repr(transparent)]
999    pub struct GcscrEl2: u64 {
1000        /// `PCRSEL` bit.
1001        const PCRSEL = 1 << 0;
1002        /// `RVCHKEN` bit.
1003        const RVCHKEN = 1 << 5;
1004        /// Exception state lock enable.
1005        const EXLOCKEN = 1 << 6;
1006        /// `PUSHMEn` bit.
1007        const PUSHMEN = 1 << 8;
1008        /// `STREn` bit.
1009        const STREN = 1 << 9;
1010    }
1011}
1012
1013#[cfg(feature = "el2")]
1014impl GcscrEl2 {
1015    /// Offset of the PCRSEL field.
1016    pub const PCRSEL_SHIFT: u32 = 0;
1017    /// Offset of the RVCHKEN field.
1018    pub const RVCHKEN_SHIFT: u32 = 5;
1019    /// Offset of the EXLOCKEN field.
1020    pub const EXLOCKEN_SHIFT: u32 = 6;
1021    /// Offset of the PUSHMEn field.
1022    pub const PUSHMEN_SHIFT: u32 = 8;
1023    /// Offset of the STREn field.
1024    pub const STREN_SHIFT: u32 = 9;
1025}
1026
1027#[cfg(feature = "el2")]
1028bitflags! {
1029    /// `HCRX_EL2` system register value.
1030    ///
1031    /// Extended Hypervisor Configuration Register.
1032    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
1033    #[repr(transparent)]
1034    pub struct HcrxEl2: u64 {
1035        /// Do not trap execution of an ST64BV0 instruction at EL0 or EL1 to EL2.
1036        const ENAS0 = 1 << 0;
1037        /// Do not trap execution of an LD64B or ST64B instruction at EL0 or EL1 to EL2.
1038        const ENALS = 1 << 1;
1039        /// Do not trap execution of an ST64BV instruction at EL0 or EL1 to EL2.
1040        const ENASR = 1 << 2;
1041        /// Determines the behavior of TLBI instructions affected by the XS attribute.
1042        const FNXS = 1 << 3;
1043        /// Determines if the fine-grained traps in HFGITR_EL2 also apply to the corresponding TLBI maintenance instructions with the nXS qualifier.
1044        const FGTNXS = 1 << 4;
1045        /// Controls mapping of the value of SMPRI_EL1.Priority for streaming execution priority at EL0 or EL1.
1046        const SMPME = 1 << 5;
1047        /// Traps MSR writes of ALLINT at EL1 using AArch64 to EL2.
1048        const TALLINT = 1 << 6;
1049        /// Enables signaling of virtual IRQ interrupts with Superpriority.
1050        const VINMI = 1 << 7;
1051        /// Enables signaling of virtual FIQ interrupts with Superpriority.
1052        const VFNMI = 1 << 8;
1053        /// Controls the required permissions for cache maintenance instructions at EL1 or EL0.
1054        const CMOW = 1 << 9;
1055        /// Controls Memory Copy and Memory Set exceptions generated from EL1.
1056        const MCE2 = 1 << 10;
1057        /// Enables execution of Memory Set and Memory Copy instructions at EL1 or EL0.
1058        const MSCEN = 1 << 11;
1059        /// `TCR2En` bit.
1060        const TCR2EN = 1 << 14;
1061        /// `SCTLR2En` bit.
1062        const SCTLR2EN = 1 << 15;
1063        /// `PTTWI` bit.
1064        const PTTWI = 1 << 16;
1065        /// `D128En` bit.
1066        const D128EN = 1 << 17;
1067        /// `EnSNERR` bit.
1068        const ENSNERR = 1 << 18;
1069        /// `TMEA` bit.
1070        const TMEA = 1 << 19;
1071        /// `EnSDERR` bit.
1072        const ENSDERR = 1 << 20;
1073        /// `EnIDCP128` bit.
1074        const ENIDCP128 = 1 << 21;
1075        /// `GCSEn` bit.
1076        const GCSEN = 1 << 22;
1077        /// `EnFPM` bit.
1078        const ENFPM = 1 << 23;
1079        /// `PACMEn` bit.
1080        const PACMEN = 1 << 24;
1081        /// `VTLBIDEn` bit.
1082        const VTLBIDEN = 1 << 25;
1083        /// `SRMASKEn` bit.
1084        const SRMASKEN = 1 << 26;
1085        /// `NVTGE` bit.
1086        const NVTGE = 1 << 27;
1087        /// `POE2En` bit.
1088        const POE2EN = 1 << 29;
1089        /// `TPLIMEn` bit.
1090        const TPLIMEN = 1 << 30;
1091        /// `FDIT` bit.
1092        const FDIT = 1 << 31;
1093        /// `NVnTTLB` bit.
1094        const NVNTTLB = 1 << 32;
1095        /// `NVnTTLBIS` bit.
1096        const NVNTTLBIS = 1 << 33;
1097        /// `NVnTTLBOS` bit.
1098        const NVNTTLBOS = 1 << 34;
1099        /// `VTLBIDOSEn` bit.
1100        const VTLBIDOSEN = 1 << 35;
1101        /// `FNB` bit.
1102        const FNB = 1 << 36;
1103        /// `VTE` bit.
1104        const VTE = 1 << 37;
1105        /// `VTAO` bit.
1106        const VTAO = 1 << 38;
1107        /// `VTCO` bit.
1108        const VTCO = 1 << 39;
1109    }
1110}
1111
1112#[cfg(feature = "el2")]
1113impl HcrxEl2 {
1114    /// Offset of the EnAS0 field.
1115    pub const ENAS0_SHIFT: u32 = 0;
1116    /// Offset of the EnALS field.
1117    pub const ENALS_SHIFT: u32 = 1;
1118    /// Offset of the EnASR field.
1119    pub const ENASR_SHIFT: u32 = 2;
1120    /// Offset of the FnXS field.
1121    pub const FNXS_SHIFT: u32 = 3;
1122    /// Offset of the FGTnXS field.
1123    pub const FGTNXS_SHIFT: u32 = 4;
1124    /// Offset of the SMPME field.
1125    pub const SMPME_SHIFT: u32 = 5;
1126    /// Offset of the TALLINT field.
1127    pub const TALLINT_SHIFT: u32 = 6;
1128    /// Offset of the VINMI field.
1129    pub const VINMI_SHIFT: u32 = 7;
1130    /// Offset of the VFNMI field.
1131    pub const VFNMI_SHIFT: u32 = 8;
1132    /// Offset of the CMOW field.
1133    pub const CMOW_SHIFT: u32 = 9;
1134    /// Offset of the MCE2 field.
1135    pub const MCE2_SHIFT: u32 = 10;
1136    /// Offset of the MSCEn field.
1137    pub const MSCEN_SHIFT: u32 = 11;
1138    /// Offset of the TCR2En field.
1139    pub const TCR2EN_SHIFT: u32 = 14;
1140    /// Offset of the SCTLR2En field.
1141    pub const SCTLR2EN_SHIFT: u32 = 15;
1142    /// Offset of the PTTWI field.
1143    pub const PTTWI_SHIFT: u32 = 16;
1144    /// Offset of the D128En field.
1145    pub const D128EN_SHIFT: u32 = 17;
1146    /// Offset of the EnSNERR field.
1147    pub const ENSNERR_SHIFT: u32 = 18;
1148    /// Offset of the TMEA field.
1149    pub const TMEA_SHIFT: u32 = 19;
1150    /// Offset of the EnSDERR field.
1151    pub const ENSDERR_SHIFT: u32 = 20;
1152    /// Offset of the EnIDCP128 field.
1153    pub const ENIDCP128_SHIFT: u32 = 21;
1154    /// Offset of the GCSEn field.
1155    pub const GCSEN_SHIFT: u32 = 22;
1156    /// Offset of the EnFPM field.
1157    pub const ENFPM_SHIFT: u32 = 23;
1158    /// Offset of the PACMEn field.
1159    pub const PACMEN_SHIFT: u32 = 24;
1160    /// Offset of the VTLBIDEn field.
1161    pub const VTLBIDEN_SHIFT: u32 = 25;
1162    /// Offset of the SRMASKEn field.
1163    pub const SRMASKEN_SHIFT: u32 = 26;
1164    /// Offset of the NVTGE field.
1165    pub const NVTGE_SHIFT: u32 = 27;
1166    /// Offset of the POE2En field.
1167    pub const POE2EN_SHIFT: u32 = 29;
1168    /// Offset of the TPLIMEn field.
1169    pub const TPLIMEN_SHIFT: u32 = 30;
1170    /// Offset of the FDIT field.
1171    pub const FDIT_SHIFT: u32 = 31;
1172    /// Offset of the NVnTTLB field.
1173    pub const NVNTTLB_SHIFT: u32 = 32;
1174    /// Offset of the NVnTTLBIS field.
1175    pub const NVNTTLBIS_SHIFT: u32 = 33;
1176    /// Offset of the NVnTTLBOS field.
1177    pub const NVNTTLBOS_SHIFT: u32 = 34;
1178    /// Offset of the VTLBIDOSEn field.
1179    pub const VTLBIDOSEN_SHIFT: u32 = 35;
1180    /// Offset of the FNB field.
1181    pub const FNB_SHIFT: u32 = 36;
1182    /// Offset of the VTE field.
1183    pub const VTE_SHIFT: u32 = 37;
1184    /// Offset of the VTAO field.
1185    pub const VTAO_SHIFT: u32 = 38;
1186    /// Offset of the VTCO field.
1187    pub const VTCO_SHIFT: u32 = 39;
1188}
1189
1190#[cfg(feature = "el2")]
1191bitflags! {
1192    /// `HCR_EL2` system register value.
1193    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
1194    #[repr(transparent)]
1195    pub struct HcrEl2: u64 {
1196        /// `VM` bit.
1197        const VM = 1 << 0;
1198        /// `SWIO` bit.
1199        const SWIO = 1 << 1;
1200        /// `PTW` bit.
1201        const PTW = 1 << 2;
1202        /// `FMO` bit.
1203        const FMO = 1 << 3;
1204        /// `IMO` bit.
1205        const IMO = 1 << 4;
1206        /// `AMO` bit.
1207        const AMO = 1 << 5;
1208        /// `VF` bit.
1209        const VF = 1 << 6;
1210        /// `VI` bit.
1211        const VI = 1 << 7;
1212        /// `VSE` bit.
1213        const VSE = 1 << 8;
1214        /// `FB` bit.
1215        const FB = 1 << 9;
1216        /// `DC` bit.
1217        const DC = 1 << 12;
1218        /// `TWI` bit.
1219        const TWI = 1 << 13;
1220        /// `TWE` bit.
1221        const TWE = 1 << 14;
1222        /// `TID0` bit.
1223        const TID0 = 1 << 15;
1224        /// `TID1` bit.
1225        const TID1 = 1 << 16;
1226        /// `TID2` bit.
1227        const TID2 = 1 << 17;
1228        /// `TID3` bit.
1229        const TID3 = 1 << 18;
1230        /// `TSC` bit.
1231        const TSC = 1 << 19;
1232        /// `TIDCP` bit.
1233        const TIDCP = 1 << 20;
1234        /// `TACR` bit.
1235        const TACR = 1 << 21;
1236        /// `TSW` bit.
1237        const TSW = 1 << 22;
1238        /// `TPCP` bit.
1239        const TPCP = 1 << 23;
1240        /// `TPU` bit.
1241        const TPU = 1 << 24;
1242        /// `TTLB` bit.
1243        const TTLB = 1 << 25;
1244        /// `TVM` bit.
1245        const TVM = 1 << 26;
1246        /// Trap general exceptions to EL2.
1247        const TGE = 1 << 27;
1248        /// `TDZ` bit.
1249        const TDZ = 1 << 28;
1250        /// `HCD` bit.
1251        const HCD = 1 << 29;
1252        /// `TRVM` bit.
1253        const TRVM = 1 << 30;
1254        /// `RW` bit.
1255        const RW = 1 << 31;
1256        /// `CD` bit.
1257        const CD = 1 << 32;
1258        /// `ID` bit.
1259        const ID = 1 << 33;
1260        /// `E2H` bit.
1261        const E2H = 1 << 34;
1262        /// `TLOR` bit.
1263        const TLOR = 1 << 35;
1264        /// `TERR` bit.
1265        const TERR = 1 << 36;
1266        /// `TEA` bit.
1267        const TEA = 1 << 37;
1268        /// `APK` bit.
1269        const APK = 1 << 40;
1270        /// `API` bit.
1271        const API = 1 << 41;
1272        /// `NV` bit.
1273        const NV = 1 << 42;
1274        /// `NV1` bit.
1275        const NV1 = 1 << 43;
1276        /// `AT` bit.
1277        const AT = 1 << 44;
1278        /// `NV2` bit.
1279        const NV2 = 1 << 45;
1280        /// `FWB` bit.
1281        const FWB = 1 << 46;
1282        /// `FIEN` bit.
1283        const FIEN = 1 << 47;
1284        /// `GPF` bit.
1285        const GPF = 1 << 48;
1286        /// `TID4` bit.
1287        const TID4 = 1 << 49;
1288        /// `TICAB` bit.
1289        const TICAB = 1 << 50;
1290        /// `AMVOFFEN` bit.
1291        const AMVOFFEN = 1 << 51;
1292        /// `TOCU` bit.
1293        const TOCU = 1 << 52;
1294        /// `EnSCXT` bit.
1295        const ENSCXT = 1 << 53;
1296        /// `TTLBIS` bit.
1297        const TTLBIS = 1 << 54;
1298        /// `TTLBOS` bit.
1299        const TTLBOS = 1 << 55;
1300        /// `ATA` bit.
1301        const ATA = 1 << 56;
1302        /// `DCT` bit.
1303        const DCT = 1 << 57;
1304        /// `TID5` bit.
1305        const TID5 = 1 << 58;
1306        /// `TWEDEn` bit.
1307        const TWEDEN = 1 << 59;
1308    }
1309}
1310
1311#[cfg(feature = "el2")]
1312impl HcrEl2 {
1313    /// Offset of the VM field.
1314    pub const VM_SHIFT: u32 = 0;
1315    /// Offset of the SWIO field.
1316    pub const SWIO_SHIFT: u32 = 1;
1317    /// Offset of the PTW field.
1318    pub const PTW_SHIFT: u32 = 2;
1319    /// Offset of the FMO field.
1320    pub const FMO_SHIFT: u32 = 3;
1321    /// Offset of the IMO field.
1322    pub const IMO_SHIFT: u32 = 4;
1323    /// Offset of the AMO field.
1324    pub const AMO_SHIFT: u32 = 5;
1325    /// Offset of the VF field.
1326    pub const VF_SHIFT: u32 = 6;
1327    /// Offset of the VI field.
1328    pub const VI_SHIFT: u32 = 7;
1329    /// Offset of the VSE field.
1330    pub const VSE_SHIFT: u32 = 8;
1331    /// Offset of the FB field.
1332    pub const FB_SHIFT: u32 = 9;
1333    /// Offset of the BSU field.
1334    pub const BSU_SHIFT: u32 = 10;
1335    /// Mask for the BSU field.
1336    pub const BSU_MASK: u64 = 0b11;
1337    /// Offset of the DC field.
1338    pub const DC_SHIFT: u32 = 12;
1339    /// Offset of the TWI field.
1340    pub const TWI_SHIFT: u32 = 13;
1341    /// Offset of the TWE field.
1342    pub const TWE_SHIFT: u32 = 14;
1343    /// Offset of the TID0 field.
1344    pub const TID0_SHIFT: u32 = 15;
1345    /// Offset of the TID1 field.
1346    pub const TID1_SHIFT: u32 = 16;
1347    /// Offset of the TID2 field.
1348    pub const TID2_SHIFT: u32 = 17;
1349    /// Offset of the TID3 field.
1350    pub const TID3_SHIFT: u32 = 18;
1351    /// Offset of the TSC field.
1352    pub const TSC_SHIFT: u32 = 19;
1353    /// Offset of the TIDCP field.
1354    pub const TIDCP_SHIFT: u32 = 20;
1355    /// Offset of the TACR field.
1356    pub const TACR_SHIFT: u32 = 21;
1357    /// Offset of the TSW field.
1358    pub const TSW_SHIFT: u32 = 22;
1359    /// Offset of the TPCP field.
1360    pub const TPCP_SHIFT: u32 = 23;
1361    /// Offset of the TPU field.
1362    pub const TPU_SHIFT: u32 = 24;
1363    /// Offset of the TTLB field.
1364    pub const TTLB_SHIFT: u32 = 25;
1365    /// Offset of the TVM field.
1366    pub const TVM_SHIFT: u32 = 26;
1367    /// Offset of the TGE field.
1368    pub const TGE_SHIFT: u32 = 27;
1369    /// Offset of the TDZ field.
1370    pub const TDZ_SHIFT: u32 = 28;
1371    /// Offset of the HCD field.
1372    pub const HCD_SHIFT: u32 = 29;
1373    /// Offset of the TRVM field.
1374    pub const TRVM_SHIFT: u32 = 30;
1375    /// Offset of the RW field.
1376    pub const RW_SHIFT: u32 = 31;
1377    /// Offset of the CD field.
1378    pub const CD_SHIFT: u32 = 32;
1379    /// Offset of the ID field.
1380    pub const ID_SHIFT: u32 = 33;
1381    /// Offset of the E2H field.
1382    pub const E2H_SHIFT: u32 = 34;
1383    /// Offset of the TLOR field.
1384    pub const TLOR_SHIFT: u32 = 35;
1385    /// Offset of the TERR field.
1386    pub const TERR_SHIFT: u32 = 36;
1387    /// Offset of the TEA field.
1388    pub const TEA_SHIFT: u32 = 37;
1389    /// Offset of the APK field.
1390    pub const APK_SHIFT: u32 = 40;
1391    /// Offset of the API field.
1392    pub const API_SHIFT: u32 = 41;
1393    /// Offset of the NV field.
1394    pub const NV_SHIFT: u32 = 42;
1395    /// Offset of the NV1 field.
1396    pub const NV1_SHIFT: u32 = 43;
1397    /// Offset of the AT field.
1398    pub const AT_SHIFT: u32 = 44;
1399    /// Offset of the NV2 field.
1400    pub const NV2_SHIFT: u32 = 45;
1401    /// Offset of the FWB field.
1402    pub const FWB_SHIFT: u32 = 46;
1403    /// Offset of the FIEN field.
1404    pub const FIEN_SHIFT: u32 = 47;
1405    /// Offset of the GPF field.
1406    pub const GPF_SHIFT: u32 = 48;
1407    /// Offset of the TID4 field.
1408    pub const TID4_SHIFT: u32 = 49;
1409    /// Offset of the TICAB field.
1410    pub const TICAB_SHIFT: u32 = 50;
1411    /// Offset of the AMVOFFEN field.
1412    pub const AMVOFFEN_SHIFT: u32 = 51;
1413    /// Offset of the TOCU field.
1414    pub const TOCU_SHIFT: u32 = 52;
1415    /// Offset of the EnSCXT field.
1416    pub const ENSCXT_SHIFT: u32 = 53;
1417    /// Offset of the TTLBIS field.
1418    pub const TTLBIS_SHIFT: u32 = 54;
1419    /// Offset of the TTLBOS field.
1420    pub const TTLBOS_SHIFT: u32 = 55;
1421    /// Offset of the ATA field.
1422    pub const ATA_SHIFT: u32 = 56;
1423    /// Offset of the DCT field.
1424    pub const DCT_SHIFT: u32 = 57;
1425    /// Offset of the TID5 field.
1426    pub const TID5_SHIFT: u32 = 58;
1427    /// Offset of the TWEDEn field.
1428    pub const TWEDEN_SHIFT: u32 = 59;
1429    /// Offset of the TWEDEL field.
1430    pub const TWEDEL_SHIFT: u32 = 60;
1431    /// Mask for the TWEDEL field.
1432    pub const TWEDEL_MASK: u64 = 0b1111;
1433
1434    /// Returns the value of the `BSU` field.
1435    pub const fn bsu(self) -> u8 {
1436        ((self.bits() >> Self::BSU_SHIFT) & 0b11) as u8
1437    }
1438
1439    /// Returns the value of the `TWEDEL` field.
1440    pub const fn twedel(self) -> u8 {
1441        ((self.bits() >> Self::TWEDEL_SHIFT) & 0b1111) as u8
1442    }
1443}
1444
1445#[cfg(feature = "el2")]
1446bitflags! {
1447    /// `HDFGRTR2_EL2` system register value.
1448    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
1449    #[repr(transparent)]
1450    pub struct Hdfgrtr2El2: u64 {
1451        /// `nPMECR_EL1` bit.
1452        const NPMECR_EL1 = 1 << 0;
1453        /// `nPMIAR_EL1` bit.
1454        const NPMIAR_EL1 = 1 << 1;
1455        /// `nPMICNTR_EL0` bit.
1456        const NPMICNTR_EL0 = 1 << 2;
1457        /// `nPMICFILTR_EL0` bit.
1458        const NPMICFILTR_EL0 = 1 << 3;
1459        /// `nPMUACR_EL1` bit.
1460        const NPMUACR_EL1 = 1 << 4;
1461        /// `nMDSELR_EL1` bit.
1462        const NMDSELR_EL1 = 1 << 5;
1463        /// `nPMSSDATA` bit.
1464        const NPMSSDATA = 1 << 6;
1465        /// `nPMSSCR_EL1` bit.
1466        const NPMSSCR_EL1 = 1 << 7;
1467        /// `nSPMEVCNTRn_EL0` bit.
1468        const NSPMEVCNTRN_EL0 = 1 << 8;
1469        /// `nSPMEVTYPERn_EL0` bit.
1470        const NSPMEVTYPERN_EL0 = 1 << 9;
1471        /// `nSPMSELR_EL0` bit.
1472        const NSPMSELR_EL0 = 1 << 10;
1473        /// `nSPMCNTEN` bit.
1474        const NSPMCNTEN = 1 << 11;
1475        /// `nSPMINTEN` bit.
1476        const NSPMINTEN = 1 << 12;
1477        /// `nSPMOVS` bit.
1478        const NSPMOVS = 1 << 13;
1479        /// `nSPMCR_EL0` bit.
1480        const NSPMCR_EL0 = 1 << 14;
1481        /// `nSPMACCESSR_EL1` bit.
1482        const NSPMACCESSR_EL1 = 1 << 15;
1483        /// `nSPMSCR_EL1` bit.
1484        const NSPMSCR_EL1 = 1 << 16;
1485        /// `nSPMID` bit.
1486        const NSPMID = 1 << 17;
1487        /// `nSPMDEVAFF_EL1` bit.
1488        const NSPMDEVAFF_EL1 = 1 << 18;
1489        /// `nPMSDSFR_EL1` bit.
1490        const NPMSDSFR_EL1 = 1 << 19;
1491        /// `nTRCITECR_EL1` bit.
1492        const NTRCITECR_EL1 = 1 << 20;
1493        /// `nTRBMPAM_EL1` bit.
1494        const NTRBMPAM_EL1 = 1 << 22;
1495        /// `nMDSTEPOP_EL1` bit.
1496        const NMDSTEPOP_EL1 = 1 << 23;
1497        /// `nPMBMAR_EL1` bit.
1498        const NPMBMAR_EL1 = 1 << 24;
1499    }
1500}
1501
1502#[cfg(feature = "el2")]
1503impl Hdfgrtr2El2 {
1504    /// Offset of the nPMECR_EL1 field.
1505    pub const NPMECR_EL1_SHIFT: u32 = 0;
1506    /// Offset of the nPMIAR_EL1 field.
1507    pub const NPMIAR_EL1_SHIFT: u32 = 1;
1508    /// Offset of the nPMICNTR_EL0 field.
1509    pub const NPMICNTR_EL0_SHIFT: u32 = 2;
1510    /// Offset of the nPMICFILTR_EL0 field.
1511    pub const NPMICFILTR_EL0_SHIFT: u32 = 3;
1512    /// Offset of the nPMUACR_EL1 field.
1513    pub const NPMUACR_EL1_SHIFT: u32 = 4;
1514    /// Offset of the nMDSELR_EL1 field.
1515    pub const NMDSELR_EL1_SHIFT: u32 = 5;
1516    /// Offset of the nPMSSDATA field.
1517    pub const NPMSSDATA_SHIFT: u32 = 6;
1518    /// Offset of the nPMSSCR_EL1 field.
1519    pub const NPMSSCR_EL1_SHIFT: u32 = 7;
1520    /// Offset of the nSPMEVCNTRn_EL0 field.
1521    pub const NSPMEVCNTRN_EL0_SHIFT: u32 = 8;
1522    /// Offset of the nSPMEVTYPERn_EL0 field.
1523    pub const NSPMEVTYPERN_EL0_SHIFT: u32 = 9;
1524    /// Offset of the nSPMSELR_EL0 field.
1525    pub const NSPMSELR_EL0_SHIFT: u32 = 10;
1526    /// Offset of the nSPMCNTEN field.
1527    pub const NSPMCNTEN_SHIFT: u32 = 11;
1528    /// Offset of the nSPMINTEN field.
1529    pub const NSPMINTEN_SHIFT: u32 = 12;
1530    /// Offset of the nSPMOVS field.
1531    pub const NSPMOVS_SHIFT: u32 = 13;
1532    /// Offset of the nSPMCR_EL0 field.
1533    pub const NSPMCR_EL0_SHIFT: u32 = 14;
1534    /// Offset of the nSPMACCESSR_EL1 field.
1535    pub const NSPMACCESSR_EL1_SHIFT: u32 = 15;
1536    /// Offset of the nSPMSCR_EL1 field.
1537    pub const NSPMSCR_EL1_SHIFT: u32 = 16;
1538    /// Offset of the nSPMID field.
1539    pub const NSPMID_SHIFT: u32 = 17;
1540    /// Offset of the nSPMDEVAFF_EL1 field.
1541    pub const NSPMDEVAFF_EL1_SHIFT: u32 = 18;
1542    /// Offset of the nPMSDSFR_EL1 field.
1543    pub const NPMSDSFR_EL1_SHIFT: u32 = 19;
1544    /// Offset of the nTRCITECR_EL1 field.
1545    pub const NTRCITECR_EL1_SHIFT: u32 = 20;
1546    /// Offset of the nTRBMPAM_EL1 field.
1547    pub const NTRBMPAM_EL1_SHIFT: u32 = 22;
1548    /// Offset of the nMDSTEPOP_EL1 field.
1549    pub const NMDSTEPOP_EL1_SHIFT: u32 = 23;
1550    /// Offset of the nPMBMAR_EL1 field.
1551    pub const NPMBMAR_EL1_SHIFT: u32 = 24;
1552}
1553
1554#[cfg(feature = "el2")]
1555bitflags! {
1556    /// `HDFGWTR2_EL2` system register value.
1557    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
1558    #[repr(transparent)]
1559    pub struct Hdfgwtr2El2: u64 {
1560        /// `nPMECR_EL1` bit.
1561        const NPMECR_EL1 = 1 << 0;
1562        /// `nPMIAR_EL1` bit.
1563        const NPMIAR_EL1 = 1 << 1;
1564        /// `nPMICNTR_EL0` bit.
1565        const NPMICNTR_EL0 = 1 << 2;
1566        /// `nPMICFILTR_EL0` bit.
1567        const NPMICFILTR_EL0 = 1 << 3;
1568        /// `nPMUACR_EL1` bit.
1569        const NPMUACR_EL1 = 1 << 4;
1570        /// `nMDSELR_EL1` bit.
1571        const NMDSELR_EL1 = 1 << 5;
1572        /// `nPMSSCR_EL1` bit.
1573        const NPMSSCR_EL1 = 1 << 7;
1574        /// `nSPMEVCNTRn_EL0` bit.
1575        const NSPMEVCNTRN_EL0 = 1 << 8;
1576        /// `nSPMEVTYPERn_EL0` bit.
1577        const NSPMEVTYPERN_EL0 = 1 << 9;
1578        /// `nSPMSELR_EL0` bit.
1579        const NSPMSELR_EL0 = 1 << 10;
1580        /// `nSPMCNTEN` bit.
1581        const NSPMCNTEN = 1 << 11;
1582        /// `nSPMINTEN` bit.
1583        const NSPMINTEN = 1 << 12;
1584        /// `nSPMOVS` bit.
1585        const NSPMOVS = 1 << 13;
1586        /// `nSPMCR_EL0` bit.
1587        const NSPMCR_EL0 = 1 << 14;
1588        /// `nSPMACCESSR_EL1` bit.
1589        const NSPMACCESSR_EL1 = 1 << 15;
1590        /// `nSPMSCR_EL1` bit.
1591        const NSPMSCR_EL1 = 1 << 16;
1592        /// `nPMSDSFR_EL1` bit.
1593        const NPMSDSFR_EL1 = 1 << 19;
1594        /// `nTRCITECR_EL1` bit.
1595        const NTRCITECR_EL1 = 1 << 20;
1596        /// `nPMZR_EL0` bit.
1597        const NPMZR_EL0 = 1 << 21;
1598        /// `nTRBMPAM_EL1` bit.
1599        const NTRBMPAM_EL1 = 1 << 22;
1600        /// `nMDSTEPOP_EL1` bit.
1601        const NMDSTEPOP_EL1 = 1 << 23;
1602        /// `nPMBMAR_EL1` bit.
1603        const NPMBMAR_EL1 = 1 << 24;
1604    }
1605}
1606
1607#[cfg(feature = "el2")]
1608impl Hdfgwtr2El2 {
1609    /// Offset of the nPMECR_EL1 field.
1610    pub const NPMECR_EL1_SHIFT: u32 = 0;
1611    /// Offset of the nPMIAR_EL1 field.
1612    pub const NPMIAR_EL1_SHIFT: u32 = 1;
1613    /// Offset of the nPMICNTR_EL0 field.
1614    pub const NPMICNTR_EL0_SHIFT: u32 = 2;
1615    /// Offset of the nPMICFILTR_EL0 field.
1616    pub const NPMICFILTR_EL0_SHIFT: u32 = 3;
1617    /// Offset of the nPMUACR_EL1 field.
1618    pub const NPMUACR_EL1_SHIFT: u32 = 4;
1619    /// Offset of the nMDSELR_EL1 field.
1620    pub const NMDSELR_EL1_SHIFT: u32 = 5;
1621    /// Offset of the nPMSSCR_EL1 field.
1622    pub const NPMSSCR_EL1_SHIFT: u32 = 7;
1623    /// Offset of the nSPMEVCNTRn_EL0 field.
1624    pub const NSPMEVCNTRN_EL0_SHIFT: u32 = 8;
1625    /// Offset of the nSPMEVTYPERn_EL0 field.
1626    pub const NSPMEVTYPERN_EL0_SHIFT: u32 = 9;
1627    /// Offset of the nSPMSELR_EL0 field.
1628    pub const NSPMSELR_EL0_SHIFT: u32 = 10;
1629    /// Offset of the nSPMCNTEN field.
1630    pub const NSPMCNTEN_SHIFT: u32 = 11;
1631    /// Offset of the nSPMINTEN field.
1632    pub const NSPMINTEN_SHIFT: u32 = 12;
1633    /// Offset of the nSPMOVS field.
1634    pub const NSPMOVS_SHIFT: u32 = 13;
1635    /// Offset of the nSPMCR_EL0 field.
1636    pub const NSPMCR_EL0_SHIFT: u32 = 14;
1637    /// Offset of the nSPMACCESSR_EL1 field.
1638    pub const NSPMACCESSR_EL1_SHIFT: u32 = 15;
1639    /// Offset of the nSPMSCR_EL1 field.
1640    pub const NSPMSCR_EL1_SHIFT: u32 = 16;
1641    /// Offset of the nPMSDSFR_EL1 field.
1642    pub const NPMSDSFR_EL1_SHIFT: u32 = 19;
1643    /// Offset of the nTRCITECR_EL1 field.
1644    pub const NTRCITECR_EL1_SHIFT: u32 = 20;
1645    /// Offset of the nPMZR_EL0 field.
1646    pub const NPMZR_EL0_SHIFT: u32 = 21;
1647    /// Offset of the nTRBMPAM_EL1 field.
1648    pub const NTRBMPAM_EL1_SHIFT: u32 = 22;
1649    /// Offset of the nMDSTEPOP_EL1 field.
1650    pub const NMDSTEPOP_EL1_SHIFT: u32 = 23;
1651    /// Offset of the nPMBMAR_EL1 field.
1652    pub const NPMBMAR_EL1_SHIFT: u32 = 24;
1653}
1654
1655#[cfg(feature = "el2")]
1656bitflags! {
1657    /// `HFGITR2_EL2` system register value.
1658    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
1659    #[repr(transparent)]
1660    pub struct Hfgitr2El2: u64 {
1661        /// `TSBCSYNC` bit.
1662        const TSBCSYNC = 1 << 0;
1663        /// `nDCCIVAPS` bit.
1664        const NDCCIVAPS = 1 << 1;
1665        /// `PLBIPERME1OS` bit.
1666        const PLBIPERME1OS = 1 << 2;
1667        /// `PLBIASIDE1OS` bit.
1668        const PLBIASIDE1OS = 1 << 3;
1669        /// `PLBIVMALLE1OS` bit.
1670        const PLBIVMALLE1OS = 1 << 4;
1671        /// `PLBIPERME1IS` bit.
1672        const PLBIPERME1IS = 1 << 5;
1673        /// `PLBIASIDE1IS` bit.
1674        const PLBIASIDE1IS = 1 << 6;
1675        /// `PLBIVMALLE1IS` bit.
1676        const PLBIVMALLE1IS = 1 << 7;
1677        /// `PLBIPERME1` bit.
1678        const PLBIPERME1 = 1 << 8;
1679        /// `PLBIASIDE1` bit.
1680        const PLBIASIDE1 = 1 << 9;
1681        /// `PLBIVMALLE1` bit.
1682        const PLBIVMALLE1 = 1 << 10;
1683        /// `PLBIPERMAE1OS` bit.
1684        const PLBIPERMAE1OS = 1 << 11;
1685        /// `PLBIPERMAE1IS` bit.
1686        const PLBIPERMAE1IS = 1 << 12;
1687        /// `PLBIPERMAE1` bit.
1688        const PLBIPERMAE1 = 1 << 13;
1689        /// `DCGBVA` bit.
1690        const DCGBVA = 1 << 14;
1691    }
1692}
1693
1694#[cfg(feature = "el2")]
1695impl Hfgitr2El2 {
1696    /// Offset of the TSBCSYNC field.
1697    pub const TSBCSYNC_SHIFT: u32 = 0;
1698    /// Offset of the nDCCIVAPS field.
1699    pub const NDCCIVAPS_SHIFT: u32 = 1;
1700    /// Offset of the PLBIPERME1OS field.
1701    pub const PLBIPERME1OS_SHIFT: u32 = 2;
1702    /// Offset of the PLBIASIDE1OS field.
1703    pub const PLBIASIDE1OS_SHIFT: u32 = 3;
1704    /// Offset of the PLBIVMALLE1OS field.
1705    pub const PLBIVMALLE1OS_SHIFT: u32 = 4;
1706    /// Offset of the PLBIPERME1IS field.
1707    pub const PLBIPERME1IS_SHIFT: u32 = 5;
1708    /// Offset of the PLBIASIDE1IS field.
1709    pub const PLBIASIDE1IS_SHIFT: u32 = 6;
1710    /// Offset of the PLBIVMALLE1IS field.
1711    pub const PLBIVMALLE1IS_SHIFT: u32 = 7;
1712    /// Offset of the PLBIPERME1 field.
1713    pub const PLBIPERME1_SHIFT: u32 = 8;
1714    /// Offset of the PLBIASIDE1 field.
1715    pub const PLBIASIDE1_SHIFT: u32 = 9;
1716    /// Offset of the PLBIVMALLE1 field.
1717    pub const PLBIVMALLE1_SHIFT: u32 = 10;
1718    /// Offset of the PLBIPERMAE1OS field.
1719    pub const PLBIPERMAE1OS_SHIFT: u32 = 11;
1720    /// Offset of the PLBIPERMAE1IS field.
1721    pub const PLBIPERMAE1IS_SHIFT: u32 = 12;
1722    /// Offset of the PLBIPERMAE1 field.
1723    pub const PLBIPERMAE1_SHIFT: u32 = 13;
1724    /// Offset of the DCGBVA field.
1725    pub const DCGBVA_SHIFT: u32 = 14;
1726}
1727
1728#[cfg(feature = "el2")]
1729bitflags! {
1730    /// `HFGRTR2_EL2` system register value.
1731    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
1732    #[repr(transparent)]
1733    pub struct Hfgrtr2El2: u64 {
1734        /// `nPFAR_EL1` bit.
1735        const NPFAR_EL1 = 1 << 0;
1736        /// `nERXGSR_EL1` bit.
1737        const NERXGSR_EL1 = 1 << 1;
1738        /// `nRCWSMASK_EL1` bit.
1739        const NRCWSMASK_EL1 = 1 << 2;
1740        /// `nCPACRMASK_EL1` bit.
1741        const NCPACRMASK_EL1 = 1 << 3;
1742        /// `nSCTLRMASK_EL1` bit.
1743        const NSCTLRMASK_EL1 = 1 << 4;
1744        /// `nSCTLR2MASK_EL1` bit.
1745        const NSCTLR2MASK_EL1 = 1 << 5;
1746        /// `nTCRMASK_EL1` bit.
1747        const NTCRMASK_EL1 = 1 << 6;
1748        /// `nTCR2MASK_EL1` bit.
1749        const NTCR2MASK_EL1 = 1 << 7;
1750        /// `nCPACRALIAS_EL1` bit.
1751        const NCPACRALIAS_EL1 = 1 << 8;
1752        /// `nSCTLRALIAS_EL1` bit.
1753        const NSCTLRALIAS_EL1 = 1 << 9;
1754        /// `nSCTLR2ALIAS_EL1` bit.
1755        const NSCTLR2ALIAS_EL1 = 1 << 10;
1756        /// `nTCRALIAS_EL1` bit.
1757        const NTCRALIAS_EL1 = 1 << 11;
1758        /// `nTCR2ALIAS_EL1` bit.
1759        const NTCR2ALIAS_EL1 = 1 << 12;
1760        /// `nACTLRMASK_EL1` bit.
1761        const NACTLRMASK_EL1 = 1 << 13;
1762        /// `nACTLRALIAS_EL1` bit.
1763        const NACTLRALIAS_EL1 = 1 << 14;
1764        /// `nTINDEX_EL0` bit.
1765        const NTINDEX_EL0 = 1 << 15;
1766        /// `nTINDEX_EL1` bit.
1767        const NTINDEX_EL1 = 1 << 16;
1768        /// `nSTINDEX_EL1` bit.
1769        const NSTINDEX_EL1 = 1 << 17;
1770        /// `nTTTBRP_EL1` bit.
1771        const NTTTBRP_EL1 = 1 << 20;
1772        /// `nTTTBRU_EL1` bit.
1773        const NTTTBRU_EL1 = 1 << 21;
1774        /// `nIRTBRP_EL1` bit.
1775        const NIRTBRP_EL1 = 1 << 22;
1776        /// `nIRTBRU_EL1` bit.
1777        const NIRTBRU_EL1 = 1 << 23;
1778        /// `nDPOTBR1_EL1` bit.
1779        const NDPOTBR1_EL1 = 1 << 24;
1780        /// `nDPOTBR0_EL1` bit.
1781        const NDPOTBR0_EL1 = 1 << 25;
1782        /// `nTPMIN1_EL1` bit.
1783        const NTPMIN1_EL1 = 1 << 26;
1784        /// `nTPMIN0_EL1` bit.
1785        const NTPMIN0_EL1 = 1 << 27;
1786        /// `nTPMIN1_EL0` bit.
1787        const NTPMIN1_EL0 = 1 << 28;
1788        /// `nTPMIN0_EL0` bit.
1789        const NTPMIN0_EL0 = 1 << 29;
1790        /// `nTLBIDIDR_EL1` bit.
1791        const NTLBIDIDR_EL1 = 1 << 30;
1792        /// `TFSR_EL1` bit.
1793        const TFSR_EL1 = 1 << 33;
1794        /// `RGSR_EL1` bit.
1795        const RGSR_EL1 = 1 << 34;
1796        /// `GCR_EL1` bit.
1797        const GCR_EL1 = 1 << 35;
1798        /// `nTPIDR3_EL0` bit.
1799        const NTPIDR3_EL0 = 1 << 36;
1800        /// `nTPIDR3_EL1` bit.
1801        const NTPIDR3_EL1 = 1 << 37;
1802    }
1803}
1804
1805#[cfg(feature = "el2")]
1806impl Hfgrtr2El2 {
1807    /// Offset of the nPFAR_EL1 field.
1808    pub const NPFAR_EL1_SHIFT: u32 = 0;
1809    /// Offset of the nERXGSR_EL1 field.
1810    pub const NERXGSR_EL1_SHIFT: u32 = 1;
1811    /// Offset of the nRCWSMASK_EL1 field.
1812    pub const NRCWSMASK_EL1_SHIFT: u32 = 2;
1813    /// Offset of the nCPACRMASK_EL1 field.
1814    pub const NCPACRMASK_EL1_SHIFT: u32 = 3;
1815    /// Offset of the nSCTLRMASK_EL1 field.
1816    pub const NSCTLRMASK_EL1_SHIFT: u32 = 4;
1817    /// Offset of the nSCTLR2MASK_EL1 field.
1818    pub const NSCTLR2MASK_EL1_SHIFT: u32 = 5;
1819    /// Offset of the nTCRMASK_EL1 field.
1820    pub const NTCRMASK_EL1_SHIFT: u32 = 6;
1821    /// Offset of the nTCR2MASK_EL1 field.
1822    pub const NTCR2MASK_EL1_SHIFT: u32 = 7;
1823    /// Offset of the nCPACRALIAS_EL1 field.
1824    pub const NCPACRALIAS_EL1_SHIFT: u32 = 8;
1825    /// Offset of the nSCTLRALIAS_EL1 field.
1826    pub const NSCTLRALIAS_EL1_SHIFT: u32 = 9;
1827    /// Offset of the nSCTLR2ALIAS_EL1 field.
1828    pub const NSCTLR2ALIAS_EL1_SHIFT: u32 = 10;
1829    /// Offset of the nTCRALIAS_EL1 field.
1830    pub const NTCRALIAS_EL1_SHIFT: u32 = 11;
1831    /// Offset of the nTCR2ALIAS_EL1 field.
1832    pub const NTCR2ALIAS_EL1_SHIFT: u32 = 12;
1833    /// Offset of the nACTLRMASK_EL1 field.
1834    pub const NACTLRMASK_EL1_SHIFT: u32 = 13;
1835    /// Offset of the nACTLRALIAS_EL1 field.
1836    pub const NACTLRALIAS_EL1_SHIFT: u32 = 14;
1837    /// Offset of the nTINDEX_EL0 field.
1838    pub const NTINDEX_EL0_SHIFT: u32 = 15;
1839    /// Offset of the nTINDEX_EL1 field.
1840    pub const NTINDEX_EL1_SHIFT: u32 = 16;
1841    /// Offset of the nSTINDEX_EL1 field.
1842    pub const NSTINDEX_EL1_SHIFT: u32 = 17;
1843    /// Offset of the nFGDTn_EL1 field.
1844    pub const NFGDTN_EL1_SHIFT: u32 = 18;
1845    /// Mask for the nFGDTn_EL1 field.
1846    pub const NFGDTN_EL1_MASK: u64 = 0b11;
1847    /// Offset of the nTTTBRP_EL1 field.
1848    pub const NTTTBRP_EL1_SHIFT: u32 = 20;
1849    /// Offset of the nTTTBRU_EL1 field.
1850    pub const NTTTBRU_EL1_SHIFT: u32 = 21;
1851    /// Offset of the nIRTBRP_EL1 field.
1852    pub const NIRTBRP_EL1_SHIFT: u32 = 22;
1853    /// Offset of the nIRTBRU_EL1 field.
1854    pub const NIRTBRU_EL1_SHIFT: u32 = 23;
1855    /// Offset of the nDPOTBR1_EL1 field.
1856    pub const NDPOTBR1_EL1_SHIFT: u32 = 24;
1857    /// Offset of the nDPOTBR0_EL1 field.
1858    pub const NDPOTBR0_EL1_SHIFT: u32 = 25;
1859    /// Offset of the nTPMIN1_EL1 field.
1860    pub const NTPMIN1_EL1_SHIFT: u32 = 26;
1861    /// Offset of the nTPMIN0_EL1 field.
1862    pub const NTPMIN0_EL1_SHIFT: u32 = 27;
1863    /// Offset of the nTPMIN1_EL0 field.
1864    pub const NTPMIN1_EL0_SHIFT: u32 = 28;
1865    /// Offset of the nTPMIN0_EL0 field.
1866    pub const NTPMIN0_EL0_SHIFT: u32 = 29;
1867    /// Offset of the nTLBIDIDR_EL1 field.
1868    pub const NTLBIDIDR_EL1_SHIFT: u32 = 30;
1869    /// Offset of the nAFGDTn_EL1 field.
1870    pub const NAFGDTN_EL1_SHIFT: u32 = 31;
1871    /// Mask for the nAFGDTn_EL1 field.
1872    pub const NAFGDTN_EL1_MASK: u64 = 0b11;
1873    /// Offset of the TFSR_EL1 field.
1874    pub const TFSR_EL1_SHIFT: u32 = 33;
1875    /// Offset of the RGSR_EL1 field.
1876    pub const RGSR_EL1_SHIFT: u32 = 34;
1877    /// Offset of the GCR_EL1 field.
1878    pub const GCR_EL1_SHIFT: u32 = 35;
1879    /// Offset of the nTPIDR3_EL0 field.
1880    pub const NTPIDR3_EL0_SHIFT: u32 = 36;
1881    /// Offset of the nTPIDR3_EL1 field.
1882    pub const NTPIDR3_EL1_SHIFT: u32 = 37;
1883
1884    /// Returns the value of the `nFGDTn_EL1` field.
1885    pub const fn nfgdtn_el1(self) -> u8 {
1886        ((self.bits() >> Self::NFGDTN_EL1_SHIFT) & 0b11) as u8
1887    }
1888
1889    /// Returns the value of the `nAFGDTn_EL1` field.
1890    pub const fn nafgdtn_el1(self) -> u8 {
1891        ((self.bits() >> Self::NAFGDTN_EL1_SHIFT) & 0b11) as u8
1892    }
1893}
1894
1895#[cfg(feature = "el2")]
1896bitflags! {
1897    /// `HFGWTR2_EL2` system register value.
1898    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
1899    #[repr(transparent)]
1900    pub struct Hfgwtr2El2: u64 {
1901        /// `nPFAR_EL1` bit.
1902        const NPFAR_EL1 = 1 << 0;
1903        /// `nRCWSMASK_EL1` bit.
1904        const NRCWSMASK_EL1 = 1 << 2;
1905        /// `nCPACRMASK_EL1` bit.
1906        const NCPACRMASK_EL1 = 1 << 3;
1907        /// `nSCTLRMASK_EL1` bit.
1908        const NSCTLRMASK_EL1 = 1 << 4;
1909        /// `nSCTLR2MASK_EL1` bit.
1910        const NSCTLR2MASK_EL1 = 1 << 5;
1911        /// `nTCRMASK_EL1` bit.
1912        const NTCRMASK_EL1 = 1 << 6;
1913        /// `nTCR2MASK_EL1` bit.
1914        const NTCR2MASK_EL1 = 1 << 7;
1915        /// `nCPACRALIAS_EL1` bit.
1916        const NCPACRALIAS_EL1 = 1 << 8;
1917        /// `nSCTLRALIAS_EL1` bit.
1918        const NSCTLRALIAS_EL1 = 1 << 9;
1919        /// `nSCTLR2ALIAS_EL1` bit.
1920        const NSCTLR2ALIAS_EL1 = 1 << 10;
1921        /// `nTCRALIAS_EL1` bit.
1922        const NTCRALIAS_EL1 = 1 << 11;
1923        /// `nTCR2ALIAS_EL1` bit.
1924        const NTCR2ALIAS_EL1 = 1 << 12;
1925        /// `nACTLRMASK_EL1` bit.
1926        const NACTLRMASK_EL1 = 1 << 13;
1927        /// `nACTLRALIAS_EL1` bit.
1928        const NACTLRALIAS_EL1 = 1 << 14;
1929        /// `nTINDEX_EL0` bit.
1930        const NTINDEX_EL0 = 1 << 15;
1931        /// `nTINDEX_EL1` bit.
1932        const NTINDEX_EL1 = 1 << 16;
1933        /// `nSTINDEX_EL1` bit.
1934        const NSTINDEX_EL1 = 1 << 17;
1935        /// `nTTTBRP_EL1` bit.
1936        const NTTTBRP_EL1 = 1 << 20;
1937        /// `nTTTBRU_EL1` bit.
1938        const NTTTBRU_EL1 = 1 << 21;
1939        /// `nIRTBRP_EL1` bit.
1940        const NIRTBRP_EL1 = 1 << 22;
1941        /// `nIRTBRU_EL1` bit.
1942        const NIRTBRU_EL1 = 1 << 23;
1943        /// `nDPOTBR1_EL1` bit.
1944        const NDPOTBR1_EL1 = 1 << 24;
1945        /// `nDPOTBR0_EL1` bit.
1946        const NDPOTBR0_EL1 = 1 << 25;
1947        /// `nTPMIN1_EL1` bit.
1948        const NTPMIN1_EL1 = 1 << 26;
1949        /// `nTPMIN0_EL1` bit.
1950        const NTPMIN0_EL1 = 1 << 27;
1951        /// `nTPMIN1_EL0` bit.
1952        const NTPMIN1_EL0 = 1 << 28;
1953        /// `nTPMIN0_EL0` bit.
1954        const NTPMIN0_EL0 = 1 << 29;
1955        /// `TFSR_EL1` bit.
1956        const TFSR_EL1 = 1 << 33;
1957        /// `RGSR_EL1` bit.
1958        const RGSR_EL1 = 1 << 34;
1959        /// `GCR_EL1` bit.
1960        const GCR_EL1 = 1 << 35;
1961        /// `nTPIDR3_EL0` bit.
1962        const NTPIDR3_EL0 = 1 << 36;
1963        /// `nTPIDR3_EL1` bit.
1964        const NTPIDR3_EL1 = 1 << 37;
1965    }
1966}
1967
1968#[cfg(feature = "el2")]
1969impl Hfgwtr2El2 {
1970    /// Offset of the nPFAR_EL1 field.
1971    pub const NPFAR_EL1_SHIFT: u32 = 0;
1972    /// Offset of the nRCWSMASK_EL1 field.
1973    pub const NRCWSMASK_EL1_SHIFT: u32 = 2;
1974    /// Offset of the nCPACRMASK_EL1 field.
1975    pub const NCPACRMASK_EL1_SHIFT: u32 = 3;
1976    /// Offset of the nSCTLRMASK_EL1 field.
1977    pub const NSCTLRMASK_EL1_SHIFT: u32 = 4;
1978    /// Offset of the nSCTLR2MASK_EL1 field.
1979    pub const NSCTLR2MASK_EL1_SHIFT: u32 = 5;
1980    /// Offset of the nTCRMASK_EL1 field.
1981    pub const NTCRMASK_EL1_SHIFT: u32 = 6;
1982    /// Offset of the nTCR2MASK_EL1 field.
1983    pub const NTCR2MASK_EL1_SHIFT: u32 = 7;
1984    /// Offset of the nCPACRALIAS_EL1 field.
1985    pub const NCPACRALIAS_EL1_SHIFT: u32 = 8;
1986    /// Offset of the nSCTLRALIAS_EL1 field.
1987    pub const NSCTLRALIAS_EL1_SHIFT: u32 = 9;
1988    /// Offset of the nSCTLR2ALIAS_EL1 field.
1989    pub const NSCTLR2ALIAS_EL1_SHIFT: u32 = 10;
1990    /// Offset of the nTCRALIAS_EL1 field.
1991    pub const NTCRALIAS_EL1_SHIFT: u32 = 11;
1992    /// Offset of the nTCR2ALIAS_EL1 field.
1993    pub const NTCR2ALIAS_EL1_SHIFT: u32 = 12;
1994    /// Offset of the nACTLRMASK_EL1 field.
1995    pub const NACTLRMASK_EL1_SHIFT: u32 = 13;
1996    /// Offset of the nACTLRALIAS_EL1 field.
1997    pub const NACTLRALIAS_EL1_SHIFT: u32 = 14;
1998    /// Offset of the nTINDEX_EL0 field.
1999    pub const NTINDEX_EL0_SHIFT: u32 = 15;
2000    /// Offset of the nTINDEX_EL1 field.
2001    pub const NTINDEX_EL1_SHIFT: u32 = 16;
2002    /// Offset of the nSTINDEX_EL1 field.
2003    pub const NSTINDEX_EL1_SHIFT: u32 = 17;
2004    /// Offset of the nFGDTn_EL1 field.
2005    pub const NFGDTN_EL1_SHIFT: u32 = 18;
2006    /// Mask for the nFGDTn_EL1 field.
2007    pub const NFGDTN_EL1_MASK: u64 = 0b11;
2008    /// Offset of the nTTTBRP_EL1 field.
2009    pub const NTTTBRP_EL1_SHIFT: u32 = 20;
2010    /// Offset of the nTTTBRU_EL1 field.
2011    pub const NTTTBRU_EL1_SHIFT: u32 = 21;
2012    /// Offset of the nIRTBRP_EL1 field.
2013    pub const NIRTBRP_EL1_SHIFT: u32 = 22;
2014    /// Offset of the nIRTBRU_EL1 field.
2015    pub const NIRTBRU_EL1_SHIFT: u32 = 23;
2016    /// Offset of the nDPOTBR1_EL1 field.
2017    pub const NDPOTBR1_EL1_SHIFT: u32 = 24;
2018    /// Offset of the nDPOTBR0_EL1 field.
2019    pub const NDPOTBR0_EL1_SHIFT: u32 = 25;
2020    /// Offset of the nTPMIN1_EL1 field.
2021    pub const NTPMIN1_EL1_SHIFT: u32 = 26;
2022    /// Offset of the nTPMIN0_EL1 field.
2023    pub const NTPMIN0_EL1_SHIFT: u32 = 27;
2024    /// Offset of the nTPMIN1_EL0 field.
2025    pub const NTPMIN1_EL0_SHIFT: u32 = 28;
2026    /// Offset of the nTPMIN0_EL0 field.
2027    pub const NTPMIN0_EL0_SHIFT: u32 = 29;
2028    /// Offset of the nAFGDTn_EL1 field.
2029    pub const NAFGDTN_EL1_SHIFT: u32 = 31;
2030    /// Mask for the nAFGDTn_EL1 field.
2031    pub const NAFGDTN_EL1_MASK: u64 = 0b11;
2032    /// Offset of the TFSR_EL1 field.
2033    pub const TFSR_EL1_SHIFT: u32 = 33;
2034    /// Offset of the RGSR_EL1 field.
2035    pub const RGSR_EL1_SHIFT: u32 = 34;
2036    /// Offset of the GCR_EL1 field.
2037    pub const GCR_EL1_SHIFT: u32 = 35;
2038    /// Offset of the nTPIDR3_EL0 field.
2039    pub const NTPIDR3_EL0_SHIFT: u32 = 36;
2040    /// Offset of the nTPIDR3_EL1 field.
2041    pub const NTPIDR3_EL1_SHIFT: u32 = 37;
2042
2043    /// Returns the value of the `nFGDTn_EL1` field.
2044    pub const fn nfgdtn_el1(self) -> u8 {
2045        ((self.bits() >> Self::NFGDTN_EL1_SHIFT) & 0b11) as u8
2046    }
2047
2048    /// Returns the value of the `nAFGDTn_EL1` field.
2049    pub const fn nafgdtn_el1(self) -> u8 {
2050        ((self.bits() >> Self::NAFGDTN_EL1_SHIFT) & 0b11) as u8
2051    }
2052}
2053
2054#[cfg(feature = "el2")]
2055bitflags! {
2056    /// `HFGWTR_EL2` system register value.
2057    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
2058    #[repr(transparent)]
2059    pub struct HfgwtrEl2: u64 {
2060        /// `AFSR0_EL1` bit.
2061        const AFSR0_EL1 = 1 << 0;
2062        /// `AFSR1_EL1` bit.
2063        const AFSR1_EL1 = 1 << 1;
2064        /// `AMAIR_EL1` bit.
2065        const AMAIR_EL1 = 1 << 3;
2066        /// `APDAKey` bit.
2067        const APDAKEY = 1 << 4;
2068        /// `APDBKey` bit.
2069        const APDBKEY = 1 << 5;
2070        /// `APGAKey` bit.
2071        const APGAKEY = 1 << 6;
2072        /// `APIAKey` bit.
2073        const APIAKEY = 1 << 7;
2074        /// `APIBKey` bit.
2075        const APIBKEY = 1 << 8;
2076        /// `CONTEXTIDR_EL1` bit.
2077        const CONTEXTIDR_EL1 = 1 << 11;
2078        /// `CPACR_EL1` bit.
2079        const CPACR_EL1 = 1 << 12;
2080        /// `CSSELR_EL1` bit.
2081        const CSSELR_EL1 = 1 << 13;
2082        /// `ESR_EL1` bit.
2083        const ESR_EL1 = 1 << 16;
2084        /// `FAR_EL1` bit.
2085        const FAR_EL1 = 1 << 17;
2086        /// `LORC_EL1` bit.
2087        const LORC_EL1 = 1 << 19;
2088        /// `LOREA_EL1` bit.
2089        const LOREA_EL1 = 1 << 20;
2090        /// `LORN_EL1` bit.
2091        const LORN_EL1 = 1 << 22;
2092        /// `LORSA_EL1` bit.
2093        const LORSA_EL1 = 1 << 23;
2094        /// `MAIR_EL1` bit.
2095        const MAIR_EL1 = 1 << 24;
2096        /// `PAR_EL1` bit.
2097        const PAR_EL1 = 1 << 27;
2098        /// `SCTLR_EL1` bit.
2099        const SCTLR_EL1 = 1 << 29;
2100        /// `SCXTNUM_EL1` bit.
2101        const SCXTNUM_EL1 = 1 << 30;
2102        /// `SCXTNUM_EL0` bit.
2103        const SCXTNUM_EL0 = 1 << 31;
2104        /// `TCR_EL1` bit.
2105        const TCR_EL1 = 1 << 32;
2106        /// `TPIDR_EL1` bit.
2107        const TPIDR_EL1 = 1 << 33;
2108        /// `TPIDRRO_EL0` bit.
2109        const TPIDRRO_EL0 = 1 << 34;
2110        /// `TPIDR_EL0` bit.
2111        const TPIDR_EL0 = 1 << 35;
2112        /// `TTBR0_EL1` bit.
2113        const TTBR0_EL1 = 1 << 36;
2114        /// `TTBR1_EL1` bit.
2115        const TTBR1_EL1 = 1 << 37;
2116        /// `VBAR_EL1` bit.
2117        const VBAR_EL1 = 1 << 38;
2118        /// `ICC_IGRPENn_EL1` bit.
2119        const ICC_IGRPENN_EL1 = 1 << 39;
2120        /// `ERRSELR_EL1` bit.
2121        const ERRSELR_EL1 = 1 << 41;
2122        /// `ERXCTLR_EL1` bit.
2123        const ERXCTLR_EL1 = 1 << 43;
2124        /// `ERXSTATUS_EL1` bit.
2125        const ERXSTATUS_EL1 = 1 << 44;
2126        /// `ERXMISCn_EL1` bit.
2127        const ERXMISCN_EL1 = 1 << 45;
2128        /// `ERXPFGCTL_EL1` bit.
2129        const ERXPFGCTL_EL1 = 1 << 47;
2130        /// `ERXPFGCDN_EL1` bit.
2131        const ERXPFGCDN_EL1 = 1 << 48;
2132        /// `ERXADDR_EL1` bit.
2133        const ERXADDR_EL1 = 1 << 49;
2134        /// `nACCDATA_EL1` bit.
2135        const NACCDATA_EL1 = 1 << 50;
2136        /// `nGCS_EL0` bit.
2137        const NGCS_EL0 = 1 << 52;
2138        /// `nGCS_EL1` bit.
2139        const NGCS_EL1 = 1 << 53;
2140        /// `nSMPRI_EL1` bit.
2141        const NSMPRI_EL1 = 1 << 54;
2142        /// `nTPIDR2_EL0` bit.
2143        const NTPIDR2_EL0 = 1 << 55;
2144        /// `nRCWMASK_EL1` bit.
2145        const NRCWMASK_EL1 = 1 << 56;
2146        /// `nPIRE0_EL1` bit.
2147        const NPIRE0_EL1 = 1 << 57;
2148        /// `nPIR_EL1` bit.
2149        const NPIR_EL1 = 1 << 58;
2150        /// `nPOR_EL0` bit.
2151        const NPOR_EL0 = 1 << 59;
2152        /// `nPOR_EL1` bit.
2153        const NPOR_EL1 = 1 << 60;
2154        /// `nS2POR_EL1` bit.
2155        const NS2POR_EL1 = 1 << 61;
2156        /// `nMAIR2_EL1` bit.
2157        const NMAIR2_EL1 = 1 << 62;
2158        /// `nAMAIR2_EL1` bit.
2159        const NAMAIR2_EL1 = 1 << 63;
2160    }
2161}
2162
2163#[cfg(feature = "el2")]
2164impl HfgwtrEl2 {
2165    /// Offset of the AFSR0_EL1 field.
2166    pub const AFSR0_EL1_SHIFT: u32 = 0;
2167    /// Offset of the AFSR1_EL1 field.
2168    pub const AFSR1_EL1_SHIFT: u32 = 1;
2169    /// Offset of the AMAIR_EL1 field.
2170    pub const AMAIR_EL1_SHIFT: u32 = 3;
2171    /// Offset of the APDAKey field.
2172    pub const APDAKEY_SHIFT: u32 = 4;
2173    /// Offset of the APDBKey field.
2174    pub const APDBKEY_SHIFT: u32 = 5;
2175    /// Offset of the APGAKey field.
2176    pub const APGAKEY_SHIFT: u32 = 6;
2177    /// Offset of the APIAKey field.
2178    pub const APIAKEY_SHIFT: u32 = 7;
2179    /// Offset of the APIBKey field.
2180    pub const APIBKEY_SHIFT: u32 = 8;
2181    /// Offset of the CONTEXTIDR_EL1 field.
2182    pub const CONTEXTIDR_EL1_SHIFT: u32 = 11;
2183    /// Offset of the CPACR_EL1 field.
2184    pub const CPACR_EL1_SHIFT: u32 = 12;
2185    /// Offset of the CSSELR_EL1 field.
2186    pub const CSSELR_EL1_SHIFT: u32 = 13;
2187    /// Offset of the ESR_EL1 field.
2188    pub const ESR_EL1_SHIFT: u32 = 16;
2189    /// Offset of the FAR_EL1 field.
2190    pub const FAR_EL1_SHIFT: u32 = 17;
2191    /// Offset of the LORC_EL1 field.
2192    pub const LORC_EL1_SHIFT: u32 = 19;
2193    /// Offset of the LOREA_EL1 field.
2194    pub const LOREA_EL1_SHIFT: u32 = 20;
2195    /// Offset of the LORN_EL1 field.
2196    pub const LORN_EL1_SHIFT: u32 = 22;
2197    /// Offset of the LORSA_EL1 field.
2198    pub const LORSA_EL1_SHIFT: u32 = 23;
2199    /// Offset of the MAIR_EL1 field.
2200    pub const MAIR_EL1_SHIFT: u32 = 24;
2201    /// Offset of the PAR_EL1 field.
2202    pub const PAR_EL1_SHIFT: u32 = 27;
2203    /// Offset of the SCTLR_EL1 field.
2204    pub const SCTLR_EL1_SHIFT: u32 = 29;
2205    /// Offset of the SCXTNUM_EL1 field.
2206    pub const SCXTNUM_EL1_SHIFT: u32 = 30;
2207    /// Offset of the SCXTNUM_EL0 field.
2208    pub const SCXTNUM_EL0_SHIFT: u32 = 31;
2209    /// Offset of the TCR_EL1 field.
2210    pub const TCR_EL1_SHIFT: u32 = 32;
2211    /// Offset of the TPIDR_EL1 field.
2212    pub const TPIDR_EL1_SHIFT: u32 = 33;
2213    /// Offset of the TPIDRRO_EL0 field.
2214    pub const TPIDRRO_EL0_SHIFT: u32 = 34;
2215    /// Offset of the TPIDR_EL0 field.
2216    pub const TPIDR_EL0_SHIFT: u32 = 35;
2217    /// Offset of the TTBR0_EL1 field.
2218    pub const TTBR0_EL1_SHIFT: u32 = 36;
2219    /// Offset of the TTBR1_EL1 field.
2220    pub const TTBR1_EL1_SHIFT: u32 = 37;
2221    /// Offset of the VBAR_EL1 field.
2222    pub const VBAR_EL1_SHIFT: u32 = 38;
2223    /// Offset of the ICC_IGRPENn_EL1 field.
2224    pub const ICC_IGRPENN_EL1_SHIFT: u32 = 39;
2225    /// Offset of the ERRSELR_EL1 field.
2226    pub const ERRSELR_EL1_SHIFT: u32 = 41;
2227    /// Offset of the ERXCTLR_EL1 field.
2228    pub const ERXCTLR_EL1_SHIFT: u32 = 43;
2229    /// Offset of the ERXSTATUS_EL1 field.
2230    pub const ERXSTATUS_EL1_SHIFT: u32 = 44;
2231    /// Offset of the ERXMISCn_EL1 field.
2232    pub const ERXMISCN_EL1_SHIFT: u32 = 45;
2233    /// Offset of the ERXPFGCTL_EL1 field.
2234    pub const ERXPFGCTL_EL1_SHIFT: u32 = 47;
2235    /// Offset of the ERXPFGCDN_EL1 field.
2236    pub const ERXPFGCDN_EL1_SHIFT: u32 = 48;
2237    /// Offset of the ERXADDR_EL1 field.
2238    pub const ERXADDR_EL1_SHIFT: u32 = 49;
2239    /// Offset of the nACCDATA_EL1 field.
2240    pub const NACCDATA_EL1_SHIFT: u32 = 50;
2241    /// Offset of the nGCS_EL0 field.
2242    pub const NGCS_EL0_SHIFT: u32 = 52;
2243    /// Offset of the nGCS_EL1 field.
2244    pub const NGCS_EL1_SHIFT: u32 = 53;
2245    /// Offset of the nSMPRI_EL1 field.
2246    pub const NSMPRI_EL1_SHIFT: u32 = 54;
2247    /// Offset of the nTPIDR2_EL0 field.
2248    pub const NTPIDR2_EL0_SHIFT: u32 = 55;
2249    /// Offset of the nRCWMASK_EL1 field.
2250    pub const NRCWMASK_EL1_SHIFT: u32 = 56;
2251    /// Offset of the nPIRE0_EL1 field.
2252    pub const NPIRE0_EL1_SHIFT: u32 = 57;
2253    /// Offset of the nPIR_EL1 field.
2254    pub const NPIR_EL1_SHIFT: u32 = 58;
2255    /// Offset of the nPOR_EL0 field.
2256    pub const NPOR_EL0_SHIFT: u32 = 59;
2257    /// Offset of the nPOR_EL1 field.
2258    pub const NPOR_EL1_SHIFT: u32 = 60;
2259    /// Offset of the nS2POR_EL1 field.
2260    pub const NS2POR_EL1_SHIFT: u32 = 61;
2261    /// Offset of the nMAIR2_EL1 field.
2262    pub const NMAIR2_EL1_SHIFT: u32 = 62;
2263    /// Offset of the nAMAIR2_EL1 field.
2264    pub const NAMAIR2_EL1_SHIFT: u32 = 63;
2265}
2266
2267#[cfg(feature = "el2")]
2268bitflags! {
2269    /// `HPFAR_EL2` system register value.
2270    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
2271    #[repr(transparent)]
2272    pub struct HpfarEl2: u64 {
2273        /// `NS` bit.
2274        const NS = 1 << 63;
2275    }
2276}
2277
2278#[cfg(feature = "el2")]
2279impl HpfarEl2 {
2280    /// Offset of the FIPA field.
2281    pub const FIPA_SHIFT: u32 = 4;
2282    /// Mask for the FIPA field.
2283    pub const FIPA_MASK: u64 = 0b11111111111111111111111111111111111111111111;
2284    /// Offset of the NS field.
2285    pub const NS_SHIFT: u32 = 63;
2286
2287    /// Returns the value of the `FIPA` field.
2288    pub const fn fipa(self) -> u64 {
2289        ((self.bits() >> Self::FIPA_SHIFT) & 0b11111111111111111111111111111111111111111111) as u64
2290    }
2291}
2292
2293#[cfg(feature = "el1")]
2294bitflags! {
2295    /// `ICC_SRE_EL1` system register value.
2296    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
2297    #[repr(transparent)]
2298    pub struct IccSreEl1: u64 {
2299        /// Enable the system register interface.
2300        const SRE = 1 << 0;
2301        /// Disable FIQ bypass.
2302        const DFB = 1 << 1;
2303        /// Disable IRQ bypass.
2304        const DIB = 1 << 2;
2305    }
2306}
2307
2308#[cfg(feature = "el1")]
2309impl IccSreEl1 {
2310    /// Offset of the SRE field.
2311    pub const SRE_SHIFT: u32 = 0;
2312    /// Offset of the DFB field.
2313    pub const DFB_SHIFT: u32 = 1;
2314    /// Offset of the DIB field.
2315    pub const DIB_SHIFT: u32 = 2;
2316}
2317
2318#[cfg(feature = "el2")]
2319bitflags! {
2320    /// `ICC_SRE_EL2` system register value.
2321    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
2322    #[repr(transparent)]
2323    pub struct IccSreEl2: u64 {
2324        /// Enable the system register interface.
2325        const SRE = 1 << 0;
2326        /// Disable FIQ bypass.
2327        const DFB = 1 << 1;
2328        /// Disable IRQ bypass.
2329        const DIB = 1 << 2;
2330        /// Enable lower exception level access.
2331        const ENABLE = 1 << 3;
2332    }
2333}
2334
2335#[cfg(feature = "el2")]
2336impl IccSreEl2 {
2337    /// Offset of the SRE field.
2338    pub const SRE_SHIFT: u32 = 0;
2339    /// Offset of the DFB field.
2340    pub const DFB_SHIFT: u32 = 1;
2341    /// Offset of the DIB field.
2342    pub const DIB_SHIFT: u32 = 2;
2343    /// Offset of the Enable field.
2344    pub const ENABLE_SHIFT: u32 = 3;
2345}
2346
2347#[cfg(feature = "el3")]
2348bitflags! {
2349    /// `ICC_SRE_EL3` system register value.
2350    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
2351    #[repr(transparent)]
2352    pub struct IccSreEl3: u64 {
2353        /// Enable the system register interface.
2354        const SRE = 1 << 0;
2355        /// Disable FIQ bypass.
2356        const DFB = 1 << 1;
2357        /// Disable IRQ bypass.
2358        const DIB = 1 << 2;
2359        /// Enable lower exception level access.
2360        const ENABLE = 1 << 3;
2361    }
2362}
2363
2364#[cfg(feature = "el3")]
2365impl IccSreEl3 {
2366    /// Offset of the SRE field.
2367    pub const SRE_SHIFT: u32 = 0;
2368    /// Offset of the DFB field.
2369    pub const DFB_SHIFT: u32 = 1;
2370    /// Offset of the DIB field.
2371    pub const DIB_SHIFT: u32 = 2;
2372    /// Offset of the Enable field.
2373    pub const ENABLE_SHIFT: u32 = 3;
2374}
2375
2376#[cfg(feature = "el2")]
2377bitflags! {
2378    /// `ICH_HCR_EL2` system register value.
2379    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
2380    #[repr(transparent)]
2381    pub struct IchHcrEl2: u64 {
2382        /// `En` bit.
2383        const EN = 1 << 0;
2384        /// `UIE` bit.
2385        const UIE = 1 << 1;
2386        /// `LRENPIE` bit.
2387        const LRENPIE = 1 << 2;
2388        /// `NPIE` bit.
2389        const NPIE = 1 << 3;
2390        /// `VGrp0EIE` bit.
2391        const VGRP0EIE = 1 << 4;
2392        /// `VGrp0DIE` bit.
2393        const VGRP0DIE = 1 << 5;
2394        /// `VGrp1EIE` bit.
2395        const VGRP1EIE = 1 << 6;
2396        /// `VGrp1DIE` bit.
2397        const VGRP1DIE = 1 << 7;
2398        /// `vSGIEOICount` bit.
2399        const VSGIEOICOUNT = 1 << 8;
2400        /// `TC` bit.
2401        const TC = 1 << 10;
2402        /// `TALL0` bit.
2403        const TALL0 = 1 << 11;
2404        /// `TALL1` bit.
2405        const TALL1 = 1 << 12;
2406        /// `TSEI` bit.
2407        const TSEI = 1 << 13;
2408        /// `TDIR` bit.
2409        const TDIR = 1 << 14;
2410        /// `DVIM` bit.
2411        const DVIM = 1 << 15;
2412    }
2413}
2414
2415#[cfg(feature = "el2")]
2416impl IchHcrEl2 {
2417    /// Offset of the En field.
2418    pub const EN_SHIFT: u32 = 0;
2419    /// Offset of the UIE field.
2420    pub const UIE_SHIFT: u32 = 1;
2421    /// Offset of the LRENPIE field.
2422    pub const LRENPIE_SHIFT: u32 = 2;
2423    /// Offset of the NPIE field.
2424    pub const NPIE_SHIFT: u32 = 3;
2425    /// Offset of the VGrp0EIE field.
2426    pub const VGRP0EIE_SHIFT: u32 = 4;
2427    /// Offset of the VGrp0DIE field.
2428    pub const VGRP0DIE_SHIFT: u32 = 5;
2429    /// Offset of the VGrp1EIE field.
2430    pub const VGRP1EIE_SHIFT: u32 = 6;
2431    /// Offset of the VGrp1DIE field.
2432    pub const VGRP1DIE_SHIFT: u32 = 7;
2433    /// Offset of the vSGIEOICount field.
2434    pub const VSGIEOICOUNT_SHIFT: u32 = 8;
2435    /// Offset of the TC field.
2436    pub const TC_SHIFT: u32 = 10;
2437    /// Offset of the TALL0 field.
2438    pub const TALL0_SHIFT: u32 = 11;
2439    /// Offset of the TALL1 field.
2440    pub const TALL1_SHIFT: u32 = 12;
2441    /// Offset of the TSEI field.
2442    pub const TSEI_SHIFT: u32 = 13;
2443    /// Offset of the TDIR field.
2444    pub const TDIR_SHIFT: u32 = 14;
2445    /// Offset of the DVIM field.
2446    pub const DVIM_SHIFT: u32 = 15;
2447    /// Offset of the EOIcount field.
2448    pub const EOICOUNT_SHIFT: u32 = 27;
2449    /// Mask for the EOIcount field.
2450    pub const EOICOUNT_MASK: u64 = 0b11111;
2451
2452    /// Returns the value of the `EOIcount` field.
2453    pub const fn eoicount(self) -> u8 {
2454        ((self.bits() >> Self::EOICOUNT_SHIFT) & 0b11111) as u8
2455    }
2456}
2457
2458#[cfg(feature = "el2")]
2459bitflags! {
2460    /// `ICH_VMCR_EL2` system register value.
2461    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
2462    #[repr(transparent)]
2463    pub struct IchVmcrEl2: u64 {
2464        /// `EN` bit.
2465        const EN = 1 << 0;
2466        /// `VENG0` bit.
2467        const VENG0 = 1 << 0;
2468        /// `VENG1` bit.
2469        const VENG1 = 1 << 1;
2470        /// `VAckCtl` bit.
2471        const VACKCTL = 1 << 2;
2472        /// `VFIQEn` bit.
2473        const VFIQEN = 1 << 3;
2474        /// `VCBPR` bit.
2475        const VCBPR = 1 << 4;
2476        /// `VEOIM` bit.
2477        const VEOIM = 1 << 9;
2478    }
2479}
2480
2481#[cfg(feature = "el2")]
2482impl IchVmcrEl2 {
2483    /// Offset of the EN field.
2484    pub const EN_SHIFT: u32 = 0;
2485    /// Offset of the VENG0 field.
2486    pub const VENG0_SHIFT: u32 = 0;
2487    /// Offset of the VENG1 field.
2488    pub const VENG1_SHIFT: u32 = 1;
2489    /// Offset of the VAckCtl field.
2490    pub const VACKCTL_SHIFT: u32 = 2;
2491    /// Offset of the VFIQEn field.
2492    pub const VFIQEN_SHIFT: u32 = 3;
2493    /// Offset of the VCBPR field.
2494    pub const VCBPR_SHIFT: u32 = 4;
2495    /// Offset of the VEOIM field.
2496    pub const VEOIM_SHIFT: u32 = 9;
2497    /// Offset of the VBPR1 field.
2498    pub const VBPR1_SHIFT: u32 = 18;
2499    /// Mask for the VBPR1 field.
2500    pub const VBPR1_MASK: u64 = 0b111;
2501    /// Offset of the VBPR0 field.
2502    pub const VBPR0_SHIFT: u32 = 21;
2503    /// Mask for the VBPR0 field.
2504    pub const VBPR0_MASK: u64 = 0b111;
2505
2506    /// Returns the value of the `VBPR1` field.
2507    pub const fn vbpr1(self) -> u8 {
2508        ((self.bits() >> Self::VBPR1_SHIFT) & 0b111) as u8
2509    }
2510
2511    /// Returns the value of the `VBPR0` field.
2512    pub const fn vbpr0(self) -> u8 {
2513        ((self.bits() >> Self::VBPR0_SHIFT) & 0b111) as u8
2514    }
2515}
2516
2517#[cfg(feature = "el1")]
2518bitflags! {
2519    /// `ID_AA64DFR0_EL1` system register value.
2520    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
2521    #[repr(transparent)]
2522    pub struct IdAa64dfr0El1: u64 {
2523    }
2524}
2525
2526#[cfg(feature = "el1")]
2527impl IdAa64dfr0El1 {
2528    /// Offset of the DebugVer field.
2529    pub const DEBUGVER_SHIFT: u32 = 0;
2530    /// Mask for the DebugVer field.
2531    pub const DEBUGVER_MASK: u64 = 0b1111;
2532    /// Offset of the TraceVer field.
2533    pub const TRACEVER_SHIFT: u32 = 4;
2534    /// Mask for the TraceVer field.
2535    pub const TRACEVER_MASK: u64 = 0b1111;
2536    /// Offset of the PMUVer field.
2537    pub const PMUVER_SHIFT: u32 = 8;
2538    /// Mask for the PMUVer field.
2539    pub const PMUVER_MASK: u64 = 0b1111;
2540    /// Offset of the BRPs field.
2541    pub const BRPS_SHIFT: u32 = 12;
2542    /// Mask for the BRPs field.
2543    pub const BRPS_MASK: u64 = 0b1111;
2544    /// Offset of the PMSS field.
2545    pub const PMSS_SHIFT: u32 = 16;
2546    /// Mask for the PMSS field.
2547    pub const PMSS_MASK: u64 = 0b1111;
2548    /// Offset of the WRPs field.
2549    pub const WRPS_SHIFT: u32 = 20;
2550    /// Mask for the WRPs field.
2551    pub const WRPS_MASK: u64 = 0b1111;
2552    /// Offset of the SEBEP field.
2553    pub const SEBEP_SHIFT: u32 = 24;
2554    /// Mask for the SEBEP field.
2555    pub const SEBEP_MASK: u64 = 0b1111;
2556    /// Offset of the CTX_CMPs field.
2557    pub const CTX_CMPS_SHIFT: u32 = 28;
2558    /// Mask for the CTX_CMPs field.
2559    pub const CTX_CMPS_MASK: u64 = 0b1111;
2560    /// Offset of the PMSVer field.
2561    pub const PMSVER_SHIFT: u32 = 32;
2562    /// Mask for the PMSVer field.
2563    pub const PMSVER_MASK: u64 = 0b1111;
2564    /// Offset of the DoubleLock field.
2565    pub const DOUBLELOCK_SHIFT: u32 = 36;
2566    /// Mask for the DoubleLock field.
2567    pub const DOUBLELOCK_MASK: u64 = 0b1111;
2568    /// Offset of the TraceFilt field.
2569    pub const TRACEFILT_SHIFT: u32 = 40;
2570    /// Mask for the TraceFilt field.
2571    pub const TRACEFILT_MASK: u64 = 0b1111;
2572    /// Offset of the TraceBuffer field.
2573    pub const TRACEBUFFER_SHIFT: u32 = 44;
2574    /// Mask for the TraceBuffer field.
2575    pub const TRACEBUFFER_MASK: u64 = 0b1111;
2576    /// Offset of the MTPMU field.
2577    pub const MTPMU_SHIFT: u32 = 48;
2578    /// Mask for the MTPMU field.
2579    pub const MTPMU_MASK: u64 = 0b1111;
2580    /// Offset of the BRBE field.
2581    pub const BRBE_SHIFT: u32 = 52;
2582    /// Mask for the BRBE field.
2583    pub const BRBE_MASK: u64 = 0b1111;
2584    /// Offset of the ExtTrcBuff field.
2585    pub const EXTTRCBUFF_SHIFT: u32 = 56;
2586    /// Mask for the ExtTrcBuff field.
2587    pub const EXTTRCBUFF_MASK: u64 = 0b1111;
2588    /// Offset of the HPMN0 field.
2589    pub const HPMN0_SHIFT: u32 = 60;
2590    /// Mask for the HPMN0 field.
2591    pub const HPMN0_MASK: u64 = 0b1111;
2592
2593    /// Returns the value of the `DebugVer` field.
2594    pub const fn debugver(self) -> u8 {
2595        ((self.bits() >> Self::DEBUGVER_SHIFT) & 0b1111) as u8
2596    }
2597
2598    /// Returns the value of the `TraceVer` field.
2599    pub const fn tracever(self) -> u8 {
2600        ((self.bits() >> Self::TRACEVER_SHIFT) & 0b1111) as u8
2601    }
2602
2603    /// Returns the value of the `PMUVer` field.
2604    pub const fn pmuver(self) -> u8 {
2605        ((self.bits() >> Self::PMUVER_SHIFT) & 0b1111) as u8
2606    }
2607
2608    /// Returns the value of the `BRPs` field.
2609    pub const fn brps(self) -> u8 {
2610        ((self.bits() >> Self::BRPS_SHIFT) & 0b1111) as u8
2611    }
2612
2613    /// Returns the value of the `PMSS` field.
2614    pub const fn pmss(self) -> u8 {
2615        ((self.bits() >> Self::PMSS_SHIFT) & 0b1111) as u8
2616    }
2617
2618    /// Returns the value of the `WRPs` field.
2619    pub const fn wrps(self) -> u8 {
2620        ((self.bits() >> Self::WRPS_SHIFT) & 0b1111) as u8
2621    }
2622
2623    /// Returns the value of the `SEBEP` field.
2624    pub const fn sebep(self) -> u8 {
2625        ((self.bits() >> Self::SEBEP_SHIFT) & 0b1111) as u8
2626    }
2627
2628    /// Returns the value of the `CTX_CMPs` field.
2629    pub const fn ctx_cmps(self) -> u8 {
2630        ((self.bits() >> Self::CTX_CMPS_SHIFT) & 0b1111) as u8
2631    }
2632
2633    /// Returns the value of the `PMSVer` field.
2634    pub const fn pmsver(self) -> u8 {
2635        ((self.bits() >> Self::PMSVER_SHIFT) & 0b1111) as u8
2636    }
2637
2638    /// Returns the value of the `DoubleLock` field.
2639    pub const fn doublelock(self) -> u8 {
2640        ((self.bits() >> Self::DOUBLELOCK_SHIFT) & 0b1111) as u8
2641    }
2642
2643    /// Returns the value of the `TraceFilt` field.
2644    pub const fn tracefilt(self) -> u8 {
2645        ((self.bits() >> Self::TRACEFILT_SHIFT) & 0b1111) as u8
2646    }
2647
2648    /// Returns the value of the `TraceBuffer` field.
2649    pub const fn tracebuffer(self) -> u8 {
2650        ((self.bits() >> Self::TRACEBUFFER_SHIFT) & 0b1111) as u8
2651    }
2652
2653    /// Returns the value of the `MTPMU` field.
2654    pub const fn mtpmu(self) -> u8 {
2655        ((self.bits() >> Self::MTPMU_SHIFT) & 0b1111) as u8
2656    }
2657
2658    /// Returns the value of the `BRBE` field.
2659    pub const fn brbe(self) -> u8 {
2660        ((self.bits() >> Self::BRBE_SHIFT) & 0b1111) as u8
2661    }
2662
2663    /// Returns the value of the `ExtTrcBuff` field.
2664    pub const fn exttrcbuff(self) -> u8 {
2665        ((self.bits() >> Self::EXTTRCBUFF_SHIFT) & 0b1111) as u8
2666    }
2667
2668    /// Returns the value of the `HPMN0` field.
2669    pub const fn hpmn0(self) -> u8 {
2670        ((self.bits() >> Self::HPMN0_SHIFT) & 0b1111) as u8
2671    }
2672}
2673
2674#[cfg(feature = "el1")]
2675bitflags! {
2676    /// `ID_AA64DFR1_EL1` system register value.
2677    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
2678    #[repr(transparent)]
2679    pub struct IdAa64dfr1El1: u64 {
2680    }
2681}
2682
2683#[cfg(feature = "el1")]
2684impl IdAa64dfr1El1 {
2685    /// Offset of the SYSPMUID field.
2686    pub const SYSPMUID_SHIFT: u32 = 0;
2687    /// Mask for the SYSPMUID field.
2688    pub const SYSPMUID_MASK: u64 = 0b11111111;
2689    /// Offset of the BRPs field.
2690    pub const BRPS_SHIFT: u32 = 8;
2691    /// Mask for the BRPs field.
2692    pub const BRPS_MASK: u64 = 0b11111111;
2693    /// Offset of the WRPs field.
2694    pub const WRPS_SHIFT: u32 = 16;
2695    /// Mask for the WRPs field.
2696    pub const WRPS_MASK: u64 = 0b11111111;
2697    /// Offset of the CTX_CMPs field.
2698    pub const CTX_CMPS_SHIFT: u32 = 24;
2699    /// Mask for the CTX_CMPs field.
2700    pub const CTX_CMPS_MASK: u64 = 0b11111111;
2701    /// Offset of the SPMU field.
2702    pub const SPMU_SHIFT: u32 = 32;
2703    /// Mask for the SPMU field.
2704    pub const SPMU_MASK: u64 = 0b1111;
2705    /// Offset of the PMICNTR field.
2706    pub const PMICNTR_SHIFT: u32 = 36;
2707    /// Mask for the PMICNTR field.
2708    pub const PMICNTR_MASK: u64 = 0b1111;
2709    /// Offset of the ABLE field.
2710    pub const ABLE_SHIFT: u32 = 40;
2711    /// Mask for the ABLE field.
2712    pub const ABLE_MASK: u64 = 0b1111;
2713    /// Offset of the ITE field.
2714    pub const ITE_SHIFT: u32 = 44;
2715    /// Mask for the ITE field.
2716    pub const ITE_MASK: u64 = 0b1111;
2717    /// Offset of the EBEP field.
2718    pub const EBEP_SHIFT: u32 = 48;
2719    /// Mask for the EBEP field.
2720    pub const EBEP_MASK: u64 = 0b1111;
2721    /// Offset of the DPFZS field.
2722    pub const DPFZS_SHIFT: u32 = 52;
2723    /// Mask for the DPFZS field.
2724    pub const DPFZS_MASK: u64 = 0b1111;
2725    /// Offset of the ABL_CMPs field.
2726    pub const ABL_CMPS_SHIFT: u32 = 56;
2727    /// Mask for the ABL_CMPs field.
2728    pub const ABL_CMPS_MASK: u64 = 0b11111111;
2729
2730    /// Returns the value of the `SYSPMUID` field.
2731    pub const fn syspmuid(self) -> u8 {
2732        ((self.bits() >> Self::SYSPMUID_SHIFT) & 0b11111111) as u8
2733    }
2734
2735    /// Returns the value of the `BRPs` field.
2736    pub const fn brps(self) -> u8 {
2737        ((self.bits() >> Self::BRPS_SHIFT) & 0b11111111) as u8
2738    }
2739
2740    /// Returns the value of the `WRPs` field.
2741    pub const fn wrps(self) -> u8 {
2742        ((self.bits() >> Self::WRPS_SHIFT) & 0b11111111) as u8
2743    }
2744
2745    /// Returns the value of the `CTX_CMPs` field.
2746    pub const fn ctx_cmps(self) -> u8 {
2747        ((self.bits() >> Self::CTX_CMPS_SHIFT) & 0b11111111) as u8
2748    }
2749
2750    /// Returns the value of the `SPMU` field.
2751    pub const fn spmu(self) -> u8 {
2752        ((self.bits() >> Self::SPMU_SHIFT) & 0b1111) as u8
2753    }
2754
2755    /// Returns the value of the `PMICNTR` field.
2756    pub const fn pmicntr(self) -> u8 {
2757        ((self.bits() >> Self::PMICNTR_SHIFT) & 0b1111) as u8
2758    }
2759
2760    /// Returns the value of the `ABLE` field.
2761    pub const fn able(self) -> u8 {
2762        ((self.bits() >> Self::ABLE_SHIFT) & 0b1111) as u8
2763    }
2764
2765    /// Returns the value of the `ITE` field.
2766    pub const fn ite(self) -> u8 {
2767        ((self.bits() >> Self::ITE_SHIFT) & 0b1111) as u8
2768    }
2769
2770    /// Returns the value of the `EBEP` field.
2771    pub const fn ebep(self) -> u8 {
2772        ((self.bits() >> Self::EBEP_SHIFT) & 0b1111) as u8
2773    }
2774
2775    /// Returns the value of the `DPFZS` field.
2776    pub const fn dpfzs(self) -> u8 {
2777        ((self.bits() >> Self::DPFZS_SHIFT) & 0b1111) as u8
2778    }
2779
2780    /// Returns the value of the `ABL_CMPs` field.
2781    pub const fn abl_cmps(self) -> u8 {
2782        ((self.bits() >> Self::ABL_CMPS_SHIFT) & 0b11111111) as u8
2783    }
2784}
2785
2786#[cfg(feature = "el1")]
2787bitflags! {
2788    /// `ID_AA64MMFR0_EL1` system register value.
2789    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
2790    #[repr(transparent)]
2791    pub struct IdAa64mmfr0El1: u64 {
2792    }
2793}
2794
2795#[cfg(feature = "el1")]
2796impl IdAa64mmfr0El1 {
2797    /// Offset of the PARange field.
2798    pub const PARANGE_SHIFT: u32 = 0;
2799    /// Mask for the PARange field.
2800    pub const PARANGE_MASK: u64 = 0b1111;
2801    /// Offset of the ASIDBits field.
2802    pub const ASIDBITS_SHIFT: u32 = 4;
2803    /// Mask for the ASIDBits field.
2804    pub const ASIDBITS_MASK: u64 = 0b1111;
2805    /// Offset of the BigEnd field.
2806    pub const BIGEND_SHIFT: u32 = 8;
2807    /// Mask for the BigEnd field.
2808    pub const BIGEND_MASK: u64 = 0b1111;
2809    /// Offset of the SNSMem field.
2810    pub const SNSMEM_SHIFT: u32 = 12;
2811    /// Mask for the SNSMem field.
2812    pub const SNSMEM_MASK: u64 = 0b1111;
2813    /// Offset of the BigEndEL0 field.
2814    pub const BIGENDEL0_SHIFT: u32 = 16;
2815    /// Mask for the BigEndEL0 field.
2816    pub const BIGENDEL0_MASK: u64 = 0b1111;
2817    /// Offset of the TGran16 field.
2818    pub const TGRAN16_SHIFT: u32 = 20;
2819    /// Mask for the TGran16 field.
2820    pub const TGRAN16_MASK: u64 = 0b1111;
2821    /// Offset of the TGran64 field.
2822    pub const TGRAN64_SHIFT: u32 = 24;
2823    /// Mask for the TGran64 field.
2824    pub const TGRAN64_MASK: u64 = 0b1111;
2825    /// Offset of the TGran4 field.
2826    pub const TGRAN4_SHIFT: u32 = 28;
2827    /// Mask for the TGran4 field.
2828    pub const TGRAN4_MASK: u64 = 0b1111;
2829    /// Offset of the TGran16_2 field.
2830    pub const TGRAN16_2_SHIFT: u32 = 32;
2831    /// Mask for the TGran16_2 field.
2832    pub const TGRAN16_2_MASK: u64 = 0b1111;
2833    /// Offset of the TGran64_2 field.
2834    pub const TGRAN64_2_SHIFT: u32 = 36;
2835    /// Mask for the TGran64_2 field.
2836    pub const TGRAN64_2_MASK: u64 = 0b1111;
2837    /// Offset of the TGran4_2 field.
2838    pub const TGRAN4_2_SHIFT: u32 = 40;
2839    /// Mask for the TGran4_2 field.
2840    pub const TGRAN4_2_MASK: u64 = 0b1111;
2841    /// Offset of the ExS field.
2842    pub const EXS_SHIFT: u32 = 44;
2843    /// Mask for the ExS field.
2844    pub const EXS_MASK: u64 = 0b1111;
2845    /// Offset of the FGT field.
2846    pub const FGT_SHIFT: u32 = 56;
2847    /// Mask for the FGT field.
2848    pub const FGT_MASK: u64 = 0b1111;
2849    /// Offset of the ECV field.
2850    pub const ECV_SHIFT: u32 = 60;
2851    /// Mask for the ECV field.
2852    pub const ECV_MASK: u64 = 0b1111;
2853
2854    /// Returns the value of the `PARange` field.
2855    pub const fn parange(self) -> u8 {
2856        ((self.bits() >> Self::PARANGE_SHIFT) & 0b1111) as u8
2857    }
2858
2859    /// Returns the value of the `ASIDBits` field.
2860    pub const fn asidbits(self) -> u8 {
2861        ((self.bits() >> Self::ASIDBITS_SHIFT) & 0b1111) as u8
2862    }
2863
2864    /// Returns the value of the `BigEnd` field.
2865    pub const fn bigend(self) -> u8 {
2866        ((self.bits() >> Self::BIGEND_SHIFT) & 0b1111) as u8
2867    }
2868
2869    /// Returns the value of the `SNSMem` field.
2870    pub const fn snsmem(self) -> u8 {
2871        ((self.bits() >> Self::SNSMEM_SHIFT) & 0b1111) as u8
2872    }
2873
2874    /// Returns the value of the `BigEndEL0` field.
2875    pub const fn bigendel0(self) -> u8 {
2876        ((self.bits() >> Self::BIGENDEL0_SHIFT) & 0b1111) as u8
2877    }
2878
2879    /// Returns the value of the `TGran16` field.
2880    pub const fn tgran16(self) -> u8 {
2881        ((self.bits() >> Self::TGRAN16_SHIFT) & 0b1111) as u8
2882    }
2883
2884    /// Returns the value of the `TGran64` field.
2885    pub const fn tgran64(self) -> u8 {
2886        ((self.bits() >> Self::TGRAN64_SHIFT) & 0b1111) as u8
2887    }
2888
2889    /// Returns the value of the `TGran4` field.
2890    pub const fn tgran4(self) -> u8 {
2891        ((self.bits() >> Self::TGRAN4_SHIFT) & 0b1111) as u8
2892    }
2893
2894    /// Returns the value of the `TGran16_2` field.
2895    pub const fn tgran16_2(self) -> u8 {
2896        ((self.bits() >> Self::TGRAN16_2_SHIFT) & 0b1111) as u8
2897    }
2898
2899    /// Returns the value of the `TGran64_2` field.
2900    pub const fn tgran64_2(self) -> u8 {
2901        ((self.bits() >> Self::TGRAN64_2_SHIFT) & 0b1111) as u8
2902    }
2903
2904    /// Returns the value of the `TGran4_2` field.
2905    pub const fn tgran4_2(self) -> u8 {
2906        ((self.bits() >> Self::TGRAN4_2_SHIFT) & 0b1111) as u8
2907    }
2908
2909    /// Returns the value of the `ExS` field.
2910    pub const fn exs(self) -> u8 {
2911        ((self.bits() >> Self::EXS_SHIFT) & 0b1111) as u8
2912    }
2913
2914    /// Returns the value of the `FGT` field.
2915    pub const fn fgt(self) -> u8 {
2916        ((self.bits() >> Self::FGT_SHIFT) & 0b1111) as u8
2917    }
2918
2919    /// Returns the value of the `ECV` field.
2920    pub const fn ecv(self) -> u8 {
2921        ((self.bits() >> Self::ECV_SHIFT) & 0b1111) as u8
2922    }
2923}
2924
2925#[cfg(feature = "el1")]
2926bitflags! {
2927    /// `ID_AA64MMFR1_EL1` system register value.
2928    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
2929    #[repr(transparent)]
2930    pub struct IdAa64mmfr1El1: u64 {
2931    }
2932}
2933
2934#[cfg(feature = "el1")]
2935impl IdAa64mmfr1El1 {
2936    /// Offset of the HAFDBS field.
2937    pub const HAFDBS_SHIFT: u32 = 0;
2938    /// Mask for the HAFDBS field.
2939    pub const HAFDBS_MASK: u64 = 0b1111;
2940    /// Offset of the VMIDBits field.
2941    pub const VMIDBITS_SHIFT: u32 = 4;
2942    /// Mask for the VMIDBits field.
2943    pub const VMIDBITS_MASK: u64 = 0b1111;
2944    /// Offset of the VH field.
2945    pub const VH_SHIFT: u32 = 8;
2946    /// Mask for the VH field.
2947    pub const VH_MASK: u64 = 0b1111;
2948    /// Offset of the HPDS field.
2949    pub const HPDS_SHIFT: u32 = 12;
2950    /// Mask for the HPDS field.
2951    pub const HPDS_MASK: u64 = 0b1111;
2952    /// Offset of the LO field.
2953    pub const LO_SHIFT: u32 = 16;
2954    /// Mask for the LO field.
2955    pub const LO_MASK: u64 = 0b1111;
2956    /// Offset of the PAN field.
2957    pub const PAN_SHIFT: u32 = 20;
2958    /// Mask for the PAN field.
2959    pub const PAN_MASK: u64 = 0b1111;
2960    /// Offset of the SpecSEI field.
2961    pub const SPECSEI_SHIFT: u32 = 24;
2962    /// Mask for the SpecSEI field.
2963    pub const SPECSEI_MASK: u64 = 0b1111;
2964    /// Offset of the XNX field.
2965    pub const XNX_SHIFT: u32 = 28;
2966    /// Mask for the XNX field.
2967    pub const XNX_MASK: u64 = 0b1111;
2968    /// Offset of the TWED field.
2969    pub const TWED_SHIFT: u32 = 32;
2970    /// Mask for the TWED field.
2971    pub const TWED_MASK: u64 = 0b1111;
2972    /// Offset of the ETS field.
2973    pub const ETS_SHIFT: u32 = 36;
2974    /// Mask for the ETS field.
2975    pub const ETS_MASK: u64 = 0b1111;
2976    /// Offset of the HCX field.
2977    pub const HCX_SHIFT: u32 = 40;
2978    /// Mask for the HCX field.
2979    pub const HCX_MASK: u64 = 0b1111;
2980    /// Offset of the AFP field.
2981    pub const AFP_SHIFT: u32 = 44;
2982    /// Mask for the AFP field.
2983    pub const AFP_MASK: u64 = 0b1111;
2984    /// Offset of the nTLBPA field.
2985    pub const NTLBPA_SHIFT: u32 = 48;
2986    /// Mask for the nTLBPA field.
2987    pub const NTLBPA_MASK: u64 = 0b1111;
2988    /// Offset of the TIDCP1 field.
2989    pub const TIDCP1_SHIFT: u32 = 52;
2990    /// Mask for the TIDCP1 field.
2991    pub const TIDCP1_MASK: u64 = 0b1111;
2992    /// Offset of the CMOW field.
2993    pub const CMOW_SHIFT: u32 = 56;
2994    /// Mask for the CMOW field.
2995    pub const CMOW_MASK: u64 = 0b1111;
2996    /// Offset of the ECBHB field.
2997    pub const ECBHB_SHIFT: u32 = 60;
2998    /// Mask for the ECBHB field.
2999    pub const ECBHB_MASK: u64 = 0b1111;
3000
3001    /// Returns the value of the `HAFDBS` field.
3002    pub const fn hafdbs(self) -> u8 {
3003        ((self.bits() >> Self::HAFDBS_SHIFT) & 0b1111) as u8
3004    }
3005
3006    /// Returns the value of the `VMIDBits` field.
3007    pub const fn vmidbits(self) -> u8 {
3008        ((self.bits() >> Self::VMIDBITS_SHIFT) & 0b1111) as u8
3009    }
3010
3011    /// Returns the value of the `VH` field.
3012    pub const fn vh(self) -> u8 {
3013        ((self.bits() >> Self::VH_SHIFT) & 0b1111) as u8
3014    }
3015
3016    /// Returns the value of the `HPDS` field.
3017    pub const fn hpds(self) -> u8 {
3018        ((self.bits() >> Self::HPDS_SHIFT) & 0b1111) as u8
3019    }
3020
3021    /// Returns the value of the `LO` field.
3022    pub const fn lo(self) -> u8 {
3023        ((self.bits() >> Self::LO_SHIFT) & 0b1111) as u8
3024    }
3025
3026    /// Returns the value of the `PAN` field.
3027    pub const fn pan(self) -> u8 {
3028        ((self.bits() >> Self::PAN_SHIFT) & 0b1111) as u8
3029    }
3030
3031    /// Returns the value of the `SpecSEI` field.
3032    pub const fn specsei(self) -> u8 {
3033        ((self.bits() >> Self::SPECSEI_SHIFT) & 0b1111) as u8
3034    }
3035
3036    /// Returns the value of the `XNX` field.
3037    pub const fn xnx(self) -> u8 {
3038        ((self.bits() >> Self::XNX_SHIFT) & 0b1111) as u8
3039    }
3040
3041    /// Returns the value of the `TWED` field.
3042    pub const fn twed(self) -> u8 {
3043        ((self.bits() >> Self::TWED_SHIFT) & 0b1111) as u8
3044    }
3045
3046    /// Returns the value of the `ETS` field.
3047    pub const fn ets(self) -> u8 {
3048        ((self.bits() >> Self::ETS_SHIFT) & 0b1111) as u8
3049    }
3050
3051    /// Returns the value of the `HCX` field.
3052    pub const fn hcx(self) -> u8 {
3053        ((self.bits() >> Self::HCX_SHIFT) & 0b1111) as u8
3054    }
3055
3056    /// Returns the value of the `AFP` field.
3057    pub const fn afp(self) -> u8 {
3058        ((self.bits() >> Self::AFP_SHIFT) & 0b1111) as u8
3059    }
3060
3061    /// Returns the value of the `nTLBPA` field.
3062    pub const fn ntlbpa(self) -> u8 {
3063        ((self.bits() >> Self::NTLBPA_SHIFT) & 0b1111) as u8
3064    }
3065
3066    /// Returns the value of the `TIDCP1` field.
3067    pub const fn tidcp1(self) -> u8 {
3068        ((self.bits() >> Self::TIDCP1_SHIFT) & 0b1111) as u8
3069    }
3070
3071    /// Returns the value of the `CMOW` field.
3072    pub const fn cmow(self) -> u8 {
3073        ((self.bits() >> Self::CMOW_SHIFT) & 0b1111) as u8
3074    }
3075
3076    /// Returns the value of the `ECBHB` field.
3077    pub const fn ecbhb(self) -> u8 {
3078        ((self.bits() >> Self::ECBHB_SHIFT) & 0b1111) as u8
3079    }
3080}
3081
3082#[cfg(feature = "el1")]
3083bitflags! {
3084    /// `ID_AA64MMFR2_EL1` system register value.
3085    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
3086    #[repr(transparent)]
3087    pub struct IdAa64mmfr2El1: u64 {
3088    }
3089}
3090
3091#[cfg(feature = "el1")]
3092impl IdAa64mmfr2El1 {
3093    /// Offset of the CnP field.
3094    pub const CNP_SHIFT: u32 = 0;
3095    /// Mask for the CnP field.
3096    pub const CNP_MASK: u64 = 0b1111;
3097    /// Offset of the UAO field.
3098    pub const UAO_SHIFT: u32 = 4;
3099    /// Mask for the UAO field.
3100    pub const UAO_MASK: u64 = 0b1111;
3101    /// Offset of the LSM field.
3102    pub const LSM_SHIFT: u32 = 8;
3103    /// Mask for the LSM field.
3104    pub const LSM_MASK: u64 = 0b1111;
3105    /// Offset of the IESB field.
3106    pub const IESB_SHIFT: u32 = 12;
3107    /// Mask for the IESB field.
3108    pub const IESB_MASK: u64 = 0b1111;
3109    /// Offset of the VARange field.
3110    pub const VARANGE_SHIFT: u32 = 16;
3111    /// Mask for the VARange field.
3112    pub const VARANGE_MASK: u64 = 0b1111;
3113    /// Offset of the CCIDX field.
3114    pub const CCIDX_SHIFT: u32 = 20;
3115    /// Mask for the CCIDX field.
3116    pub const CCIDX_MASK: u64 = 0b1111;
3117    /// Offset of the NV field.
3118    pub const NV_SHIFT: u32 = 24;
3119    /// Mask for the NV field.
3120    pub const NV_MASK: u64 = 0b1111;
3121    /// Offset of the ST field.
3122    pub const ST_SHIFT: u32 = 28;
3123    /// Mask for the ST field.
3124    pub const ST_MASK: u64 = 0b1111;
3125    /// Offset of the AT field.
3126    pub const AT_SHIFT: u32 = 32;
3127    /// Mask for the AT field.
3128    pub const AT_MASK: u64 = 0b1111;
3129    /// Offset of the IDS field.
3130    pub const IDS_SHIFT: u32 = 36;
3131    /// Mask for the IDS field.
3132    pub const IDS_MASK: u64 = 0b1111;
3133    /// Offset of the FWB field.
3134    pub const FWB_SHIFT: u32 = 40;
3135    /// Mask for the FWB field.
3136    pub const FWB_MASK: u64 = 0b1111;
3137    /// Offset of the TTL field.
3138    pub const TTL_SHIFT: u32 = 48;
3139    /// Mask for the TTL field.
3140    pub const TTL_MASK: u64 = 0b1111;
3141    /// Offset of the BBM field.
3142    pub const BBM_SHIFT: u32 = 52;
3143    /// Mask for the BBM field.
3144    pub const BBM_MASK: u64 = 0b1111;
3145    /// Offset of the EVT field.
3146    pub const EVT_SHIFT: u32 = 56;
3147    /// Mask for the EVT field.
3148    pub const EVT_MASK: u64 = 0b1111;
3149    /// Offset of the E0PD field.
3150    pub const E0PD_SHIFT: u32 = 60;
3151    /// Mask for the E0PD field.
3152    pub const E0PD_MASK: u64 = 0b1111;
3153
3154    /// Returns the value of the `CnP` field.
3155    pub const fn cnp(self) -> u8 {
3156        ((self.bits() >> Self::CNP_SHIFT) & 0b1111) as u8
3157    }
3158
3159    /// Returns the value of the `UAO` field.
3160    pub const fn uao(self) -> u8 {
3161        ((self.bits() >> Self::UAO_SHIFT) & 0b1111) as u8
3162    }
3163
3164    /// Returns the value of the `LSM` field.
3165    pub const fn lsm(self) -> u8 {
3166        ((self.bits() >> Self::LSM_SHIFT) & 0b1111) as u8
3167    }
3168
3169    /// Returns the value of the `IESB` field.
3170    pub const fn iesb(self) -> u8 {
3171        ((self.bits() >> Self::IESB_SHIFT) & 0b1111) as u8
3172    }
3173
3174    /// Returns the value of the `VARange` field.
3175    pub const fn varange(self) -> u8 {
3176        ((self.bits() >> Self::VARANGE_SHIFT) & 0b1111) as u8
3177    }
3178
3179    /// Returns the value of the `CCIDX` field.
3180    pub const fn ccidx(self) -> u8 {
3181        ((self.bits() >> Self::CCIDX_SHIFT) & 0b1111) as u8
3182    }
3183
3184    /// Returns the value of the `NV` field.
3185    pub const fn nv(self) -> u8 {
3186        ((self.bits() >> Self::NV_SHIFT) & 0b1111) as u8
3187    }
3188
3189    /// Returns the value of the `ST` field.
3190    pub const fn st(self) -> u8 {
3191        ((self.bits() >> Self::ST_SHIFT) & 0b1111) as u8
3192    }
3193
3194    /// Returns the value of the `AT` field.
3195    pub const fn at(self) -> u8 {
3196        ((self.bits() >> Self::AT_SHIFT) & 0b1111) as u8
3197    }
3198
3199    /// Returns the value of the `IDS` field.
3200    pub const fn ids(self) -> u8 {
3201        ((self.bits() >> Self::IDS_SHIFT) & 0b1111) as u8
3202    }
3203
3204    /// Returns the value of the `FWB` field.
3205    pub const fn fwb(self) -> u8 {
3206        ((self.bits() >> Self::FWB_SHIFT) & 0b1111) as u8
3207    }
3208
3209    /// Returns the value of the `TTL` field.
3210    pub const fn ttl(self) -> u8 {
3211        ((self.bits() >> Self::TTL_SHIFT) & 0b1111) as u8
3212    }
3213
3214    /// Returns the value of the `BBM` field.
3215    pub const fn bbm(self) -> u8 {
3216        ((self.bits() >> Self::BBM_SHIFT) & 0b1111) as u8
3217    }
3218
3219    /// Returns the value of the `EVT` field.
3220    pub const fn evt(self) -> u8 {
3221        ((self.bits() >> Self::EVT_SHIFT) & 0b1111) as u8
3222    }
3223
3224    /// Returns the value of the `E0PD` field.
3225    pub const fn e0pd(self) -> u8 {
3226        ((self.bits() >> Self::E0PD_SHIFT) & 0b1111) as u8
3227    }
3228}
3229
3230#[cfg(feature = "el1")]
3231bitflags! {
3232    /// `ID_AA64MMFR3_EL1` system register value.
3233    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
3234    #[repr(transparent)]
3235    pub struct IdAa64mmfr3El1: u64 {
3236    }
3237}
3238
3239#[cfg(feature = "el1")]
3240impl IdAa64mmfr3El1 {
3241    /// Offset of the TCRX field.
3242    pub const TCRX_SHIFT: u32 = 0;
3243    /// Mask for the TCRX field.
3244    pub const TCRX_MASK: u64 = 0b1111;
3245    /// Offset of the SCTLRX field.
3246    pub const SCTLRX_SHIFT: u32 = 4;
3247    /// Mask for the SCTLRX field.
3248    pub const SCTLRX_MASK: u64 = 0b1111;
3249    /// Offset of the S1PIE field.
3250    pub const S1PIE_SHIFT: u32 = 8;
3251    /// Mask for the S1PIE field.
3252    pub const S1PIE_MASK: u64 = 0b1111;
3253    /// Offset of the S2PIE field.
3254    pub const S2PIE_SHIFT: u32 = 12;
3255    /// Mask for the S2PIE field.
3256    pub const S2PIE_MASK: u64 = 0b1111;
3257    /// Offset of the S1POE field.
3258    pub const S1POE_SHIFT: u32 = 16;
3259    /// Mask for the S1POE field.
3260    pub const S1POE_MASK: u64 = 0b1111;
3261    /// Offset of the S2POE field.
3262    pub const S2POE_SHIFT: u32 = 20;
3263    /// Mask for the S2POE field.
3264    pub const S2POE_MASK: u64 = 0b1111;
3265    /// Offset of the AIE field.
3266    pub const AIE_SHIFT: u32 = 24;
3267    /// Mask for the AIE field.
3268    pub const AIE_MASK: u64 = 0b1111;
3269    /// Offset of the MEC field.
3270    pub const MEC_SHIFT: u32 = 28;
3271    /// Mask for the MEC field.
3272    pub const MEC_MASK: u64 = 0b1111;
3273    /// Offset of the D128 field.
3274    pub const D128_SHIFT: u32 = 32;
3275    /// Mask for the D128 field.
3276    pub const D128_MASK: u64 = 0b1111;
3277    /// Offset of the D128_2 field.
3278    pub const D128_2_SHIFT: u32 = 36;
3279    /// Mask for the D128_2 field.
3280    pub const D128_2_MASK: u64 = 0b1111;
3281    /// Offset of the SNERR field.
3282    pub const SNERR_SHIFT: u32 = 40;
3283    /// Mask for the SNERR field.
3284    pub const SNERR_MASK: u64 = 0b1111;
3285    /// Offset of the ANERR field.
3286    pub const ANERR_SHIFT: u32 = 44;
3287    /// Mask for the ANERR field.
3288    pub const ANERR_MASK: u64 = 0b1111;
3289    /// Offset of the SDERR field.
3290    pub const SDERR_SHIFT: u32 = 52;
3291    /// Mask for the SDERR field.
3292    pub const SDERR_MASK: u64 = 0b1111;
3293    /// Offset of the ADERR field.
3294    pub const ADERR_SHIFT: u32 = 56;
3295    /// Mask for the ADERR field.
3296    pub const ADERR_MASK: u64 = 0b1111;
3297    /// Offset of the Spec_FPACC field.
3298    pub const SPEC_FPACC_SHIFT: u32 = 60;
3299    /// Mask for the Spec_FPACC field.
3300    pub const SPEC_FPACC_MASK: u64 = 0b1111;
3301
3302    /// Returns the value of the `TCRX` field.
3303    pub const fn tcrx(self) -> u8 {
3304        ((self.bits() >> Self::TCRX_SHIFT) & 0b1111) as u8
3305    }
3306
3307    /// Returns the value of the `SCTLRX` field.
3308    pub const fn sctlrx(self) -> u8 {
3309        ((self.bits() >> Self::SCTLRX_SHIFT) & 0b1111) as u8
3310    }
3311
3312    /// Returns the value of the `S1PIE` field.
3313    pub const fn s1pie(self) -> u8 {
3314        ((self.bits() >> Self::S1PIE_SHIFT) & 0b1111) as u8
3315    }
3316
3317    /// Returns the value of the `S2PIE` field.
3318    pub const fn s2pie(self) -> u8 {
3319        ((self.bits() >> Self::S2PIE_SHIFT) & 0b1111) as u8
3320    }
3321
3322    /// Returns the value of the `S1POE` field.
3323    pub const fn s1poe(self) -> u8 {
3324        ((self.bits() >> Self::S1POE_SHIFT) & 0b1111) as u8
3325    }
3326
3327    /// Returns the value of the `S2POE` field.
3328    pub const fn s2poe(self) -> u8 {
3329        ((self.bits() >> Self::S2POE_SHIFT) & 0b1111) as u8
3330    }
3331
3332    /// Returns the value of the `AIE` field.
3333    pub const fn aie(self) -> u8 {
3334        ((self.bits() >> Self::AIE_SHIFT) & 0b1111) as u8
3335    }
3336
3337    /// Returns the value of the `MEC` field.
3338    pub const fn mec(self) -> u8 {
3339        ((self.bits() >> Self::MEC_SHIFT) & 0b1111) as u8
3340    }
3341
3342    /// Returns the value of the `D128` field.
3343    pub const fn d128(self) -> u8 {
3344        ((self.bits() >> Self::D128_SHIFT) & 0b1111) as u8
3345    }
3346
3347    /// Returns the value of the `D128_2` field.
3348    pub const fn d128_2(self) -> u8 {
3349        ((self.bits() >> Self::D128_2_SHIFT) & 0b1111) as u8
3350    }
3351
3352    /// Returns the value of the `SNERR` field.
3353    pub const fn snerr(self) -> u8 {
3354        ((self.bits() >> Self::SNERR_SHIFT) & 0b1111) as u8
3355    }
3356
3357    /// Returns the value of the `ANERR` field.
3358    pub const fn anerr(self) -> u8 {
3359        ((self.bits() >> Self::ANERR_SHIFT) & 0b1111) as u8
3360    }
3361
3362    /// Returns the value of the `SDERR` field.
3363    pub const fn sderr(self) -> u8 {
3364        ((self.bits() >> Self::SDERR_SHIFT) & 0b1111) as u8
3365    }
3366
3367    /// Returns the value of the `ADERR` field.
3368    pub const fn aderr(self) -> u8 {
3369        ((self.bits() >> Self::ADERR_SHIFT) & 0b1111) as u8
3370    }
3371
3372    /// Returns the value of the `Spec_FPACC` field.
3373    pub const fn spec_fpacc(self) -> u8 {
3374        ((self.bits() >> Self::SPEC_FPACC_SHIFT) & 0b1111) as u8
3375    }
3376}
3377
3378#[cfg(feature = "el1")]
3379bitflags! {
3380    /// `ID_AA64PFR0_EL1` system register value.
3381    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
3382    #[repr(transparent)]
3383    pub struct IdAa64pfr0El1: u64 {
3384    }
3385}
3386
3387#[cfg(feature = "el1")]
3388impl IdAa64pfr0El1 {
3389    /// Offset of the EL0 field.
3390    pub const EL0_SHIFT: u32 = 0;
3391    /// Mask for the EL0 field.
3392    pub const EL0_MASK: u64 = 0b1111;
3393    /// Offset of the EL1 field.
3394    pub const EL1_SHIFT: u32 = 4;
3395    /// Mask for the EL1 field.
3396    pub const EL1_MASK: u64 = 0b1111;
3397    /// Offset of the EL2 field.
3398    pub const EL2_SHIFT: u32 = 8;
3399    /// Mask for the EL2 field.
3400    pub const EL2_MASK: u64 = 0b1111;
3401    /// Offset of the EL3 field.
3402    pub const EL3_SHIFT: u32 = 12;
3403    /// Mask for the EL3 field.
3404    pub const EL3_MASK: u64 = 0b1111;
3405    /// Offset of the FP field.
3406    pub const FP_SHIFT: u32 = 16;
3407    /// Mask for the FP field.
3408    pub const FP_MASK: u64 = 0b1111;
3409    /// Offset of the AdvSIMD field.
3410    pub const ADVSIMD_SHIFT: u32 = 20;
3411    /// Mask for the AdvSIMD field.
3412    pub const ADVSIMD_MASK: u64 = 0b1111;
3413    /// Offset of the GIC field.
3414    pub const GIC_SHIFT: u32 = 24;
3415    /// Mask for the GIC field.
3416    pub const GIC_MASK: u64 = 0b1111;
3417    /// Offset of the RAS field.
3418    pub const RAS_SHIFT: u32 = 28;
3419    /// Mask for the RAS field.
3420    pub const RAS_MASK: u64 = 0b1111;
3421    /// Offset of the SVE field.
3422    pub const SVE_SHIFT: u32 = 32;
3423    /// Mask for the SVE field.
3424    pub const SVE_MASK: u64 = 0b1111;
3425    /// Offset of the SEL2 field.
3426    pub const SEL2_SHIFT: u32 = 36;
3427    /// Mask for the SEL2 field.
3428    pub const SEL2_MASK: u64 = 0b1111;
3429    /// Offset of the MPAM field.
3430    pub const MPAM_SHIFT: u32 = 40;
3431    /// Mask for the MPAM field.
3432    pub const MPAM_MASK: u64 = 0b1111;
3433    /// Offset of the AMU field.
3434    pub const AMU_SHIFT: u32 = 44;
3435    /// Mask for the AMU field.
3436    pub const AMU_MASK: u64 = 0b1111;
3437    /// Offset of the DIT field.
3438    pub const DIT_SHIFT: u32 = 48;
3439    /// Mask for the DIT field.
3440    pub const DIT_MASK: u64 = 0b1111;
3441    /// Offset of the RME field.
3442    pub const RME_SHIFT: u32 = 52;
3443    /// Mask for the RME field.
3444    pub const RME_MASK: u64 = 0b1111;
3445    /// Offset of the CSV2 field.
3446    pub const CSV2_SHIFT: u32 = 56;
3447    /// Mask for the CSV2 field.
3448    pub const CSV2_MASK: u64 = 0b1111;
3449    /// Offset of the CSV3 field.
3450    pub const CSV3_SHIFT: u32 = 60;
3451    /// Mask for the CSV3 field.
3452    pub const CSV3_MASK: u64 = 0b1111;
3453
3454    /// Returns the value of the `EL0` field.
3455    pub const fn el0(self) -> u8 {
3456        ((self.bits() >> Self::EL0_SHIFT) & 0b1111) as u8
3457    }
3458
3459    /// Returns the value of the `EL1` field.
3460    pub const fn el1(self) -> u8 {
3461        ((self.bits() >> Self::EL1_SHIFT) & 0b1111) as u8
3462    }
3463
3464    /// Returns the value of the `EL2` field.
3465    pub const fn el2(self) -> u8 {
3466        ((self.bits() >> Self::EL2_SHIFT) & 0b1111) as u8
3467    }
3468
3469    /// Returns the value of the `EL3` field.
3470    pub const fn el3(self) -> u8 {
3471        ((self.bits() >> Self::EL3_SHIFT) & 0b1111) as u8
3472    }
3473
3474    /// Returns the value of the `FP` field.
3475    pub const fn fp(self) -> u8 {
3476        ((self.bits() >> Self::FP_SHIFT) & 0b1111) as u8
3477    }
3478
3479    /// Returns the value of the `AdvSIMD` field.
3480    pub const fn advsimd(self) -> u8 {
3481        ((self.bits() >> Self::ADVSIMD_SHIFT) & 0b1111) as u8
3482    }
3483
3484    /// Returns the value of the `GIC` field.
3485    pub const fn gic(self) -> u8 {
3486        ((self.bits() >> Self::GIC_SHIFT) & 0b1111) as u8
3487    }
3488
3489    /// Returns the value of the `RAS` field.
3490    pub const fn ras(self) -> u8 {
3491        ((self.bits() >> Self::RAS_SHIFT) & 0b1111) as u8
3492    }
3493
3494    /// Returns the value of the `SVE` field.
3495    pub const fn sve(self) -> u8 {
3496        ((self.bits() >> Self::SVE_SHIFT) & 0b1111) as u8
3497    }
3498
3499    /// Returns the value of the `SEL2` field.
3500    pub const fn sel2(self) -> u8 {
3501        ((self.bits() >> Self::SEL2_SHIFT) & 0b1111) as u8
3502    }
3503
3504    /// Returns the value of the `MPAM` field.
3505    pub const fn mpam(self) -> u8 {
3506        ((self.bits() >> Self::MPAM_SHIFT) & 0b1111) as u8
3507    }
3508
3509    /// Returns the value of the `AMU` field.
3510    pub const fn amu(self) -> u8 {
3511        ((self.bits() >> Self::AMU_SHIFT) & 0b1111) as u8
3512    }
3513
3514    /// Returns the value of the `DIT` field.
3515    pub const fn dit(self) -> u8 {
3516        ((self.bits() >> Self::DIT_SHIFT) & 0b1111) as u8
3517    }
3518
3519    /// Returns the value of the `RME` field.
3520    pub const fn rme(self) -> u8 {
3521        ((self.bits() >> Self::RME_SHIFT) & 0b1111) as u8
3522    }
3523
3524    /// Returns the value of the `CSV2` field.
3525    pub const fn csv2(self) -> u8 {
3526        ((self.bits() >> Self::CSV2_SHIFT) & 0b1111) as u8
3527    }
3528
3529    /// Returns the value of the `CSV3` field.
3530    pub const fn csv3(self) -> u8 {
3531        ((self.bits() >> Self::CSV3_SHIFT) & 0b1111) as u8
3532    }
3533}
3534
3535#[cfg(feature = "el1")]
3536bitflags! {
3537    /// `ID_AA64PFR1_EL1` system register value.
3538    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
3539    #[repr(transparent)]
3540    pub struct IdAa64pfr1El1: u64 {
3541    }
3542}
3543
3544#[cfg(feature = "el1")]
3545impl IdAa64pfr1El1 {
3546    /// Offset of the BT field.
3547    pub const BT_SHIFT: u32 = 0;
3548    /// Mask for the BT field.
3549    pub const BT_MASK: u64 = 0b1111;
3550    /// Offset of the SSBS field.
3551    pub const SSBS_SHIFT: u32 = 4;
3552    /// Mask for the SSBS field.
3553    pub const SSBS_MASK: u64 = 0b1111;
3554    /// Offset of the MTE field.
3555    pub const MTE_SHIFT: u32 = 8;
3556    /// Mask for the MTE field.
3557    pub const MTE_MASK: u64 = 0b1111;
3558    /// Offset of the RAS_frac field.
3559    pub const RAS_FRAC_SHIFT: u32 = 12;
3560    /// Mask for the RAS_frac field.
3561    pub const RAS_FRAC_MASK: u64 = 0b1111;
3562    /// Offset of the MPAM_frac field.
3563    pub const MPAM_FRAC_SHIFT: u32 = 16;
3564    /// Mask for the MPAM_frac field.
3565    pub const MPAM_FRAC_MASK: u64 = 0b1111;
3566    /// Offset of the SME field.
3567    pub const SME_SHIFT: u32 = 24;
3568    /// Mask for the SME field.
3569    pub const SME_MASK: u64 = 0b1111;
3570    /// Offset of the RNDR_trap field.
3571    pub const RNDR_TRAP_SHIFT: u32 = 28;
3572    /// Mask for the RNDR_trap field.
3573    pub const RNDR_TRAP_MASK: u64 = 0b1111;
3574    /// Offset of the CSV2_frac field.
3575    pub const CSV2_FRAC_SHIFT: u32 = 32;
3576    /// Mask for the CSV2_frac field.
3577    pub const CSV2_FRAC_MASK: u64 = 0b1111;
3578    /// Offset of the NMI field.
3579    pub const NMI_SHIFT: u32 = 36;
3580    /// Mask for the NMI field.
3581    pub const NMI_MASK: u64 = 0b1111;
3582    /// Offset of the MTE_frac field.
3583    pub const MTE_FRAC_SHIFT: u32 = 40;
3584    /// Mask for the MTE_frac field.
3585    pub const MTE_FRAC_MASK: u64 = 0b1111;
3586    /// Offset of the GCS field.
3587    pub const GCS_SHIFT: u32 = 44;
3588    /// Mask for the GCS field.
3589    pub const GCS_MASK: u64 = 0b1111;
3590    /// Offset of the THE field.
3591    pub const THE_SHIFT: u32 = 48;
3592    /// Mask for the THE field.
3593    pub const THE_MASK: u64 = 0b1111;
3594    /// Offset of the MTEX field.
3595    pub const MTEX_SHIFT: u32 = 52;
3596    /// Mask for the MTEX field.
3597    pub const MTEX_MASK: u64 = 0b1111;
3598    /// Offset of the DF2 field.
3599    pub const DF2_SHIFT: u32 = 56;
3600    /// Mask for the DF2 field.
3601    pub const DF2_MASK: u64 = 0b1111;
3602    /// Offset of the PFAR field.
3603    pub const PFAR_SHIFT: u32 = 60;
3604    /// Mask for the PFAR field.
3605    pub const PFAR_MASK: u64 = 0b1111;
3606
3607    /// Returns the value of the `BT` field.
3608    pub const fn bt(self) -> u8 {
3609        ((self.bits() >> Self::BT_SHIFT) & 0b1111) as u8
3610    }
3611
3612    /// Returns the value of the `SSBS` field.
3613    pub const fn ssbs(self) -> u8 {
3614        ((self.bits() >> Self::SSBS_SHIFT) & 0b1111) as u8
3615    }
3616
3617    /// Returns the value of the `MTE` field.
3618    pub const fn mte(self) -> u8 {
3619        ((self.bits() >> Self::MTE_SHIFT) & 0b1111) as u8
3620    }
3621
3622    /// Returns the value of the `RAS_frac` field.
3623    pub const fn ras_frac(self) -> u8 {
3624        ((self.bits() >> Self::RAS_FRAC_SHIFT) & 0b1111) as u8
3625    }
3626
3627    /// Returns the value of the `MPAM_frac` field.
3628    pub const fn mpam_frac(self) -> u8 {
3629        ((self.bits() >> Self::MPAM_FRAC_SHIFT) & 0b1111) as u8
3630    }
3631
3632    /// Returns the value of the `SME` field.
3633    pub const fn sme(self) -> u8 {
3634        ((self.bits() >> Self::SME_SHIFT) & 0b1111) as u8
3635    }
3636
3637    /// Returns the value of the `RNDR_trap` field.
3638    pub const fn rndr_trap(self) -> u8 {
3639        ((self.bits() >> Self::RNDR_TRAP_SHIFT) & 0b1111) as u8
3640    }
3641
3642    /// Returns the value of the `CSV2_frac` field.
3643    pub const fn csv2_frac(self) -> u8 {
3644        ((self.bits() >> Self::CSV2_FRAC_SHIFT) & 0b1111) as u8
3645    }
3646
3647    /// Returns the value of the `NMI` field.
3648    pub const fn nmi(self) -> u8 {
3649        ((self.bits() >> Self::NMI_SHIFT) & 0b1111) as u8
3650    }
3651
3652    /// Returns the value of the `MTE_frac` field.
3653    pub const fn mte_frac(self) -> u8 {
3654        ((self.bits() >> Self::MTE_FRAC_SHIFT) & 0b1111) as u8
3655    }
3656
3657    /// Returns the value of the `GCS` field.
3658    pub const fn gcs(self) -> u8 {
3659        ((self.bits() >> Self::GCS_SHIFT) & 0b1111) as u8
3660    }
3661
3662    /// Returns the value of the `THE` field.
3663    pub const fn the(self) -> u8 {
3664        ((self.bits() >> Self::THE_SHIFT) & 0b1111) as u8
3665    }
3666
3667    /// Returns the value of the `MTEX` field.
3668    pub const fn mtex(self) -> u8 {
3669        ((self.bits() >> Self::MTEX_SHIFT) & 0b1111) as u8
3670    }
3671
3672    /// Returns the value of the `DF2` field.
3673    pub const fn df2(self) -> u8 {
3674        ((self.bits() >> Self::DF2_SHIFT) & 0b1111) as u8
3675    }
3676
3677    /// Returns the value of the `PFAR` field.
3678    pub const fn pfar(self) -> u8 {
3679        ((self.bits() >> Self::PFAR_SHIFT) & 0b1111) as u8
3680    }
3681}
3682
3683#[cfg(feature = "el1")]
3684bitflags! {
3685    /// `ID_AA64SMFR0_EL1` system register value.
3686    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
3687    #[repr(transparent)]
3688    pub struct IdAa64smfr0El1: u64 {
3689        /// `SMOP4` bit.
3690        const SMOP4 = 1 << 0;
3691        /// `STMOP` bit.
3692        const STMOP = 1 << 16;
3693        /// `SFEXPA` bit.
3694        const SFEXPA = 1 << 23;
3695        /// `AES` bit.
3696        const AES = 1 << 24;
3697        /// `SBitPerm` bit.
3698        const SBITPERM = 1 << 25;
3699        /// `SF8DP2` bit.
3700        const SF8DP2 = 1 << 28;
3701        /// `SF8DP4` bit.
3702        const SF8DP4 = 1 << 29;
3703        /// `SF8FMA` bit.
3704        const SF8FMA = 1 << 30;
3705        /// `F32F32` bit.
3706        const F32F32 = 1 << 32;
3707        /// `BI32I32` bit.
3708        const BI32I32 = 1 << 33;
3709        /// `B16F32` bit.
3710        const B16F32 = 1 << 34;
3711        /// `F16F32` bit.
3712        const F16F32 = 1 << 35;
3713        /// `F8F32` bit.
3714        const F8F32 = 1 << 40;
3715        /// `F8F16` bit.
3716        const F8F16 = 1 << 41;
3717        /// `F16F16` bit.
3718        const F16F16 = 1 << 42;
3719        /// `B16B16` bit.
3720        const B16B16 = 1 << 43;
3721        /// `F64F64` bit.
3722        const F64F64 = 1 << 48;
3723        /// `LUTv2` bit.
3724        const LUTV2 = 1 << 60;
3725        /// `LUT6` bit.
3726        const LUT6 = 1 << 61;
3727        /// `FA64` bit.
3728        const FA64 = 1 << 63;
3729    }
3730}
3731
3732#[cfg(feature = "el1")]
3733impl IdAa64smfr0El1 {
3734    /// Offset of the SMOP4 field.
3735    pub const SMOP4_SHIFT: u32 = 0;
3736    /// Offset of the STMOP field.
3737    pub const STMOP_SHIFT: u32 = 16;
3738    /// Offset of the SFEXPA field.
3739    pub const SFEXPA_SHIFT: u32 = 23;
3740    /// Offset of the AES field.
3741    pub const AES_SHIFT: u32 = 24;
3742    /// Offset of the SBitPerm field.
3743    pub const SBITPERM_SHIFT: u32 = 25;
3744    /// Offset of the SF8DP2 field.
3745    pub const SF8DP2_SHIFT: u32 = 28;
3746    /// Offset of the SF8DP4 field.
3747    pub const SF8DP4_SHIFT: u32 = 29;
3748    /// Offset of the SF8FMA field.
3749    pub const SF8FMA_SHIFT: u32 = 30;
3750    /// Offset of the F32F32 field.
3751    pub const F32F32_SHIFT: u32 = 32;
3752    /// Offset of the BI32I32 field.
3753    pub const BI32I32_SHIFT: u32 = 33;
3754    /// Offset of the B16F32 field.
3755    pub const B16F32_SHIFT: u32 = 34;
3756    /// Offset of the F16F32 field.
3757    pub const F16F32_SHIFT: u32 = 35;
3758    /// Offset of the I8I32 field.
3759    pub const I8I32_SHIFT: u32 = 36;
3760    /// Mask for the I8I32 field.
3761    pub const I8I32_MASK: u64 = 0b1111;
3762    /// Offset of the F8F32 field.
3763    pub const F8F32_SHIFT: u32 = 40;
3764    /// Offset of the F8F16 field.
3765    pub const F8F16_SHIFT: u32 = 41;
3766    /// Offset of the F16F16 field.
3767    pub const F16F16_SHIFT: u32 = 42;
3768    /// Offset of the B16B16 field.
3769    pub const B16B16_SHIFT: u32 = 43;
3770    /// Offset of the I16I32 field.
3771    pub const I16I32_SHIFT: u32 = 44;
3772    /// Mask for the I16I32 field.
3773    pub const I16I32_MASK: u64 = 0b1111;
3774    /// Offset of the F64F64 field.
3775    pub const F64F64_SHIFT: u32 = 48;
3776    /// Offset of the I16I64 field.
3777    pub const I16I64_SHIFT: u32 = 52;
3778    /// Mask for the I16I64 field.
3779    pub const I16I64_MASK: u64 = 0b1111;
3780    /// Offset of the SMEver field.
3781    pub const SMEVER_SHIFT: u32 = 56;
3782    /// Mask for the SMEver field.
3783    pub const SMEVER_MASK: u64 = 0b1111;
3784    /// Offset of the LUTv2 field.
3785    pub const LUTV2_SHIFT: u32 = 60;
3786    /// Offset of the LUT6 field.
3787    pub const LUT6_SHIFT: u32 = 61;
3788    /// Offset of the FA64 field.
3789    pub const FA64_SHIFT: u32 = 63;
3790
3791    /// Returns the value of the `I8I32` field.
3792    pub const fn i8i32(self) -> u8 {
3793        ((self.bits() >> Self::I8I32_SHIFT) & 0b1111) as u8
3794    }
3795
3796    /// Returns the value of the `I16I32` field.
3797    pub const fn i16i32(self) -> u8 {
3798        ((self.bits() >> Self::I16I32_SHIFT) & 0b1111) as u8
3799    }
3800
3801    /// Returns the value of the `I16I64` field.
3802    pub const fn i16i64(self) -> u8 {
3803        ((self.bits() >> Self::I16I64_SHIFT) & 0b1111) as u8
3804    }
3805
3806    /// Returns the value of the `SMEver` field.
3807    pub const fn smever(self) -> u8 {
3808        ((self.bits() >> Self::SMEVER_SHIFT) & 0b1111) as u8
3809    }
3810}
3811
3812#[cfg(feature = "el1")]
3813bitflags! {
3814    /// `ISR_EL1` system register value.
3815    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
3816    #[repr(transparent)]
3817    pub struct IsrEl1: u64 {
3818        /// `F` bit.
3819        const F = 1 << 6;
3820        /// `I` bit.
3821        const I = 1 << 7;
3822        /// `A` bit.
3823        const A = 1 << 8;
3824        /// `FS` bit.
3825        const FS = 1 << 9;
3826        /// `IS` bit.
3827        const IS = 1 << 10;
3828    }
3829}
3830
3831#[cfg(feature = "el1")]
3832impl IsrEl1 {
3833    /// Offset of the F field.
3834    pub const F_SHIFT: u32 = 6;
3835    /// Offset of the I field.
3836    pub const I_SHIFT: u32 = 7;
3837    /// Offset of the A field.
3838    pub const A_SHIFT: u32 = 8;
3839    /// Offset of the FS field.
3840    pub const FS_SHIFT: u32 = 9;
3841    /// Offset of the IS field.
3842    pub const IS_SHIFT: u32 = 10;
3843}
3844
3845#[cfg(feature = "el1")]
3846bitflags! {
3847    /// `MAIR_EL1` system register value.
3848    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
3849    #[repr(transparent)]
3850    pub struct MairEl1: u64 {
3851    }
3852}
3853
3854#[cfg(feature = "el1")]
3855impl MairEl1 {
3856    /// Offset of the Attr<n> field.
3857    pub const ATTR_SHIFT: u32 = 0;
3858    /// Mask for the Attr<n> field.
3859    pub const ATTR_MASK: u64 = 0b11111111;
3860
3861    /// Returns the value of the given `Attr<n>` field.
3862    pub const fn attr(self, n: u32) -> u8 {
3863        assert!(n < 8);
3864        ((self.bits() >> (Self::ATTR_SHIFT + (n - 0) * 8)) & 0b11111111) as u8
3865    }
3866}
3867
3868#[cfg(feature = "el2")]
3869bitflags! {
3870    /// `MAIR_EL2` system register value.
3871    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
3872    #[repr(transparent)]
3873    pub struct MairEl2: u64 {
3874    }
3875}
3876
3877#[cfg(feature = "el2")]
3878impl MairEl2 {
3879    /// Offset of the Attr<n> field.
3880    pub const ATTR_SHIFT: u32 = 0;
3881    /// Mask for the Attr<n> field.
3882    pub const ATTR_MASK: u64 = 0b11111111;
3883
3884    /// Returns the value of the given `Attr<n>` field.
3885    pub const fn attr(self, n: u32) -> u8 {
3886        assert!(n < 8);
3887        ((self.bits() >> (Self::ATTR_SHIFT + (n - 0) * 8)) & 0b11111111) as u8
3888    }
3889}
3890
3891#[cfg(feature = "el3")]
3892bitflags! {
3893    /// `MAIR_EL3` system register value.
3894    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
3895    #[repr(transparent)]
3896    pub struct MairEl3: u64 {
3897    }
3898}
3899
3900#[cfg(feature = "el3")]
3901impl MairEl3 {
3902    /// Offset of the Attr<n> field.
3903    pub const ATTR_SHIFT: u32 = 0;
3904    /// Mask for the Attr<n> field.
3905    pub const ATTR_MASK: u64 = 0b11111111;
3906
3907    /// Returns the value of the given `Attr<n>` field.
3908    pub const fn attr(self, n: u32) -> u8 {
3909        assert!(n < 8);
3910        ((self.bits() >> (Self::ATTR_SHIFT + (n - 0) * 8)) & 0b11111111) as u8
3911    }
3912}
3913
3914#[cfg(feature = "el1")]
3915bitflags! {
3916    /// `MDCCINT_EL1` system register value.
3917    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
3918    #[repr(transparent)]
3919    pub struct MdccintEl1: u64 {
3920        /// `TX` bit.
3921        const TX = 1 << 29;
3922        /// `RX` bit.
3923        const RX = 1 << 30;
3924    }
3925}
3926
3927#[cfg(feature = "el1")]
3928impl MdccintEl1 {
3929    /// Offset of the TX field.
3930    pub const TX_SHIFT: u32 = 29;
3931    /// Offset of the RX field.
3932    pub const RX_SHIFT: u32 = 30;
3933}
3934
3935#[cfg(feature = "el2")]
3936bitflags! {
3937    /// `MDCR_EL2` system register value.
3938    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
3939    #[repr(transparent)]
3940    pub struct MdcrEl2: u64 {
3941        /// `TPMCR` bit.
3942        const TPMCR = 1 << 5;
3943        /// `TPM` bit.
3944        const TPM = 1 << 6;
3945        /// `HPME` bit.
3946        const HPME = 1 << 7;
3947        /// `TDE` bit.
3948        const TDE = 1 << 8;
3949        /// `TDA` bit.
3950        const TDA = 1 << 9;
3951        /// `TDOSA` bit.
3952        const TDOSA = 1 << 10;
3953        /// `TDRA` bit.
3954        const TDRA = 1 << 11;
3955        /// `TPMS` bit.
3956        const TPMS = 1 << 14;
3957        /// `EnSPM` bit.
3958        const ENSPM = 1 << 15;
3959        /// `HPMD` bit.
3960        const HPMD = 1 << 17;
3961        /// `TTRF` bit.
3962        const TTRF = 1 << 19;
3963        /// `HCCD` bit.
3964        const HCCD = 1 << 23;
3965        /// `HLP` bit.
3966        const HLP = 1 << 26;
3967        /// `TDCC` bit.
3968        const TDCC = 1 << 27;
3969        /// `MTPME` bit.
3970        const MTPME = 1 << 28;
3971        /// `HPMFZO` bit.
3972        const HPMFZO = 1 << 29;
3973        /// `HPMFZS` bit.
3974        const HPMFZS = 1 << 36;
3975        /// `EBWE` bit.
3976        const EBWE = 1 << 43;
3977        /// `EnSTEPOP` bit.
3978        const ENSTEPOP = 1 << 50;
3979    }
3980}
3981
3982#[cfg(feature = "el2")]
3983impl MdcrEl2 {
3984    /// Offset of the HPMN field.
3985    pub const HPMN_SHIFT: u32 = 0;
3986    /// Mask for the HPMN field.
3987    pub const HPMN_MASK: u64 = 0b11111;
3988    /// Offset of the TPMCR field.
3989    pub const TPMCR_SHIFT: u32 = 5;
3990    /// Offset of the TPM field.
3991    pub const TPM_SHIFT: u32 = 6;
3992    /// Offset of the HPME field.
3993    pub const HPME_SHIFT: u32 = 7;
3994    /// Offset of the TDE field.
3995    pub const TDE_SHIFT: u32 = 8;
3996    /// Offset of the TDA field.
3997    pub const TDA_SHIFT: u32 = 9;
3998    /// Offset of the TDOSA field.
3999    pub const TDOSA_SHIFT: u32 = 10;
4000    /// Offset of the TDRA field.
4001    pub const TDRA_SHIFT: u32 = 11;
4002    /// Offset of the E2PB field.
4003    pub const E2PB_SHIFT: u32 = 12;
4004    /// Mask for the E2PB field.
4005    pub const E2PB_MASK: u64 = 0b11;
4006    /// Offset of the TPMS field.
4007    pub const TPMS_SHIFT: u32 = 14;
4008    /// Offset of the EnSPM field.
4009    pub const ENSPM_SHIFT: u32 = 15;
4010    /// Offset of the HPMD field.
4011    pub const HPMD_SHIFT: u32 = 17;
4012    /// Offset of the TTRF field.
4013    pub const TTRF_SHIFT: u32 = 19;
4014    /// Offset of the HCCD field.
4015    pub const HCCD_SHIFT: u32 = 23;
4016    /// Offset of the E2TB field.
4017    pub const E2TB_SHIFT: u32 = 24;
4018    /// Mask for the E2TB field.
4019    pub const E2TB_MASK: u64 = 0b11;
4020    /// Offset of the HLP field.
4021    pub const HLP_SHIFT: u32 = 26;
4022    /// Offset of the TDCC field.
4023    pub const TDCC_SHIFT: u32 = 27;
4024    /// Offset of the MTPME field.
4025    pub const MTPME_SHIFT: u32 = 28;
4026    /// Offset of the HPMFZO field.
4027    pub const HPMFZO_SHIFT: u32 = 29;
4028    /// Offset of the PMSSE field.
4029    pub const PMSSE_SHIFT: u32 = 30;
4030    /// Mask for the PMSSE field.
4031    pub const PMSSE_MASK: u64 = 0b11;
4032    /// Offset of the HPMFZS field.
4033    pub const HPMFZS_SHIFT: u32 = 36;
4034    /// Offset of the PMEE field.
4035    pub const PMEE_SHIFT: u32 = 40;
4036    /// Mask for the PMEE field.
4037    pub const PMEE_MASK: u64 = 0b11;
4038    /// Offset of the EBWE field.
4039    pub const EBWE_SHIFT: u32 = 43;
4040    /// Offset of the EnSTEPOP field.
4041    pub const ENSTEPOP_SHIFT: u32 = 50;
4042
4043    /// Returns the value of the `HPMN` field.
4044    pub const fn hpmn(self) -> u8 {
4045        ((self.bits() >> Self::HPMN_SHIFT) & 0b11111) as u8
4046    }
4047
4048    /// Returns the value of the `E2PB` field.
4049    pub const fn e2pb(self) -> u8 {
4050        ((self.bits() >> Self::E2PB_SHIFT) & 0b11) as u8
4051    }
4052
4053    /// Returns the value of the `E2TB` field.
4054    pub const fn e2tb(self) -> u8 {
4055        ((self.bits() >> Self::E2TB_SHIFT) & 0b11) as u8
4056    }
4057
4058    /// Returns the value of the `PMSSE` field.
4059    pub const fn pmsse(self) -> u8 {
4060        ((self.bits() >> Self::PMSSE_SHIFT) & 0b11) as u8
4061    }
4062
4063    /// Returns the value of the `PMEE` field.
4064    pub const fn pmee(self) -> u8 {
4065        ((self.bits() >> Self::PMEE_SHIFT) & 0b11) as u8
4066    }
4067}
4068
4069#[cfg(feature = "el3")]
4070bitflags! {
4071    /// `MDCR_EL3` system register value.
4072    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
4073    #[repr(transparent)]
4074    pub struct MdcrEl3: u64 {
4075        /// Realm Trace enable. Enables tracing in Realm state.
4076        const RLTE = 1 << 0;
4077        /// `EPMADE` bit.
4078        const EPMADE = 1 << 2;
4079        /// `ETADE` bit.
4080        const ETADE = 1 << 3;
4081        /// `EDADE` bit.
4082        const EDADE = 1 << 4;
4083        /// Trap Performance Monitor register accesses
4084        const TPM = 1 << 6;
4085        /// Do not trap various PMUv3p9 related system register accesses to EL3.
4086        const ENPM2 = 1 << 7;
4087        /// `TDA` bit.
4088        const TDA = 1 << 9;
4089        /// `TDOSA` bit.
4090        const TDOSA = 1 << 10;
4091        /// Non-secure Profiling Buffer Extended. Together with MDCR_EL3.NSPB, controls the Profiling Buffer owning Security state and accesses to Statistical Profiling and Profiling Buffer System registers from EL2 and EL1.
4092        const NSPBE = 1 << 11;
4093        /// Set to one to disable AArch64 Secure self-hosted debug. Debug exceptions, other than Breakpoint Instruction exceptions, are disabled from all ELs in Secure state.
4094        const SDD = 1 << 16;
4095        /// Secure Performance Monitors Enable. Controls event counting in Secure state and EL3.
4096        const SPME = 1 << 17;
4097        /// Secure Trace enable. Enables tracing in Secure state.
4098        const STE = 1 << 18;
4099        /// Trap Trace Filter controls. Traps use of the Trace Filter control registers at EL2 and EL1 to EL3.
4100        const TTRF = 1 << 19;
4101        /// `EDAD` bit.
4102        const EDAD = 1 << 20;
4103        /// `EPMAD` bit.
4104        const EPMAD = 1 << 21;
4105        /// `ETAD` bit.
4106        const ETAD = 1 << 22;
4107        /// Secure Cycle Counter Disable. Prohibits PMCCNTR_EL0 from counting in Secure state.
4108        const SCCD = 1 << 23;
4109        /// Non-secure Trace Buffer Extended. Together with MDCR_EL3.NSTB, controls the trace buffer owning Security state and accesses to trace buffer System registers from EL2 and EL1.
4110        const NSTBE = 1 << 26;
4111        /// `TDCC` bit.
4112        const TDCC = 1 << 27;
4113        /// Multi-threaded PMU Enable. Enables use of the PMEVTYPER<n>_EL0.MT bits.
4114        const MTPME = 1 << 28;
4115        /// Monitor Cycle Counter Disable. Prohibits the Cycle Counter, PMCCNTR_EL0, from counting at EL3.
4116        const MCCD = 1 << 34;
4117        /// Monitor Performance Monitors Extended control. In conjunction with MDCR_EL3.SPME, controls when event counters are enabled at EL3 and in other Secure Exception levels.
4118        const MPMX = 1 << 35;
4119        /// Trap accesses to PMSNEVFR_EL1. Controls access to Statistical Profiling PMSNEVFR_EL1 System register from EL2 and EL1.
4120        const ENPMSN = 1 << 36;
4121        /// `E3BREW` bit.
4122        const E3BREW = 1 << 37;
4123        /// `E3BREC` bit.
4124        const E3BREC = 1 << 38;
4125        /// `EnTB2` bit.
4126        const ENTB2 = 1 << 39;
4127        /// Enable access to SPE registers. When disabled, accesses to SPE registers generate a trap to EL3.
4128        const ENPMS3 = 1 << 42;
4129        /// `EBWE` bit.
4130        const EBWE = 1 << 43;
4131        /// `EnPMSS` bit.
4132        const ENPMSS = 1 << 44;
4133        /// `EnITE` bit.
4134        const ENITE = 1 << 47;
4135        /// `EnSTEPOP` bit.
4136        const ENSTEPOP = 1 << 50;
4137        /// `EnPMS4` bit.
4138        const ENPMS4 = 1 << 55;
4139    }
4140}
4141
4142#[cfg(feature = "el3")]
4143impl MdcrEl3 {
4144    /// Offset of the RLTE field.
4145    pub const RLTE_SHIFT: u32 = 0;
4146    /// Offset of the EPMADE field.
4147    pub const EPMADE_SHIFT: u32 = 2;
4148    /// Offset of the ETADE field.
4149    pub const ETADE_SHIFT: u32 = 3;
4150    /// Offset of the EDADE field.
4151    pub const EDADE_SHIFT: u32 = 4;
4152    /// Offset of the TPM field.
4153    pub const TPM_SHIFT: u32 = 6;
4154    /// Offset of the EnPM2 field.
4155    pub const ENPM2_SHIFT: u32 = 7;
4156    /// Offset of the TDA field.
4157    pub const TDA_SHIFT: u32 = 9;
4158    /// Offset of the TDOSA field.
4159    pub const TDOSA_SHIFT: u32 = 10;
4160    /// Offset of the NSPBE field.
4161    pub const NSPBE_SHIFT: u32 = 11;
4162    /// Offset of the NSPB field.
4163    pub const NSPB_SHIFT: u32 = 12;
4164    /// Mask for the NSPB field.
4165    pub const NSPB_MASK: u64 = 0b11;
4166    /// Offset of the SPD32 field.
4167    pub const SPD32_SHIFT: u32 = 14;
4168    /// Mask for the SPD32 field.
4169    pub const SPD32_MASK: u64 = 0b11;
4170    /// Offset of the SDD field.
4171    pub const SDD_SHIFT: u32 = 16;
4172    /// Offset of the SPME field.
4173    pub const SPME_SHIFT: u32 = 17;
4174    /// Offset of the STE field.
4175    pub const STE_SHIFT: u32 = 18;
4176    /// Offset of the TTRF field.
4177    pub const TTRF_SHIFT: u32 = 19;
4178    /// Offset of the EDAD field.
4179    pub const EDAD_SHIFT: u32 = 20;
4180    /// Offset of the EPMAD field.
4181    pub const EPMAD_SHIFT: u32 = 21;
4182    /// Offset of the ETAD field.
4183    pub const ETAD_SHIFT: u32 = 22;
4184    /// Offset of the SCCD field.
4185    pub const SCCD_SHIFT: u32 = 23;
4186    /// Offset of the NSTB field.
4187    pub const NSTB_SHIFT: u32 = 24;
4188    /// Mask for the NSTB field.
4189    pub const NSTB_MASK: u64 = 0b11;
4190    /// Offset of the NSTBE field.
4191    pub const NSTBE_SHIFT: u32 = 26;
4192    /// Offset of the TDCC field.
4193    pub const TDCC_SHIFT: u32 = 27;
4194    /// Offset of the MTPME field.
4195    pub const MTPME_SHIFT: u32 = 28;
4196    /// Offset of the PMSSE field.
4197    pub const PMSSE_SHIFT: u32 = 30;
4198    /// Mask for the PMSSE field.
4199    pub const PMSSE_MASK: u64 = 0b11;
4200    /// Offset of the SBRBE field.
4201    pub const SBRBE_SHIFT: u32 = 32;
4202    /// Mask for the SBRBE field.
4203    pub const SBRBE_MASK: u64 = 0b11;
4204    /// Offset of the MCCD field.
4205    pub const MCCD_SHIFT: u32 = 34;
4206    /// Offset of the MPMX field.
4207    pub const MPMX_SHIFT: u32 = 35;
4208    /// Offset of the EnPMSN field.
4209    pub const ENPMSN_SHIFT: u32 = 36;
4210    /// Offset of the E3BREW field.
4211    pub const E3BREW_SHIFT: u32 = 37;
4212    /// Offset of the E3BREC field.
4213    pub const E3BREC_SHIFT: u32 = 38;
4214    /// Offset of the EnTB2 field.
4215    pub const ENTB2_SHIFT: u32 = 39;
4216    /// Offset of the PMEE field.
4217    pub const PMEE_SHIFT: u32 = 40;
4218    /// Mask for the PMEE field.
4219    pub const PMEE_MASK: u64 = 0b11;
4220    /// Offset of the EnPMS3 field.
4221    pub const ENPMS3_SHIFT: u32 = 42;
4222    /// Offset of the EBWE field.
4223    pub const EBWE_SHIFT: u32 = 43;
4224    /// Offset of the EnPMSS field.
4225    pub const ENPMSS_SHIFT: u32 = 44;
4226    /// Offset of the EPMSSAD field.
4227    pub const EPMSSAD_SHIFT: u32 = 45;
4228    /// Mask for the EPMSSAD field.
4229    pub const EPMSSAD_MASK: u64 = 0b11;
4230    /// Offset of the EnITE field.
4231    pub const ENITE_SHIFT: u32 = 47;
4232    /// Offset of the ETBAD field.
4233    pub const ETBAD_SHIFT: u32 = 48;
4234    /// Mask for the ETBAD field.
4235    pub const ETBAD_MASK: u64 = 0b11;
4236    /// Offset of the EnSTEPOP field.
4237    pub const ENSTEPOP_SHIFT: u32 = 50;
4238    /// Offset of the PMSEE field.
4239    pub const PMSEE_SHIFT: u32 = 51;
4240    /// Mask for the PMSEE field.
4241    pub const PMSEE_MASK: u64 = 0b11;
4242    /// Offset of the TRBEE field.
4243    pub const TRBEE_SHIFT: u32 = 53;
4244    /// Mask for the TRBEE field.
4245    pub const TRBEE_MASK: u64 = 0b11;
4246    /// Offset of the EnPMS4 field.
4247    pub const ENPMS4_SHIFT: u32 = 55;
4248
4249    /// Returns the value of the `NSPB` field.
4250    pub const fn nspb(self) -> u8 {
4251        ((self.bits() >> Self::NSPB_SHIFT) & 0b11) as u8
4252    }
4253
4254    /// Returns the value of the `SPD32` field.
4255    pub const fn spd32(self) -> u8 {
4256        ((self.bits() >> Self::SPD32_SHIFT) & 0b11) as u8
4257    }
4258
4259    /// Returns the value of the `NSTB` field.
4260    pub const fn nstb(self) -> u8 {
4261        ((self.bits() >> Self::NSTB_SHIFT) & 0b11) as u8
4262    }
4263
4264    /// Returns the value of the `PMSSE` field.
4265    pub const fn pmsse(self) -> u8 {
4266        ((self.bits() >> Self::PMSSE_SHIFT) & 0b11) as u8
4267    }
4268
4269    /// Returns the value of the `SBRBE` field.
4270    pub const fn sbrbe(self) -> u8 {
4271        ((self.bits() >> Self::SBRBE_SHIFT) & 0b11) as u8
4272    }
4273
4274    /// Returns the value of the `PMEE` field.
4275    pub const fn pmee(self) -> u8 {
4276        ((self.bits() >> Self::PMEE_SHIFT) & 0b11) as u8
4277    }
4278
4279    /// Returns the value of the `EPMSSAD` field.
4280    pub const fn epmssad(self) -> u8 {
4281        ((self.bits() >> Self::EPMSSAD_SHIFT) & 0b11) as u8
4282    }
4283
4284    /// Returns the value of the `ETBAD` field.
4285    pub const fn etbad(self) -> u8 {
4286        ((self.bits() >> Self::ETBAD_SHIFT) & 0b11) as u8
4287    }
4288
4289    /// Returns the value of the `PMSEE` field.
4290    pub const fn pmsee(self) -> u8 {
4291        ((self.bits() >> Self::PMSEE_SHIFT) & 0b11) as u8
4292    }
4293
4294    /// Returns the value of the `TRBEE` field.
4295    pub const fn trbee(self) -> u8 {
4296        ((self.bits() >> Self::TRBEE_SHIFT) & 0b11) as u8
4297    }
4298}
4299
4300#[cfg(feature = "el1")]
4301bitflags! {
4302    /// `MDSCR_EL1` system register value.
4303    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
4304    #[repr(transparent)]
4305    pub struct MdscrEl1: u64 {
4306        /// `SS` bit.
4307        const SS = 1 << 0;
4308        /// `ERR` bit.
4309        const ERR = 1 << 6;
4310        /// `TDCC` bit.
4311        const TDCC = 1 << 12;
4312        /// `KDE` bit.
4313        const KDE = 1 << 13;
4314        /// `HDE` bit.
4315        const HDE = 1 << 14;
4316        /// `MDE` bit.
4317        const MDE = 1 << 15;
4318        /// `SC2` bit.
4319        const SC2 = 1 << 19;
4320        /// `TDA` bit.
4321        const TDA = 1 << 21;
4322        /// `TXU` bit.
4323        const TXU = 1 << 26;
4324        /// `RXO` bit.
4325        const RXO = 1 << 27;
4326        /// `TXfull` bit.
4327        const TXFULL = 1 << 29;
4328        /// `RXfull` bit.
4329        const RXFULL = 1 << 30;
4330        /// `TFO` bit.
4331        const TFO = 1 << 31;
4332        /// `EMBWE` bit.
4333        const EMBWE = 1 << 32;
4334        /// `TTA` bit.
4335        const TTA = 1 << 33;
4336        /// `EnSPM` bit.
4337        const ENSPM = 1 << 34;
4338        /// `EHBWE` bit.
4339        const EHBWE = 1 << 35;
4340        /// `EnSTEPOP` bit.
4341        const ENSTEPOP = 1 << 50;
4342    }
4343}
4344
4345#[cfg(feature = "el1")]
4346impl MdscrEl1 {
4347    /// Offset of the SS field.
4348    pub const SS_SHIFT: u32 = 0;
4349    /// Offset of the ERR field.
4350    pub const ERR_SHIFT: u32 = 6;
4351    /// Offset of the TDCC field.
4352    pub const TDCC_SHIFT: u32 = 12;
4353    /// Offset of the KDE field.
4354    pub const KDE_SHIFT: u32 = 13;
4355    /// Offset of the HDE field.
4356    pub const HDE_SHIFT: u32 = 14;
4357    /// Offset of the MDE field.
4358    pub const MDE_SHIFT: u32 = 15;
4359    /// Offset of the SC2 field.
4360    pub const SC2_SHIFT: u32 = 19;
4361    /// Offset of the TDA field.
4362    pub const TDA_SHIFT: u32 = 21;
4363    /// Offset of the INTdis field.
4364    pub const INTDIS_SHIFT: u32 = 22;
4365    /// Mask for the INTdis field.
4366    pub const INTDIS_MASK: u64 = 0b11;
4367    /// Offset of the TXU field.
4368    pub const TXU_SHIFT: u32 = 26;
4369    /// Offset of the RXO field.
4370    pub const RXO_SHIFT: u32 = 27;
4371    /// Offset of the TXfull field.
4372    pub const TXFULL_SHIFT: u32 = 29;
4373    /// Offset of the RXfull field.
4374    pub const RXFULL_SHIFT: u32 = 30;
4375    /// Offset of the TFO field.
4376    pub const TFO_SHIFT: u32 = 31;
4377    /// Offset of the EMBWE field.
4378    pub const EMBWE_SHIFT: u32 = 32;
4379    /// Offset of the TTA field.
4380    pub const TTA_SHIFT: u32 = 33;
4381    /// Offset of the EnSPM field.
4382    pub const ENSPM_SHIFT: u32 = 34;
4383    /// Offset of the EHBWE field.
4384    pub const EHBWE_SHIFT: u32 = 35;
4385    /// Offset of the EnSTEPOP field.
4386    pub const ENSTEPOP_SHIFT: u32 = 50;
4387
4388    /// Returns the value of the `INTdis` field.
4389    pub const fn intdis(self) -> u8 {
4390        ((self.bits() >> Self::INTDIS_SHIFT) & 0b11) as u8
4391    }
4392}
4393
4394#[cfg(feature = "el1")]
4395bitflags! {
4396    /// `MIDR_EL1` system register value.
4397    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
4398    #[repr(transparent)]
4399    pub struct MidrEl1: u64 {
4400    }
4401}
4402
4403#[cfg(feature = "el1")]
4404impl MidrEl1 {
4405    /// Offset of the Revision field.
4406    pub const REVISION_SHIFT: u32 = 0;
4407    /// Mask for the Revision field.
4408    pub const REVISION_MASK: u64 = 0b1111;
4409    /// Offset of the PartNum field.
4410    pub const PARTNUM_SHIFT: u32 = 4;
4411    /// Mask for the PartNum field.
4412    pub const PARTNUM_MASK: u64 = 0b111111111111;
4413    /// Offset of the Architecture field.
4414    pub const ARCHITECTURE_SHIFT: u32 = 16;
4415    /// Mask for the Architecture field.
4416    pub const ARCHITECTURE_MASK: u64 = 0b1111;
4417    /// Offset of the Variant field.
4418    pub const VARIANT_SHIFT: u32 = 20;
4419    /// Mask for the Variant field.
4420    pub const VARIANT_MASK: u64 = 0b1111;
4421    /// Offset of the Implementer field.
4422    pub const IMPLEMENTER_SHIFT: u32 = 24;
4423    /// Mask for the Implementer field.
4424    pub const IMPLEMENTER_MASK: u64 = 0b11111111;
4425
4426    /// Returns the value of the `Revision` field.
4427    pub const fn revision(self) -> u8 {
4428        ((self.bits() >> Self::REVISION_SHIFT) & 0b1111) as u8
4429    }
4430
4431    /// Returns the value of the `PartNum` field.
4432    pub const fn partnum(self) -> u16 {
4433        ((self.bits() >> Self::PARTNUM_SHIFT) & 0b111111111111) as u16
4434    }
4435
4436    /// Returns the value of the `Architecture` field.
4437    pub const fn architecture(self) -> u8 {
4438        ((self.bits() >> Self::ARCHITECTURE_SHIFT) & 0b1111) as u8
4439    }
4440
4441    /// Returns the value of the `Variant` field.
4442    pub const fn variant(self) -> u8 {
4443        ((self.bits() >> Self::VARIANT_SHIFT) & 0b1111) as u8
4444    }
4445
4446    /// Returns the value of the `Implementer` field.
4447    pub const fn implementer(self) -> u8 {
4448        ((self.bits() >> Self::IMPLEMENTER_SHIFT) & 0b11111111) as u8
4449    }
4450}
4451
4452#[cfg(feature = "el2")]
4453bitflags! {
4454    /// `MPAM2_EL2` system register value.
4455    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
4456    #[repr(transparent)]
4457    pub struct Mpam2El2: u64 {
4458        /// `TRAPMPAM1EL1` bit.
4459        const TRAPMPAM1EL1 = 1 << 48;
4460        /// `TRAPMPAM0EL1` bit.
4461        const TRAPMPAM0EL1 = 1 << 49;
4462        /// `EnMPAMSM` bit.
4463        const ENMPAMSM = 1 << 50;
4464        /// `ALTSP_FRCD` bit.
4465        const ALTSP_FRCD = 1 << 54;
4466        /// `ALTSP_EL2` bit.
4467        const ALTSP_EL2 = 1 << 55;
4468        /// `ALTSP_HFC` bit.
4469        const ALTSP_HFC = 1 << 56;
4470        /// `TIDR` bit.
4471        const TIDR = 1 << 58;
4472        /// `MPAMEN` bit.
4473        const MPAMEN = 1 << 63;
4474    }
4475}
4476
4477#[cfg(feature = "el2")]
4478impl Mpam2El2 {
4479    /// Offset of the PARTID field.
4480    pub const PARTID_SHIFT: u32 = 0;
4481    /// Mask for the PARTID field.
4482    pub const PARTID_MASK: u64 = 0b1111111111111111;
4483    /// Offset of the PARTID_I field.
4484    pub const PARTID_I_SHIFT: u32 = 0;
4485    /// Mask for the PARTID_I field.
4486    pub const PARTID_I_MASK: u64 = 0b1111111111111111;
4487    /// Offset of the PARTID_D field.
4488    pub const PARTID_D_SHIFT: u32 = 16;
4489    /// Mask for the PARTID_D field.
4490    pub const PARTID_D_MASK: u64 = 0b1111111111111111;
4491    /// Offset of the altPARTID field.
4492    pub const ALTPARTID_SHIFT: u32 = 16;
4493    /// Mask for the altPARTID field.
4494    pub const ALTPARTID_MASK: u64 = 0b1111111111111111;
4495    /// Offset of the PMG field.
4496    pub const PMG_SHIFT: u32 = 32;
4497    /// Mask for the PMG field.
4498    pub const PMG_MASK: u64 = 0b1111111111111111;
4499    /// Offset of the PMG_I field.
4500    pub const PMG_I_SHIFT: u32 = 32;
4501    /// Mask for the PMG_I field.
4502    pub const PMG_I_MASK: u64 = 0b11111111;
4503    /// Offset of the PMG_D field.
4504    pub const PMG_D_SHIFT: u32 = 40;
4505    /// Mask for the PMG_D field.
4506    pub const PMG_D_MASK: u64 = 0b11111111;
4507    /// Offset of the TRAPMPAM1EL1 field.
4508    pub const TRAPMPAM1EL1_SHIFT: u32 = 48;
4509    /// Offset of the altPMG field.
4510    pub const ALTPMG_SHIFT: u32 = 48;
4511    /// Mask for the altPMG field.
4512    pub const ALTPMG_MASK: u64 = 0b1111111111111111;
4513    /// Offset of the TRAPMPAM0EL1 field.
4514    pub const TRAPMPAM0EL1_SHIFT: u32 = 49;
4515    /// Offset of the EnMPAMSM field.
4516    pub const ENMPAMSM_SHIFT: u32 = 50;
4517    /// Offset of the ALTSP_FRCD field.
4518    pub const ALTSP_FRCD_SHIFT: u32 = 54;
4519    /// Offset of the ALTSP_EL2 field.
4520    pub const ALTSP_EL2_SHIFT: u32 = 55;
4521    /// Offset of the ALTSP_HFC field.
4522    pub const ALTSP_HFC_SHIFT: u32 = 56;
4523    /// Offset of the TIDR field.
4524    pub const TIDR_SHIFT: u32 = 58;
4525    /// Offset of the MPAMEN field.
4526    pub const MPAMEN_SHIFT: u32 = 63;
4527
4528    /// Returns the value of the `PARTID` field.
4529    pub const fn partid(self) -> u16 {
4530        ((self.bits() >> Self::PARTID_SHIFT) & 0b1111111111111111) as u16
4531    }
4532
4533    /// Returns the value of the `PARTID_I` field.
4534    pub const fn partid_i(self) -> u16 {
4535        ((self.bits() >> Self::PARTID_I_SHIFT) & 0b1111111111111111) as u16
4536    }
4537
4538    /// Returns the value of the `PARTID_D` field.
4539    pub const fn partid_d(self) -> u16 {
4540        ((self.bits() >> Self::PARTID_D_SHIFT) & 0b1111111111111111) as u16
4541    }
4542
4543    /// Returns the value of the `altPARTID` field.
4544    pub const fn altpartid(self) -> u16 {
4545        ((self.bits() >> Self::ALTPARTID_SHIFT) & 0b1111111111111111) as u16
4546    }
4547
4548    /// Returns the value of the `PMG` field.
4549    pub const fn pmg(self) -> u16 {
4550        ((self.bits() >> Self::PMG_SHIFT) & 0b1111111111111111) as u16
4551    }
4552
4553    /// Returns the value of the `PMG_I` field.
4554    pub const fn pmg_i(self) -> u8 {
4555        ((self.bits() >> Self::PMG_I_SHIFT) & 0b11111111) as u8
4556    }
4557
4558    /// Returns the value of the `PMG_D` field.
4559    pub const fn pmg_d(self) -> u8 {
4560        ((self.bits() >> Self::PMG_D_SHIFT) & 0b11111111) as u8
4561    }
4562
4563    /// Returns the value of the `altPMG` field.
4564    pub const fn altpmg(self) -> u16 {
4565        ((self.bits() >> Self::ALTPMG_SHIFT) & 0b1111111111111111) as u16
4566    }
4567}
4568
4569#[cfg(feature = "el3")]
4570bitflags! {
4571    /// `MPAM3_EL3` system register value.
4572    ///
4573    /// Holds information to generate MPAM labels for memory requests when executing at EL3.
4574    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
4575    #[repr(transparent)]
4576    pub struct Mpam3El3: u64 {
4577        /// `RT_ALTSP_NS` bit.
4578        const RT_ALTSP_NS = 1 << 52;
4579        /// `ALTSP_EL3` bit.
4580        const ALTSP_EL3 = 1 << 55;
4581        /// `ALTSP_HFC` bit.
4582        const ALTSP_HFC = 1 << 56;
4583        /// `ALTSP_HEN` bit.
4584        const ALTSP_HEN = 1 << 57;
4585        /// `FORCE_NS` bit.
4586        const FORCE_NS = 1 << 60;
4587        /// `SDEFLT` bit.
4588        const SDEFLT = 1 << 61;
4589        /// Trap direct accesses to MPAM System registers that are not UNDEFINED from all ELn lower than EL3.
4590        const TRAPLOWER = 1 << 62;
4591        /// MPAM Enable. If set, MPAM information is output based on the MPAMn_ELx register for ELn according the MPAM configuration. If not set, the default PARTID and default PMG are output in MPAM information when executing at any ELn.
4592        const MPAMEN = 1 << 63;
4593    }
4594}
4595
4596#[cfg(feature = "el3")]
4597impl Mpam3El3 {
4598    /// Offset of the PARTID field.
4599    pub const PARTID_SHIFT: u32 = 0;
4600    /// Mask for the PARTID field.
4601    pub const PARTID_MASK: u64 = 0b1111111111111111;
4602    /// Offset of the PARTID_I field.
4603    pub const PARTID_I_SHIFT: u32 = 0;
4604    /// Mask for the PARTID_I field.
4605    pub const PARTID_I_MASK: u64 = 0b1111111111111111;
4606    /// Offset of the PARTID_D field.
4607    pub const PARTID_D_SHIFT: u32 = 16;
4608    /// Mask for the PARTID_D field.
4609    pub const PARTID_D_MASK: u64 = 0b1111111111111111;
4610    /// Offset of the altPARTID field.
4611    pub const ALTPARTID_SHIFT: u32 = 16;
4612    /// Mask for the altPARTID field.
4613    pub const ALTPARTID_MASK: u64 = 0b1111111111111111;
4614    /// Offset of the PMG field.
4615    pub const PMG_SHIFT: u32 = 32;
4616    /// Mask for the PMG field.
4617    pub const PMG_MASK: u64 = 0b1111111111111111;
4618    /// Offset of the PMG_I field.
4619    pub const PMG_I_SHIFT: u32 = 32;
4620    /// Mask for the PMG_I field.
4621    pub const PMG_I_MASK: u64 = 0b11111111;
4622    /// Offset of the PMG_D field.
4623    pub const PMG_D_SHIFT: u32 = 40;
4624    /// Mask for the PMG_D field.
4625    pub const PMG_D_MASK: u64 = 0b11111111;
4626    /// Offset of the altPMG field.
4627    pub const ALTPMG_SHIFT: u32 = 48;
4628    /// Mask for the altPMG field.
4629    pub const ALTPMG_MASK: u64 = 0b1111111111111111;
4630    /// Offset of the RT_ALTSP_NS field.
4631    pub const RT_ALTSP_NS_SHIFT: u32 = 52;
4632    /// Offset of the ALTSP_EL3 field.
4633    pub const ALTSP_EL3_SHIFT: u32 = 55;
4634    /// Offset of the ALTSP_HFC field.
4635    pub const ALTSP_HFC_SHIFT: u32 = 56;
4636    /// Offset of the ALTSP_HEN field.
4637    pub const ALTSP_HEN_SHIFT: u32 = 57;
4638    /// Offset of the FORCE_NS field.
4639    pub const FORCE_NS_SHIFT: u32 = 60;
4640    /// Offset of the SDEFLT field.
4641    pub const SDEFLT_SHIFT: u32 = 61;
4642    /// Offset of the TRAPLOWER field.
4643    pub const TRAPLOWER_SHIFT: u32 = 62;
4644    /// Offset of the MPAMEN field.
4645    pub const MPAMEN_SHIFT: u32 = 63;
4646
4647    /// Returns the value of the `PARTID` field.
4648    pub const fn partid(self) -> u16 {
4649        ((self.bits() >> Self::PARTID_SHIFT) & 0b1111111111111111) as u16
4650    }
4651
4652    /// Returns the value of the `PARTID_I` field.
4653    pub const fn partid_i(self) -> u16 {
4654        ((self.bits() >> Self::PARTID_I_SHIFT) & 0b1111111111111111) as u16
4655    }
4656
4657    /// Returns the value of the `PARTID_D` field.
4658    pub const fn partid_d(self) -> u16 {
4659        ((self.bits() >> Self::PARTID_D_SHIFT) & 0b1111111111111111) as u16
4660    }
4661
4662    /// Returns the value of the `altPARTID` field.
4663    pub const fn altpartid(self) -> u16 {
4664        ((self.bits() >> Self::ALTPARTID_SHIFT) & 0b1111111111111111) as u16
4665    }
4666
4667    /// Returns the value of the `PMG` field.
4668    pub const fn pmg(self) -> u16 {
4669        ((self.bits() >> Self::PMG_SHIFT) & 0b1111111111111111) as u16
4670    }
4671
4672    /// Returns the value of the `PMG_I` field.
4673    pub const fn pmg_i(self) -> u8 {
4674        ((self.bits() >> Self::PMG_I_SHIFT) & 0b11111111) as u8
4675    }
4676
4677    /// Returns the value of the `PMG_D` field.
4678    pub const fn pmg_d(self) -> u8 {
4679        ((self.bits() >> Self::PMG_D_SHIFT) & 0b11111111) as u8
4680    }
4681
4682    /// Returns the value of the `altPMG` field.
4683    pub const fn altpmg(self) -> u16 {
4684        ((self.bits() >> Self::ALTPMG_SHIFT) & 0b1111111111111111) as u16
4685    }
4686}
4687
4688#[cfg(feature = "el2")]
4689bitflags! {
4690    /// `MPAMHCR_EL2` system register value.
4691    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
4692    #[repr(transparent)]
4693    pub struct MpamhcrEl2: u64 {
4694        /// `EL0_VPMEN` bit.
4695        const EL0_VPMEN = 1 << 0;
4696        /// `EL1_VPMEN` bit.
4697        const EL1_VPMEN = 1 << 1;
4698        /// `VPMEN` bit.
4699        const VPMEN = 1 << 2;
4700        /// `VMMEN` bit.
4701        const VMMEN = 1 << 3;
4702        /// `SMVPMEN` bit.
4703        const SMVPMEN = 1 << 4;
4704        /// `SMVMMEN` bit.
4705        const SMVMMEN = 1 << 5;
4706        /// `GSTAPP_PLK` bit.
4707        const GSTAPP_PLK = 1 << 8;
4708        /// `TRAP_MPAMIDR_EL1` bit.
4709        const TRAP_MPAMIDR_EL1 = 1 << 31;
4710    }
4711}
4712
4713#[cfg(feature = "el2")]
4714impl MpamhcrEl2 {
4715    /// Offset of the EL0_VPMEN field.
4716    pub const EL0_VPMEN_SHIFT: u32 = 0;
4717    /// Offset of the EL1_VPMEN field.
4718    pub const EL1_VPMEN_SHIFT: u32 = 1;
4719    /// Offset of the VPMEN field.
4720    pub const VPMEN_SHIFT: u32 = 2;
4721    /// Offset of the VMMEN field.
4722    pub const VMMEN_SHIFT: u32 = 3;
4723    /// Offset of the SMVPMEN field.
4724    pub const SMVPMEN_SHIFT: u32 = 4;
4725    /// Offset of the SMVMMEN field.
4726    pub const SMVMMEN_SHIFT: u32 = 5;
4727    /// Offset of the GSTAPP_PLK field.
4728    pub const GSTAPP_PLK_SHIFT: u32 = 8;
4729    /// Offset of the TRAP_MPAMIDR_EL1 field.
4730    pub const TRAP_MPAMIDR_EL1_SHIFT: u32 = 31;
4731}
4732
4733#[cfg(feature = "el1")]
4734bitflags! {
4735    /// `MPAMIDR_EL1` system register value.
4736    ///
4737    /// Indicates the maximum PARTID and PMG values supported in the implementation and the support for other optional features.
4738    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
4739    #[repr(transparent)]
4740    pub struct MpamidrEl1: u64 {
4741        /// Indicates support for MPAM virtualization.
4742        const HAS_HCR = 1 << 17;
4743        /// `HAS_ALT_ID` bit.
4744        const HAS_ALT_ID = 1 << 21;
4745        /// `HAS_INSTR_ALT_ID` bit.
4746        const HAS_INSTR_ALT_ID = 1 << 22;
4747        /// `HAS_BW_CTRL` bit.
4748        const HAS_BW_CTRL = 1 << 56;
4749        /// `HAS_ALTSP` bit.
4750        const HAS_ALTSP = 1 << 57;
4751        /// `HAS_TIDR` bit.
4752        const HAS_TIDR = 1 << 58;
4753        /// `SP4` bit.
4754        const SP4 = 1 << 59;
4755        /// `HAS_FORCE_NS` bit.
4756        const HAS_FORCE_NS = 1 << 60;
4757        /// `HAS_SDEFLT` bit.
4758        const HAS_SDEFLT = 1 << 61;
4759    }
4760}
4761
4762#[cfg(feature = "el1")]
4763impl MpamidrEl1 {
4764    /// Offset of the PARTID_MAX field.
4765    pub const PARTID_MAX_SHIFT: u32 = 0;
4766    /// Mask for the PARTID_MAX field.
4767    pub const PARTID_MAX_MASK: u64 = 0b1111111111111111;
4768    /// Offset of the HAS_HCR field.
4769    pub const HAS_HCR_SHIFT: u32 = 17;
4770    /// Offset of the VPMR_MAX field.
4771    pub const VPMR_MAX_SHIFT: u32 = 18;
4772    /// Mask for the VPMR_MAX field.
4773    pub const VPMR_MAX_MASK: u64 = 0b111;
4774    /// Offset of the HAS_ALT_ID field.
4775    pub const HAS_ALT_ID_SHIFT: u32 = 21;
4776    /// Offset of the HAS_INSTR_ALT_ID field.
4777    pub const HAS_INSTR_ALT_ID_SHIFT: u32 = 22;
4778    /// Offset of the HAS_BW_CTRL field.
4779    pub const HAS_BW_CTRL_SHIFT: u32 = 56;
4780    /// Offset of the HAS_ALTSP field.
4781    pub const HAS_ALTSP_SHIFT: u32 = 57;
4782    /// Offset of the HAS_TIDR field.
4783    pub const HAS_TIDR_SHIFT: u32 = 58;
4784    /// Offset of the SP4 field.
4785    pub const SP4_SHIFT: u32 = 59;
4786    /// Offset of the HAS_FORCE_NS field.
4787    pub const HAS_FORCE_NS_SHIFT: u32 = 60;
4788    /// Offset of the HAS_SDEFLT field.
4789    pub const HAS_SDEFLT_SHIFT: u32 = 61;
4790
4791    /// Returns the value of the `PARTID_MAX` field.
4792    pub const fn partid_max(self) -> u16 {
4793        ((self.bits() >> Self::PARTID_MAX_SHIFT) & 0b1111111111111111) as u16
4794    }
4795
4796    /// Returns the value of the `VPMR_MAX` field.
4797    ///
4798    /// Indicates the maximum register index n for the `MPAMVPM<n>_EL2` registers.
4799    pub const fn vpmr_max(self) -> u8 {
4800        ((self.bits() >> Self::VPMR_MAX_SHIFT) & 0b111) as u8
4801    }
4802}
4803
4804#[cfg(feature = "el2")]
4805bitflags! {
4806    /// `MPAMVPM0_EL2` system register value.
4807    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
4808    #[repr(transparent)]
4809    pub struct Mpamvpm0El2: u64 {
4810    }
4811}
4812
4813#[cfg(feature = "el2")]
4814impl Mpamvpm0El2 {
4815    /// Offset of the PhyPARTID0 field.
4816    pub const PHYPARTID0_SHIFT: u32 = 0;
4817    /// Mask for the PhyPARTID0 field.
4818    pub const PHYPARTID0_MASK: u64 = 0b1111111111111111;
4819    /// Offset of the PhyPARTID1 field.
4820    pub const PHYPARTID1_SHIFT: u32 = 16;
4821    /// Mask for the PhyPARTID1 field.
4822    pub const PHYPARTID1_MASK: u64 = 0b1111111111111111;
4823    /// Offset of the PhyPARTID2 field.
4824    pub const PHYPARTID2_SHIFT: u32 = 32;
4825    /// Mask for the PhyPARTID2 field.
4826    pub const PHYPARTID2_MASK: u64 = 0b1111111111111111;
4827    /// Offset of the PhyPARTID3 field.
4828    pub const PHYPARTID3_SHIFT: u32 = 48;
4829    /// Mask for the PhyPARTID3 field.
4830    pub const PHYPARTID3_MASK: u64 = 0b1111111111111111;
4831
4832    /// Returns the value of the `PhyPARTID0` field.
4833    pub const fn phypartid0(self) -> u16 {
4834        ((self.bits() >> Self::PHYPARTID0_SHIFT) & 0b1111111111111111) as u16
4835    }
4836
4837    /// Returns the value of the `PhyPARTID1` field.
4838    pub const fn phypartid1(self) -> u16 {
4839        ((self.bits() >> Self::PHYPARTID1_SHIFT) & 0b1111111111111111) as u16
4840    }
4841
4842    /// Returns the value of the `PhyPARTID2` field.
4843    pub const fn phypartid2(self) -> u16 {
4844        ((self.bits() >> Self::PHYPARTID2_SHIFT) & 0b1111111111111111) as u16
4845    }
4846
4847    /// Returns the value of the `PhyPARTID3` field.
4848    pub const fn phypartid3(self) -> u16 {
4849        ((self.bits() >> Self::PHYPARTID3_SHIFT) & 0b1111111111111111) as u16
4850    }
4851}
4852
4853#[cfg(feature = "el2")]
4854bitflags! {
4855    /// `MPAMVPM1_EL2` system register value.
4856    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
4857    #[repr(transparent)]
4858    pub struct Mpamvpm1El2: u64 {
4859    }
4860}
4861
4862#[cfg(feature = "el2")]
4863impl Mpamvpm1El2 {
4864    /// Offset of the PhyPARTID4 field.
4865    pub const PHYPARTID4_SHIFT: u32 = 0;
4866    /// Mask for the PhyPARTID4 field.
4867    pub const PHYPARTID4_MASK: u64 = 0b1111111111111111;
4868    /// Offset of the PhyPARTID5 field.
4869    pub const PHYPARTID5_SHIFT: u32 = 16;
4870    /// Mask for the PhyPARTID5 field.
4871    pub const PHYPARTID5_MASK: u64 = 0b1111111111111111;
4872    /// Offset of the PhyPARTID6 field.
4873    pub const PHYPARTID6_SHIFT: u32 = 32;
4874    /// Mask for the PhyPARTID6 field.
4875    pub const PHYPARTID6_MASK: u64 = 0b1111111111111111;
4876    /// Offset of the PhyPARTID7 field.
4877    pub const PHYPARTID7_SHIFT: u32 = 48;
4878    /// Mask for the PhyPARTID7 field.
4879    pub const PHYPARTID7_MASK: u64 = 0b1111111111111111;
4880
4881    /// Returns the value of the `PhyPARTID4` field.
4882    pub const fn phypartid4(self) -> u16 {
4883        ((self.bits() >> Self::PHYPARTID4_SHIFT) & 0b1111111111111111) as u16
4884    }
4885
4886    /// Returns the value of the `PhyPARTID5` field.
4887    pub const fn phypartid5(self) -> u16 {
4888        ((self.bits() >> Self::PHYPARTID5_SHIFT) & 0b1111111111111111) as u16
4889    }
4890
4891    /// Returns the value of the `PhyPARTID6` field.
4892    pub const fn phypartid6(self) -> u16 {
4893        ((self.bits() >> Self::PHYPARTID6_SHIFT) & 0b1111111111111111) as u16
4894    }
4895
4896    /// Returns the value of the `PhyPARTID7` field.
4897    pub const fn phypartid7(self) -> u16 {
4898        ((self.bits() >> Self::PHYPARTID7_SHIFT) & 0b1111111111111111) as u16
4899    }
4900}
4901
4902#[cfg(feature = "el2")]
4903bitflags! {
4904    /// `MPAMVPM2_EL2` system register value.
4905    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
4906    #[repr(transparent)]
4907    pub struct Mpamvpm2El2: u64 {
4908    }
4909}
4910
4911#[cfg(feature = "el2")]
4912impl Mpamvpm2El2 {
4913    /// Offset of the PhyPARTID8 field.
4914    pub const PHYPARTID8_SHIFT: u32 = 0;
4915    /// Mask for the PhyPARTID8 field.
4916    pub const PHYPARTID8_MASK: u64 = 0b1111111111111111;
4917    /// Offset of the PhyPARTID9 field.
4918    pub const PHYPARTID9_SHIFT: u32 = 16;
4919    /// Mask for the PhyPARTID9 field.
4920    pub const PHYPARTID9_MASK: u64 = 0b1111111111111111;
4921    /// Offset of the PhyPARTID10 field.
4922    pub const PHYPARTID10_SHIFT: u32 = 32;
4923    /// Mask for the PhyPARTID10 field.
4924    pub const PHYPARTID10_MASK: u64 = 0b1111111111111111;
4925    /// Offset of the PhyPARTID11 field.
4926    pub const PHYPARTID11_SHIFT: u32 = 48;
4927    /// Mask for the PhyPARTID11 field.
4928    pub const PHYPARTID11_MASK: u64 = 0b1111111111111111;
4929
4930    /// Returns the value of the `PhyPARTID8` field.
4931    pub const fn phypartid8(self) -> u16 {
4932        ((self.bits() >> Self::PHYPARTID8_SHIFT) & 0b1111111111111111) as u16
4933    }
4934
4935    /// Returns the value of the `PhyPARTID9` field.
4936    pub const fn phypartid9(self) -> u16 {
4937        ((self.bits() >> Self::PHYPARTID9_SHIFT) & 0b1111111111111111) as u16
4938    }
4939
4940    /// Returns the value of the `PhyPARTID10` field.
4941    pub const fn phypartid10(self) -> u16 {
4942        ((self.bits() >> Self::PHYPARTID10_SHIFT) & 0b1111111111111111) as u16
4943    }
4944
4945    /// Returns the value of the `PhyPARTID11` field.
4946    pub const fn phypartid11(self) -> u16 {
4947        ((self.bits() >> Self::PHYPARTID11_SHIFT) & 0b1111111111111111) as u16
4948    }
4949}
4950
4951#[cfg(feature = "el2")]
4952bitflags! {
4953    /// `MPAMVPM3_EL2` system register value.
4954    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
4955    #[repr(transparent)]
4956    pub struct Mpamvpm3El2: u64 {
4957    }
4958}
4959
4960#[cfg(feature = "el2")]
4961impl Mpamvpm3El2 {
4962    /// Offset of the PhyPARTID12 field.
4963    pub const PHYPARTID12_SHIFT: u32 = 0;
4964    /// Mask for the PhyPARTID12 field.
4965    pub const PHYPARTID12_MASK: u64 = 0b1111111111111111;
4966    /// Offset of the PhyPARTID13 field.
4967    pub const PHYPARTID13_SHIFT: u32 = 16;
4968    /// Mask for the PhyPARTID13 field.
4969    pub const PHYPARTID13_MASK: u64 = 0b1111111111111111;
4970    /// Offset of the PhyPARTID14 field.
4971    pub const PHYPARTID14_SHIFT: u32 = 32;
4972    /// Mask for the PhyPARTID14 field.
4973    pub const PHYPARTID14_MASK: u64 = 0b1111111111111111;
4974    /// Offset of the PhyPARTID15 field.
4975    pub const PHYPARTID15_SHIFT: u32 = 48;
4976    /// Mask for the PhyPARTID15 field.
4977    pub const PHYPARTID15_MASK: u64 = 0b1111111111111111;
4978
4979    /// Returns the value of the `PhyPARTID12` field.
4980    pub const fn phypartid12(self) -> u16 {
4981        ((self.bits() >> Self::PHYPARTID12_SHIFT) & 0b1111111111111111) as u16
4982    }
4983
4984    /// Returns the value of the `PhyPARTID13` field.
4985    pub const fn phypartid13(self) -> u16 {
4986        ((self.bits() >> Self::PHYPARTID13_SHIFT) & 0b1111111111111111) as u16
4987    }
4988
4989    /// Returns the value of the `PhyPARTID14` field.
4990    pub const fn phypartid14(self) -> u16 {
4991        ((self.bits() >> Self::PHYPARTID14_SHIFT) & 0b1111111111111111) as u16
4992    }
4993
4994    /// Returns the value of the `PhyPARTID15` field.
4995    pub const fn phypartid15(self) -> u16 {
4996        ((self.bits() >> Self::PHYPARTID15_SHIFT) & 0b1111111111111111) as u16
4997    }
4998}
4999
5000#[cfg(feature = "el2")]
5001bitflags! {
5002    /// `MPAMVPM4_EL2` system register value.
5003    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
5004    #[repr(transparent)]
5005    pub struct Mpamvpm4El2: u64 {
5006    }
5007}
5008
5009#[cfg(feature = "el2")]
5010impl Mpamvpm4El2 {
5011    /// Offset of the PhyPARTID16 field.
5012    pub const PHYPARTID16_SHIFT: u32 = 0;
5013    /// Mask for the PhyPARTID16 field.
5014    pub const PHYPARTID16_MASK: u64 = 0b1111111111111111;
5015    /// Offset of the PhyPARTID17 field.
5016    pub const PHYPARTID17_SHIFT: u32 = 16;
5017    /// Mask for the PhyPARTID17 field.
5018    pub const PHYPARTID17_MASK: u64 = 0b1111111111111111;
5019    /// Offset of the PhyPARTID18 field.
5020    pub const PHYPARTID18_SHIFT: u32 = 32;
5021    /// Mask for the PhyPARTID18 field.
5022    pub const PHYPARTID18_MASK: u64 = 0b1111111111111111;
5023    /// Offset of the PhyPARTID19 field.
5024    pub const PHYPARTID19_SHIFT: u32 = 48;
5025    /// Mask for the PhyPARTID19 field.
5026    pub const PHYPARTID19_MASK: u64 = 0b1111111111111111;
5027
5028    /// Returns the value of the `PhyPARTID16` field.
5029    pub const fn phypartid16(self) -> u16 {
5030        ((self.bits() >> Self::PHYPARTID16_SHIFT) & 0b1111111111111111) as u16
5031    }
5032
5033    /// Returns the value of the `PhyPARTID17` field.
5034    pub const fn phypartid17(self) -> u16 {
5035        ((self.bits() >> Self::PHYPARTID17_SHIFT) & 0b1111111111111111) as u16
5036    }
5037
5038    /// Returns the value of the `PhyPARTID18` field.
5039    pub const fn phypartid18(self) -> u16 {
5040        ((self.bits() >> Self::PHYPARTID18_SHIFT) & 0b1111111111111111) as u16
5041    }
5042
5043    /// Returns the value of the `PhyPARTID19` field.
5044    pub const fn phypartid19(self) -> u16 {
5045        ((self.bits() >> Self::PHYPARTID19_SHIFT) & 0b1111111111111111) as u16
5046    }
5047}
5048
5049#[cfg(feature = "el2")]
5050bitflags! {
5051    /// `MPAMVPM5_EL2` system register value.
5052    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
5053    #[repr(transparent)]
5054    pub struct Mpamvpm5El2: u64 {
5055    }
5056}
5057
5058#[cfg(feature = "el2")]
5059impl Mpamvpm5El2 {
5060    /// Offset of the PhyPARTID20 field.
5061    pub const PHYPARTID20_SHIFT: u32 = 0;
5062    /// Mask for the PhyPARTID20 field.
5063    pub const PHYPARTID20_MASK: u64 = 0b1111111111111111;
5064    /// Offset of the PhyPARTID21 field.
5065    pub const PHYPARTID21_SHIFT: u32 = 16;
5066    /// Mask for the PhyPARTID21 field.
5067    pub const PHYPARTID21_MASK: u64 = 0b1111111111111111;
5068    /// Offset of the PhyPARTID22 field.
5069    pub const PHYPARTID22_SHIFT: u32 = 32;
5070    /// Mask for the PhyPARTID22 field.
5071    pub const PHYPARTID22_MASK: u64 = 0b1111111111111111;
5072    /// Offset of the PhyPARTID23 field.
5073    pub const PHYPARTID23_SHIFT: u32 = 48;
5074    /// Mask for the PhyPARTID23 field.
5075    pub const PHYPARTID23_MASK: u64 = 0b1111111111111111;
5076
5077    /// Returns the value of the `PhyPARTID20` field.
5078    pub const fn phypartid20(self) -> u16 {
5079        ((self.bits() >> Self::PHYPARTID20_SHIFT) & 0b1111111111111111) as u16
5080    }
5081
5082    /// Returns the value of the `PhyPARTID21` field.
5083    pub const fn phypartid21(self) -> u16 {
5084        ((self.bits() >> Self::PHYPARTID21_SHIFT) & 0b1111111111111111) as u16
5085    }
5086
5087    /// Returns the value of the `PhyPARTID22` field.
5088    pub const fn phypartid22(self) -> u16 {
5089        ((self.bits() >> Self::PHYPARTID22_SHIFT) & 0b1111111111111111) as u16
5090    }
5091
5092    /// Returns the value of the `PhyPARTID23` field.
5093    pub const fn phypartid23(self) -> u16 {
5094        ((self.bits() >> Self::PHYPARTID23_SHIFT) & 0b1111111111111111) as u16
5095    }
5096}
5097
5098#[cfg(feature = "el2")]
5099bitflags! {
5100    /// `MPAMVPM6_EL2` system register value.
5101    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
5102    #[repr(transparent)]
5103    pub struct Mpamvpm6El2: u64 {
5104    }
5105}
5106
5107#[cfg(feature = "el2")]
5108impl Mpamvpm6El2 {
5109    /// Offset of the PhyPARTID24 field.
5110    pub const PHYPARTID24_SHIFT: u32 = 0;
5111    /// Mask for the PhyPARTID24 field.
5112    pub const PHYPARTID24_MASK: u64 = 0b1111111111111111;
5113    /// Offset of the PhyPARTID25 field.
5114    pub const PHYPARTID25_SHIFT: u32 = 16;
5115    /// Mask for the PhyPARTID25 field.
5116    pub const PHYPARTID25_MASK: u64 = 0b1111111111111111;
5117    /// Offset of the PhyPARTID26 field.
5118    pub const PHYPARTID26_SHIFT: u32 = 32;
5119    /// Mask for the PhyPARTID26 field.
5120    pub const PHYPARTID26_MASK: u64 = 0b1111111111111111;
5121    /// Offset of the PhyPARTID27 field.
5122    pub const PHYPARTID27_SHIFT: u32 = 48;
5123    /// Mask for the PhyPARTID27 field.
5124    pub const PHYPARTID27_MASK: u64 = 0b1111111111111111;
5125
5126    /// Returns the value of the `PhyPARTID24` field.
5127    pub const fn phypartid24(self) -> u16 {
5128        ((self.bits() >> Self::PHYPARTID24_SHIFT) & 0b1111111111111111) as u16
5129    }
5130
5131    /// Returns the value of the `PhyPARTID25` field.
5132    pub const fn phypartid25(self) -> u16 {
5133        ((self.bits() >> Self::PHYPARTID25_SHIFT) & 0b1111111111111111) as u16
5134    }
5135
5136    /// Returns the value of the `PhyPARTID26` field.
5137    pub const fn phypartid26(self) -> u16 {
5138        ((self.bits() >> Self::PHYPARTID26_SHIFT) & 0b1111111111111111) as u16
5139    }
5140
5141    /// Returns the value of the `PhyPARTID27` field.
5142    pub const fn phypartid27(self) -> u16 {
5143        ((self.bits() >> Self::PHYPARTID27_SHIFT) & 0b1111111111111111) as u16
5144    }
5145}
5146
5147#[cfg(feature = "el2")]
5148bitflags! {
5149    /// `MPAMVPM7_EL2` system register value.
5150    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
5151    #[repr(transparent)]
5152    pub struct Mpamvpm7El2: u64 {
5153    }
5154}
5155
5156#[cfg(feature = "el2")]
5157impl Mpamvpm7El2 {
5158    /// Offset of the PhyPARTID28 field.
5159    pub const PHYPARTID28_SHIFT: u32 = 0;
5160    /// Mask for the PhyPARTID28 field.
5161    pub const PHYPARTID28_MASK: u64 = 0b1111111111111111;
5162    /// Offset of the PhyPARTID29 field.
5163    pub const PHYPARTID29_SHIFT: u32 = 16;
5164    /// Mask for the PhyPARTID29 field.
5165    pub const PHYPARTID29_MASK: u64 = 0b1111111111111111;
5166    /// Offset of the PhyPARTID30 field.
5167    pub const PHYPARTID30_SHIFT: u32 = 32;
5168    /// Mask for the PhyPARTID30 field.
5169    pub const PHYPARTID30_MASK: u64 = 0b1111111111111111;
5170    /// Offset of the PhyPARTID31 field.
5171    pub const PHYPARTID31_SHIFT: u32 = 48;
5172    /// Mask for the PhyPARTID31 field.
5173    pub const PHYPARTID31_MASK: u64 = 0b1111111111111111;
5174
5175    /// Returns the value of the `PhyPARTID28` field.
5176    pub const fn phypartid28(self) -> u16 {
5177        ((self.bits() >> Self::PHYPARTID28_SHIFT) & 0b1111111111111111) as u16
5178    }
5179
5180    /// Returns the value of the `PhyPARTID29` field.
5181    pub const fn phypartid29(self) -> u16 {
5182        ((self.bits() >> Self::PHYPARTID29_SHIFT) & 0b1111111111111111) as u16
5183    }
5184
5185    /// Returns the value of the `PhyPARTID30` field.
5186    pub const fn phypartid30(self) -> u16 {
5187        ((self.bits() >> Self::PHYPARTID30_SHIFT) & 0b1111111111111111) as u16
5188    }
5189
5190    /// Returns the value of the `PhyPARTID31` field.
5191    pub const fn phypartid31(self) -> u16 {
5192        ((self.bits() >> Self::PHYPARTID31_SHIFT) & 0b1111111111111111) as u16
5193    }
5194}
5195
5196#[cfg(feature = "el2")]
5197bitflags! {
5198    /// `MPAMVPMV_EL2` system register value.
5199    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
5200    #[repr(transparent)]
5201    pub struct MpamvpmvEl2: u64 {
5202        /// `VPM_V<m>` bit 0.
5203        const VPM_V0 = 1 << 0;
5204        /// `VPM_V<m>` bit 1.
5205        const VPM_V1 = 1 << 1;
5206        /// `VPM_V<m>` bit 2.
5207        const VPM_V2 = 1 << 2;
5208        /// `VPM_V<m>` bit 3.
5209        const VPM_V3 = 1 << 3;
5210        /// `VPM_V<m>` bit 4.
5211        const VPM_V4 = 1 << 4;
5212        /// `VPM_V<m>` bit 5.
5213        const VPM_V5 = 1 << 5;
5214        /// `VPM_V<m>` bit 6.
5215        const VPM_V6 = 1 << 6;
5216        /// `VPM_V<m>` bit 7.
5217        const VPM_V7 = 1 << 7;
5218        /// `VPM_V<m>` bit 8.
5219        const VPM_V8 = 1 << 8;
5220        /// `VPM_V<m>` bit 9.
5221        const VPM_V9 = 1 << 9;
5222        /// `VPM_V<m>` bit 10.
5223        const VPM_V10 = 1 << 10;
5224        /// `VPM_V<m>` bit 11.
5225        const VPM_V11 = 1 << 11;
5226        /// `VPM_V<m>` bit 12.
5227        const VPM_V12 = 1 << 12;
5228        /// `VPM_V<m>` bit 13.
5229        const VPM_V13 = 1 << 13;
5230        /// `VPM_V<m>` bit 14.
5231        const VPM_V14 = 1 << 14;
5232        /// `VPM_V<m>` bit 15.
5233        const VPM_V15 = 1 << 15;
5234        /// `VPM_V<m>` bit 16.
5235        const VPM_V16 = 1 << 16;
5236        /// `VPM_V<m>` bit 17.
5237        const VPM_V17 = 1 << 17;
5238        /// `VPM_V<m>` bit 18.
5239        const VPM_V18 = 1 << 18;
5240        /// `VPM_V<m>` bit 19.
5241        const VPM_V19 = 1 << 19;
5242        /// `VPM_V<m>` bit 20.
5243        const VPM_V20 = 1 << 20;
5244        /// `VPM_V<m>` bit 21.
5245        const VPM_V21 = 1 << 21;
5246        /// `VPM_V<m>` bit 22.
5247        const VPM_V22 = 1 << 22;
5248        /// `VPM_V<m>` bit 23.
5249        const VPM_V23 = 1 << 23;
5250        /// `VPM_V<m>` bit 24.
5251        const VPM_V24 = 1 << 24;
5252        /// `VPM_V<m>` bit 25.
5253        const VPM_V25 = 1 << 25;
5254        /// `VPM_V<m>` bit 26.
5255        const VPM_V26 = 1 << 26;
5256        /// `VPM_V<m>` bit 27.
5257        const VPM_V27 = 1 << 27;
5258        /// `VPM_V<m>` bit 28.
5259        const VPM_V28 = 1 << 28;
5260        /// `VPM_V<m>` bit 29.
5261        const VPM_V29 = 1 << 29;
5262        /// `VPM_V<m>` bit 30.
5263        const VPM_V30 = 1 << 30;
5264        /// `VPM_V<m>` bit 31.
5265        const VPM_V31 = 1 << 31;
5266    }
5267}
5268
5269#[cfg(feature = "el2")]
5270impl MpamvpmvEl2 {
5271    /// Offset of the VPM_V<m> field.
5272    pub const VPM_V_SHIFT: u32 = 0;
5273}
5274
5275#[cfg(feature = "el1")]
5276bitflags! {
5277    /// `MPIDR_EL1` system register value.
5278    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
5279    #[repr(transparent)]
5280    pub struct MpidrEl1: u64 {
5281        /// RES1 bits in the `MPIDR_EL1` register.
5282        const RES1 = 0b10000000000000000000000000000000;
5283        /// `MT` bit.
5284        const MT = 1 << 24;
5285        /// `U` bit.
5286        const U = 1 << 30;
5287    }
5288}
5289
5290#[cfg(feature = "el1")]
5291impl MpidrEl1 {
5292    /// Offset of the Aff0 field.
5293    pub const AFF0_SHIFT: u32 = 0;
5294    /// Mask for the Aff0 field.
5295    pub const AFF0_MASK: u64 = 0b11111111;
5296    /// Offset of the Aff1 field.
5297    pub const AFF1_SHIFT: u32 = 8;
5298    /// Mask for the Aff1 field.
5299    pub const AFF1_MASK: u64 = 0b11111111;
5300    /// Offset of the Aff2 field.
5301    pub const AFF2_SHIFT: u32 = 16;
5302    /// Mask for the Aff2 field.
5303    pub const AFF2_MASK: u64 = 0b11111111;
5304    /// Offset of the MT field.
5305    pub const MT_SHIFT: u32 = 24;
5306    /// Offset of the U field.
5307    pub const U_SHIFT: u32 = 30;
5308    /// Offset of the Aff3 field.
5309    pub const AFF3_SHIFT: u32 = 32;
5310    /// Mask for the Aff3 field.
5311    pub const AFF3_MASK: u64 = 0b11111111;
5312
5313    /// Returns the value of the `Aff0` field.
5314    pub const fn aff0(self) -> u8 {
5315        ((self.bits() >> Self::AFF0_SHIFT) & 0b11111111) as u8
5316    }
5317
5318    /// Returns the value of the `Aff1` field.
5319    pub const fn aff1(self) -> u8 {
5320        ((self.bits() >> Self::AFF1_SHIFT) & 0b11111111) as u8
5321    }
5322
5323    /// Returns the value of the `Aff2` field.
5324    pub const fn aff2(self) -> u8 {
5325        ((self.bits() >> Self::AFF2_SHIFT) & 0b11111111) as u8
5326    }
5327
5328    /// Returns the value of the `Aff3` field.
5329    pub const fn aff3(self) -> u8 {
5330        ((self.bits() >> Self::AFF3_SHIFT) & 0b11111111) as u8
5331    }
5332}
5333
5334#[cfg(feature = "el1")]
5335bitflags! {
5336    /// `PAR_EL1` system register value.
5337    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
5338    #[repr(transparent)]
5339    pub struct ParEl1: u64 {
5340        /// RES1 bits in the `PAR_EL1` register.
5341        const RES1 = 0b100000000000;
5342        /// `F` bit.
5343        const F = 1 << 0;
5344        /// `PTW` bit.
5345        const PTW = 1 << 8;
5346        /// `NS` bit.
5347        const NS = 1 << 9;
5348        /// `S` bit.
5349        const S = 1 << 9;
5350        /// `NSE` bit.
5351        const NSE = 1 << 11;
5352        /// `AssuredOnly` bit.
5353        const ASSUREDONLY = 1 << 12;
5354        /// `TopLevel` bit.
5355        const TOPLEVEL = 1 << 13;
5356        /// `Overlay` bit.
5357        const OVERLAY = 1 << 14;
5358        /// `DirtyBit` bit.
5359        const DIRTYBIT = 1 << 15;
5360    }
5361}
5362
5363#[cfg(feature = "el1")]
5364impl ParEl1 {
5365    /// Offset of the F field.
5366    pub const F_SHIFT: u32 = 0;
5367    /// Offset of the FST field.
5368    pub const FST_SHIFT: u32 = 1;
5369    /// Mask for the FST field.
5370    pub const FST_MASK: u64 = 0b111111;
5371    /// Offset of the SH field.
5372    pub const SH_SHIFT: u32 = 7;
5373    /// Mask for the SH field.
5374    pub const SH_MASK: u64 = 0b11;
5375    /// Offset of the PTW field.
5376    pub const PTW_SHIFT: u32 = 8;
5377    /// Offset of the NS field.
5378    pub const NS_SHIFT: u32 = 9;
5379    /// Offset of the S field.
5380    pub const S_SHIFT: u32 = 9;
5381    /// Offset of the NSE field.
5382    pub const NSE_SHIFT: u32 = 11;
5383    /// Offset of the AssuredOnly field.
5384    pub const ASSUREDONLY_SHIFT: u32 = 12;
5385    /// Offset of the PA[47:12] field.
5386    pub const PA_47_12_SHIFT: u32 = 12;
5387    /// Mask for the PA[47:12] field.
5388    pub const PA_47_12_MASK: u64 = 0b111111111111111111111111111111111111;
5389    /// Offset of the TopLevel field.
5390    pub const TOPLEVEL_SHIFT: u32 = 13;
5391    /// Offset of the Overlay field.
5392    pub const OVERLAY_SHIFT: u32 = 14;
5393    /// Offset of the DirtyBit field.
5394    pub const DIRTYBIT_SHIFT: u32 = 15;
5395    /// Offset of the PA[51:48] field.
5396    pub const PA_51_48_SHIFT: u32 = 48;
5397    /// Mask for the PA[51:48] field.
5398    pub const PA_51_48_MASK: u64 = 0b1111;
5399    /// Offset of the ATTR field.
5400    pub const ATTR_SHIFT: u32 = 56;
5401    /// Mask for the ATTR field.
5402    pub const ATTR_MASK: u64 = 0b11111111;
5403
5404    /// Returns the value of the `FST` field.
5405    pub const fn fst(self) -> u8 {
5406        ((self.bits() >> Self::FST_SHIFT) & 0b111111) as u8
5407    }
5408
5409    /// Returns the value of the `SH` field.
5410    pub const fn sh(self) -> u8 {
5411        ((self.bits() >> Self::SH_SHIFT) & 0b11) as u8
5412    }
5413
5414    /// Returns the value of the `PA[47:12]` field.
5415    pub const fn pa_47_12(self) -> u64 {
5416        ((self.bits() >> Self::PA_47_12_SHIFT) & 0b111111111111111111111111111111111111) as u64
5417    }
5418
5419    /// Returns the value of the `PA[51:48]` field.
5420    pub const fn pa_51_48(self) -> u8 {
5421        ((self.bits() >> Self::PA_51_48_SHIFT) & 0b1111) as u8
5422    }
5423
5424    /// Returns the value of the `ATTR` field.
5425    pub const fn attr(self) -> u8 {
5426        ((self.bits() >> Self::ATTR_SHIFT) & 0b11111111) as u8
5427    }
5428}
5429
5430bitflags! {
5431    /// `PMCR_EL0` system register value.
5432    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
5433    #[repr(transparent)]
5434    pub struct PmcrEl0: u64 {
5435        /// Enable. Affected counters are enabled by PMCNTENSET_EL0.
5436        const E = 1 << 0;
5437        /// Event counter reset. Reset all affected event counters PMEVCNTR<n>_EL0 to zero.
5438        const P = 1 << 1;
5439        /// Cycle counter reset. Reset PMCCNTR_EL0 to zero.
5440        const C = 1 << 2;
5441        /// Clock divider. If set PMCCNTR_EL0 counts once every 64 clock cycles.
5442        const D = 1 << 3;
5443        /// Enable export of events in an IMPLEMENTATION DEFINED PMU event export bus. If set, export events where not prohibited.
5444        const X = 1 << 4;
5445        /// If set, cycle counting by PMCCNTR_EL0 is disabled in prohibited regions.
5446        const DP = 1 << 5;
5447        /// `LC` bit.
5448        const LC = 1 << 6;
5449        /// `LP` bit.
5450        const LP = 1 << 7;
5451        /// `FZO` bit.
5452        const FZO = 1 << 9;
5453        /// `FZS` bit.
5454        const FZS = 1 << 32;
5455    }
5456}
5457
5458impl PmcrEl0 {
5459    /// Offset of the E field.
5460    pub const E_SHIFT: u32 = 0;
5461    /// Offset of the P field.
5462    pub const P_SHIFT: u32 = 1;
5463    /// Offset of the C field.
5464    pub const C_SHIFT: u32 = 2;
5465    /// Offset of the D field.
5466    pub const D_SHIFT: u32 = 3;
5467    /// Offset of the X field.
5468    pub const X_SHIFT: u32 = 4;
5469    /// Offset of the DP field.
5470    pub const DP_SHIFT: u32 = 5;
5471    /// Offset of the LC field.
5472    pub const LC_SHIFT: u32 = 6;
5473    /// Offset of the LP field.
5474    pub const LP_SHIFT: u32 = 7;
5475    /// Offset of the FZO field.
5476    pub const FZO_SHIFT: u32 = 9;
5477    /// Offset of the N field.
5478    pub const N_SHIFT: u32 = 11;
5479    /// Mask for the N field.
5480    pub const N_MASK: u64 = 0b11111;
5481    /// Offset of the IDCODE field.
5482    pub const IDCODE_SHIFT: u32 = 16;
5483    /// Mask for the IDCODE field.
5484    pub const IDCODE_MASK: u64 = 0b11111111;
5485    /// Offset of the IMP field.
5486    pub const IMP_SHIFT: u32 = 24;
5487    /// Mask for the IMP field.
5488    pub const IMP_MASK: u64 = 0b11111111;
5489    /// Offset of the FZS field.
5490    pub const FZS_SHIFT: u32 = 32;
5491
5492    /// Returns the value of the `N` field.
5493    pub const fn n(self) -> u8 {
5494        ((self.bits() >> Self::N_SHIFT) & 0b11111) as u8
5495    }
5496
5497    /// Returns the value of the `IDCODE` field.
5498    pub const fn idcode(self) -> u8 {
5499        ((self.bits() >> Self::IDCODE_SHIFT) & 0b11111111) as u8
5500    }
5501
5502    /// Returns the value of the `IMP` field.
5503    pub const fn imp(self) -> u8 {
5504        ((self.bits() >> Self::IMP_SHIFT) & 0b11111111) as u8
5505    }
5506}
5507
5508#[cfg(feature = "el1")]
5509bitflags! {
5510    /// `RGSR_EL1` system register value.
5511    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
5512    #[repr(transparent)]
5513    pub struct RgsrEl1: u64 {
5514    }
5515}
5516
5517#[cfg(feature = "el1")]
5518impl RgsrEl1 {
5519    /// Offset of the TAG field.
5520    pub const TAG_SHIFT: u32 = 0;
5521    /// Mask for the TAG field.
5522    pub const TAG_MASK: u64 = 0b1111;
5523    /// Offset of the SEED field.
5524    pub const SEED_SHIFT: u32 = 8;
5525    /// Mask for the SEED field.
5526    pub const SEED_MASK: u64 = 0b1111111111111111;
5527
5528    /// Returns the value of the `TAG` field.
5529    pub const fn tag(self) -> u8 {
5530        ((self.bits() >> Self::TAG_SHIFT) & 0b1111) as u8
5531    }
5532
5533    /// Returns the value of the `SEED` field.
5534    pub const fn seed(self) -> u16 {
5535        ((self.bits() >> Self::SEED_SHIFT) & 0b1111111111111111) as u16
5536    }
5537}
5538
5539#[cfg(feature = "el3")]
5540bitflags! {
5541    /// `SCR_EL3` system register value.
5542    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
5543    #[repr(transparent)]
5544    pub struct ScrEl3: u64 {
5545        /// RES1 bits in the `SCR_EL3` register.
5546        const RES1 = 0b110000;
5547        /// Non-secure.
5548        const NS = 1 << 0;
5549        /// Take physical IRQs at EL3.
5550        const IRQ = 1 << 1;
5551        /// Take physical FIQs at EL3.
5552        const FIQ = 1 << 2;
5553        /// Take external abort and SError exceptions at EL3.
5554        const EA = 1 << 3;
5555        /// Disable SMC instructions.
5556        const SMD = 1 << 7;
5557        /// Enable HVC instructions.
5558        const HCE = 1 << 8;
5559        /// Disable execution from non-secure memory.
5560        const SIF = 1 << 9;
5561        /// Enable AArch64 in lower ELs.
5562        const RW = 1 << 10;
5563        /// Trap physical secure timer to EL3.
5564        const ST = 1 << 11;
5565        /// Trap WFI to EL3.
5566        const TWI = 1 << 12;
5567        /// Trap WFE to EL3.
5568        const TWE = 1 << 13;
5569        /// Trap LOR register access to EL3.
5570        const TLOR = 1 << 14;
5571        /// Trap error record register access to EL3.
5572        const TERR = 1 << 15;
5573        /// Don't trap PAC key registers to EL3.
5574        const APK = 1 << 16;
5575        /// Don't trap PAuth instructions to EL3.
5576        const API = 1 << 17;
5577        /// Enable Secure EL2.
5578        const EEL2 = 1 << 18;
5579        /// Synchronous external aborts are taken as SErrors.
5580        const EASE = 1 << 19;
5581        /// Take SError exceptions at EL3.
5582        const NMEA = 1 << 20;
5583        /// Enable fault injection at lower ELs.
5584        const FIEN = 1 << 21;
5585        /// Trap ID group 3 registers to EL3.
5586        const TID3 = 1 << 22;
5587        /// Trap ID group 5 register to EL3.
5588        const TID5 = 1 << 23;
5589        /// `POE2En` bit.
5590        const POE2EN = 1 << 24;
5591        /// Enable SCXT at lower ELs.
5592        const ENSCXT = 1 << 25;
5593        /// Enable memory tagging at lower ELs.
5594        const ATA = 1 << 26;
5595        /// Enable fine-grained traps to EL2.
5596        const FGTEN = 1 << 27;
5597        /// Enable access to CNTPOFF_EL2.
5598        const ECVEN = 1 << 28;
5599        /// Enable a configurable delay for WFE traps.
5600        const TWEDEN = 1 << 29;
5601        /// Enable activity monitors virtual offsets.
5602        const AMVOFFEN = 1 << 35;
5603        /// Enable ST64BV0 at lower ELs.
5604        const ENAS0 = 1 << 36;
5605        /// Enable ACCDATA_EL1 at lower ELs.
5606        const ADEN = 1 << 37;
5607        /// Enable HCRX_EL2.
5608        const HXEN = 1 << 38;
5609        /// Enable guarded control stack.
5610        const GCSEN = 1 << 39;
5611        /// Trap RNDR and RNDRRS to EL3.
5612        const TRNDR = 1 << 40;
5613        /// Enable TPIDR2_EL0 at lower ELs.
5614        const ENTP2 = 1 << 41;
5615        /// Enable RCW and RCWS mask registers at lower ELs.
5616        const RCWMASKEN = 1 << 42;
5617        /// Enable TCR2_ELx registers at lower ELs.
5618        const TCR2EN = 1 << 43;
5619        /// Enable SCTLR2_ELx registers at lower ELs.
5620        const SCTLR2EN = 1 << 44;
5621        /// Enable permission indirection and overlay registers at lower ELs.
5622        const PIEN = 1 << 45;
5623        /// Enable MAIR2_ELx and AMAIR2_ELx at lower ELs.
5624        const AIEN = 1 << 46;
5625        /// Enable 128-bit system registers at  lower ELs.
5626        const D128EN = 1 << 47;
5627        /// Route GPFs to EL3.
5628        const GPF = 1 << 48;
5629        /// Enable MECID registers at EL2.
5630        const MECEN = 1 << 49;
5631        /// Enable access to FPMR at lower ELs.
5632        const ENFPM = 1 << 50;
5633        /// Take synchronous external abort and physical SError exception to EL3.
5634        const TMEA = 1 << 51;
5635        /// Trap writes to Error Record registers to EL3.
5636        const TWERR = 1 << 52;
5637        /// Enable access to physical fault address registers at lower ELs.
5638        const PFAREN = 1 << 53;
5639        /// Enable access to mask registers at lower ELs.
5640        const SRMASKEN = 1 << 54;
5641        /// Enable implementation-defined 128-bit system registers.
5642        const ENIDCP128 = 1 << 55;
5643        /// `VTLBIDEn` bit.
5644        const VTLBIDEN = 1 << 56;
5645        /// A delegated SError exception is pending.
5646        const DSE = 1 << 57;
5647        /// Enable delegated SError exceptions.
5648        const ENDSE = 1 << 58;
5649        /// Enable fine-grained traps to EL2.
5650        const FGTEN2 = 1 << 59;
5651        /// Enable HDBSSBR_EL2 and HDBSSPROD_EL2 registers at EL2.
5652        const HDBSSEN = 1 << 60;
5653        /// Enable HACDBSBR_EL2 and HACDBSCONS_EL2 registers at EL2.
5654        const HACDBSEN = 1 << 61;
5655        /// Non-secure realm world bit.
5656        const NSE = 1 << 62;
5657        /// `TPLIMEn` bit.
5658        const TPLIMEN = 1 << 63;
5659    }
5660}
5661
5662#[cfg(feature = "el3")]
5663impl ScrEl3 {
5664    /// Offset of the NS field.
5665    pub const NS_SHIFT: u32 = 0;
5666    /// Offset of the IRQ field.
5667    pub const IRQ_SHIFT: u32 = 1;
5668    /// Offset of the FIQ field.
5669    pub const FIQ_SHIFT: u32 = 2;
5670    /// Offset of the EA field.
5671    pub const EA_SHIFT: u32 = 3;
5672    /// Offset of the SMD field.
5673    pub const SMD_SHIFT: u32 = 7;
5674    /// Offset of the HCE field.
5675    pub const HCE_SHIFT: u32 = 8;
5676    /// Offset of the SIF field.
5677    pub const SIF_SHIFT: u32 = 9;
5678    /// Offset of the RW field.
5679    pub const RW_SHIFT: u32 = 10;
5680    /// Offset of the ST field.
5681    pub const ST_SHIFT: u32 = 11;
5682    /// Offset of the TWI field.
5683    pub const TWI_SHIFT: u32 = 12;
5684    /// Offset of the TWE field.
5685    pub const TWE_SHIFT: u32 = 13;
5686    /// Offset of the TLOR field.
5687    pub const TLOR_SHIFT: u32 = 14;
5688    /// Offset of the TERR field.
5689    pub const TERR_SHIFT: u32 = 15;
5690    /// Offset of the APK field.
5691    pub const APK_SHIFT: u32 = 16;
5692    /// Offset of the API field.
5693    pub const API_SHIFT: u32 = 17;
5694    /// Offset of the EEL2 field.
5695    pub const EEL2_SHIFT: u32 = 18;
5696    /// Offset of the EASE field.
5697    pub const EASE_SHIFT: u32 = 19;
5698    /// Offset of the NMEA field.
5699    pub const NMEA_SHIFT: u32 = 20;
5700    /// Offset of the FIEN field.
5701    pub const FIEN_SHIFT: u32 = 21;
5702    /// Offset of the TID3 field.
5703    pub const TID3_SHIFT: u32 = 22;
5704    /// Offset of the TID5 field.
5705    pub const TID5_SHIFT: u32 = 23;
5706    /// Offset of the POE2En field.
5707    pub const POE2EN_SHIFT: u32 = 24;
5708    /// Offset of the EnSCXT field.
5709    pub const ENSCXT_SHIFT: u32 = 25;
5710    /// Offset of the ATA field.
5711    pub const ATA_SHIFT: u32 = 26;
5712    /// Offset of the FGTEn field.
5713    pub const FGTEN_SHIFT: u32 = 27;
5714    /// Offset of the ECVEn field.
5715    pub const ECVEN_SHIFT: u32 = 28;
5716    /// Offset of the TWEDEn field.
5717    pub const TWEDEN_SHIFT: u32 = 29;
5718    /// Offset of the TWEDEL field.
5719    pub const TWEDEL_SHIFT: u32 = 30;
5720    /// Mask for the TWEDEL field.
5721    pub const TWEDEL_MASK: u64 = 0b1111;
5722    /// Offset of the AMVOFFEN field.
5723    pub const AMVOFFEN_SHIFT: u32 = 35;
5724    /// Offset of the EnAS0 field.
5725    pub const ENAS0_SHIFT: u32 = 36;
5726    /// Offset of the ADEn field.
5727    pub const ADEN_SHIFT: u32 = 37;
5728    /// Offset of the HXEn field.
5729    pub const HXEN_SHIFT: u32 = 38;
5730    /// Offset of the GCSEn field.
5731    pub const GCSEN_SHIFT: u32 = 39;
5732    /// Offset of the TRNDR field.
5733    pub const TRNDR_SHIFT: u32 = 40;
5734    /// Offset of the EnTP2 field.
5735    pub const ENTP2_SHIFT: u32 = 41;
5736    /// Offset of the RCWMASKEn field.
5737    pub const RCWMASKEN_SHIFT: u32 = 42;
5738    /// Offset of the TCR2En field.
5739    pub const TCR2EN_SHIFT: u32 = 43;
5740    /// Offset of the SCTLR2En field.
5741    pub const SCTLR2EN_SHIFT: u32 = 44;
5742    /// Offset of the PIEn field.
5743    pub const PIEN_SHIFT: u32 = 45;
5744    /// Offset of the AIEn field.
5745    pub const AIEN_SHIFT: u32 = 46;
5746    /// Offset of the D128En field.
5747    pub const D128EN_SHIFT: u32 = 47;
5748    /// Offset of the GPF field.
5749    pub const GPF_SHIFT: u32 = 48;
5750    /// Offset of the MECEn field.
5751    pub const MECEN_SHIFT: u32 = 49;
5752    /// Offset of the EnFPM field.
5753    pub const ENFPM_SHIFT: u32 = 50;
5754    /// Offset of the TMEA field.
5755    pub const TMEA_SHIFT: u32 = 51;
5756    /// Offset of the TWERR field.
5757    pub const TWERR_SHIFT: u32 = 52;
5758    /// Offset of the PFAREn field.
5759    pub const PFAREN_SHIFT: u32 = 53;
5760    /// Offset of the SRMASKEn field.
5761    pub const SRMASKEN_SHIFT: u32 = 54;
5762    /// Offset of the EnIDCP128 field.
5763    pub const ENIDCP128_SHIFT: u32 = 55;
5764    /// Offset of the VTLBIDEn field.
5765    pub const VTLBIDEN_SHIFT: u32 = 56;
5766    /// Offset of the DSE field.
5767    pub const DSE_SHIFT: u32 = 57;
5768    /// Offset of the EnDSE field.
5769    pub const ENDSE_SHIFT: u32 = 58;
5770    /// Offset of the FGTEn2 field.
5771    pub const FGTEN2_SHIFT: u32 = 59;
5772    /// Offset of the HDBSSEn field.
5773    pub const HDBSSEN_SHIFT: u32 = 60;
5774    /// Offset of the HACDBSEn field.
5775    pub const HACDBSEN_SHIFT: u32 = 61;
5776    /// Offset of the NSE field.
5777    pub const NSE_SHIFT: u32 = 62;
5778    /// Offset of the TPLIMEn field.
5779    pub const TPLIMEN_SHIFT: u32 = 63;
5780
5781    /// Returns the value of the `TWEDEL` field.
5782    pub const fn twedel(self) -> u8 {
5783        ((self.bits() >> Self::TWEDEL_SHIFT) & 0b1111) as u8
5784    }
5785}
5786
5787#[cfg(feature = "el1")]
5788bitflags! {
5789    /// `SCTLR_EL1` system register value.
5790    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
5791    #[repr(transparent)]
5792    pub struct SctlrEl1: u64 {
5793        /// `M` bit.
5794        const M = 1 << 0;
5795        /// `A` bit.
5796        const A = 1 << 1;
5797        /// `C` bit.
5798        const C = 1 << 2;
5799        /// `SA` bit.
5800        const SA = 1 << 3;
5801        /// `SA0` bit.
5802        const SA0 = 1 << 4;
5803        /// `CP15BEN` bit.
5804        const CP15BEN = 1 << 5;
5805        /// `nAA` bit.
5806        const NAA = 1 << 6;
5807        /// `ITD` bit.
5808        const ITD = 1 << 7;
5809        /// `SED` bit.
5810        const SED = 1 << 8;
5811        /// `UMA` bit.
5812        const UMA = 1 << 9;
5813        /// `EnRCTX` bit.
5814        const ENRCTX = 1 << 10;
5815        /// `EOS` bit.
5816        const EOS = 1 << 11;
5817        /// `I` bit.
5818        const I = 1 << 12;
5819        /// `EnDB` bit.
5820        const ENDB = 1 << 13;
5821        /// `DZE` bit.
5822        const DZE = 1 << 14;
5823        /// `UCT` bit.
5824        const UCT = 1 << 15;
5825        /// `nTWI` bit.
5826        const NTWI = 1 << 16;
5827        /// `nTWE` bit.
5828        const NTWE = 1 << 18;
5829        /// `WXN` bit.
5830        const WXN = 1 << 19;
5831        /// `TSCXT` bit.
5832        const TSCXT = 1 << 20;
5833        /// `IESB` bit.
5834        const IESB = 1 << 21;
5835        /// `EIS` bit.
5836        const EIS = 1 << 22;
5837        /// Do not set Privileged Access Never, on taking an exception to EL1.
5838        const SPAN = 1 << 23;
5839        /// `UCI` bit.
5840        const UCI = 1 << 26;
5841        /// `EnDA` bit.
5842        const ENDA = 1 << 27;
5843        /// `nTLSMD` bit.
5844        const NTLSMD = 1 << 28;
5845        /// `LSMAOE` bit.
5846        const LSMAOE = 1 << 29;
5847        /// Enable pointer authentication using APIBKey_EL1.
5848        const ENIB = 1 << 30;
5849        /// Enable pointer authentication using APIAKey_EL1.
5850        const ENIA = 1 << 31;
5851        /// `CMOW` bit.
5852        const CMOW = 1 << 32;
5853        /// `MSCEn` bit.
5854        const MSCEN = 1 << 33;
5855        /// `EnFPM` bit.
5856        const ENFPM = 1 << 34;
5857        /// `BT0` bit.
5858        const BT0 = 1 << 35;
5859        /// `BT1` bit.
5860        const BT1 = 1 << 36;
5861        /// `ITFSB` bit.
5862        const ITFSB = 1 << 37;
5863        /// `ATA0` bit.
5864        const ATA0 = 1 << 42;
5865        /// `ATA` bit.
5866        const ATA = 1 << 43;
5867        /// Default PSTATE.SSBS value on Exception Entry.
5868        const DSSBS = 1 << 44;
5869        /// `TWEDEn` bit.
5870        const TWEDEN = 1 << 45;
5871        /// `EnASR` bit.
5872        const ENASR = 1 << 54;
5873        /// `EnAS0` bit.
5874        const ENAS0 = 1 << 55;
5875        /// `EnALS` bit.
5876        const ENALS = 1 << 56;
5877        /// `EPAN` bit.
5878        const EPAN = 1 << 57;
5879        /// `TCSO0` bit.
5880        const TCSO0 = 1 << 58;
5881        /// `TCSO` bit.
5882        const TCSO = 1 << 59;
5883        /// `EnTP2` bit.
5884        const ENTP2 = 1 << 60;
5885        /// `NMI` bit.
5886        const NMI = 1 << 61;
5887        /// SP Interrupt Mask enable.
5888        const SPINTMASK = 1 << 62;
5889        /// `TIDCP` bit.
5890        const TIDCP = 1 << 63;
5891    }
5892}
5893
5894#[cfg(feature = "el1")]
5895impl SctlrEl1 {
5896    /// Offset of the M field.
5897    pub const M_SHIFT: u32 = 0;
5898    /// Offset of the A field.
5899    pub const A_SHIFT: u32 = 1;
5900    /// Offset of the C field.
5901    pub const C_SHIFT: u32 = 2;
5902    /// Offset of the SA field.
5903    pub const SA_SHIFT: u32 = 3;
5904    /// Offset of the SA0 field.
5905    pub const SA0_SHIFT: u32 = 4;
5906    /// Offset of the CP15BEN field.
5907    pub const CP15BEN_SHIFT: u32 = 5;
5908    /// Offset of the nAA field.
5909    pub const NAA_SHIFT: u32 = 6;
5910    /// Offset of the ITD field.
5911    pub const ITD_SHIFT: u32 = 7;
5912    /// Offset of the SED field.
5913    pub const SED_SHIFT: u32 = 8;
5914    /// Offset of the UMA field.
5915    pub const UMA_SHIFT: u32 = 9;
5916    /// Offset of the EnRCTX field.
5917    pub const ENRCTX_SHIFT: u32 = 10;
5918    /// Offset of the EOS field.
5919    pub const EOS_SHIFT: u32 = 11;
5920    /// Offset of the I field.
5921    pub const I_SHIFT: u32 = 12;
5922    /// Offset of the EnDB field.
5923    pub const ENDB_SHIFT: u32 = 13;
5924    /// Offset of the DZE field.
5925    pub const DZE_SHIFT: u32 = 14;
5926    /// Offset of the UCT field.
5927    pub const UCT_SHIFT: u32 = 15;
5928    /// Offset of the nTWI field.
5929    pub const NTWI_SHIFT: u32 = 16;
5930    /// Offset of the nTWE field.
5931    pub const NTWE_SHIFT: u32 = 18;
5932    /// Offset of the WXN field.
5933    pub const WXN_SHIFT: u32 = 19;
5934    /// Offset of the TSCXT field.
5935    pub const TSCXT_SHIFT: u32 = 20;
5936    /// Offset of the IESB field.
5937    pub const IESB_SHIFT: u32 = 21;
5938    /// Offset of the EIS field.
5939    pub const EIS_SHIFT: u32 = 22;
5940    /// Offset of the SPAN field.
5941    pub const SPAN_SHIFT: u32 = 23;
5942    /// Offset of the UCI field.
5943    pub const UCI_SHIFT: u32 = 26;
5944    /// Offset of the EnDA field.
5945    pub const ENDA_SHIFT: u32 = 27;
5946    /// Offset of the nTLSMD field.
5947    pub const NTLSMD_SHIFT: u32 = 28;
5948    /// Offset of the LSMAOE field.
5949    pub const LSMAOE_SHIFT: u32 = 29;
5950    /// Offset of the EnIB field.
5951    pub const ENIB_SHIFT: u32 = 30;
5952    /// Offset of the EnIA field.
5953    pub const ENIA_SHIFT: u32 = 31;
5954    /// Offset of the CMOW field.
5955    pub const CMOW_SHIFT: u32 = 32;
5956    /// Offset of the MSCEn field.
5957    pub const MSCEN_SHIFT: u32 = 33;
5958    /// Offset of the EnFPM field.
5959    pub const ENFPM_SHIFT: u32 = 34;
5960    /// Offset of the BT0 field.
5961    pub const BT0_SHIFT: u32 = 35;
5962    /// Offset of the BT1 field.
5963    pub const BT1_SHIFT: u32 = 36;
5964    /// Offset of the ITFSB field.
5965    pub const ITFSB_SHIFT: u32 = 37;
5966    /// Offset of the TCF0 field.
5967    pub const TCF0_SHIFT: u32 = 38;
5968    /// Mask for the TCF0 field.
5969    pub const TCF0_MASK: u64 = 0b11;
5970    /// Offset of the TCF field.
5971    pub const TCF_SHIFT: u32 = 40;
5972    /// Mask for the TCF field.
5973    pub const TCF_MASK: u64 = 0b11;
5974    /// Offset of the ATA0 field.
5975    pub const ATA0_SHIFT: u32 = 42;
5976    /// Offset of the ATA field.
5977    pub const ATA_SHIFT: u32 = 43;
5978    /// Offset of the DSSBS field.
5979    pub const DSSBS_SHIFT: u32 = 44;
5980    /// Offset of the TWEDEn field.
5981    pub const TWEDEN_SHIFT: u32 = 45;
5982    /// Offset of the TWEDEL field.
5983    pub const TWEDEL_SHIFT: u32 = 46;
5984    /// Mask for the TWEDEL field.
5985    pub const TWEDEL_MASK: u64 = 0b1111;
5986    /// Offset of the EnASR field.
5987    pub const ENASR_SHIFT: u32 = 54;
5988    /// Offset of the EnAS0 field.
5989    pub const ENAS0_SHIFT: u32 = 55;
5990    /// Offset of the EnALS field.
5991    pub const ENALS_SHIFT: u32 = 56;
5992    /// Offset of the EPAN field.
5993    pub const EPAN_SHIFT: u32 = 57;
5994    /// Offset of the TCSO0 field.
5995    pub const TCSO0_SHIFT: u32 = 58;
5996    /// Offset of the TCSO field.
5997    pub const TCSO_SHIFT: u32 = 59;
5998    /// Offset of the EnTP2 field.
5999    pub const ENTP2_SHIFT: u32 = 60;
6000    /// Offset of the NMI field.
6001    pub const NMI_SHIFT: u32 = 61;
6002    /// Offset of the SPINTMASK field.
6003    pub const SPINTMASK_SHIFT: u32 = 62;
6004    /// Offset of the TIDCP field.
6005    pub const TIDCP_SHIFT: u32 = 63;
6006
6007    /// Returns the value of the `TCF0` field.
6008    pub const fn tcf0(self) -> u8 {
6009        ((self.bits() >> Self::TCF0_SHIFT) & 0b11) as u8
6010    }
6011
6012    /// Returns the value of the `TCF` field.
6013    pub const fn tcf(self) -> u8 {
6014        ((self.bits() >> Self::TCF_SHIFT) & 0b11) as u8
6015    }
6016
6017    /// Returns the value of the `TWEDEL` field.
6018    pub const fn twedel(self) -> u8 {
6019        ((self.bits() >> Self::TWEDEL_SHIFT) & 0b1111) as u8
6020    }
6021}
6022
6023#[cfg(feature = "el2")]
6024bitflags! {
6025    /// `SCTLR_EL2` system register value.
6026    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
6027    #[repr(transparent)]
6028    pub struct SctlrEl2: u64 {
6029        /// `M` bit.
6030        const M = 1 << 0;
6031        /// `A` bit.
6032        const A = 1 << 1;
6033        /// `C` bit.
6034        const C = 1 << 2;
6035        /// `SA` bit.
6036        const SA = 1 << 3;
6037        /// `SA0` bit.
6038        const SA0 = 1 << 4;
6039        /// `CP15BEN` bit.
6040        const CP15BEN = 1 << 5;
6041        /// `nAA` bit.
6042        const NAA = 1 << 6;
6043        /// `SED` bit.
6044        const SED = 1 << 8;
6045        /// `UMA` bit.
6046        const UMA = 1 << 9;
6047        /// `EnRCTX` bit.
6048        const ENRCTX = 1 << 10;
6049        /// `EOS` bit.
6050        const EOS = 1 << 11;
6051        /// `I` bit.
6052        const I = 1 << 12;
6053        /// `EnDB` bit.
6054        const ENDB = 1 << 13;
6055        /// `DZE` bit.
6056        const DZE = 1 << 14;
6057        /// `UCT` bit.
6058        const UCT = 1 << 15;
6059        /// `nTWI` bit.
6060        const NTWI = 1 << 16;
6061        /// `nTWE` bit.
6062        const NTWE = 1 << 18;
6063        /// `WXN` bit.
6064        const WXN = 1 << 19;
6065        /// `IESB` bit.
6066        const IESB = 1 << 21;
6067        /// `EIS` bit.
6068        const EIS = 1 << 22;
6069        /// Do not set Privileged Access Never, on taking an exception to EL2.
6070        const SPAN = 1 << 23;
6071        /// `UCI` bit.
6072        const UCI = 1 << 26;
6073        /// `EnDA` bit.
6074        const ENDA = 1 << 27;
6075        /// `nTLSMD` bit.
6076        const NTLSMD = 1 << 28;
6077        /// `LSMAOE` bit.
6078        const LSMAOE = 1 << 29;
6079        /// Enable pointer authentication using APIBKey_EL1.
6080        const ENIB = 1 << 30;
6081        /// Enable pointer authentication using APIAKey_EL1.
6082        const ENIA = 1 << 31;
6083        /// `CMOW` bit.
6084        const CMOW = 1 << 32;
6085        /// `MSCEn` bit.
6086        const MSCEN = 1 << 33;
6087        /// `EnFPM` bit.
6088        const ENFPM = 1 << 34;
6089        /// `BT0` bit.
6090        const BT0 = 1 << 35;
6091        /// `BT` bit.
6092        const BT = 1 << 36;
6093        /// `ITFSB` bit.
6094        const ITFSB = 1 << 37;
6095        /// `ATA0` bit.
6096        const ATA0 = 1 << 42;
6097        /// `ATA` bit.
6098        const ATA = 1 << 43;
6099        /// Default PSTATE.SSBS value on Exception Entry.
6100        const DSSBS = 1 << 44;
6101        /// `TWEDEn` bit.
6102        const TWEDEN = 1 << 45;
6103        /// `EnASR` bit.
6104        const ENASR = 1 << 54;
6105        /// `EnAS0` bit.
6106        const ENAS0 = 1 << 55;
6107        /// `EnALS` bit.
6108        const ENALS = 1 << 56;
6109        /// `EPAN` bit.
6110        const EPAN = 1 << 57;
6111        /// `TCSO0` bit.
6112        const TCSO0 = 1 << 58;
6113        /// `TCSO` bit.
6114        const TCSO = 1 << 59;
6115        /// `EnTP2` bit.
6116        const ENTP2 = 1 << 60;
6117        /// `NMI` bit.
6118        const NMI = 1 << 61;
6119        /// SP Interrupt Mask enable.
6120        const SPINTMASK = 1 << 62;
6121        /// `TIDCP` bit.
6122        const TIDCP = 1 << 63;
6123    }
6124}
6125
6126#[cfg(feature = "el2")]
6127impl SctlrEl2 {
6128    /// Offset of the M field.
6129    pub const M_SHIFT: u32 = 0;
6130    /// Offset of the A field.
6131    pub const A_SHIFT: u32 = 1;
6132    /// Offset of the C field.
6133    pub const C_SHIFT: u32 = 2;
6134    /// Offset of the SA field.
6135    pub const SA_SHIFT: u32 = 3;
6136    /// Offset of the SA0 field.
6137    pub const SA0_SHIFT: u32 = 4;
6138    /// Offset of the CP15BEN field.
6139    pub const CP15BEN_SHIFT: u32 = 5;
6140    /// Offset of the nAA field.
6141    pub const NAA_SHIFT: u32 = 6;
6142    /// Offset of the SED field.
6143    pub const SED_SHIFT: u32 = 8;
6144    /// Offset of the UMA field.
6145    pub const UMA_SHIFT: u32 = 9;
6146    /// Offset of the EnRCTX field.
6147    pub const ENRCTX_SHIFT: u32 = 10;
6148    /// Offset of the EOS field.
6149    pub const EOS_SHIFT: u32 = 11;
6150    /// Offset of the I field.
6151    pub const I_SHIFT: u32 = 12;
6152    /// Offset of the EnDB field.
6153    pub const ENDB_SHIFT: u32 = 13;
6154    /// Offset of the DZE field.
6155    pub const DZE_SHIFT: u32 = 14;
6156    /// Offset of the UCT field.
6157    pub const UCT_SHIFT: u32 = 15;
6158    /// Offset of the nTWI field.
6159    pub const NTWI_SHIFT: u32 = 16;
6160    /// Offset of the nTWE field.
6161    pub const NTWE_SHIFT: u32 = 18;
6162    /// Offset of the WXN field.
6163    pub const WXN_SHIFT: u32 = 19;
6164    /// Offset of the IESB field.
6165    pub const IESB_SHIFT: u32 = 21;
6166    /// Offset of the EIS field.
6167    pub const EIS_SHIFT: u32 = 22;
6168    /// Offset of the SPAN field.
6169    pub const SPAN_SHIFT: u32 = 23;
6170    /// Offset of the UCI field.
6171    pub const UCI_SHIFT: u32 = 26;
6172    /// Offset of the EnDA field.
6173    pub const ENDA_SHIFT: u32 = 27;
6174    /// Offset of the nTLSMD field.
6175    pub const NTLSMD_SHIFT: u32 = 28;
6176    /// Offset of the LSMAOE field.
6177    pub const LSMAOE_SHIFT: u32 = 29;
6178    /// Offset of the EnIB field.
6179    pub const ENIB_SHIFT: u32 = 30;
6180    /// Offset of the EnIA field.
6181    pub const ENIA_SHIFT: u32 = 31;
6182    /// Offset of the CMOW field.
6183    pub const CMOW_SHIFT: u32 = 32;
6184    /// Offset of the MSCEn field.
6185    pub const MSCEN_SHIFT: u32 = 33;
6186    /// Offset of the EnFPM field.
6187    pub const ENFPM_SHIFT: u32 = 34;
6188    /// Offset of the BT0 field.
6189    pub const BT0_SHIFT: u32 = 35;
6190    /// Offset of the BT field.
6191    pub const BT_SHIFT: u32 = 36;
6192    /// Offset of the ITFSB field.
6193    pub const ITFSB_SHIFT: u32 = 37;
6194    /// Offset of the TCF0 field.
6195    pub const TCF0_SHIFT: u32 = 38;
6196    /// Mask for the TCF0 field.
6197    pub const TCF0_MASK: u64 = 0b11;
6198    /// Offset of the TCF field.
6199    pub const TCF_SHIFT: u32 = 40;
6200    /// Mask for the TCF field.
6201    pub const TCF_MASK: u64 = 0b11;
6202    /// Offset of the ATA0 field.
6203    pub const ATA0_SHIFT: u32 = 42;
6204    /// Offset of the ATA field.
6205    pub const ATA_SHIFT: u32 = 43;
6206    /// Offset of the DSSBS field.
6207    pub const DSSBS_SHIFT: u32 = 44;
6208    /// Offset of the TWEDEn field.
6209    pub const TWEDEN_SHIFT: u32 = 45;
6210    /// Offset of the TWEDEL field.
6211    pub const TWEDEL_SHIFT: u32 = 46;
6212    /// Mask for the TWEDEL field.
6213    pub const TWEDEL_MASK: u64 = 0b1111;
6214    /// Offset of the EnASR field.
6215    pub const ENASR_SHIFT: u32 = 54;
6216    /// Offset of the EnAS0 field.
6217    pub const ENAS0_SHIFT: u32 = 55;
6218    /// Offset of the EnALS field.
6219    pub const ENALS_SHIFT: u32 = 56;
6220    /// Offset of the EPAN field.
6221    pub const EPAN_SHIFT: u32 = 57;
6222    /// Offset of the TCSO0 field.
6223    pub const TCSO0_SHIFT: u32 = 58;
6224    /// Offset of the TCSO field.
6225    pub const TCSO_SHIFT: u32 = 59;
6226    /// Offset of the EnTP2 field.
6227    pub const ENTP2_SHIFT: u32 = 60;
6228    /// Offset of the NMI field.
6229    pub const NMI_SHIFT: u32 = 61;
6230    /// Offset of the SPINTMASK field.
6231    pub const SPINTMASK_SHIFT: u32 = 62;
6232    /// Offset of the TIDCP field.
6233    pub const TIDCP_SHIFT: u32 = 63;
6234
6235    /// Returns the value of the `TCF0` field.
6236    pub const fn tcf0(self) -> u8 {
6237        ((self.bits() >> Self::TCF0_SHIFT) & 0b11) as u8
6238    }
6239
6240    /// Returns the value of the `TCF` field.
6241    pub const fn tcf(self) -> u8 {
6242        ((self.bits() >> Self::TCF_SHIFT) & 0b11) as u8
6243    }
6244
6245    /// Returns the value of the `TWEDEL` field.
6246    pub const fn twedel(self) -> u8 {
6247        ((self.bits() >> Self::TWEDEL_SHIFT) & 0b1111) as u8
6248    }
6249}
6250
6251#[cfg(feature = "el3")]
6252bitflags! {
6253    /// `SCTLR_EL3` system register value.
6254    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
6255    #[repr(transparent)]
6256    pub struct SctlrEl3: u64 {
6257        /// RES1 bits in the `SCTLR_EL3` register.
6258        const RES1 = 0b110000100001010000000000110000;
6259        /// MMU enable for EL3 stage 1 address translation.
6260        const M = 1 << 0;
6261        /// Alignment check enable.
6262        const A = 1 << 1;
6263        /// Cacheability control, for data accesses at EL3.
6264        const C = 1 << 2;
6265        /// SP alignment check enable.
6266        const SA = 1 << 3;
6267        /// `nAA` bit.
6268        const NAA = 1 << 6;
6269        /// `EOS` bit.
6270        const EOS = 1 << 11;
6271        /// Cacheability control, for instruction accesses at EL3.
6272        const I = 1 << 12;
6273        /// `EnDB` bit.
6274        const ENDB = 1 << 13;
6275        /// Write permission implies XN (Execute-never). For the EL3 translation regime, this bit can force all memory regions that are writable to be treated as XN.
6276        const WXN = 1 << 19;
6277        /// Enable Implicit Error Synchronization events.
6278        const IESB = 1 << 21;
6279        /// `EIS` bit.
6280        const EIS = 1 << 22;
6281        /// `EnDA` bit.
6282        const ENDA = 1 << 27;
6283        /// Enable pointer authentication using APIBKey_EL1.
6284        const ENIB = 1 << 30;
6285        /// Enable pointer authentication using APIAKey_EL1.
6286        const ENIA = 1 << 31;
6287        /// `BT` bit.
6288        const BT = 1 << 36;
6289        /// `ITFSB` bit.
6290        const ITFSB = 1 << 37;
6291        /// `ATA` bit.
6292        const ATA = 1 << 43;
6293        /// `DSSBS` bit.
6294        const DSSBS = 1 << 44;
6295        /// `TCSO` bit.
6296        const TCSO = 1 << 59;
6297        /// `NMI` bit.
6298        const NMI = 1 << 61;
6299        /// `SPINTMASK` bit.
6300        const SPINTMASK = 1 << 62;
6301    }
6302}
6303
6304#[cfg(feature = "el3")]
6305impl SctlrEl3 {
6306    /// Offset of the M field.
6307    pub const M_SHIFT: u32 = 0;
6308    /// Offset of the A field.
6309    pub const A_SHIFT: u32 = 1;
6310    /// Offset of the C field.
6311    pub const C_SHIFT: u32 = 2;
6312    /// Offset of the SA field.
6313    pub const SA_SHIFT: u32 = 3;
6314    /// Offset of the nAA field.
6315    pub const NAA_SHIFT: u32 = 6;
6316    /// Offset of the EOS field.
6317    pub const EOS_SHIFT: u32 = 11;
6318    /// Offset of the I field.
6319    pub const I_SHIFT: u32 = 12;
6320    /// Offset of the EnDB field.
6321    pub const ENDB_SHIFT: u32 = 13;
6322    /// Offset of the WXN field.
6323    pub const WXN_SHIFT: u32 = 19;
6324    /// Offset of the IESB field.
6325    pub const IESB_SHIFT: u32 = 21;
6326    /// Offset of the EIS field.
6327    pub const EIS_SHIFT: u32 = 22;
6328    /// Offset of the EnDA field.
6329    pub const ENDA_SHIFT: u32 = 27;
6330    /// Offset of the EnIB field.
6331    pub const ENIB_SHIFT: u32 = 30;
6332    /// Offset of the EnIA field.
6333    pub const ENIA_SHIFT: u32 = 31;
6334    /// Offset of the BT field.
6335    pub const BT_SHIFT: u32 = 36;
6336    /// Offset of the ITFSB field.
6337    pub const ITFSB_SHIFT: u32 = 37;
6338    /// Offset of the TCF field.
6339    pub const TCF_SHIFT: u32 = 40;
6340    /// Mask for the TCF field.
6341    pub const TCF_MASK: u64 = 0b11;
6342    /// Offset of the ATA field.
6343    pub const ATA_SHIFT: u32 = 43;
6344    /// Offset of the DSSBS field.
6345    pub const DSSBS_SHIFT: u32 = 44;
6346    /// Offset of the TCSO field.
6347    pub const TCSO_SHIFT: u32 = 59;
6348    /// Offset of the NMI field.
6349    pub const NMI_SHIFT: u32 = 61;
6350    /// Offset of the SPINTMASK field.
6351    pub const SPINTMASK_SHIFT: u32 = 62;
6352
6353    /// Returns the value of the `TCF` field.
6354    pub const fn tcf(self) -> u8 {
6355        ((self.bits() >> Self::TCF_SHIFT) & 0b11) as u8
6356    }
6357}
6358
6359#[cfg(feature = "el3")]
6360bitflags! {
6361    /// `SMCR_EL3` system register value.
6362    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
6363    #[repr(transparent)]
6364    pub struct SmcrEl3: u64 {
6365        /// `EZT0` bit.
6366        const EZT0 = 1 << 30;
6367        /// `FA64` bit.
6368        const FA64 = 1 << 31;
6369    }
6370}
6371
6372#[cfg(feature = "el3")]
6373impl SmcrEl3 {
6374    /// Offset of the LEN field.
6375    pub const LEN_SHIFT: u32 = 0;
6376    /// Mask for the LEN field.
6377    pub const LEN_MASK: u64 = 0b1111;
6378    /// Offset of the EZT0 field.
6379    pub const EZT0_SHIFT: u32 = 30;
6380    /// Offset of the FA64 field.
6381    pub const FA64_SHIFT: u32 = 31;
6382
6383    /// Returns the value of the `LEN` field.
6384    pub const fn len(self) -> u8 {
6385        ((self.bits() >> Self::LEN_SHIFT) & 0b1111) as u8
6386    }
6387}
6388
6389#[cfg(feature = "el1")]
6390bitflags! {
6391    /// `SPSR_EL1` system register value.
6392    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
6393    #[repr(transparent)]
6394    pub struct SpsrEl1: u64 {
6395        /// `M[4]` bit.
6396        const M_4 = 1 << 4;
6397        /// `T` bit.
6398        const T = 1 << 5;
6399        /// `F` bit.
6400        const F = 1 << 6;
6401        /// `I` bit.
6402        const I = 1 << 7;
6403        /// `A` bit.
6404        const A = 1 << 8;
6405        /// `D` bit.
6406        const D = 1 << 9;
6407        /// `E` bit.
6408        const E = 1 << 9;
6409        /// `ALLINT` bit.
6410        const ALLINT = 1 << 13;
6411        /// `BTYPE2` bit.
6412        const BTYPE2 = 1 << 14;
6413        /// `IL` bit.
6414        const IL = 1 << 20;
6415        /// `SS` bit.
6416        const SS = 1 << 21;
6417        /// `PAN` bit.
6418        const PAN = 1 << 22;
6419        /// `UAO` bit.
6420        const UAO = 1 << 23;
6421        /// `DIT` bit.
6422        const DIT = 1 << 24;
6423        /// `TCO` bit.
6424        const TCO = 1 << 25;
6425        /// `Q` bit.
6426        const Q = 1 << 27;
6427        /// `V` bit.
6428        const V = 1 << 28;
6429        /// `C` bit.
6430        const C = 1 << 29;
6431        /// `Z` bit.
6432        const Z = 1 << 30;
6433        /// `N` bit.
6434        const N = 1 << 31;
6435        /// `PM` bit.
6436        const PM = 1 << 32;
6437        /// `PPEND` bit.
6438        const PPEND = 1 << 33;
6439        /// `EXLOCK` bit.
6440        const EXLOCK = 1 << 34;
6441        /// `PACM` bit.
6442        const PACM = 1 << 35;
6443        /// `UINJ` bit.
6444        const UINJ = 1 << 36;
6445    }
6446}
6447
6448#[cfg(feature = "el1")]
6449impl SpsrEl1 {
6450    /// Offset of the M[3:0] field.
6451    pub const M_3_0_SHIFT: u32 = 0;
6452    /// Mask for the M[3:0] field.
6453    pub const M_3_0_MASK: u64 = 0b1111;
6454    /// Offset of the M[4] field.
6455    pub const M_4_SHIFT: u32 = 4;
6456    /// Offset of the T field.
6457    pub const T_SHIFT: u32 = 5;
6458    /// Offset of the F field.
6459    pub const F_SHIFT: u32 = 6;
6460    /// Offset of the I field.
6461    pub const I_SHIFT: u32 = 7;
6462    /// Offset of the A field.
6463    pub const A_SHIFT: u32 = 8;
6464    /// Offset of the D field.
6465    pub const D_SHIFT: u32 = 9;
6466    /// Offset of the E field.
6467    pub const E_SHIFT: u32 = 9;
6468    /// Offset of the BTYPE field.
6469    pub const BTYPE_SHIFT: u32 = 10;
6470    /// Mask for the BTYPE field.
6471    pub const BTYPE_MASK: u64 = 0b11;
6472    /// Offset of the ALLINT field.
6473    pub const ALLINT_SHIFT: u32 = 13;
6474    /// Offset of the BTYPE2 field.
6475    pub const BTYPE2_SHIFT: u32 = 14;
6476    /// Offset of the GE field.
6477    pub const GE_SHIFT: u32 = 16;
6478    /// Mask for the GE field.
6479    pub const GE_MASK: u64 = 0b1111;
6480    /// Offset of the IL field.
6481    pub const IL_SHIFT: u32 = 20;
6482    /// Offset of the SS field.
6483    pub const SS_SHIFT: u32 = 21;
6484    /// Offset of the PAN field.
6485    pub const PAN_SHIFT: u32 = 22;
6486    /// Offset of the UAO field.
6487    pub const UAO_SHIFT: u32 = 23;
6488    /// Offset of the DIT field.
6489    pub const DIT_SHIFT: u32 = 24;
6490    /// Offset of the TCO field.
6491    pub const TCO_SHIFT: u32 = 25;
6492    /// Offset of the Q field.
6493    pub const Q_SHIFT: u32 = 27;
6494    /// Offset of the V field.
6495    pub const V_SHIFT: u32 = 28;
6496    /// Offset of the C field.
6497    pub const C_SHIFT: u32 = 29;
6498    /// Offset of the Z field.
6499    pub const Z_SHIFT: u32 = 30;
6500    /// Offset of the N field.
6501    pub const N_SHIFT: u32 = 31;
6502    /// Offset of the PM field.
6503    pub const PM_SHIFT: u32 = 32;
6504    /// Offset of the PPEND field.
6505    pub const PPEND_SHIFT: u32 = 33;
6506    /// Offset of the EXLOCK field.
6507    pub const EXLOCK_SHIFT: u32 = 34;
6508    /// Offset of the PACM field.
6509    pub const PACM_SHIFT: u32 = 35;
6510    /// Offset of the UINJ field.
6511    pub const UINJ_SHIFT: u32 = 36;
6512
6513    /// Returns the value of the `M[3:0]` field.
6514    pub const fn m_3_0(self) -> u8 {
6515        ((self.bits() >> Self::M_3_0_SHIFT) & 0b1111) as u8
6516    }
6517
6518    /// Returns the value of the `BTYPE` field.
6519    pub const fn btype(self) -> u8 {
6520        ((self.bits() >> Self::BTYPE_SHIFT) & 0b11) as u8
6521    }
6522
6523    /// Returns the value of the `GE` field.
6524    pub const fn ge(self) -> u8 {
6525        ((self.bits() >> Self::GE_SHIFT) & 0b1111) as u8
6526    }
6527}
6528
6529#[cfg(feature = "el2")]
6530bitflags! {
6531    /// `SPSR_EL2` system register value.
6532    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
6533    #[repr(transparent)]
6534    pub struct SpsrEl2: u64 {
6535        /// `M[4]` bit.
6536        const M_4 = 1 << 4;
6537        /// `T` bit.
6538        const T = 1 << 5;
6539        /// `F` bit.
6540        const F = 1 << 6;
6541        /// `I` bit.
6542        const I = 1 << 7;
6543        /// `A` bit.
6544        const A = 1 << 8;
6545        /// `D` bit.
6546        const D = 1 << 9;
6547        /// `E` bit.
6548        const E = 1 << 9;
6549        /// `ALLINT` bit.
6550        const ALLINT = 1 << 13;
6551        /// `BTYPE2` bit.
6552        const BTYPE2 = 1 << 14;
6553        /// `IL` bit.
6554        const IL = 1 << 20;
6555        /// `SS` bit.
6556        const SS = 1 << 21;
6557        /// `PAN` bit.
6558        const PAN = 1 << 22;
6559        /// `UAO` bit.
6560        const UAO = 1 << 23;
6561        /// `DIT` bit.
6562        const DIT = 1 << 24;
6563        /// `TCO` bit.
6564        const TCO = 1 << 25;
6565        /// `Q` bit.
6566        const Q = 1 << 27;
6567        /// `V` bit.
6568        const V = 1 << 28;
6569        /// `C` bit.
6570        const C = 1 << 29;
6571        /// `Z` bit.
6572        const Z = 1 << 30;
6573        /// `N` bit.
6574        const N = 1 << 31;
6575        /// `PM` bit.
6576        const PM = 1 << 32;
6577        /// `PPEND` bit.
6578        const PPEND = 1 << 33;
6579        /// `EXLOCK` bit.
6580        const EXLOCK = 1 << 34;
6581        /// `PACM` bit.
6582        const PACM = 1 << 35;
6583        /// `UINJ` bit.
6584        const UINJ = 1 << 36;
6585    }
6586}
6587
6588#[cfg(feature = "el2")]
6589impl SpsrEl2 {
6590    /// Offset of the M[3:0] field.
6591    pub const M_3_0_SHIFT: u32 = 0;
6592    /// Mask for the M[3:0] field.
6593    pub const M_3_0_MASK: u64 = 0b1111;
6594    /// Offset of the M[4] field.
6595    pub const M_4_SHIFT: u32 = 4;
6596    /// Offset of the T field.
6597    pub const T_SHIFT: u32 = 5;
6598    /// Offset of the F field.
6599    pub const F_SHIFT: u32 = 6;
6600    /// Offset of the I field.
6601    pub const I_SHIFT: u32 = 7;
6602    /// Offset of the A field.
6603    pub const A_SHIFT: u32 = 8;
6604    /// Offset of the D field.
6605    pub const D_SHIFT: u32 = 9;
6606    /// Offset of the E field.
6607    pub const E_SHIFT: u32 = 9;
6608    /// Offset of the BTYPE field.
6609    pub const BTYPE_SHIFT: u32 = 10;
6610    /// Mask for the BTYPE field.
6611    pub const BTYPE_MASK: u64 = 0b11;
6612    /// Offset of the ALLINT field.
6613    pub const ALLINT_SHIFT: u32 = 13;
6614    /// Offset of the BTYPE2 field.
6615    pub const BTYPE2_SHIFT: u32 = 14;
6616    /// Offset of the GE field.
6617    pub const GE_SHIFT: u32 = 16;
6618    /// Mask for the GE field.
6619    pub const GE_MASK: u64 = 0b1111;
6620    /// Offset of the IL field.
6621    pub const IL_SHIFT: u32 = 20;
6622    /// Offset of the SS field.
6623    pub const SS_SHIFT: u32 = 21;
6624    /// Offset of the PAN field.
6625    pub const PAN_SHIFT: u32 = 22;
6626    /// Offset of the UAO field.
6627    pub const UAO_SHIFT: u32 = 23;
6628    /// Offset of the DIT field.
6629    pub const DIT_SHIFT: u32 = 24;
6630    /// Offset of the TCO field.
6631    pub const TCO_SHIFT: u32 = 25;
6632    /// Offset of the Q field.
6633    pub const Q_SHIFT: u32 = 27;
6634    /// Offset of the V field.
6635    pub const V_SHIFT: u32 = 28;
6636    /// Offset of the C field.
6637    pub const C_SHIFT: u32 = 29;
6638    /// Offset of the Z field.
6639    pub const Z_SHIFT: u32 = 30;
6640    /// Offset of the N field.
6641    pub const N_SHIFT: u32 = 31;
6642    /// Offset of the PM field.
6643    pub const PM_SHIFT: u32 = 32;
6644    /// Offset of the PPEND field.
6645    pub const PPEND_SHIFT: u32 = 33;
6646    /// Offset of the EXLOCK field.
6647    pub const EXLOCK_SHIFT: u32 = 34;
6648    /// Offset of the PACM field.
6649    pub const PACM_SHIFT: u32 = 35;
6650    /// Offset of the UINJ field.
6651    pub const UINJ_SHIFT: u32 = 36;
6652
6653    /// Returns the value of the `M[3:0]` field.
6654    pub const fn m_3_0(self) -> u8 {
6655        ((self.bits() >> Self::M_3_0_SHIFT) & 0b1111) as u8
6656    }
6657
6658    /// Returns the value of the `BTYPE` field.
6659    pub const fn btype(self) -> u8 {
6660        ((self.bits() >> Self::BTYPE_SHIFT) & 0b11) as u8
6661    }
6662
6663    /// Returns the value of the `GE` field.
6664    pub const fn ge(self) -> u8 {
6665        ((self.bits() >> Self::GE_SHIFT) & 0b1111) as u8
6666    }
6667}
6668
6669#[cfg(feature = "el3")]
6670bitflags! {
6671    /// `SPSR_EL3` system register value.
6672    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
6673    #[repr(transparent)]
6674    pub struct SpsrEl3: u64 {
6675        /// `M[4]` bit.
6676        const M_4 = 1 << 4;
6677        /// `T` bit.
6678        const T = 1 << 5;
6679        /// `F` bit.
6680        const F = 1 << 6;
6681        /// `I` bit.
6682        const I = 1 << 7;
6683        /// `A` bit.
6684        const A = 1 << 8;
6685        /// `D` bit.
6686        const D = 1 << 9;
6687        /// `E` bit.
6688        const E = 1 << 9;
6689        /// `ALLINT` bit.
6690        const ALLINT = 1 << 13;
6691        /// `BTYPE2` bit.
6692        const BTYPE2 = 1 << 14;
6693        /// `IL` bit.
6694        const IL = 1 << 20;
6695        /// `SS` bit.
6696        const SS = 1 << 21;
6697        /// `PAN` bit.
6698        const PAN = 1 << 22;
6699        /// `UAO` bit.
6700        const UAO = 1 << 23;
6701        /// `DIT` bit.
6702        const DIT = 1 << 24;
6703        /// `TCO` bit.
6704        const TCO = 1 << 25;
6705        /// `Q` bit.
6706        const Q = 1 << 27;
6707        /// `V` bit.
6708        const V = 1 << 28;
6709        /// `C` bit.
6710        const C = 1 << 29;
6711        /// `Z` bit.
6712        const Z = 1 << 30;
6713        /// `N` bit.
6714        const N = 1 << 31;
6715        /// `PM` bit.
6716        const PM = 1 << 32;
6717        /// `PPEND` bit.
6718        const PPEND = 1 << 33;
6719        /// `EXLOCK` bit.
6720        const EXLOCK = 1 << 34;
6721        /// `PACM` bit.
6722        const PACM = 1 << 35;
6723        /// `UINJ` bit.
6724        const UINJ = 1 << 36;
6725    }
6726}
6727
6728#[cfg(feature = "el3")]
6729impl SpsrEl3 {
6730    /// Offset of the M[3:0] field.
6731    pub const M_3_0_SHIFT: u32 = 0;
6732    /// Mask for the M[3:0] field.
6733    pub const M_3_0_MASK: u64 = 0b1111;
6734    /// Offset of the M[4] field.
6735    pub const M_4_SHIFT: u32 = 4;
6736    /// Offset of the T field.
6737    pub const T_SHIFT: u32 = 5;
6738    /// Offset of the F field.
6739    pub const F_SHIFT: u32 = 6;
6740    /// Offset of the I field.
6741    pub const I_SHIFT: u32 = 7;
6742    /// Offset of the A field.
6743    pub const A_SHIFT: u32 = 8;
6744    /// Offset of the D field.
6745    pub const D_SHIFT: u32 = 9;
6746    /// Offset of the E field.
6747    pub const E_SHIFT: u32 = 9;
6748    /// Offset of the BTYPE field.
6749    pub const BTYPE_SHIFT: u32 = 10;
6750    /// Mask for the BTYPE field.
6751    pub const BTYPE_MASK: u64 = 0b11;
6752    /// Offset of the ALLINT field.
6753    pub const ALLINT_SHIFT: u32 = 13;
6754    /// Offset of the BTYPE2 field.
6755    pub const BTYPE2_SHIFT: u32 = 14;
6756    /// Offset of the GE field.
6757    pub const GE_SHIFT: u32 = 16;
6758    /// Mask for the GE field.
6759    pub const GE_MASK: u64 = 0b1111;
6760    /// Offset of the IL field.
6761    pub const IL_SHIFT: u32 = 20;
6762    /// Offset of the SS field.
6763    pub const SS_SHIFT: u32 = 21;
6764    /// Offset of the PAN field.
6765    pub const PAN_SHIFT: u32 = 22;
6766    /// Offset of the UAO field.
6767    pub const UAO_SHIFT: u32 = 23;
6768    /// Offset of the DIT field.
6769    pub const DIT_SHIFT: u32 = 24;
6770    /// Offset of the TCO field.
6771    pub const TCO_SHIFT: u32 = 25;
6772    /// Offset of the Q field.
6773    pub const Q_SHIFT: u32 = 27;
6774    /// Offset of the V field.
6775    pub const V_SHIFT: u32 = 28;
6776    /// Offset of the C field.
6777    pub const C_SHIFT: u32 = 29;
6778    /// Offset of the Z field.
6779    pub const Z_SHIFT: u32 = 30;
6780    /// Offset of the N field.
6781    pub const N_SHIFT: u32 = 31;
6782    /// Offset of the PM field.
6783    pub const PM_SHIFT: u32 = 32;
6784    /// Offset of the PPEND field.
6785    pub const PPEND_SHIFT: u32 = 33;
6786    /// Offset of the EXLOCK field.
6787    pub const EXLOCK_SHIFT: u32 = 34;
6788    /// Offset of the PACM field.
6789    pub const PACM_SHIFT: u32 = 35;
6790    /// Offset of the UINJ field.
6791    pub const UINJ_SHIFT: u32 = 36;
6792
6793    /// Returns the value of the `M[3:0]` field.
6794    pub const fn m_3_0(self) -> u8 {
6795        ((self.bits() >> Self::M_3_0_SHIFT) & 0b1111) as u8
6796    }
6797
6798    /// Returns the value of the `BTYPE` field.
6799    pub const fn btype(self) -> u8 {
6800        ((self.bits() >> Self::BTYPE_SHIFT) & 0b11) as u8
6801    }
6802
6803    /// Returns the value of the `GE` field.
6804    pub const fn ge(self) -> u8 {
6805        ((self.bits() >> Self::GE_SHIFT) & 0b1111) as u8
6806    }
6807}
6808
6809#[cfg(feature = "el1")]
6810bitflags! {
6811    /// `SP_EL1` system register value.
6812    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
6813    #[repr(transparent)]
6814    pub struct SpEl1: u64 {
6815    }
6816}
6817
6818#[cfg(feature = "el1")]
6819impl SpEl1 {
6820    /// Offset of the StackPointer field.
6821    pub const STACKPOINTER_SHIFT: u32 = 0;
6822    /// Mask for the StackPointer field.
6823    pub const STACKPOINTER_MASK: u64 =
6824        0b1111111111111111111111111111111111111111111111111111111111111111;
6825
6826    /// Returns the value of the `StackPointer` field.
6827    pub const fn stackpointer(self) -> u64 {
6828        ((self.bits() >> Self::STACKPOINTER_SHIFT)
6829            & 0b1111111111111111111111111111111111111111111111111111111111111111) as u64
6830    }
6831}
6832
6833#[cfg(feature = "el2")]
6834bitflags! {
6835    /// `SP_EL2` system register value.
6836    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
6837    #[repr(transparent)]
6838    pub struct SpEl2: u64 {
6839    }
6840}
6841
6842#[cfg(feature = "el2")]
6843impl SpEl2 {
6844    /// Offset of the StackPointer field.
6845    pub const STACKPOINTER_SHIFT: u32 = 0;
6846    /// Mask for the StackPointer field.
6847    pub const STACKPOINTER_MASK: u64 =
6848        0b1111111111111111111111111111111111111111111111111111111111111111;
6849
6850    /// Returns the value of the `StackPointer` field.
6851    pub const fn stackpointer(self) -> u64 {
6852        ((self.bits() >> Self::STACKPOINTER_SHIFT)
6853            & 0b1111111111111111111111111111111111111111111111111111111111111111) as u64
6854    }
6855}
6856
6857#[cfg(feature = "el1")]
6858bitflags! {
6859    /// `TCR2_EL1` system register value.
6860    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
6861    #[repr(transparent)]
6862    pub struct Tcr2El1: u64 {
6863        /// `PnCH` bit.
6864        const PNCH = 1 << 0;
6865        /// `PIE` bit.
6866        const PIE = 1 << 1;
6867        /// `E0POE` bit.
6868        const E0POE = 1 << 2;
6869        /// `POE` bit.
6870        const POE = 1 << 3;
6871        /// `AIE` bit.
6872        const AIE = 1 << 4;
6873        /// `D128` bit.
6874        const D128 = 1 << 5;
6875        /// `PTTWI` bit.
6876        const PTTWI = 1 << 10;
6877        /// `HAFT` bit.
6878        const HAFT = 1 << 11;
6879        /// `DisCH0` bit.
6880        const DISCH0 = 1 << 14;
6881        /// `DisCH1` bit.
6882        const DISCH1 = 1 << 15;
6883        /// `A2` bit.
6884        const A2 = 1 << 16;
6885        /// `FNG0` bit.
6886        const FNG0 = 1 << 17;
6887        /// `FNG1` bit.
6888        const FNG1 = 1 << 18;
6889        /// `POE2F` bit.
6890        const POE2F = 1 << 19;
6891        /// `FNGNA0` bit.
6892        const FNGNA0 = 1 << 20;
6893        /// `FNGNA1` bit.
6894        const FNGNA1 = 1 << 21;
6895        /// `TVAD0` bit.
6896        const TVAD0 = 1 << 35;
6897        /// `TVAD1` bit.
6898        const TVAD1 = 1 << 36;
6899    }
6900}
6901
6902#[cfg(feature = "el1")]
6903impl Tcr2El1 {
6904    /// Offset of the PnCH field.
6905    pub const PNCH_SHIFT: u32 = 0;
6906    /// Offset of the PIE field.
6907    pub const PIE_SHIFT: u32 = 1;
6908    /// Offset of the E0POE field.
6909    pub const E0POE_SHIFT: u32 = 2;
6910    /// Offset of the POE field.
6911    pub const POE_SHIFT: u32 = 3;
6912    /// Offset of the AIE field.
6913    pub const AIE_SHIFT: u32 = 4;
6914    /// Offset of the D128 field.
6915    pub const D128_SHIFT: u32 = 5;
6916    /// Offset of the PTTWI field.
6917    pub const PTTWI_SHIFT: u32 = 10;
6918    /// Offset of the HAFT field.
6919    pub const HAFT_SHIFT: u32 = 11;
6920    /// Offset of the DisCH0 field.
6921    pub const DISCH0_SHIFT: u32 = 14;
6922    /// Offset of the DisCH1 field.
6923    pub const DISCH1_SHIFT: u32 = 15;
6924    /// Offset of the A2 field.
6925    pub const A2_SHIFT: u32 = 16;
6926    /// Offset of the FNG0 field.
6927    pub const FNG0_SHIFT: u32 = 17;
6928    /// Offset of the FNG1 field.
6929    pub const FNG1_SHIFT: u32 = 18;
6930    /// Offset of the POE2F field.
6931    pub const POE2F_SHIFT: u32 = 19;
6932    /// Offset of the FNGNA0 field.
6933    pub const FNGNA0_SHIFT: u32 = 20;
6934    /// Offset of the FNGNA1 field.
6935    pub const FNGNA1_SHIFT: u32 = 21;
6936    /// Offset of the POIW field.
6937    pub const POIW_SHIFT: u32 = 22;
6938    /// Mask for the POIW field.
6939    pub const POIW_MASK: u64 = 0b111;
6940    /// Offset of the VTB0 field.
6941    pub const VTB0_SHIFT: u32 = 25;
6942    /// Mask for the VTB0 field.
6943    pub const VTB0_MASK: u64 = 0b11111;
6944    /// Offset of the VTB1 field.
6945    pub const VTB1_SHIFT: u32 = 30;
6946    /// Mask for the VTB1 field.
6947    pub const VTB1_MASK: u64 = 0b11111;
6948    /// Offset of the TVAD0 field.
6949    pub const TVAD0_SHIFT: u32 = 35;
6950    /// Offset of the TVAD1 field.
6951    pub const TVAD1_SHIFT: u32 = 36;
6952
6953    /// Returns the value of the `POIW` field.
6954    pub const fn poiw(self) -> u8 {
6955        ((self.bits() >> Self::POIW_SHIFT) & 0b111) as u8
6956    }
6957
6958    /// Returns the value of the `VTB0` field.
6959    pub const fn vtb0(self) -> u8 {
6960        ((self.bits() >> Self::VTB0_SHIFT) & 0b11111) as u8
6961    }
6962
6963    /// Returns the value of the `VTB1` field.
6964    pub const fn vtb1(self) -> u8 {
6965        ((self.bits() >> Self::VTB1_SHIFT) & 0b11111) as u8
6966    }
6967}
6968
6969#[cfg(feature = "el2")]
6970bitflags! {
6971    /// `TCR2_EL2` system register value.
6972    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
6973    #[repr(transparent)]
6974    pub struct Tcr2El2: u64 {
6975        /// `PnCH` bit.
6976        const PNCH = 1 << 0;
6977        /// `PIE` bit.
6978        const PIE = 1 << 1;
6979        /// `E0POE` bit.
6980        const E0POE = 1 << 2;
6981        /// `POE` bit.
6982        const POE = 1 << 3;
6983        /// `AIE` bit.
6984        const AIE = 1 << 4;
6985        /// `D128` bit.
6986        const D128 = 1 << 5;
6987        /// `PTTWI` bit.
6988        const PTTWI = 1 << 10;
6989        /// `HAFT` bit.
6990        const HAFT = 1 << 11;
6991        /// `AMEC0` bit.
6992        const AMEC0 = 1 << 12;
6993        /// `AMEC1` bit.
6994        const AMEC1 = 1 << 13;
6995        /// `DisCH0` bit.
6996        const DISCH0 = 1 << 14;
6997        /// `DisCH1` bit.
6998        const DISCH1 = 1 << 15;
6999        /// `A2` bit.
7000        const A2 = 1 << 16;
7001        /// `FNG0` bit.
7002        const FNG0 = 1 << 17;
7003        /// `FNG1` bit.
7004        const FNG1 = 1 << 18;
7005        /// `POE2F` bit.
7006        const POE2F = 1 << 19;
7007        /// `TVAD0` bit.
7008        const TVAD0 = 1 << 35;
7009        /// `TVAD1` bit.
7010        const TVAD1 = 1 << 36;
7011    }
7012}
7013
7014#[cfg(feature = "el2")]
7015impl Tcr2El2 {
7016    /// Offset of the PnCH field.
7017    pub const PNCH_SHIFT: u32 = 0;
7018    /// Offset of the PIE field.
7019    pub const PIE_SHIFT: u32 = 1;
7020    /// Offset of the E0POE field.
7021    pub const E0POE_SHIFT: u32 = 2;
7022    /// Offset of the POE field.
7023    pub const POE_SHIFT: u32 = 3;
7024    /// Offset of the AIE field.
7025    pub const AIE_SHIFT: u32 = 4;
7026    /// Offset of the D128 field.
7027    pub const D128_SHIFT: u32 = 5;
7028    /// Offset of the PTTWI field.
7029    pub const PTTWI_SHIFT: u32 = 10;
7030    /// Offset of the HAFT field.
7031    pub const HAFT_SHIFT: u32 = 11;
7032    /// Offset of the AMEC0 field.
7033    pub const AMEC0_SHIFT: u32 = 12;
7034    /// Offset of the AMEC1 field.
7035    pub const AMEC1_SHIFT: u32 = 13;
7036    /// Offset of the DisCH0 field.
7037    pub const DISCH0_SHIFT: u32 = 14;
7038    /// Offset of the DisCH1 field.
7039    pub const DISCH1_SHIFT: u32 = 15;
7040    /// Offset of the A2 field.
7041    pub const A2_SHIFT: u32 = 16;
7042    /// Offset of the FNG0 field.
7043    pub const FNG0_SHIFT: u32 = 17;
7044    /// Offset of the FNG1 field.
7045    pub const FNG1_SHIFT: u32 = 18;
7046    /// Offset of the POE2F field.
7047    pub const POE2F_SHIFT: u32 = 19;
7048    /// Offset of the POIW field.
7049    pub const POIW_SHIFT: u32 = 22;
7050    /// Mask for the POIW field.
7051    pub const POIW_MASK: u64 = 0b111;
7052    /// Offset of the VTB0 field.
7053    pub const VTB0_SHIFT: u32 = 25;
7054    /// Mask for the VTB0 field.
7055    pub const VTB0_MASK: u64 = 0b11111;
7056    /// Offset of the VTB1 field.
7057    pub const VTB1_SHIFT: u32 = 30;
7058    /// Mask for the VTB1 field.
7059    pub const VTB1_MASK: u64 = 0b11111;
7060    /// Offset of the TVAD0 field.
7061    pub const TVAD0_SHIFT: u32 = 35;
7062    /// Offset of the TVAD1 field.
7063    pub const TVAD1_SHIFT: u32 = 36;
7064
7065    /// Returns the value of the `POIW` field.
7066    pub const fn poiw(self) -> u8 {
7067        ((self.bits() >> Self::POIW_SHIFT) & 0b111) as u8
7068    }
7069
7070    /// Returns the value of the `VTB0` field.
7071    pub const fn vtb0(self) -> u8 {
7072        ((self.bits() >> Self::VTB0_SHIFT) & 0b11111) as u8
7073    }
7074
7075    /// Returns the value of the `VTB1` field.
7076    pub const fn vtb1(self) -> u8 {
7077        ((self.bits() >> Self::VTB1_SHIFT) & 0b11111) as u8
7078    }
7079}
7080
7081#[cfg(feature = "el1")]
7082bitflags! {
7083    /// `TCR_EL1` system register value.
7084    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
7085    #[repr(transparent)]
7086    pub struct TcrEl1: u64 {
7087        /// `EPD0` bit.
7088        const EPD0 = 1 << 7;
7089        /// `A1` bit.
7090        const A1 = 1 << 22;
7091        /// `EPD1` bit.
7092        const EPD1 = 1 << 23;
7093        /// `AS` bit.
7094        const AS = 1 << 36;
7095        /// `TBI0` bit.
7096        const TBI0 = 1 << 37;
7097        /// `TBI1` bit.
7098        const TBI1 = 1 << 38;
7099        /// `HA` bit.
7100        const HA = 1 << 39;
7101        /// `HD` bit.
7102        const HD = 1 << 40;
7103        /// `HPD0` bit.
7104        const HPD0 = 1 << 41;
7105        /// `HPD1` bit.
7106        const HPD1 = 1 << 42;
7107        /// `HWU059` bit.
7108        const HWU059 = 1 << 43;
7109        /// `HWU060` bit.
7110        const HWU060 = 1 << 44;
7111        /// `HWU061` bit.
7112        const HWU061 = 1 << 45;
7113        /// `HWU062` bit.
7114        const HWU062 = 1 << 46;
7115        /// `HWU159` bit.
7116        const HWU159 = 1 << 47;
7117        /// `HWU160` bit.
7118        const HWU160 = 1 << 48;
7119        /// `HWU161` bit.
7120        const HWU161 = 1 << 49;
7121        /// `HWU162` bit.
7122        const HWU162 = 1 << 50;
7123        /// `TBID0` bit.
7124        const TBID0 = 1 << 51;
7125        /// `TBID1` bit.
7126        const TBID1 = 1 << 52;
7127        /// `NFD0` bit.
7128        const NFD0 = 1 << 53;
7129        /// `NFD1` bit.
7130        const NFD1 = 1 << 54;
7131        /// `E0PD0` bit.
7132        const E0PD0 = 1 << 55;
7133        /// `E0PD1` bit.
7134        const E0PD1 = 1 << 56;
7135        /// `TCMA0` bit.
7136        const TCMA0 = 1 << 57;
7137        /// `TCMA1` bit.
7138        const TCMA1 = 1 << 58;
7139        /// `DS` bit.
7140        const DS = 1 << 59;
7141        /// `MTX0` bit.
7142        const MTX0 = 1 << 60;
7143        /// `MTX1` bit.
7144        const MTX1 = 1 << 61;
7145    }
7146}
7147
7148#[cfg(feature = "el1")]
7149impl TcrEl1 {
7150    /// Offset of the T0SZ field.
7151    pub const T0SZ_SHIFT: u32 = 0;
7152    /// Mask for the T0SZ field.
7153    pub const T0SZ_MASK: u64 = 0b111111;
7154    /// Offset of the EPD0 field.
7155    pub const EPD0_SHIFT: u32 = 7;
7156    /// Offset of the IRGN0 field.
7157    pub const IRGN0_SHIFT: u32 = 8;
7158    /// Mask for the IRGN0 field.
7159    pub const IRGN0_MASK: u64 = 0b11;
7160    /// Offset of the ORGN0 field.
7161    pub const ORGN0_SHIFT: u32 = 10;
7162    /// Mask for the ORGN0 field.
7163    pub const ORGN0_MASK: u64 = 0b11;
7164    /// Offset of the SH0 field.
7165    pub const SH0_SHIFT: u32 = 12;
7166    /// Mask for the SH0 field.
7167    pub const SH0_MASK: u64 = 0b11;
7168    /// Offset of the TG0 field.
7169    pub const TG0_SHIFT: u32 = 14;
7170    /// Mask for the TG0 field.
7171    pub const TG0_MASK: u64 = 0b11;
7172    /// Offset of the T1SZ field.
7173    pub const T1SZ_SHIFT: u32 = 16;
7174    /// Mask for the T1SZ field.
7175    pub const T1SZ_MASK: u64 = 0b111111;
7176    /// Offset of the A1 field.
7177    pub const A1_SHIFT: u32 = 22;
7178    /// Offset of the EPD1 field.
7179    pub const EPD1_SHIFT: u32 = 23;
7180    /// Offset of the IRGN1 field.
7181    pub const IRGN1_SHIFT: u32 = 24;
7182    /// Mask for the IRGN1 field.
7183    pub const IRGN1_MASK: u64 = 0b11;
7184    /// Offset of the ORGN1 field.
7185    pub const ORGN1_SHIFT: u32 = 26;
7186    /// Mask for the ORGN1 field.
7187    pub const ORGN1_MASK: u64 = 0b11;
7188    /// Offset of the SH1 field.
7189    pub const SH1_SHIFT: u32 = 28;
7190    /// Mask for the SH1 field.
7191    pub const SH1_MASK: u64 = 0b11;
7192    /// Offset of the TG1 field.
7193    pub const TG1_SHIFT: u32 = 30;
7194    /// Mask for the TG1 field.
7195    pub const TG1_MASK: u64 = 0b11;
7196    /// Offset of the IPS field.
7197    pub const IPS_SHIFT: u32 = 32;
7198    /// Mask for the IPS field.
7199    pub const IPS_MASK: u64 = 0b111;
7200    /// Offset of the AS field.
7201    pub const AS_SHIFT: u32 = 36;
7202    /// Offset of the TBI0 field.
7203    pub const TBI0_SHIFT: u32 = 37;
7204    /// Offset of the TBI1 field.
7205    pub const TBI1_SHIFT: u32 = 38;
7206    /// Offset of the HA field.
7207    pub const HA_SHIFT: u32 = 39;
7208    /// Offset of the HD field.
7209    pub const HD_SHIFT: u32 = 40;
7210    /// Offset of the HPD0 field.
7211    pub const HPD0_SHIFT: u32 = 41;
7212    /// Offset of the HPD1 field.
7213    pub const HPD1_SHIFT: u32 = 42;
7214    /// Offset of the HWU059 field.
7215    pub const HWU059_SHIFT: u32 = 43;
7216    /// Offset of the HWU060 field.
7217    pub const HWU060_SHIFT: u32 = 44;
7218    /// Offset of the HWU061 field.
7219    pub const HWU061_SHIFT: u32 = 45;
7220    /// Offset of the HWU062 field.
7221    pub const HWU062_SHIFT: u32 = 46;
7222    /// Offset of the HWU159 field.
7223    pub const HWU159_SHIFT: u32 = 47;
7224    /// Offset of the HWU160 field.
7225    pub const HWU160_SHIFT: u32 = 48;
7226    /// Offset of the HWU161 field.
7227    pub const HWU161_SHIFT: u32 = 49;
7228    /// Offset of the HWU162 field.
7229    pub const HWU162_SHIFT: u32 = 50;
7230    /// Offset of the TBID0 field.
7231    pub const TBID0_SHIFT: u32 = 51;
7232    /// Offset of the TBID1 field.
7233    pub const TBID1_SHIFT: u32 = 52;
7234    /// Offset of the NFD0 field.
7235    pub const NFD0_SHIFT: u32 = 53;
7236    /// Offset of the NFD1 field.
7237    pub const NFD1_SHIFT: u32 = 54;
7238    /// Offset of the E0PD0 field.
7239    pub const E0PD0_SHIFT: u32 = 55;
7240    /// Offset of the E0PD1 field.
7241    pub const E0PD1_SHIFT: u32 = 56;
7242    /// Offset of the TCMA0 field.
7243    pub const TCMA0_SHIFT: u32 = 57;
7244    /// Offset of the TCMA1 field.
7245    pub const TCMA1_SHIFT: u32 = 58;
7246    /// Offset of the DS field.
7247    pub const DS_SHIFT: u32 = 59;
7248    /// Offset of the MTX0 field.
7249    pub const MTX0_SHIFT: u32 = 60;
7250    /// Offset of the MTX1 field.
7251    pub const MTX1_SHIFT: u32 = 61;
7252
7253    /// Returns the value of the `T0SZ` field.
7254    pub const fn t0sz(self) -> u8 {
7255        ((self.bits() >> Self::T0SZ_SHIFT) & 0b111111) as u8
7256    }
7257
7258    /// Returns the value of the `IRGN0` field.
7259    pub const fn irgn0(self) -> u8 {
7260        ((self.bits() >> Self::IRGN0_SHIFT) & 0b11) as u8
7261    }
7262
7263    /// Returns the value of the `ORGN0` field.
7264    pub const fn orgn0(self) -> u8 {
7265        ((self.bits() >> Self::ORGN0_SHIFT) & 0b11) as u8
7266    }
7267
7268    /// Returns the value of the `SH0` field.
7269    pub const fn sh0(self) -> u8 {
7270        ((self.bits() >> Self::SH0_SHIFT) & 0b11) as u8
7271    }
7272
7273    /// Returns the value of the `TG0` field.
7274    pub const fn tg0(self) -> u8 {
7275        ((self.bits() >> Self::TG0_SHIFT) & 0b11) as u8
7276    }
7277
7278    /// Returns the value of the `T1SZ` field.
7279    pub const fn t1sz(self) -> u8 {
7280        ((self.bits() >> Self::T1SZ_SHIFT) & 0b111111) as u8
7281    }
7282
7283    /// Returns the value of the `IRGN1` field.
7284    pub const fn irgn1(self) -> u8 {
7285        ((self.bits() >> Self::IRGN1_SHIFT) & 0b11) as u8
7286    }
7287
7288    /// Returns the value of the `ORGN1` field.
7289    pub const fn orgn1(self) -> u8 {
7290        ((self.bits() >> Self::ORGN1_SHIFT) & 0b11) as u8
7291    }
7292
7293    /// Returns the value of the `SH1` field.
7294    pub const fn sh1(self) -> u8 {
7295        ((self.bits() >> Self::SH1_SHIFT) & 0b11) as u8
7296    }
7297
7298    /// Returns the value of the `TG1` field.
7299    pub const fn tg1(self) -> u8 {
7300        ((self.bits() >> Self::TG1_SHIFT) & 0b11) as u8
7301    }
7302
7303    /// Returns the value of the `IPS` field.
7304    pub const fn ips(self) -> u8 {
7305        ((self.bits() >> Self::IPS_SHIFT) & 0b111) as u8
7306    }
7307}
7308
7309#[cfg(feature = "el2")]
7310bitflags! {
7311    /// `TCR_EL2` system register value.
7312    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
7313    #[repr(transparent)]
7314    pub struct TcrEl2: u64 {
7315        /// RES1 bits in the `TCR_EL2` register.
7316        const RES1 = 0b10000000100000000000000000000000;
7317        /// `EPD0` bit.
7318        const EPD0 = 1 << 7;
7319        /// `TBI` bit.
7320        const TBI = 1 << 20;
7321        /// `A1` bit.
7322        const A1 = 1 << 22;
7323        /// `EPD1` bit.
7324        const EPD1 = 1 << 23;
7325        /// `HPD` bit.
7326        const HPD = 1 << 24;
7327        /// `HWU59` bit.
7328        const HWU59 = 1 << 25;
7329        /// `HWU60` bit.
7330        const HWU60 = 1 << 26;
7331        /// `HWU61` bit.
7332        const HWU61 = 1 << 27;
7333        /// `HWU62` bit.
7334        const HWU62 = 1 << 28;
7335        /// `TBID` bit.
7336        const TBID = 1 << 29;
7337        /// `TCMA` bit.
7338        const TCMA = 1 << 30;
7339        /// `MTX` bit.
7340        const MTX = 1 << 33;
7341        /// `AS` bit.
7342        const AS = 1 << 36;
7343        /// `TBI0` bit.
7344        const TBI0 = 1 << 37;
7345        /// `TBI1` bit.
7346        const TBI1 = 1 << 38;
7347        /// `HPD0` bit.
7348        const HPD0 = 1 << 41;
7349        /// `HPD1` bit.
7350        const HPD1 = 1 << 42;
7351        /// `HWU059` bit.
7352        const HWU059 = 1 << 43;
7353        /// `HWU060` bit.
7354        const HWU060 = 1 << 44;
7355        /// `HWU061` bit.
7356        const HWU061 = 1 << 45;
7357        /// `HWU062` bit.
7358        const HWU062 = 1 << 46;
7359        /// `HWU159` bit.
7360        const HWU159 = 1 << 47;
7361        /// `HWU160` bit.
7362        const HWU160 = 1 << 48;
7363        /// `HWU161` bit.
7364        const HWU161 = 1 << 49;
7365        /// `HWU162` bit.
7366        const HWU162 = 1 << 50;
7367        /// `TBID0` bit.
7368        const TBID0 = 1 << 51;
7369        /// `TBID1` bit.
7370        const TBID1 = 1 << 52;
7371        /// `NFD0` bit.
7372        const NFD0 = 1 << 53;
7373        /// `TVAD` bit.
7374        const TVAD = 1 << 53;
7375        /// `NFD1` bit.
7376        const NFD1 = 1 << 54;
7377        /// `E0PD0` bit.
7378        const E0PD0 = 1 << 55;
7379        /// `E0PD1` bit.
7380        const E0PD1 = 1 << 56;
7381        /// `TCMA0` bit.
7382        const TCMA0 = 1 << 57;
7383        /// `TCMA1` bit.
7384        const TCMA1 = 1 << 58;
7385        /// `MTX0` bit.
7386        const MTX0 = 1 << 60;
7387        /// `MTX1` bit.
7388        const MTX1 = 1 << 61;
7389    }
7390}
7391
7392#[cfg(feature = "el2")]
7393impl TcrEl2 {
7394    /// Offset of the T0SZ field.
7395    pub const T0SZ_SHIFT: u32 = 0;
7396    /// Mask for the T0SZ field.
7397    pub const T0SZ_MASK: u64 = 0b111111;
7398    /// Offset of the EPD0 field.
7399    pub const EPD0_SHIFT: u32 = 7;
7400    /// Offset of the IRGN0 field.
7401    pub const IRGN0_SHIFT: u32 = 8;
7402    /// Mask for the IRGN0 field.
7403    pub const IRGN0_MASK: u64 = 0b11;
7404    /// Offset of the ORGN0 field.
7405    pub const ORGN0_SHIFT: u32 = 10;
7406    /// Mask for the ORGN0 field.
7407    pub const ORGN0_MASK: u64 = 0b11;
7408    /// Offset of the SH0 field.
7409    pub const SH0_SHIFT: u32 = 12;
7410    /// Mask for the SH0 field.
7411    pub const SH0_MASK: u64 = 0b11;
7412    /// Offset of the TG0 field.
7413    pub const TG0_SHIFT: u32 = 14;
7414    /// Mask for the TG0 field.
7415    pub const TG0_MASK: u64 = 0b11;
7416    /// Offset of the PS field.
7417    pub const PS_SHIFT: u32 = 16;
7418    /// Mask for the PS field.
7419    pub const PS_MASK: u64 = 0b111;
7420    /// Offset of the T1SZ field.
7421    pub const T1SZ_SHIFT: u32 = 16;
7422    /// Mask for the T1SZ field.
7423    pub const T1SZ_MASK: u64 = 0b111111;
7424    /// Offset of the TBI field.
7425    pub const TBI_SHIFT: u32 = 20;
7426    /// Offset of the A1 field.
7427    pub const A1_SHIFT: u32 = 22;
7428    /// Offset of the EPD1 field.
7429    pub const EPD1_SHIFT: u32 = 23;
7430    /// Offset of the HPD field.
7431    pub const HPD_SHIFT: u32 = 24;
7432    /// Offset of the IRGN1 field.
7433    pub const IRGN1_SHIFT: u32 = 24;
7434    /// Mask for the IRGN1 field.
7435    pub const IRGN1_MASK: u64 = 0b11;
7436    /// Offset of the HWU59 field.
7437    pub const HWU59_SHIFT: u32 = 25;
7438    /// Offset of the HWU60 field.
7439    pub const HWU60_SHIFT: u32 = 26;
7440    /// Offset of the ORGN1 field.
7441    pub const ORGN1_SHIFT: u32 = 26;
7442    /// Mask for the ORGN1 field.
7443    pub const ORGN1_MASK: u64 = 0b11;
7444    /// Offset of the HWU61 field.
7445    pub const HWU61_SHIFT: u32 = 27;
7446    /// Offset of the HWU62 field.
7447    pub const HWU62_SHIFT: u32 = 28;
7448    /// Offset of the SH1 field.
7449    pub const SH1_SHIFT: u32 = 28;
7450    /// Mask for the SH1 field.
7451    pub const SH1_MASK: u64 = 0b11;
7452    /// Offset of the TBID field.
7453    pub const TBID_SHIFT: u32 = 29;
7454    /// Offset of the TCMA field.
7455    pub const TCMA_SHIFT: u32 = 30;
7456    /// Offset of the TG1 field.
7457    pub const TG1_SHIFT: u32 = 30;
7458    /// Mask for the TG1 field.
7459    pub const TG1_MASK: u64 = 0b11;
7460    /// Offset of the IPS field.
7461    pub const IPS_SHIFT: u32 = 32;
7462    /// Mask for the IPS field.
7463    pub const IPS_MASK: u64 = 0b111;
7464    /// Offset of the MTX field.
7465    pub const MTX_SHIFT: u32 = 33;
7466    /// Offset of the AS field.
7467    pub const AS_SHIFT: u32 = 36;
7468    /// Offset of the TBI0 field.
7469    pub const TBI0_SHIFT: u32 = 37;
7470    /// Offset of the TBI1 field.
7471    pub const TBI1_SHIFT: u32 = 38;
7472    /// Offset of the HPD0 field.
7473    pub const HPD0_SHIFT: u32 = 41;
7474    /// Offset of the HPD1 field.
7475    pub const HPD1_SHIFT: u32 = 42;
7476    /// Offset of the HWU059 field.
7477    pub const HWU059_SHIFT: u32 = 43;
7478    /// Offset of the HWU060 field.
7479    pub const HWU060_SHIFT: u32 = 44;
7480    /// Offset of the HWU061 field.
7481    pub const HWU061_SHIFT: u32 = 45;
7482    /// Offset of the HWU062 field.
7483    pub const HWU062_SHIFT: u32 = 46;
7484    /// Offset of the HWU159 field.
7485    pub const HWU159_SHIFT: u32 = 47;
7486    /// Offset of the HWU160 field.
7487    pub const HWU160_SHIFT: u32 = 48;
7488    /// Offset of the VTB field.
7489    pub const VTB_SHIFT: u32 = 48;
7490    /// Mask for the VTB field.
7491    pub const VTB_MASK: u64 = 0b11111;
7492    /// Offset of the HWU161 field.
7493    pub const HWU161_SHIFT: u32 = 49;
7494    /// Offset of the HWU162 field.
7495    pub const HWU162_SHIFT: u32 = 50;
7496    /// Offset of the TBID0 field.
7497    pub const TBID0_SHIFT: u32 = 51;
7498    /// Offset of the TBID1 field.
7499    pub const TBID1_SHIFT: u32 = 52;
7500    /// Offset of the NFD0 field.
7501    pub const NFD0_SHIFT: u32 = 53;
7502    /// Offset of the TVAD field.
7503    pub const TVAD_SHIFT: u32 = 53;
7504    /// Offset of the NFD1 field.
7505    pub const NFD1_SHIFT: u32 = 54;
7506    /// Offset of the E0PD0 field.
7507    pub const E0PD0_SHIFT: u32 = 55;
7508    /// Offset of the E0PD1 field.
7509    pub const E0PD1_SHIFT: u32 = 56;
7510    /// Offset of the TCMA0 field.
7511    pub const TCMA0_SHIFT: u32 = 57;
7512    /// Offset of the TCMA1 field.
7513    pub const TCMA1_SHIFT: u32 = 58;
7514    /// Offset of the MTX0 field.
7515    pub const MTX0_SHIFT: u32 = 60;
7516    /// Offset of the MTX1 field.
7517    pub const MTX1_SHIFT: u32 = 61;
7518
7519    /// Returns the value of the `T0SZ` field.
7520    pub const fn t0sz(self) -> u8 {
7521        ((self.bits() >> Self::T0SZ_SHIFT) & 0b111111) as u8
7522    }
7523
7524    /// Returns the value of the `IRGN0` field.
7525    pub const fn irgn0(self) -> u8 {
7526        ((self.bits() >> Self::IRGN0_SHIFT) & 0b11) as u8
7527    }
7528
7529    /// Returns the value of the `ORGN0` field.
7530    pub const fn orgn0(self) -> u8 {
7531        ((self.bits() >> Self::ORGN0_SHIFT) & 0b11) as u8
7532    }
7533
7534    /// Returns the value of the `SH0` field.
7535    pub const fn sh0(self) -> u8 {
7536        ((self.bits() >> Self::SH0_SHIFT) & 0b11) as u8
7537    }
7538
7539    /// Returns the value of the `TG0` field.
7540    pub const fn tg0(self) -> u8 {
7541        ((self.bits() >> Self::TG0_SHIFT) & 0b11) as u8
7542    }
7543
7544    /// Returns the value of the `PS` field.
7545    pub const fn ps(self) -> u8 {
7546        ((self.bits() >> Self::PS_SHIFT) & 0b111) as u8
7547    }
7548
7549    /// Returns the value of the `T1SZ` field.
7550    pub const fn t1sz(self) -> u8 {
7551        ((self.bits() >> Self::T1SZ_SHIFT) & 0b111111) as u8
7552    }
7553
7554    /// Returns the value of the `IRGN1` field.
7555    pub const fn irgn1(self) -> u8 {
7556        ((self.bits() >> Self::IRGN1_SHIFT) & 0b11) as u8
7557    }
7558
7559    /// Returns the value of the `ORGN1` field.
7560    pub const fn orgn1(self) -> u8 {
7561        ((self.bits() >> Self::ORGN1_SHIFT) & 0b11) as u8
7562    }
7563
7564    /// Returns the value of the `SH1` field.
7565    pub const fn sh1(self) -> u8 {
7566        ((self.bits() >> Self::SH1_SHIFT) & 0b11) as u8
7567    }
7568
7569    /// Returns the value of the `TG1` field.
7570    pub const fn tg1(self) -> u8 {
7571        ((self.bits() >> Self::TG1_SHIFT) & 0b11) as u8
7572    }
7573
7574    /// Returns the value of the `IPS` field.
7575    pub const fn ips(self) -> u8 {
7576        ((self.bits() >> Self::IPS_SHIFT) & 0b111) as u8
7577    }
7578
7579    /// Returns the value of the `VTB` field.
7580    pub const fn vtb(self) -> u8 {
7581        ((self.bits() >> Self::VTB_SHIFT) & 0b11111) as u8
7582    }
7583}
7584
7585#[cfg(feature = "el3")]
7586bitflags! {
7587    /// `TCR_EL3` system register value.
7588    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
7589    #[repr(transparent)]
7590    pub struct TcrEl3: u64 {
7591        /// RES1 bits in the `TCR_EL3` register.
7592        const RES1 = 0b10000000100000000000000000000000;
7593        /// `TBI` bit.
7594        const TBI = 1 << 20;
7595        /// `HA` bit.
7596        const HA = 1 << 21;
7597        /// `HD` bit.
7598        const HD = 1 << 22;
7599        /// `HPD` bit.
7600        const HPD = 1 << 24;
7601        /// `HWU59` bit.
7602        const HWU59 = 1 << 25;
7603        /// `HWU60` bit.
7604        const HWU60 = 1 << 26;
7605        /// `HWU61` bit.
7606        const HWU61 = 1 << 27;
7607        /// `HWU62` bit.
7608        const HWU62 = 1 << 28;
7609        /// `TBID` bit.
7610        const TBID = 1 << 29;
7611        /// `TCMA` bit.
7612        const TCMA = 1 << 30;
7613        /// `DS` bit.
7614        const DS = 1 << 32;
7615        /// `MTX` bit.
7616        const MTX = 1 << 33;
7617        /// `PnCH` bit.
7618        const PNCH = 1 << 34;
7619        /// `PIE` bit.
7620        const PIE = 1 << 35;
7621        /// `POE` bit.
7622        const POE = 1 << 36;
7623        /// `AIE` bit.
7624        const AIE = 1 << 37;
7625        /// `D128` bit.
7626        const D128 = 1 << 38;
7627        /// `PTTWI` bit.
7628        const PTTWI = 1 << 41;
7629        /// `HAFT` bit.
7630        const HAFT = 1 << 42;
7631        /// `DisCH0` bit.
7632        const DISCH0 = 1 << 43;
7633        /// `POE2F` bit.
7634        const POE2F = 1 << 44;
7635        /// `TVAD` bit.
7636        const TVAD = 1 << 53;
7637    }
7638}
7639
7640#[cfg(feature = "el3")]
7641impl TcrEl3 {
7642    /// Offset of the T0SZ field.
7643    pub const T0SZ_SHIFT: u32 = 0;
7644    /// Mask for the T0SZ field.
7645    pub const T0SZ_MASK: u64 = 0b111111;
7646    /// Offset of the IRGN0 field.
7647    pub const IRGN0_SHIFT: u32 = 8;
7648    /// Mask for the IRGN0 field.
7649    pub const IRGN0_MASK: u64 = 0b11;
7650    /// Offset of the ORGN0 field.
7651    pub const ORGN0_SHIFT: u32 = 10;
7652    /// Mask for the ORGN0 field.
7653    pub const ORGN0_MASK: u64 = 0b11;
7654    /// Offset of the SH0 field.
7655    pub const SH0_SHIFT: u32 = 12;
7656    /// Mask for the SH0 field.
7657    pub const SH0_MASK: u64 = 0b11;
7658    /// Offset of the TG0 field.
7659    pub const TG0_SHIFT: u32 = 14;
7660    /// Mask for the TG0 field.
7661    pub const TG0_MASK: u64 = 0b11;
7662    /// Offset of the PS field.
7663    pub const PS_SHIFT: u32 = 16;
7664    /// Mask for the PS field.
7665    pub const PS_MASK: u64 = 0b111;
7666    /// Offset of the TBI field.
7667    pub const TBI_SHIFT: u32 = 20;
7668    /// Offset of the HA field.
7669    pub const HA_SHIFT: u32 = 21;
7670    /// Offset of the HD field.
7671    pub const HD_SHIFT: u32 = 22;
7672    /// Offset of the HPD field.
7673    pub const HPD_SHIFT: u32 = 24;
7674    /// Offset of the HWU59 field.
7675    pub const HWU59_SHIFT: u32 = 25;
7676    /// Offset of the HWU60 field.
7677    pub const HWU60_SHIFT: u32 = 26;
7678    /// Offset of the HWU61 field.
7679    pub const HWU61_SHIFT: u32 = 27;
7680    /// Offset of the HWU62 field.
7681    pub const HWU62_SHIFT: u32 = 28;
7682    /// Offset of the TBID field.
7683    pub const TBID_SHIFT: u32 = 29;
7684    /// Offset of the TCMA field.
7685    pub const TCMA_SHIFT: u32 = 30;
7686    /// Offset of the DS field.
7687    pub const DS_SHIFT: u32 = 32;
7688    /// Offset of the MTX field.
7689    pub const MTX_SHIFT: u32 = 33;
7690    /// Offset of the PnCH field.
7691    pub const PNCH_SHIFT: u32 = 34;
7692    /// Offset of the PIE field.
7693    pub const PIE_SHIFT: u32 = 35;
7694    /// Offset of the POE field.
7695    pub const POE_SHIFT: u32 = 36;
7696    /// Offset of the AIE field.
7697    pub const AIE_SHIFT: u32 = 37;
7698    /// Offset of the D128 field.
7699    pub const D128_SHIFT: u32 = 38;
7700    /// Offset of the PTTWI field.
7701    pub const PTTWI_SHIFT: u32 = 41;
7702    /// Offset of the HAFT field.
7703    pub const HAFT_SHIFT: u32 = 42;
7704    /// Offset of the DisCH0 field.
7705    pub const DISCH0_SHIFT: u32 = 43;
7706    /// Offset of the POE2F field.
7707    pub const POE2F_SHIFT: u32 = 44;
7708    /// Offset of the POIW field.
7709    pub const POIW_SHIFT: u32 = 45;
7710    /// Mask for the POIW field.
7711    pub const POIW_MASK: u64 = 0b111;
7712    /// Offset of the VTB field.
7713    pub const VTB_SHIFT: u32 = 48;
7714    /// Mask for the VTB field.
7715    pub const VTB_MASK: u64 = 0b11111;
7716    /// Offset of the TVAD field.
7717    pub const TVAD_SHIFT: u32 = 53;
7718
7719    /// Returns the value of the `T0SZ` field.
7720    pub const fn t0sz(self) -> u8 {
7721        ((self.bits() >> Self::T0SZ_SHIFT) & 0b111111) as u8
7722    }
7723
7724    /// Returns the value of the `IRGN0` field.
7725    pub const fn irgn0(self) -> u8 {
7726        ((self.bits() >> Self::IRGN0_SHIFT) & 0b11) as u8
7727    }
7728
7729    /// Returns the value of the `ORGN0` field.
7730    pub const fn orgn0(self) -> u8 {
7731        ((self.bits() >> Self::ORGN0_SHIFT) & 0b11) as u8
7732    }
7733
7734    /// Returns the value of the `SH0` field.
7735    pub const fn sh0(self) -> u8 {
7736        ((self.bits() >> Self::SH0_SHIFT) & 0b11) as u8
7737    }
7738
7739    /// Returns the value of the `TG0` field.
7740    pub const fn tg0(self) -> u8 {
7741        ((self.bits() >> Self::TG0_SHIFT) & 0b11) as u8
7742    }
7743
7744    /// Returns the value of the `PS` field.
7745    pub const fn ps(self) -> u8 {
7746        ((self.bits() >> Self::PS_SHIFT) & 0b111) as u8
7747    }
7748
7749    /// Returns the value of the `POIW` field.
7750    pub const fn poiw(self) -> u8 {
7751        ((self.bits() >> Self::POIW_SHIFT) & 0b111) as u8
7752    }
7753
7754    /// Returns the value of the `VTB` field.
7755    pub const fn vtb(self) -> u8 {
7756        ((self.bits() >> Self::VTB_SHIFT) & 0b11111) as u8
7757    }
7758}
7759
7760#[cfg(feature = "el1")]
7761bitflags! {
7762    /// `TFSRE0_EL1` system register value.
7763    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
7764    #[repr(transparent)]
7765    pub struct Tfsre0El1: u64 {
7766        /// `TF0` bit.
7767        const TF0 = 1 << 0;
7768        /// `TF1` bit.
7769        const TF1 = 1 << 1;
7770    }
7771}
7772
7773#[cfg(feature = "el1")]
7774impl Tfsre0El1 {
7775    /// Offset of the TF0 field.
7776    pub const TF0_SHIFT: u32 = 0;
7777    /// Offset of the TF1 field.
7778    pub const TF1_SHIFT: u32 = 1;
7779}
7780
7781#[cfg(feature = "el1")]
7782bitflags! {
7783    /// `TFSR_EL1` system register value.
7784    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
7785    #[repr(transparent)]
7786    pub struct TfsrEl1: u64 {
7787        /// `TF0` bit.
7788        const TF0 = 1 << 0;
7789        /// `TF1` bit.
7790        const TF1 = 1 << 1;
7791    }
7792}
7793
7794#[cfg(feature = "el1")]
7795impl TfsrEl1 {
7796    /// Offset of the TF0 field.
7797    pub const TF0_SHIFT: u32 = 0;
7798    /// Offset of the TF1 field.
7799    pub const TF1_SHIFT: u32 = 1;
7800}
7801
7802#[cfg(feature = "el2")]
7803bitflags! {
7804    /// `TFSR_EL2` system register value.
7805    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
7806    #[repr(transparent)]
7807    pub struct TfsrEl2: u64 {
7808        /// `TF0` bit.
7809        const TF0 = 1 << 0;
7810        /// `TF1` bit.
7811        const TF1 = 1 << 1;
7812    }
7813}
7814
7815#[cfg(feature = "el2")]
7816impl TfsrEl2 {
7817    /// Offset of the TF0 field.
7818    pub const TF0_SHIFT: u32 = 0;
7819    /// Offset of the TF1 field.
7820    pub const TF1_SHIFT: u32 = 1;
7821}
7822
7823bitflags! {
7824    /// `TPIDRRO_EL0` system register value.
7825    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
7826    #[repr(transparent)]
7827    pub struct TpidrroEl0: u64 {
7828    }
7829}
7830
7831impl TpidrroEl0 {
7832    /// Offset of the ThreadID field.
7833    pub const THREADID_SHIFT: u32 = 0;
7834    /// Mask for the ThreadID field.
7835    pub const THREADID_MASK: u64 =
7836        0b1111111111111111111111111111111111111111111111111111111111111111;
7837
7838    /// Returns the value of the `ThreadID` field.
7839    pub const fn threadid(self) -> u64 {
7840        ((self.bits() >> Self::THREADID_SHIFT)
7841            & 0b1111111111111111111111111111111111111111111111111111111111111111) as u64
7842    }
7843}
7844
7845bitflags! {
7846    /// `TPIDR_EL0` system register value.
7847    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
7848    #[repr(transparent)]
7849    pub struct TpidrEl0: u64 {
7850    }
7851}
7852
7853impl TpidrEl0 {
7854    /// Offset of the ThreadID field.
7855    pub const THREADID_SHIFT: u32 = 0;
7856    /// Mask for the ThreadID field.
7857    pub const THREADID_MASK: u64 =
7858        0b1111111111111111111111111111111111111111111111111111111111111111;
7859
7860    /// Returns the value of the `ThreadID` field.
7861    pub const fn threadid(self) -> u64 {
7862        ((self.bits() >> Self::THREADID_SHIFT)
7863            & 0b1111111111111111111111111111111111111111111111111111111111111111) as u64
7864    }
7865}
7866
7867#[cfg(feature = "el1")]
7868bitflags! {
7869    /// `TPIDR_EL1` system register value.
7870    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
7871    #[repr(transparent)]
7872    pub struct TpidrEl1: u64 {
7873    }
7874}
7875
7876#[cfg(feature = "el1")]
7877impl TpidrEl1 {
7878    /// Offset of the ThreadID field.
7879    pub const THREADID_SHIFT: u32 = 0;
7880    /// Mask for the ThreadID field.
7881    pub const THREADID_MASK: u64 =
7882        0b1111111111111111111111111111111111111111111111111111111111111111;
7883
7884    /// Returns the value of the `ThreadID` field.
7885    pub const fn threadid(self) -> u64 {
7886        ((self.bits() >> Self::THREADID_SHIFT)
7887            & 0b1111111111111111111111111111111111111111111111111111111111111111) as u64
7888    }
7889}
7890
7891#[cfg(feature = "el2")]
7892bitflags! {
7893    /// `TPIDR_EL2` system register value.
7894    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
7895    #[repr(transparent)]
7896    pub struct TpidrEl2: u64 {
7897    }
7898}
7899
7900#[cfg(feature = "el2")]
7901impl TpidrEl2 {
7902    /// Offset of the ThreadID field.
7903    pub const THREADID_SHIFT: u32 = 0;
7904    /// Mask for the ThreadID field.
7905    pub const THREADID_MASK: u64 =
7906        0b1111111111111111111111111111111111111111111111111111111111111111;
7907
7908    /// Returns the value of the `ThreadID` field.
7909    pub const fn threadid(self) -> u64 {
7910        ((self.bits() >> Self::THREADID_SHIFT)
7911            & 0b1111111111111111111111111111111111111111111111111111111111111111) as u64
7912    }
7913}
7914
7915#[cfg(feature = "el1")]
7916bitflags! {
7917    /// `TTBR0_EL1` system register value.
7918    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
7919    #[repr(transparent)]
7920    pub struct Ttbr0El1: u64 {
7921        /// `CnP` bit.
7922        const CNP = 1 << 0;
7923    }
7924}
7925
7926#[cfg(feature = "el1")]
7927impl Ttbr0El1 {
7928    /// Offset of the CnP field.
7929    pub const CNP_SHIFT: u32 = 0;
7930    /// Offset of the BADDR[47:1] field.
7931    pub const BADDR_47_1_SHIFT: u32 = 1;
7932    /// Mask for the BADDR[47:1] field.
7933    pub const BADDR_47_1_MASK: u64 = 0b11111111111111111111111111111111111111111111111;
7934    /// Offset of the SKL field.
7935    pub const SKL_SHIFT: u32 = 1;
7936    /// Mask for the SKL field.
7937    pub const SKL_MASK: u64 = 0b11;
7938    /// Offset of the ASID field.
7939    pub const ASID_SHIFT: u32 = 48;
7940    /// Mask for the ASID field.
7941    pub const ASID_MASK: u64 = 0b1111111111111111;
7942
7943    /// Returns the value of the `BADDR[47:1]` field.
7944    pub const fn baddr_47_1(self) -> u64 {
7945        ((self.bits() >> Self::BADDR_47_1_SHIFT)
7946            & 0b11111111111111111111111111111111111111111111111) as u64
7947    }
7948
7949    /// Returns the value of the `SKL` field.
7950    pub const fn skl(self) -> u8 {
7951        ((self.bits() >> Self::SKL_SHIFT) & 0b11) as u8
7952    }
7953
7954    /// Returns the value of the `ASID` field.
7955    pub const fn asid(self) -> u16 {
7956        ((self.bits() >> Self::ASID_SHIFT) & 0b1111111111111111) as u16
7957    }
7958}
7959
7960#[cfg(feature = "el2")]
7961bitflags! {
7962    /// `TTBR0_EL2` system register value.
7963    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
7964    #[repr(transparent)]
7965    pub struct Ttbr0El2: u64 {
7966        /// `CnP` bit.
7967        const CNP = 1 << 0;
7968    }
7969}
7970
7971#[cfg(feature = "el2")]
7972impl Ttbr0El2 {
7973    /// Offset of the CnP field.
7974    pub const CNP_SHIFT: u32 = 0;
7975    /// Offset of the BADDR[47:1] field.
7976    pub const BADDR_47_1_SHIFT: u32 = 1;
7977    /// Mask for the BADDR[47:1] field.
7978    pub const BADDR_47_1_MASK: u64 = 0b11111111111111111111111111111111111111111111111;
7979    /// Offset of the SKL field.
7980    pub const SKL_SHIFT: u32 = 1;
7981    /// Mask for the SKL field.
7982    pub const SKL_MASK: u64 = 0b11;
7983    /// Offset of the ASID field.
7984    pub const ASID_SHIFT: u32 = 48;
7985    /// Mask for the ASID field.
7986    pub const ASID_MASK: u64 = 0b1111111111111111;
7987
7988    /// Returns the value of the `BADDR[47:1]` field.
7989    pub const fn baddr_47_1(self) -> u64 {
7990        ((self.bits() >> Self::BADDR_47_1_SHIFT)
7991            & 0b11111111111111111111111111111111111111111111111) as u64
7992    }
7993
7994    /// Returns the value of the `SKL` field.
7995    pub const fn skl(self) -> u8 {
7996        ((self.bits() >> Self::SKL_SHIFT) & 0b11) as u8
7997    }
7998
7999    /// Returns the value of the `ASID` field.
8000    pub const fn asid(self) -> u16 {
8001        ((self.bits() >> Self::ASID_SHIFT) & 0b1111111111111111) as u16
8002    }
8003}
8004
8005#[cfg(feature = "el3")]
8006bitflags! {
8007    /// `TTBR0_EL3` system register value.
8008    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
8009    #[repr(transparent)]
8010    pub struct Ttbr0El3: u64 {
8011        /// `CnP` bit.
8012        const CNP = 1 << 0;
8013    }
8014}
8015
8016#[cfg(feature = "el3")]
8017impl Ttbr0El3 {
8018    /// Offset of the CnP field.
8019    pub const CNP_SHIFT: u32 = 0;
8020    /// Offset of the SKL field.
8021    pub const SKL_SHIFT: u32 = 1;
8022    /// Mask for the SKL field.
8023    pub const SKL_MASK: u64 = 0b11;
8024
8025    /// Returns the value of the `SKL` field.
8026    pub const fn skl(self) -> u8 {
8027        ((self.bits() >> Self::SKL_SHIFT) & 0b11) as u8
8028    }
8029}
8030
8031#[cfg(feature = "el1")]
8032bitflags! {
8033    /// `TTBR1_EL1` system register value.
8034    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
8035    #[repr(transparent)]
8036    pub struct Ttbr1El1: u64 {
8037        /// `CnP` bit.
8038        const CNP = 1 << 0;
8039    }
8040}
8041
8042#[cfg(feature = "el1")]
8043impl Ttbr1El1 {
8044    /// Offset of the CnP field.
8045    pub const CNP_SHIFT: u32 = 0;
8046    /// Offset of the BADDR[47:1] field.
8047    pub const BADDR_47_1_SHIFT: u32 = 1;
8048    /// Mask for the BADDR[47:1] field.
8049    pub const BADDR_47_1_MASK: u64 = 0b11111111111111111111111111111111111111111111111;
8050    /// Offset of the SKL field.
8051    pub const SKL_SHIFT: u32 = 1;
8052    /// Mask for the SKL field.
8053    pub const SKL_MASK: u64 = 0b11;
8054    /// Offset of the ASID field.
8055    pub const ASID_SHIFT: u32 = 48;
8056    /// Mask for the ASID field.
8057    pub const ASID_MASK: u64 = 0b1111111111111111;
8058
8059    /// Returns the value of the `BADDR[47:1]` field.
8060    pub const fn baddr_47_1(self) -> u64 {
8061        ((self.bits() >> Self::BADDR_47_1_SHIFT)
8062            & 0b11111111111111111111111111111111111111111111111) as u64
8063    }
8064
8065    /// Returns the value of the `SKL` field.
8066    pub const fn skl(self) -> u8 {
8067        ((self.bits() >> Self::SKL_SHIFT) & 0b11) as u8
8068    }
8069
8070    /// Returns the value of the `ASID` field.
8071    pub const fn asid(self) -> u16 {
8072        ((self.bits() >> Self::ASID_SHIFT) & 0b1111111111111111) as u16
8073    }
8074}
8075
8076#[cfg(feature = "el2")]
8077bitflags! {
8078    /// `TTBR1_EL2` system register value.
8079    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
8080    #[repr(transparent)]
8081    pub struct Ttbr1El2: u64 {
8082        /// `CnP` bit.
8083        const CNP = 1 << 0;
8084    }
8085}
8086
8087#[cfg(feature = "el2")]
8088impl Ttbr1El2 {
8089    /// Offset of the CnP field.
8090    pub const CNP_SHIFT: u32 = 0;
8091    /// Offset of the BADDR[47:1] field.
8092    pub const BADDR_47_1_SHIFT: u32 = 1;
8093    /// Mask for the BADDR[47:1] field.
8094    pub const BADDR_47_1_MASK: u64 = 0b11111111111111111111111111111111111111111111111;
8095    /// Offset of the SKL field.
8096    pub const SKL_SHIFT: u32 = 1;
8097    /// Mask for the SKL field.
8098    pub const SKL_MASK: u64 = 0b11;
8099    /// Offset of the ASID field.
8100    pub const ASID_SHIFT: u32 = 48;
8101    /// Mask for the ASID field.
8102    pub const ASID_MASK: u64 = 0b1111111111111111;
8103
8104    /// Returns the value of the `BADDR[47:1]` field.
8105    pub const fn baddr_47_1(self) -> u64 {
8106        ((self.bits() >> Self::BADDR_47_1_SHIFT)
8107            & 0b11111111111111111111111111111111111111111111111) as u64
8108    }
8109
8110    /// Returns the value of the `SKL` field.
8111    pub const fn skl(self) -> u8 {
8112        ((self.bits() >> Self::SKL_SHIFT) & 0b11) as u8
8113    }
8114
8115    /// Returns the value of the `ASID` field.
8116    pub const fn asid(self) -> u16 {
8117        ((self.bits() >> Self::ASID_SHIFT) & 0b1111111111111111) as u16
8118    }
8119}
8120
8121#[cfg(feature = "el1")]
8122bitflags! {
8123    /// `VBAR_EL1` system register value.
8124    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
8125    #[repr(transparent)]
8126    pub struct VbarEl1: u64 {
8127        /// `UT` bit.
8128        const UT = 1 << 0;
8129    }
8130}
8131
8132#[cfg(feature = "el1")]
8133impl VbarEl1 {
8134    /// Offset of the UT field.
8135    pub const UT_SHIFT: u32 = 0;
8136    /// Offset of the VBA field.
8137    pub const VBA_SHIFT: u32 = 11;
8138    /// Mask for the VBA field.
8139    pub const VBA_MASK: u64 = 0b11111111111111111111111111111111111111111111111111111;
8140
8141    /// Returns the value of the `VBA` field.
8142    pub const fn vba(self) -> u64 {
8143        ((self.bits() >> Self::VBA_SHIFT) & 0b11111111111111111111111111111111111111111111111111111)
8144            as u64
8145    }
8146}
8147
8148#[cfg(feature = "el2")]
8149bitflags! {
8150    /// `VBAR_EL2` system register value.
8151    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
8152    #[repr(transparent)]
8153    pub struct VbarEl2: u64 {
8154        /// `UT` bit.
8155        const UT = 1 << 0;
8156    }
8157}
8158
8159#[cfg(feature = "el2")]
8160impl VbarEl2 {
8161    /// Offset of the UT field.
8162    pub const UT_SHIFT: u32 = 0;
8163    /// Offset of the VBA field.
8164    pub const VBA_SHIFT: u32 = 11;
8165    /// Mask for the VBA field.
8166    pub const VBA_MASK: u64 = 0b11111111111111111111111111111111111111111111111111111;
8167
8168    /// Returns the value of the `VBA` field.
8169    pub const fn vba(self) -> u64 {
8170        ((self.bits() >> Self::VBA_SHIFT) & 0b11111111111111111111111111111111111111111111111111111)
8171            as u64
8172    }
8173}
8174
8175#[cfg(feature = "el2")]
8176bitflags! {
8177    /// `VDISR_EL2` system register value.
8178    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
8179    #[repr(transparent)]
8180    pub struct VdisrEl2: u64 {
8181        /// `LPAE` bit.
8182        const LPAE = 1 << 9;
8183        /// `ExT` bit.
8184        const EXT = 1 << 12;
8185        /// `IDS` bit.
8186        const IDS = 1 << 24;
8187        /// `A` bit.
8188        const A = 1 << 31;
8189    }
8190}
8191
8192#[cfg(feature = "el2")]
8193impl VdisrEl2 {
8194    /// Offset of the ISS field.
8195    pub const ISS_SHIFT: u32 = 0;
8196    /// Mask for the ISS field.
8197    pub const ISS_MASK: u64 = 0b111111111111111111111111;
8198    /// Offset of the STATUS field.
8199    pub const STATUS_SHIFT: u32 = 0;
8200    /// Mask for the STATUS field.
8201    pub const STATUS_MASK: u64 = 0b111111;
8202    /// Offset of the LPAE field.
8203    pub const LPAE_SHIFT: u32 = 9;
8204    /// Offset of the ExT field.
8205    pub const EXT_SHIFT: u32 = 12;
8206    /// Offset of the AET field.
8207    pub const AET_SHIFT: u32 = 14;
8208    /// Mask for the AET field.
8209    pub const AET_MASK: u64 = 0b11;
8210    /// Offset of the IDS field.
8211    pub const IDS_SHIFT: u32 = 24;
8212    /// Offset of the A field.
8213    pub const A_SHIFT: u32 = 31;
8214
8215    /// Returns the value of the `ISS` field.
8216    pub const fn iss(self) -> u32 {
8217        ((self.bits() >> Self::ISS_SHIFT) & 0b111111111111111111111111) as u32
8218    }
8219
8220    /// Returns the value of the `STATUS` field.
8221    pub const fn status(self) -> u8 {
8222        ((self.bits() >> Self::STATUS_SHIFT) & 0b111111) as u8
8223    }
8224
8225    /// Returns the value of the `AET` field.
8226    pub const fn aet(self) -> u8 {
8227        ((self.bits() >> Self::AET_SHIFT) & 0b11) as u8
8228    }
8229}
8230
8231#[cfg(feature = "el2")]
8232bitflags! {
8233    /// `VMPIDR_EL2` system register value.
8234    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
8235    #[repr(transparent)]
8236    pub struct VmpidrEl2: u64 {
8237        /// RES1 bits in the `VMPIDR_EL2` register.
8238        const RES1 = 0b10000000000000000000000000000000;
8239        /// `MT` bit.
8240        const MT = 1 << 24;
8241        /// `U` bit.
8242        const U = 1 << 30;
8243    }
8244}
8245
8246#[cfg(feature = "el2")]
8247impl VmpidrEl2 {
8248    /// Offset of the Aff0 field.
8249    pub const AFF0_SHIFT: u32 = 0;
8250    /// Mask for the Aff0 field.
8251    pub const AFF0_MASK: u64 = 0b11111111;
8252    /// Offset of the Aff1 field.
8253    pub const AFF1_SHIFT: u32 = 8;
8254    /// Mask for the Aff1 field.
8255    pub const AFF1_MASK: u64 = 0b11111111;
8256    /// Offset of the Aff2 field.
8257    pub const AFF2_SHIFT: u32 = 16;
8258    /// Mask for the Aff2 field.
8259    pub const AFF2_MASK: u64 = 0b11111111;
8260    /// Offset of the MT field.
8261    pub const MT_SHIFT: u32 = 24;
8262    /// Offset of the U field.
8263    pub const U_SHIFT: u32 = 30;
8264    /// Offset of the Aff3 field.
8265    pub const AFF3_SHIFT: u32 = 32;
8266    /// Mask for the Aff3 field.
8267    pub const AFF3_MASK: u64 = 0b11111111;
8268
8269    /// Returns the value of the `Aff0` field.
8270    pub const fn aff0(self) -> u8 {
8271        ((self.bits() >> Self::AFF0_SHIFT) & 0b11111111) as u8
8272    }
8273
8274    /// Returns the value of the `Aff1` field.
8275    pub const fn aff1(self) -> u8 {
8276        ((self.bits() >> Self::AFF1_SHIFT) & 0b11111111) as u8
8277    }
8278
8279    /// Returns the value of the `Aff2` field.
8280    pub const fn aff2(self) -> u8 {
8281        ((self.bits() >> Self::AFF2_SHIFT) & 0b11111111) as u8
8282    }
8283
8284    /// Returns the value of the `Aff3` field.
8285    pub const fn aff3(self) -> u8 {
8286        ((self.bits() >> Self::AFF3_SHIFT) & 0b11111111) as u8
8287    }
8288}
8289
8290#[cfg(feature = "el2")]
8291bitflags! {
8292    /// `VPIDR_EL2` system register value.
8293    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
8294    #[repr(transparent)]
8295    pub struct VpidrEl2: u64 {
8296    }
8297}
8298
8299#[cfg(feature = "el2")]
8300impl VpidrEl2 {
8301    /// Offset of the Revision field.
8302    pub const REVISION_SHIFT: u32 = 0;
8303    /// Mask for the Revision field.
8304    pub const REVISION_MASK: u64 = 0b1111;
8305    /// Offset of the PartNum field.
8306    pub const PARTNUM_SHIFT: u32 = 4;
8307    /// Mask for the PartNum field.
8308    pub const PARTNUM_MASK: u64 = 0b111111111111;
8309    /// Offset of the Architecture field.
8310    pub const ARCHITECTURE_SHIFT: u32 = 16;
8311    /// Mask for the Architecture field.
8312    pub const ARCHITECTURE_MASK: u64 = 0b1111;
8313    /// Offset of the Variant field.
8314    pub const VARIANT_SHIFT: u32 = 20;
8315    /// Mask for the Variant field.
8316    pub const VARIANT_MASK: u64 = 0b1111;
8317    /// Offset of the Implementer field.
8318    pub const IMPLEMENTER_SHIFT: u32 = 24;
8319    /// Mask for the Implementer field.
8320    pub const IMPLEMENTER_MASK: u64 = 0b11111111;
8321
8322    /// Returns the value of the `Revision` field.
8323    pub const fn revision(self) -> u8 {
8324        ((self.bits() >> Self::REVISION_SHIFT) & 0b1111) as u8
8325    }
8326
8327    /// Returns the value of the `PartNum` field.
8328    pub const fn partnum(self) -> u16 {
8329        ((self.bits() >> Self::PARTNUM_SHIFT) & 0b111111111111) as u16
8330    }
8331
8332    /// Returns the value of the `Architecture` field.
8333    pub const fn architecture(self) -> u8 {
8334        ((self.bits() >> Self::ARCHITECTURE_SHIFT) & 0b1111) as u8
8335    }
8336
8337    /// Returns the value of the `Variant` field.
8338    pub const fn variant(self) -> u8 {
8339        ((self.bits() >> Self::VARIANT_SHIFT) & 0b1111) as u8
8340    }
8341
8342    /// Returns the value of the `Implementer` field.
8343    pub const fn implementer(self) -> u8 {
8344        ((self.bits() >> Self::IMPLEMENTER_SHIFT) & 0b11111111) as u8
8345    }
8346}
8347
8348#[cfg(feature = "el2")]
8349bitflags! {
8350    /// `VSESR_EL2` system register value.
8351    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
8352    #[repr(transparent)]
8353    pub struct VsesrEl2: u64 {
8354        /// `ExT` bit.
8355        const EXT = 1 << 12;
8356        /// `IDS` bit.
8357        const IDS = 1 << 24;
8358    }
8359}
8360
8361#[cfg(feature = "el2")]
8362impl VsesrEl2 {
8363    /// Offset of the ISS field.
8364    pub const ISS_SHIFT: u32 = 0;
8365    /// Mask for the ISS field.
8366    pub const ISS_MASK: u64 = 0b111111111111111111111111;
8367    /// Offset of the ExT field.
8368    pub const EXT_SHIFT: u32 = 12;
8369    /// Offset of the AET field.
8370    pub const AET_SHIFT: u32 = 14;
8371    /// Mask for the AET field.
8372    pub const AET_MASK: u64 = 0b11;
8373    /// Offset of the IDS field.
8374    pub const IDS_SHIFT: u32 = 24;
8375
8376    /// Returns the value of the `ISS` field.
8377    pub const fn iss(self) -> u32 {
8378        ((self.bits() >> Self::ISS_SHIFT) & 0b111111111111111111111111) as u32
8379    }
8380
8381    /// Returns the value of the `AET` field.
8382    pub const fn aet(self) -> u8 {
8383        ((self.bits() >> Self::AET_SHIFT) & 0b11) as u8
8384    }
8385}
8386
8387#[cfg(feature = "el2")]
8388bitflags! {
8389    /// `VTCR_EL2` system register value.
8390    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
8391    #[repr(transparent)]
8392    pub struct VtcrEl2: u64 {
8393        /// RES1 bits in the `VTCR_EL2` register.
8394        const RES1 = 0b10000000000000000000000000000000;
8395        /// `VS` bit.
8396        const VS = 1 << 19;
8397        /// `HA` bit.
8398        const HA = 1 << 21;
8399        /// `HD` bit.
8400        const HD = 1 << 22;
8401        /// `HWU59` bit.
8402        const HWU59 = 1 << 25;
8403        /// `HWU60` bit.
8404        const HWU60 = 1 << 26;
8405        /// `HWU61` bit.
8406        const HWU61 = 1 << 27;
8407        /// `HWU62` bit.
8408        const HWU62 = 1 << 28;
8409        /// `NSW` bit.
8410        const NSW = 1 << 29;
8411        /// `NSA` bit.
8412        const NSA = 1 << 30;
8413        /// `DS` bit.
8414        const DS = 1 << 32;
8415        /// `SL2` bit.
8416        const SL2 = 1 << 33;
8417        /// `AssuredOnly` bit.
8418        const ASSUREDONLY = 1 << 34;
8419        /// `TL1` bit.
8420        const TL1 = 1 << 35;
8421        /// `S2PIE` bit.
8422        const S2PIE = 1 << 36;
8423        /// `S2POE` bit.
8424        const S2POE = 1 << 37;
8425        /// `D128` bit.
8426        const D128 = 1 << 38;
8427        /// `GCSH` bit.
8428        const GCSH = 1 << 40;
8429        /// `TL0` bit.
8430        const TL0 = 1 << 41;
8431        /// `HAFT` bit.
8432        const HAFT = 1 << 44;
8433        /// `HDBSS` bit.
8434        const HDBSS = 1 << 45;
8435    }
8436}
8437
8438#[cfg(feature = "el2")]
8439impl VtcrEl2 {
8440    /// Offset of the T0SZ field.
8441    pub const T0SZ_SHIFT: u32 = 0;
8442    /// Mask for the T0SZ field.
8443    pub const T0SZ_MASK: u64 = 0b111111;
8444    /// Offset of the SL0 field.
8445    pub const SL0_SHIFT: u32 = 6;
8446    /// Mask for the SL0 field.
8447    pub const SL0_MASK: u64 = 0b11;
8448    /// Offset of the IRGN0 field.
8449    pub const IRGN0_SHIFT: u32 = 8;
8450    /// Mask for the IRGN0 field.
8451    pub const IRGN0_MASK: u64 = 0b11;
8452    /// Offset of the ORGN0 field.
8453    pub const ORGN0_SHIFT: u32 = 10;
8454    /// Mask for the ORGN0 field.
8455    pub const ORGN0_MASK: u64 = 0b11;
8456    /// Offset of the SH0 field.
8457    pub const SH0_SHIFT: u32 = 12;
8458    /// Mask for the SH0 field.
8459    pub const SH0_MASK: u64 = 0b11;
8460    /// Offset of the TG0 field.
8461    pub const TG0_SHIFT: u32 = 14;
8462    /// Mask for the TG0 field.
8463    pub const TG0_MASK: u64 = 0b11;
8464    /// Offset of the PS field.
8465    pub const PS_SHIFT: u32 = 16;
8466    /// Mask for the PS field.
8467    pub const PS_MASK: u64 = 0b111;
8468    /// Offset of the VS field.
8469    pub const VS_SHIFT: u32 = 19;
8470    /// Offset of the HA field.
8471    pub const HA_SHIFT: u32 = 21;
8472    /// Offset of the HD field.
8473    pub const HD_SHIFT: u32 = 22;
8474    /// Offset of the HWU59 field.
8475    pub const HWU59_SHIFT: u32 = 25;
8476    /// Offset of the HWU60 field.
8477    pub const HWU60_SHIFT: u32 = 26;
8478    /// Offset of the HWU61 field.
8479    pub const HWU61_SHIFT: u32 = 27;
8480    /// Offset of the HWU62 field.
8481    pub const HWU62_SHIFT: u32 = 28;
8482    /// Offset of the NSW field.
8483    pub const NSW_SHIFT: u32 = 29;
8484    /// Offset of the NSA field.
8485    pub const NSA_SHIFT: u32 = 30;
8486    /// Offset of the DS field.
8487    pub const DS_SHIFT: u32 = 32;
8488    /// Offset of the SL2 field.
8489    pub const SL2_SHIFT: u32 = 33;
8490    /// Offset of the AssuredOnly field.
8491    pub const ASSUREDONLY_SHIFT: u32 = 34;
8492    /// Offset of the TL1 field.
8493    pub const TL1_SHIFT: u32 = 35;
8494    /// Offset of the S2PIE field.
8495    pub const S2PIE_SHIFT: u32 = 36;
8496    /// Offset of the S2POE field.
8497    pub const S2POE_SHIFT: u32 = 37;
8498    /// Offset of the D128 field.
8499    pub const D128_SHIFT: u32 = 38;
8500    /// Offset of the GCSH field.
8501    pub const GCSH_SHIFT: u32 = 40;
8502    /// Offset of the TL0 field.
8503    pub const TL0_SHIFT: u32 = 41;
8504    /// Offset of the HAFT field.
8505    pub const HAFT_SHIFT: u32 = 44;
8506    /// Offset of the HDBSS field.
8507    pub const HDBSS_SHIFT: u32 = 45;
8508
8509    /// Returns the value of the `T0SZ` field.
8510    pub const fn t0sz(self) -> u8 {
8511        ((self.bits() >> Self::T0SZ_SHIFT) & 0b111111) as u8
8512    }
8513
8514    /// Returns the value of the `SL0` field.
8515    pub const fn sl0(self) -> u8 {
8516        ((self.bits() >> Self::SL0_SHIFT) & 0b11) as u8
8517    }
8518
8519    /// Returns the value of the `IRGN0` field.
8520    pub const fn irgn0(self) -> u8 {
8521        ((self.bits() >> Self::IRGN0_SHIFT) & 0b11) as u8
8522    }
8523
8524    /// Returns the value of the `ORGN0` field.
8525    pub const fn orgn0(self) -> u8 {
8526        ((self.bits() >> Self::ORGN0_SHIFT) & 0b11) as u8
8527    }
8528
8529    /// Returns the value of the `SH0` field.
8530    pub const fn sh0(self) -> u8 {
8531        ((self.bits() >> Self::SH0_SHIFT) & 0b11) as u8
8532    }
8533
8534    /// Returns the value of the `TG0` field.
8535    pub const fn tg0(self) -> u8 {
8536        ((self.bits() >> Self::TG0_SHIFT) & 0b11) as u8
8537    }
8538
8539    /// Returns the value of the `PS` field.
8540    pub const fn ps(self) -> u8 {
8541        ((self.bits() >> Self::PS_SHIFT) & 0b111) as u8
8542    }
8543}
8544
8545#[cfg(feature = "el2")]
8546bitflags! {
8547    /// `VTTBR_EL2` system register value.
8548    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
8549    #[repr(transparent)]
8550    pub struct VttbrEl2: u64 {
8551        /// `CnP` bit.
8552        const CNP = 1 << 0;
8553    }
8554}
8555
8556#[cfg(feature = "el2")]
8557impl VttbrEl2 {
8558    /// Offset of the CnP field.
8559    pub const CNP_SHIFT: u32 = 0;
8560    /// Offset of the BADDR field.
8561    pub const BADDR_SHIFT: u32 = 1;
8562    /// Mask for the BADDR field.
8563    pub const BADDR_MASK: u64 = 0b11111111111111111111111111111111111111111111111;
8564    /// Offset of the SKL field.
8565    pub const SKL_SHIFT: u32 = 1;
8566    /// Mask for the SKL field.
8567    pub const SKL_MASK: u64 = 0b11;
8568    /// Offset of the VMID field.
8569    pub const VMID_SHIFT: u32 = 48;
8570    /// Mask for the VMID field.
8571    pub const VMID_MASK: u64 = 0b1111111111111111;
8572
8573    /// Returns the value of the `BADDR` field.
8574    pub const fn baddr(self) -> u64 {
8575        ((self.bits() >> Self::BADDR_SHIFT) & 0b11111111111111111111111111111111111111111111111)
8576            as u64
8577    }
8578
8579    /// Returns the value of the `SKL` field.
8580    pub const fn skl(self) -> u8 {
8581        ((self.bits() >> Self::SKL_SHIFT) & 0b11) as u8
8582    }
8583
8584    /// Returns the value of the `VMID` field.
8585    pub const fn vmid(self) -> u16 {
8586        ((self.bits() >> Self::VMID_SHIFT) & 0b1111111111111111) as u16
8587    }
8588}
8589
8590#[cfg(feature = "el3")]
8591bitflags! {
8592    /// `ZCR_EL3` system register value.
8593    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
8594    #[repr(transparent)]
8595    pub struct ZcrEl3: u64 {
8596    }
8597}
8598
8599#[cfg(feature = "el3")]
8600impl ZcrEl3 {
8601    /// Offset of the LEN field.
8602    pub const LEN_SHIFT: u32 = 0;
8603    /// Mask for the LEN field.
8604    pub const LEN_MASK: u64 = 0b1111;
8605
8606    /// Returns the value of the `LEN` field.
8607    pub const fn len(self) -> u8 {
8608        ((self.bits() >> Self::LEN_SHIFT) & 0b1111) as u8
8609    }
8610}
8611
8612#[cfg(feature = "el1")]
8613read_write_sysreg!(actlr_el1, u64, safe_read, fake::SYSREGS);
8614#[cfg(feature = "el2")]
8615read_write_sysreg!(actlr_el2, u64, safe_read, fake::SYSREGS);
8616#[cfg(feature = "el1")]
8617read_write_sysreg!(afsr0_el1, u64, safe_read, fake::SYSREGS);
8618#[cfg(feature = "el2")]
8619read_write_sysreg!(afsr0_el2, u64, safe_read, fake::SYSREGS);
8620#[cfg(feature = "el1")]
8621read_write_sysreg!(afsr1_el1, u64, safe_read, fake::SYSREGS);
8622#[cfg(feature = "el2")]
8623read_write_sysreg!(afsr1_el2, u64, safe_read, fake::SYSREGS);
8624#[cfg(feature = "el1")]
8625read_write_sysreg!(amair_el1, u64, safe_read, fake::SYSREGS);
8626#[cfg(feature = "el2")]
8627read_write_sysreg!(amair_el2, u64, safe_read, fake::SYSREGS);
8628#[cfg(feature = "el1")]
8629read_write_sysreg!(apiakeyhi_el1: s3_0_c2_c1_1, u64: ApiakeyhiEl1, safe_read, fake::SYSREGS);
8630#[cfg(feature = "el1")]
8631read_write_sysreg!(apiakeylo_el1: s3_0_c2_c1_0, u64: ApiakeyloEl1, safe_read, fake::SYSREGS);
8632#[cfg(feature = "el1")]
8633read_sysreg!(ccsidr_el1, u64: CcsidrEl1, safe, fake::SYSREGS);
8634#[cfg(feature = "el1")]
8635read_sysreg!(clidr_el1, u64: ClidrEl1, safe, fake::SYSREGS);
8636read_write_sysreg!(cntfrq_el0, u64: CntfrqEl0, safe_read, safe_write, fake::SYSREGS);
8637#[cfg(feature = "el2")]
8638read_write_sysreg!(cnthctl_el2, u64: CnthctlEl2, safe_read, safe_write, fake::SYSREGS);
8639#[cfg(feature = "el2")]
8640read_write_sysreg!(cntvoff_el2, u64: CntvoffEl2, safe_read, safe_write, fake::SYSREGS);
8641#[cfg(feature = "el1")]
8642read_write_sysreg!(contextidr_el1, u64: ContextidrEl1, safe_read, safe_write, fake::SYSREGS);
8643#[cfg(feature = "el2")]
8644read_write_sysreg!(contextidr_el2: s3_4_c13_c0_1, u64: ContextidrEl2, safe_read, safe_write, fake::SYSREGS);
8645#[cfg(feature = "el1")]
8646read_write_sysreg!(cpacr_el1, u64: CpacrEl1, safe_read, fake::SYSREGS);
8647#[cfg(feature = "el2")]
8648read_write_sysreg!(cptr_el2, u64: CptrEl2, safe_read, fake::SYSREGS);
8649#[cfg(feature = "el3")]
8650read_write_sysreg!(cptr_el3, u64: CptrEl3, safe_read, fake::SYSREGS);
8651#[cfg(feature = "el1")]
8652read_write_sysreg!(csselr_el1, u64: CsselrEl1, safe_read, safe_write, fake::SYSREGS);
8653read_sysreg!(ctr_el0, u64: CtrEl0, safe, fake::SYSREGS);
8654#[cfg(feature = "el1")]
8655read_write_sysreg!(disr_el1: s3_0_c12_c1_1, u64: DisrEl1, safe_read, safe_write, fake::SYSREGS);
8656read_write_sysreg!(dit: s3_3_c4_c2_5, u64: Dit, safe_read, safe_write, fake::SYSREGS);
8657#[cfg(feature = "el1")]
8658read_write_sysreg!(elr_el1, u64: ElrEl1, safe_read, fake::SYSREGS);
8659#[cfg(feature = "el2")]
8660read_write_sysreg!(elr_el2, u64: ElrEl2, safe_read, fake::SYSREGS);
8661#[cfg(feature = "el1")]
8662read_write_sysreg!(esr_el1, u64: EsrEl1, safe_read, safe_write, fake::SYSREGS);
8663#[cfg(feature = "el2")]
8664read_write_sysreg!(esr_el2, u64: EsrEl2, safe_read, safe_write, fake::SYSREGS);
8665#[cfg(feature = "el3")]
8666read_write_sysreg!(esr_el3, u64: EsrEl3, safe_read, safe_write, fake::SYSREGS);
8667#[cfg(feature = "el1")]
8668read_write_sysreg!(far_el1, u64: FarEl1, safe_read, fake::SYSREGS);
8669#[cfg(feature = "el2")]
8670read_write_sysreg!(far_el2, u64: FarEl2, safe_read, fake::SYSREGS);
8671#[cfg(feature = "el1")]
8672read_write_sysreg!(gcr_el1: s3_0_c1_c0_6, u64: GcrEl1, safe_read, fake::SYSREGS);
8673#[cfg(feature = "el1")]
8674read_write_sysreg!(gcscr_el1: s3_0_c2_c5_0, u64: GcscrEl1, safe_read, fake::SYSREGS);
8675#[cfg(feature = "el2")]
8676read_write_sysreg!(gcscr_el2: s3_4_c2_c5_0, u64: GcscrEl2, safe_read, fake::SYSREGS);
8677#[cfg(feature = "el2")]
8678read_write_sysreg!(hacr_el2, u64, safe_read, fake::SYSREGS);
8679#[cfg(feature = "el2")]
8680read_write_sysreg!(hcrx_el2: s3_4_c1_c2_2, u64: HcrxEl2, safe_read, fake::SYSREGS);
8681#[cfg(feature = "el2")]
8682read_write_sysreg!(hcr_el2, u64: HcrEl2, safe_read, fake::SYSREGS);
8683#[cfg(feature = "el2")]
8684read_write_sysreg!(hdfgrtr2_el2: s3_4_c3_c1_0, u64: Hdfgrtr2El2, safe_read, fake::SYSREGS);
8685#[cfg(feature = "el2")]
8686read_write_sysreg!(hdfgwtr2_el2: s3_4_c3_c1_1, u64: Hdfgwtr2El2, safe_read, fake::SYSREGS);
8687#[cfg(feature = "el2")]
8688read_write_sysreg!(hfgitr2_el2: s3_4_c3_c1_7, u64: Hfgitr2El2, safe_read, fake::SYSREGS);
8689#[cfg(feature = "el2")]
8690read_write_sysreg!(hfgrtr2_el2: s3_4_c3_c1_2, u64: Hfgrtr2El2, safe_read, fake::SYSREGS);
8691#[cfg(feature = "el2")]
8692read_write_sysreg!(hfgwtr2_el2: s3_4_c3_c1_3, u64: Hfgwtr2El2, safe_read, fake::SYSREGS);
8693#[cfg(feature = "el2")]
8694read_write_sysreg!(hfgwtr_el2: s3_4_c1_c1_5, u64: HfgwtrEl2, safe_read, fake::SYSREGS);
8695#[cfg(feature = "el2")]
8696read_write_sysreg!(hpfar_el2, u64: HpfarEl2, safe_read, fake::SYSREGS);
8697#[cfg(feature = "el2")]
8698read_write_sysreg!(hstr_el2, u64, safe_read, safe_write, fake::SYSREGS);
8699#[cfg(feature = "el1")]
8700read_write_sysreg!(icc_sre_el1: s3_0_c12_c12_5, u64: IccSreEl1, safe_read, fake::SYSREGS);
8701#[cfg(feature = "el2")]
8702read_write_sysreg!(icc_sre_el2: s3_4_c12_c9_5, u64: IccSreEl2, safe_read, fake::SYSREGS);
8703#[cfg(feature = "el3")]
8704read_write_sysreg! {
8705    /// # Safety
8706    ///
8707    /// The SRE bit of `icc_sre_el3` must not be changed from 1 to 0, as this can result in unpredictable behaviour.
8708    icc_sre_el3: s3_6_c12_c12_5, u64: IccSreEl3, safe_read, fake::SYSREGS
8709}
8710#[cfg(feature = "el2")]
8711read_write_sysreg!(ich_hcr_el2: s3_4_c12_c11_0, u64: IchHcrEl2, safe_read, fake::SYSREGS);
8712#[cfg(feature = "el2")]
8713read_write_sysreg!(ich_vmcr_el2: s3_4_c12_c11_7, u64: IchVmcrEl2, safe_read, safe_write, fake::SYSREGS);
8714#[cfg(feature = "el1")]
8715read_sysreg!(id_aa64dfr0_el1, u64: IdAa64dfr0El1, safe, fake::SYSREGS);
8716#[cfg(feature = "el1")]
8717read_sysreg!(id_aa64dfr1_el1, u64: IdAa64dfr1El1, safe, fake::SYSREGS);
8718#[cfg(feature = "el1")]
8719read_sysreg!(id_aa64mmfr0_el1, u64: IdAa64mmfr0El1, safe, fake::SYSREGS);
8720#[cfg(feature = "el1")]
8721read_sysreg!(id_aa64mmfr1_el1, u64: IdAa64mmfr1El1, safe, fake::SYSREGS);
8722#[cfg(feature = "el1")]
8723read_sysreg!(id_aa64mmfr2_el1, u64: IdAa64mmfr2El1, safe, fake::SYSREGS);
8724#[cfg(feature = "el1")]
8725read_sysreg!(id_aa64mmfr3_el1, u64: IdAa64mmfr3El1, safe, fake::SYSREGS);
8726#[cfg(feature = "el1")]
8727read_sysreg!(id_aa64pfr0_el1, u64: IdAa64pfr0El1, safe, fake::SYSREGS);
8728#[cfg(feature = "el1")]
8729read_sysreg!(id_aa64pfr1_el1, u64: IdAa64pfr1El1, safe, fake::SYSREGS);
8730#[cfg(feature = "el1")]
8731read_sysreg!(id_aa64smfr0_el1, u64: IdAa64smfr0El1, safe, fake::SYSREGS);
8732#[cfg(feature = "el1")]
8733read_sysreg!(isr_el1, u64: IsrEl1, safe, fake::SYSREGS);
8734#[cfg(feature = "el1")]
8735read_write_sysreg!(mair_el1, u64: MairEl1, safe_read, fake::SYSREGS);
8736#[cfg(feature = "el2")]
8737read_write_sysreg!(mair_el2, u64: MairEl2, safe_read, fake::SYSREGS);
8738#[cfg(feature = "el3")]
8739read_write_sysreg! {
8740    /// # Safety
8741    ///
8742    /// The caller must ensure that `value` is a correct and safe configuration value for the EL3 memory attribute indirection register.
8743    mair_el3, u64: MairEl3, safe_read, fake::SYSREGS
8744}
8745#[cfg(feature = "el1")]
8746read_write_sysreg!(mdccint_el1, u64: MdccintEl1, safe_read, safe_write, fake::SYSREGS);
8747#[cfg(feature = "el2")]
8748read_write_sysreg!(mdcr_el2, u64: MdcrEl2, safe_read, safe_write, fake::SYSREGS);
8749#[cfg(feature = "el3")]
8750read_write_sysreg!(mdcr_el3, u64: MdcrEl3, safe_read, safe_write, fake::SYSREGS);
8751#[cfg(feature = "el1")]
8752read_write_sysreg!(mdscr_el1, u64: MdscrEl1, safe_read, safe_write, fake::SYSREGS);
8753#[cfg(feature = "el1")]
8754read_sysreg!(midr_el1, u64: MidrEl1, safe, fake::SYSREGS);
8755#[cfg(feature = "el2")]
8756read_write_sysreg!(mpam2_el2: s3_4_c10_c5_0, u64: Mpam2El2, safe_read, fake::SYSREGS);
8757#[cfg(feature = "el3")]
8758read_write_sysreg!(mpam3_el3: s3_6_c10_c5_0, u64: Mpam3El3, safe_read, fake::SYSREGS);
8759#[cfg(feature = "el2")]
8760read_write_sysreg!(mpamhcr_el2: s3_4_c10_c4_0, u64: MpamhcrEl2, safe_read, fake::SYSREGS);
8761#[cfg(feature = "el1")]
8762read_sysreg!(mpamidr_el1: s3_0_c10_c4_4, u64: MpamidrEl1, safe, fake::SYSREGS);
8763#[cfg(feature = "el2")]
8764read_write_sysreg!(mpamvpm0_el2: s3_4_c10_c6_0, u64: Mpamvpm0El2, safe_read, fake::SYSREGS);
8765#[cfg(feature = "el2")]
8766read_write_sysreg!(mpamvpm1_el2: s3_4_c10_c6_1, u64: Mpamvpm1El2, safe_read, fake::SYSREGS);
8767#[cfg(feature = "el2")]
8768read_write_sysreg!(mpamvpm2_el2: s3_4_c10_c6_2, u64: Mpamvpm2El2, safe_read, fake::SYSREGS);
8769#[cfg(feature = "el2")]
8770read_write_sysreg!(mpamvpm3_el2: s3_4_c10_c6_3, u64: Mpamvpm3El2, safe_read, fake::SYSREGS);
8771#[cfg(feature = "el2")]
8772read_write_sysreg!(mpamvpm4_el2: s3_4_c10_c6_4, u64: Mpamvpm4El2, safe_read, fake::SYSREGS);
8773#[cfg(feature = "el2")]
8774read_write_sysreg!(mpamvpm5_el2: s3_4_c10_c6_5, u64: Mpamvpm5El2, safe_read, fake::SYSREGS);
8775#[cfg(feature = "el2")]
8776read_write_sysreg!(mpamvpm6_el2: s3_4_c10_c6_6, u64: Mpamvpm6El2, safe_read, fake::SYSREGS);
8777#[cfg(feature = "el2")]
8778read_write_sysreg!(mpamvpm7_el2: s3_4_c10_c6_7, u64: Mpamvpm7El2, safe_read, fake::SYSREGS);
8779#[cfg(feature = "el2")]
8780read_write_sysreg!(mpamvpmv_el2: s3_4_c10_c4_1, u64: MpamvpmvEl2, safe_read, fake::SYSREGS);
8781#[cfg(feature = "el1")]
8782read_sysreg!(mpidr_el1, u64: MpidrEl1, safe, fake::SYSREGS);
8783#[cfg(feature = "el1")]
8784read_write_sysreg!(par_el1, u64: ParEl1, safe_read, fake::SYSREGS);
8785read_write_sysreg!(pmcr_el0: s3_3_c9_c12_0, u64: PmcrEl0, safe_read, safe_write, fake::SYSREGS);
8786#[cfg(feature = "el1")]
8787read_write_sysreg!(rgsr_el1: s3_0_c1_c0_5, u64: RgsrEl1, safe_read, safe_write, fake::SYSREGS);
8788#[cfg(feature = "el3")]
8789read_write_sysreg!(scr_el3, u64: ScrEl3, safe_read, fake::SYSREGS);
8790#[cfg(feature = "el1")]
8791read_write_sysreg!(sctlr_el1, u64: SctlrEl1, safe_read, fake::SYSREGS);
8792#[cfg(feature = "el2")]
8793read_write_sysreg!(sctlr_el2, u64: SctlrEl2, safe_read, fake::SYSREGS);
8794#[cfg(feature = "el3")]
8795read_write_sysreg! {
8796    /// # Safety
8797    ///
8798    /// The caller must ensure that `value` is a correct and safe configuration value for the EL3 system control register.
8799    sctlr_el3, u64: SctlrEl3, safe_read, fake::SYSREGS
8800}
8801#[cfg(feature = "el3")]
8802read_write_sysreg!(smcr_el3: s3_6_c1_c2_6, u64: SmcrEl3, safe_read, fake::SYSREGS);
8803#[cfg(feature = "el1")]
8804read_write_sysreg!(spsr_el1, u64: SpsrEl1, safe_read, fake::SYSREGS);
8805#[cfg(feature = "el2")]
8806read_write_sysreg!(spsr_el2, u64: SpsrEl2, safe_read, fake::SYSREGS);
8807#[cfg(feature = "el3")]
8808read_write_sysreg!(spsr_el3, u64: SpsrEl3, safe_read, fake::SYSREGS);
8809#[cfg(feature = "el1")]
8810read_write_sysreg!(sp_el1, u64: SpEl1, safe_read, fake::SYSREGS);
8811#[cfg(feature = "el2")]
8812read_write_sysreg!(sp_el2, u64: SpEl2, safe_read, fake::SYSREGS);
8813#[cfg(feature = "el1")]
8814read_write_sysreg!(tcr2_el1: s3_0_c2_c0_3, u64: Tcr2El1, safe_read, fake::SYSREGS);
8815#[cfg(feature = "el2")]
8816read_write_sysreg!(tcr2_el2: s3_4_c2_c0_3, u64: Tcr2El2, safe_read, fake::SYSREGS);
8817#[cfg(feature = "el1")]
8818read_write_sysreg!(tcr_el1, u64: TcrEl1, safe_read, fake::SYSREGS);
8819#[cfg(feature = "el2")]
8820read_write_sysreg!(tcr_el2, u64: TcrEl2, safe_read, fake::SYSREGS);
8821#[cfg(feature = "el3")]
8822read_write_sysreg! {
8823    /// # Safety
8824    ///
8825    /// The caller must ensure that `value` is a correct and safe configuration value for the EL3 translation control register.
8826    tcr_el3, u64: TcrEl3, safe_read, fake::SYSREGS
8827}
8828#[cfg(feature = "el1")]
8829read_write_sysreg!(tfsre0_el1: s3_0_c5_c6_1, u64: Tfsre0El1, safe_read, safe_write, fake::SYSREGS);
8830#[cfg(feature = "el1")]
8831read_write_sysreg!(tfsr_el1: s3_0_c5_c6_0, u64: TfsrEl1, safe_read, safe_write, fake::SYSREGS);
8832#[cfg(feature = "el2")]
8833read_write_sysreg!(tfsr_el2: s3_4_c5_c6_0, u64: TfsrEl2, safe_read, safe_write, fake::SYSREGS);
8834read_write_sysreg!(tpidrro_el0, u64: TpidrroEl0, safe_read, fake::SYSREGS);
8835read_write_sysreg!(tpidr_el0, u64: TpidrEl0, safe_read, fake::SYSREGS);
8836#[cfg(feature = "el1")]
8837read_write_sysreg!(tpidr_el1, u64: TpidrEl1, safe_read, fake::SYSREGS);
8838#[cfg(feature = "el2")]
8839read_write_sysreg!(tpidr_el2, u64: TpidrEl2, safe_read, fake::SYSREGS);
8840#[cfg(feature = "el1")]
8841read_write_sysreg! {
8842    /// # Safety
8843    ///
8844    /// The base address must point to a valid and properly aligned translation table.
8845    ttbr0_el1, u64: Ttbr0El1, safe_read, fake::SYSREGS
8846}
8847#[cfg(feature = "el2")]
8848read_write_sysreg! {
8849    /// # Safety
8850    ///
8851    /// The base address must point to a valid and properly aligned translation table.
8852    ttbr0_el2, u64: Ttbr0El2, safe_read, fake::SYSREGS
8853}
8854#[cfg(feature = "el3")]
8855read_write_sysreg! {
8856    /// # Safety
8857    ///
8858    /// The base address must point to a valid and properly aligned translation table.
8859    ttbr0_el3, u64: Ttbr0El3, safe_read, fake::SYSREGS
8860}
8861#[cfg(feature = "el1")]
8862read_write_sysreg! {
8863    /// # Safety
8864    ///
8865    /// The base address must point to a valid and properly aligned translation table.
8866    ttbr1_el1, u64: Ttbr1El1, safe_read, fake::SYSREGS
8867}
8868#[cfg(feature = "el2")]
8869read_write_sysreg! {
8870    /// # Safety
8871    ///
8872    /// The base address must point to a valid and properly aligned translation table.
8873    ttbr1_el2, u64: Ttbr1El2, safe_read, fake::SYSREGS
8874}
8875#[cfg(feature = "el1")]
8876read_write_sysreg! {
8877    /// # Safety
8878    ///
8879    /// The base address must point to a valid exception vector.
8880    vbar_el1, u64: VbarEl1, safe_read, fake::SYSREGS
8881}
8882#[cfg(feature = "el2")]
8883read_write_sysreg! {
8884    /// # Safety
8885    ///
8886    /// The base address must point to a valid exception vector.
8887    vbar_el2, u64: VbarEl2, safe_read, fake::SYSREGS
8888}
8889#[cfg(feature = "el2")]
8890read_write_sysreg!(vdisr_el2: s3_4_c12_c1_1, u64: VdisrEl2, safe_read, safe_write, fake::SYSREGS);
8891#[cfg(feature = "el2")]
8892read_write_sysreg!(vmpidr_el2, u64: VmpidrEl2, safe_read, safe_write, fake::SYSREGS);
8893#[cfg(feature = "el2")]
8894read_write_sysreg!(vpidr_el2, u64: VpidrEl2, safe_read, safe_write, fake::SYSREGS);
8895#[cfg(feature = "el2")]
8896read_write_sysreg!(vsesr_el2: s3_4_c5_c2_3, u64: VsesrEl2, safe_read, safe_write, fake::SYSREGS);
8897#[cfg(feature = "el2")]
8898read_write_sysreg!(vtcr_el2, u64: VtcrEl2, safe_read, fake::SYSREGS);
8899#[cfg(feature = "el2")]
8900read_write_sysreg! {
8901    /// # Safety
8902    ///
8903    /// The base address must point to a valid and properly aligned stage 2 translation table.
8904    vttbr_el2, u64: VttbrEl2, safe_read, fake::SYSREGS
8905}
8906#[cfg(feature = "el3")]
8907read_write_sysreg!(zcr_el3: s3_6_c1_c2_0, u64: ZcrEl3, safe_read, fake::SYSREGS);
arm_sysregs/lib.rs

arm_sysregs/
lib.rs
