Enum CleverOpcode

Source

#[non_exhaustive]pub enum CleverOpcode {
Show 248 variants    Und0,
    Add {
        lock: bool,
        flags: bool,
    },
    Sub {
        lock: bool,
        flags: bool,
    },
    And {
        lock: bool,
        flags: bool,
    },
    Or {
        lock: bool,
        flags: bool,
    },
    Xor {
        lock: bool,
        flags: bool,
    },
    Mul {
        ss: u16,
        flags: bool,
    },
    Div {
        ss: u16,
        wide: bool,
        flags: bool,
    },
    Mov,
    Lea,
    MovRD {
        r: CleverRegister,
    },
    MovRS {
        r: CleverRegister,
    },
    LeaRD {
        r: CleverRegister,
    },
    Nop10 {
        any: u16,
    },
    Nop11 {
        any: u16,
    },
    Nop12 {
        any: u16,
    },
    Nop13 {
        any: u16,
    },
    Push,
    Pop,
    PushR {
        r: CleverRegister,
    },
    PopR {
        r: CleverRegister,
    },
    Stogpr,
    Stoar,
    Rstogpr,
    Rstoar,
    Pushgpr,
    Pushar,
    Popgpr,
    Popar,
    Movsx {
        flags: bool,
    },
    Bswap {
        flags: bool,
    },
    Movsif {
        flags: bool,
    },
    Movxf {
        ss: u16,
        int: bool,
        flags: bool,
    },
    Movfsi {
        flags: bool,
    },
    Movfx {
        ss: u16,
        int: bool,
        flags: bool,
    },
    Cvtf {
        flags: bool,
    },
    Repbi {
        cc: ConditionCode,
    },
    Repbc,
    Bcpy {
        ss: u16,
    },
    Bsto {
        ss: u16,
    },
    Bsca {
        ss: u16,
    },
    Bcmp {
        ss: u16,
    },
    Btst {
        ss: u16,
    },
    Lsh {
        l: bool,
        f: bool,
    },
    Rsh {
        l: bool,
        f: bool,
    },
    Arsh {
        l: bool,
        f: bool,
    },
    Lshc {
        l: bool,
        f: bool,
    },
    Rshc {
        l: bool,
        f: bool,
    },
    Lrot {
        l: bool,
        f: bool,
    },
    Rrot {
        l: bool,
        f: bool,
    },
    LshR {
        r: CleverRegister,
    },
    RshR {
        r: CleverRegister,
    },
    ArshR {
        r: CleverRegister,
    },
    LshcR {
        r: CleverRegister,
    },
    RshcR {
        r: CleverRegister,
    },
    LrotR {
        r: CleverRegister,
    },
    RrotR {
        r: CleverRegister,
    },
    Imul {
        ss: u16,
        flags: bool,
    },
    AddRD {
        r: CleverRegister,
    },
    SubRD {
        r: CleverRegister,
    },
    AndRD {
        r: CleverRegister,
    },
    OrRD {
        r: CleverRegister,
    },
    XorRD {
        r: CleverRegister,
    },
    BNot {
        l: bool,
        f: bool,
    },
    Neg {
        l: bool,
        f: bool,
    },
    Idiv {
        ss: u16,
        wide: bool,
        flags: bool,
    },
    AddRS {
        r: CleverRegister,
    },
    SubRS {
        r: CleverRegister,
    },
    AndRS {
        r: CleverRegister,
    },
    OrRS {
        r: CleverRegister,
    },
    XorRS {
        r: CleverRegister,
    },
    BNotR {
        r: CleverRegister,
    },
    NegR {
        r: CleverRegister,
    },
    Cmp,
    Test,
    CmpR {
        r: CleverRegister,
    },
    TestR {
        r: CleverRegister,
    },
    Round {
        f: bool,
    },
    Ceil {
        f: bool,
    },
    Floor {
        f: bool,
    },
    FAbs {
        f: bool,
    },
    FNeg {
        f: bool,
    },
    FInv {
        f: bool,
    },
    FAdd {
        f: bool,
    },
    FSub {
        f: bool,
    },
    FMul {
        f: bool,
    },
    FDiv {
        f: bool,
    },
    FRem {
        f: bool,
    },
    FFma {
        f: bool,
    },
    FCmpz,
    FCmp,
    Exp {
        f: bool,
    },
    Ln {
        f: bool,
    },
    Lg {
        f: bool,
    },
    Sin {
        f: bool,
    },
    Cos {
        f: bool,
    },
    Tan {
        f: bool,
    },
    Asin {
        f: bool,
    },
    Acos {
        f: bool,
    },
    Atan {
        f: bool,
    },
    Exp2 {
        f: bool,
    },
    Log10 {
        f: bool,
    },
    Lnp1 {
        f: bool,
    },
    Expm1 {
        f: bool,
    },
    Sqrt {
        f: bool,
    },
    FRaiseExcept,
    FTriggerExcept,
    Xchg,
    Cmpxchg,
    Wcmpxchg,
    Fence,
    RPoll {
        r: CleverRegister,
    },
    Vec,
    Vmov,
    VShuffle,
    CBP0A {
        w: i8,
    },
    CBC0A {
        w: i8,
    },
    CBV0A {
        w: i8,
    },
    CBZ0A {
        w: i8,
    },
    CBL0A {
        w: i8,
    },
    CBLE0A {
        w: i8,
    },
    CBBE0A {
        w: i8,
    },
    CBM0A {
        w: i8,
    },
    CBPS0A {
        w: i8,
    },
    CBA0A {
        w: i8,
    },
    CBG0A {
        w: i8,
    },
    CBGE0A {
        w: i8,
    },
    CBNZ0A {
        w: i8,
    },
    CBNV0A {
        w: i8,
    },
    CBNC0A {
        w: i8,
    },
    CBNP0A {
        w: i8,
    },
    CBP0R {
        w: i8,
    },
    CBC0R {
        w: i8,
    },
    CBV0R {
        w: i8,
    },
    CBZ0R {
        w: i8,
    },
    CBL0R {
        w: i8,
    },
    CBLE0R {
        w: i8,
    },
    CBBE0R {
        w: i8,
    },
    CBM0R {
        w: i8,
    },
    CBPS0R {
        w: i8,
    },
    CBA0R {
        w: i8,
    },
    CBG0R {
        w: i8,
    },
    CBGE0R {
        w: i8,
    },
    CBNZ0R {
        w: i8,
    },
    CBNV0R {
        w: i8,
    },
    CBNC0R {
        w: i8,
    },
    CBNP0R {
        w: i8,
    },
    CBP1A {
        w: i8,
    },
    CBC1A {
        w: i8,
    },
    CBV1A {
        w: i8,
    },
    CBZ1A {
        w: i8,
    },
    CBL1A {
        w: i8,
    },
    CBLE1A {
        w: i8,
    },
    CBBE1A {
        w: i8,
    },
    CBM1A {
        w: i8,
    },
    CBPS1A {
        w: i8,
    },
    CBA1A {
        w: i8,
    },
    CBG1A {
        w: i8,
    },
    CBGE1A {
        w: i8,
    },
    CBNZ1A {
        w: i8,
    },
    CBNV1A {
        w: i8,
    },
    CBNC1A {
        w: i8,
    },
    CBNP1A {
        w: i8,
    },
    CBP1R {
        w: i8,
    },
    CBC1R {
        w: i8,
    },
    CBV1R {
        w: i8,
    },
    CBZ1R {
        w: i8,
    },
    CBL1R {
        w: i8,
    },
    CBLE1R {
        w: i8,
    },
    CBBE1R {
        w: i8,
    },
    CBM1R {
        w: i8,
    },
    CBPS1R {
        w: i8,
    },
    CBA1R {
        w: i8,
    },
    CBG1R {
        w: i8,
    },
    CBGE1R {
        w: i8,
    },
    CBNZ1R {
        w: i8,
    },
    CBNV1R {
        w: i8,
    },
    CBNC1R {
        w: i8,
    },
    CBNP1R {
        w: i8,
    },
    CBP2A {
        w: i8,
    },
    CBC2A {
        w: i8,
    },
    CBV2A {
        w: i8,
    },
    CBZ2A {
        w: i8,
    },
    CBL2A {
        w: i8,
    },
    CBLE2A {
        w: i8,
    },
    CBBE2A {
        w: i8,
    },
    CBM2A {
        w: i8,
    },
    CBPS2A {
        w: i8,
    },
    CBA2A {
        w: i8,
    },
    CBG2A {
        w: i8,
    },
    CBGE2A {
        w: i8,
    },
    CBNZ2A {
        w: i8,
    },
    CBNV2A {
        w: i8,
    },
    CBNC2A {
        w: i8,
    },
    CBNP2A {
        w: i8,
    },
    CBP2R {
        w: i8,
    },
    CBC2R {
        w: i8,
    },
    CBV2R {
        w: i8,
    },
    CBZ2R {
        w: i8,
    },
    CBL2R {
        w: i8,
    },
    CBLE2R {
        w: i8,
    },
    CBBE2R {
        w: i8,
    },
    CBM2R {
        w: i8,
    },
    CBPS2R {
        w: i8,
    },
    CBA2R {
        w: i8,
    },
    CBG2R {
        w: i8,
    },
    CBGE2R {
        w: i8,
    },
    CBNZ2R {
        w: i8,
    },
    CBNV2R {
        w: i8,
    },
    CBNC2R {
        w: i8,
    },
    CBNP2R {
        w: i8,
    },
    JmpA {
        ss: u16,
    },
    CallA {
        ss: u16,
    },
    FcallA {
        ss: u16,
    },
    Ret,
    Scall,
    Int {
        i: u16,
    },
    IjmpA {
        r: CleverRegister,
    },
    IcallA {
        r: CleverRegister,
    },
    IfcallA,
    JmpSM {
        ss: u16,
    },
    CallSM {
        v: bool,
        ss: u16,
    },
    RetRSM,
    JmpR {
        ss: u16,
    },
    CallR {
        ss: u16,
    },
    FcallR {
        ss: u16,
    },
    IjmpR {
        r: CleverRegister,
    },
    IcallR {
        r: CleverRegister,
    },
    IfcallR,
    JmpSMR {
        ss: u16,
    },
    CallSMR {
        ss: u16,
        v: bool,
    },
    Halt,
    Pcfl,
    FlAll,
    Dflush,
    Iflush,
    In {
        ss: u16,
    },
    Out {
        ss: u16,
    },
    StoRegF,
    RstRegF,
    Scret,
    Iret,
    Hcall,
    Hret,
    Hresume,
    VMCreate,
    VMDestroy,
    Und255,
}

Variants (Non-exhaustive)§

This enum is marked as non-exhaustive

Non-exhaustive enums could have additional variants added in future. Therefore, when matching against variants of non-exhaustive enums, an extra wildcard arm must be added to account for any future variants.

§