1#![allow(clippy::missing_safety_doc)]
2#![allow(clippy::identity_op)]
3#![allow(clippy::unnecessary_cast)]
4#![allow(clippy::erasing_op)]
5#[doc = "Instruction local memory base address."]
6pub mod milmb {
7 #[doc = "ILM (Instruction Local Memory) Base Register"]
8 #[repr(transparent)]
9 #[derive(Copy, Clone, Eq, PartialEq)]
10 pub struct Milmb(pub u32);
11 impl Milmb {
12 #[doc = "ILM Enable"]
13 #[must_use]
14 #[inline(always)]
15 pub const fn ien(&self) -> bool {
16 let val = (self.0 >> 0usize) & 0x01;
17 val != 0
18 }
19 #[doc = "ILM Enable"]
20 #[inline(always)]
21 pub const fn set_ien(&mut self, val: bool) {
22 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
23 }
24 #[doc = "ECC Enable"]
25 #[must_use]
26 #[inline(always)]
27 pub const fn eccen(&self) -> u8 {
28 let val = (self.0 >> 1usize) & 0x03;
29 val as u8
30 }
31 #[doc = "ECC Enable"]
32 #[inline(always)]
33 pub const fn set_eccen(&mut self, val: u8) {
34 self.0 = (self.0 & !(0x03 << 1usize)) | (((val as u32) & 0x03) << 1usize);
35 }
36 #[doc = "Read/Write ECC"]
37 #[must_use]
38 #[inline(always)]
39 pub const fn rwecc(&self) -> bool {
40 let val = (self.0 >> 3usize) & 0x01;
41 val != 0
42 }
43 #[doc = "Read/Write ECC"]
44 #[inline(always)]
45 pub const fn set_rwecc(&mut self, val: bool) {
46 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
47 }
48 #[doc = "Base Physical Address (IBPA)"]
49 #[must_use]
50 #[inline(always)]
51 pub const fn ibpa(&self) -> u32 {
52 let val = (self.0 >> 10usize) & 0x003f_ffff;
53 val as u32
54 }
55 #[doc = "Base Physical Address (IBPA)"]
56 #[inline(always)]
57 pub const fn set_ibpa(&mut self, val: u32) {
58 self.0 =
59 (self.0 & !(0x003f_ffff << 10usize)) | (((val as u32) & 0x003f_ffff) << 10usize);
60 }
61 }
62 impl Default for Milmb {
63 #[inline(always)]
64 fn default() -> Milmb {
65 Milmb(0)
66 }
67 }
68 impl core::fmt::Debug for Milmb {
69 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
70 f.debug_struct("Milmb")
71 .field("ien", &self.ien())
72 .field("eccen", &self.eccen())
73 .field("rwecc", &self.rwecc())
74 .field("ibpa", &self.ibpa())
75 .finish()
76 }
77 }
78 #[cfg(feature = "defmt")]
79 impl defmt::Format for Milmb {
80 fn format(&self, f: defmt::Formatter) {
81 defmt::write!(
82 f,
83 "Milmb {{ ien: {=bool:?}, eccen: {=u8:?}, rwecc: {=bool:?}, ibpa: {=u32:?} }}",
84 self.ien(),
85 self.eccen(),
86 self.rwecc(),
87 self.ibpa()
88 )
89 }
90 }
91 #[inline(always)]
92 unsafe fn _read() -> usize {
93 let r: usize;
94 unsafe {
95 core :: arch :: asm ! ("csrrs {0}, 0x7c0, x0" , out (reg) r);
96 }
97 r
98 }
99 #[inline(always)]
100 unsafe fn _write(bits: usize) {
101 unsafe {
102 core :: arch :: asm ! ("csrrw x0, 0x7c0, {0}" , in (reg) bits);
103 }
104 }
105 #[inline(always)]
106 unsafe fn _set(bits: usize) {
107 unsafe {
108 core :: arch :: asm ! ("csrrs x0, 0x7c0, {0}" , in (reg) bits);
109 }
110 }
111 #[inline(always)]
112 unsafe fn _clear(bits: usize) {
113 unsafe {
114 core :: arch :: asm ! ("csrrc x0, 0x7c0, {0}" , in (reg) bits);
115 }
116 }
117 #[doc = r" Read the CSR value."]
118 #[inline]
119 pub fn read() -> Milmb {
120 unsafe { Milmb(_read() as u32) }
121 }
122 #[doc = r" Write the CSR value."]
123 #[inline]
124 pub unsafe fn write(val: Milmb) {
125 unsafe {
126 _write(val.0 as usize);
127 }
128 }
129 #[doc = r" Read-modify-write the CSR."]
130 #[inline]
131 pub unsafe fn modify<R>(f: impl FnOnce(&mut Milmb) -> R) -> R {
132 let mut val = read();
133 let res = f(&mut val);
134 unsafe {
135 write(val);
136 }
137 res
138 }
139 #[doc = "ILM Enable"]
140 #[inline]
141 pub unsafe fn set_ien() {
142 unsafe {
143 _set(1usize);
144 }
145 }
146 #[doc = "ILM Enable"]
147 #[inline]
148 pub unsafe fn clear_ien() {
149 unsafe {
150 _clear(1usize);
151 }
152 }
153 #[doc = "ECC Enable"]
154 #[inline]
155 pub unsafe fn set_eccen(val: u8) {
156 let mut bits = unsafe { _read() };
157 bits &= !(3usize << 1usize);
158 bits |= (val as usize & 3usize) << 1usize;
159 unsafe {
160 _write(bits);
161 }
162 }
163 #[doc = "Read/Write ECC"]
164 #[inline]
165 pub unsafe fn set_rwecc() {
166 unsafe {
167 _set(8usize);
168 }
169 }
170 #[doc = "Read/Write ECC"]
171 #[inline]
172 pub unsafe fn clear_rwecc() {
173 unsafe {
174 _clear(8usize);
175 }
176 }
177 #[doc = "Base Physical Address (IBPA)"]
178 #[inline]
179 pub unsafe fn set_ibpa(val: u32) {
180 let mut bits = unsafe { _read() };
181 bits &= !(4194303usize << 10usize);
182 bits |= (val as usize & 4194303usize) << 10usize;
183 unsafe {
184 _write(bits);
185 }
186 }
187}
188#[doc = "Data local memory base address."]
189pub mod mdlmb {
190 #[doc = "DLM (Data Local Memory) Base Register"]
191 #[repr(transparent)]
192 #[derive(Copy, Clone, Eq, PartialEq)]
193 pub struct Mdlmb(pub u32);
194 impl Mdlmb {
195 #[doc = "DLM Enable"]
196 #[must_use]
197 #[inline(always)]
198 pub const fn den(&self) -> bool {
199 let val = (self.0 >> 0usize) & 0x01;
200 val != 0
201 }
202 #[doc = "DLM Enable"]
203 #[inline(always)]
204 pub const fn set_den(&mut self, val: bool) {
205 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
206 }
207 #[doc = "ECC Enable"]
208 #[must_use]
209 #[inline(always)]
210 pub const fn eccen(&self) -> u8 {
211 let val = (self.0 >> 1usize) & 0x03;
212 val as u8
213 }
214 #[doc = "ECC Enable"]
215 #[inline(always)]
216 pub const fn set_eccen(&mut self, val: u8) {
217 self.0 = (self.0 & !(0x03 << 1usize)) | (((val as u32) & 0x03) << 1usize);
218 }
219 #[doc = "Read/Write ECC"]
220 #[must_use]
221 #[inline(always)]
222 pub const fn rwecc(&self) -> bool {
223 let val = (self.0 >> 3usize) & 0x01;
224 val != 0
225 }
226 #[doc = "Read/Write ECC"]
227 #[inline(always)]
228 pub const fn set_rwecc(&mut self, val: bool) {
229 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
230 }
231 #[doc = "Reserved"]
232 #[must_use]
233 #[inline(always)]
234 pub const fn reserved(&self) -> u8 {
235 let val = (self.0 >> 4usize) & 0x3f;
236 val as u8
237 }
238 #[doc = "Reserved"]
239 #[inline(always)]
240 pub const fn set_reserved(&mut self, val: u8) {
241 self.0 = (self.0 & !(0x3f << 4usize)) | (((val as u32) & 0x3f) << 4usize);
242 }
243 #[doc = "Base Physical Address (DBPA)"]
244 #[must_use]
245 #[inline(always)]
246 pub const fn dbpa(&self) -> u32 {
247 let val = (self.0 >> 10usize) & 0x003f_ffff;
248 val as u32
249 }
250 #[doc = "Base Physical Address (DBPA)"]
251 #[inline(always)]
252 pub const fn set_dbpa(&mut self, val: u32) {
253 self.0 =
254 (self.0 & !(0x003f_ffff << 10usize)) | (((val as u32) & 0x003f_ffff) << 10usize);
255 }
256 }
257 impl Default for Mdlmb {
258 #[inline(always)]
259 fn default() -> Mdlmb {
260 Mdlmb(0)
261 }
262 }
263 impl core::fmt::Debug for Mdlmb {
264 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
265 f.debug_struct("Mdlmb")
266 .field("den", &self.den())
267 .field("eccen", &self.eccen())
268 .field("rwecc", &self.rwecc())
269 .field("reserved", &self.reserved())
270 .field("dbpa", &self.dbpa())
271 .finish()
272 }
273 }
274 #[cfg(feature = "defmt")]
275 impl defmt::Format for Mdlmb {
276 fn format(&self, f: defmt::Formatter) {
277 defmt::write!(
278 f,
279 "Mdlmb {{ den: {=bool:?}, eccen: {=u8:?}, rwecc: {=bool:?}, reserved: {=u8:?}, dbpa: {=u32:?} }}",
280 self.den(),
281 self.eccen(),
282 self.rwecc(),
283 self.reserved(),
284 self.dbpa()
285 )
286 }
287 }
288 #[inline(always)]
289 unsafe fn _read() -> usize {
290 let r: usize;
291 unsafe {
292 core :: arch :: asm ! ("csrrs {0}, 0x7c1, x0" , out (reg) r);
293 }
294 r
295 }
296 #[inline(always)]
297 unsafe fn _write(bits: usize) {
298 unsafe {
299 core :: arch :: asm ! ("csrrw x0, 0x7c1, {0}" , in (reg) bits);
300 }
301 }
302 #[inline(always)]
303 unsafe fn _set(bits: usize) {
304 unsafe {
305 core :: arch :: asm ! ("csrrs x0, 0x7c1, {0}" , in (reg) bits);
306 }
307 }
308 #[inline(always)]
309 unsafe fn _clear(bits: usize) {
310 unsafe {
311 core :: arch :: asm ! ("csrrc x0, 0x7c1, {0}" , in (reg) bits);
312 }
313 }
314 #[doc = r" Read the CSR value."]
315 #[inline]
316 pub fn read() -> Mdlmb {
317 unsafe { Mdlmb(_read() as u32) }
318 }
319 #[doc = r" Write the CSR value."]
320 #[inline]
321 pub unsafe fn write(val: Mdlmb) {
322 unsafe {
323 _write(val.0 as usize);
324 }
325 }
326 #[doc = r" Read-modify-write the CSR."]
327 #[inline]
328 pub unsafe fn modify<R>(f: impl FnOnce(&mut Mdlmb) -> R) -> R {
329 let mut val = read();
330 let res = f(&mut val);
331 unsafe {
332 write(val);
333 }
334 res
335 }
336 #[doc = "DLM Enable"]
337 #[inline]
338 pub unsafe fn set_den() {
339 unsafe {
340 _set(1usize);
341 }
342 }
343 #[doc = "DLM Enable"]
344 #[inline]
345 pub unsafe fn clear_den() {
346 unsafe {
347 _clear(1usize);
348 }
349 }
350 #[doc = "ECC Enable"]
351 #[inline]
352 pub unsafe fn set_eccen(val: u8) {
353 let mut bits = unsafe { _read() };
354 bits &= !(3usize << 1usize);
355 bits |= (val as usize & 3usize) << 1usize;
356 unsafe {
357 _write(bits);
358 }
359 }
360 #[doc = "Read/Write ECC"]
361 #[inline]
362 pub unsafe fn set_rwecc() {
363 unsafe {
364 _set(8usize);
365 }
366 }
367 #[doc = "Read/Write ECC"]
368 #[inline]
369 pub unsafe fn clear_rwecc() {
370 unsafe {
371 _clear(8usize);
372 }
373 }
374 #[doc = "Reserved"]
375 #[inline]
376 pub unsafe fn set_reserved(val: u8) {
377 let mut bits = unsafe { _read() };
378 bits &= !(63usize << 4usize);
379 bits |= (val as usize & 63usize) << 4usize;
380 unsafe {
381 _write(bits);
382 }
383 }
384 #[doc = "Base Physical Address (DBPA)"]
385 #[inline]
386 pub unsafe fn set_dbpa(val: u32) {
387 let mut bits = unsafe { _read() };
388 bits &= !(4194303usize << 10usize);
389 bits |= (val as usize & 4194303usize) << 10usize;
390 unsafe {
391 _write(bits);
392 }
393 }
394}
395#[doc = "ECC code."]
396pub mod mecc_code {
397 #[doc = "ECC Code Register"]
398 #[repr(transparent)]
399 #[derive(Copy, Clone, Eq, PartialEq)]
400 pub struct MeccCode(pub u32);
401 impl MeccCode {
402 #[doc = "ECC Code"]
403 #[must_use]
404 #[inline(always)]
405 pub const fn code(&self) -> u8 {
406 let val = (self.0 >> 0usize) & 0x7f;
407 val as u8
408 }
409 #[doc = "ECC Code"]
410 #[inline(always)]
411 pub const fn set_code(&mut self, val: u8) {
412 self.0 = (self.0 & !(0x7f << 0usize)) | (((val as u32) & 0x7f) << 0usize);
413 }
414 #[doc = "Correctable Error Flag"]
415 #[must_use]
416 #[inline(always)]
417 pub const fn c(&self) -> bool {
418 let val = (self.0 >> 16usize) & 0x01;
419 val != 0
420 }
421 #[doc = "Correctable Error Flag"]
422 #[inline(always)]
423 pub const fn set_c(&mut self, val: bool) {
424 self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
425 }
426 #[doc = "Parity Error Flag"]
427 #[must_use]
428 #[inline(always)]
429 pub const fn p(&self) -> bool {
430 let val = (self.0 >> 17usize) & 0x01;
431 val != 0
432 }
433 #[doc = "Parity Error Flag"]
434 #[inline(always)]
435 pub const fn set_p(&mut self, val: bool) {
436 self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
437 }
438 #[doc = "RAM Identifier"]
439 #[must_use]
440 #[inline(always)]
441 pub const fn ramid(&self) -> u8 {
442 let val = (self.0 >> 18usize) & 0x0f;
443 val as u8
444 }
445 #[doc = "RAM Identifier"]
446 #[inline(always)]
447 pub const fn set_ramid(&mut self, val: u8) {
448 self.0 = (self.0 & !(0x0f << 18usize)) | (((val as u32) & 0x0f) << 18usize);
449 }
450 #[doc = "Instruction Error Flag"]
451 #[must_use]
452 #[inline(always)]
453 pub const fn insn(&self) -> bool {
454 let val = (self.0 >> 22usize) & 0x01;
455 val != 0
456 }
457 #[doc = "Instruction Error Flag"]
458 #[inline(always)]
459 pub const fn set_insn(&mut self, val: bool) {
460 self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
461 }
462 #[doc = "Syndrome"]
463 #[must_use]
464 #[inline(always)]
465 pub const fn syndr(&self) -> bool {
466 let val = (self.0 >> 23usize) & 0x01;
467 val != 0
468 }
469 #[doc = "Syndrome"]
470 #[inline(always)]
471 pub const fn set_syndr(&mut self, val: bool) {
472 self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
473 }
474 }
475 impl Default for MeccCode {
476 #[inline(always)]
477 fn default() -> MeccCode {
478 MeccCode(0)
479 }
480 }
481 impl core::fmt::Debug for MeccCode {
482 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
483 f.debug_struct("MeccCode")
484 .field("code", &self.code())
485 .field("c", &self.c())
486 .field("p", &self.p())
487 .field("ramid", &self.ramid())
488 .field("insn", &self.insn())
489 .field("syndr", &self.syndr())
490 .finish()
491 }
492 }
493 #[cfg(feature = "defmt")]
494 impl defmt::Format for MeccCode {
495 fn format(&self, f: defmt::Formatter) {
496 defmt::write!(
497 f,
498 "MeccCode {{ code: {=u8:?}, c: {=bool:?}, p: {=bool:?}, ramid: {=u8:?}, insn: {=bool:?}, syndr: {=bool:?} }}",
499 self.code(),
500 self.c(),
501 self.p(),
502 self.ramid(),
503 self.insn(),
504 self.syndr()
505 )
506 }
507 }
508 #[inline(always)]
509 unsafe fn _read() -> usize {
510 let r: usize;
511 unsafe {
512 core :: arch :: asm ! ("csrrs {0}, 0x7c2, x0" , out (reg) r);
513 }
514 r
515 }
516 #[inline(always)]
517 unsafe fn _write(bits: usize) {
518 unsafe {
519 core :: arch :: asm ! ("csrrw x0, 0x7c2, {0}" , in (reg) bits);
520 }
521 }
522 #[inline(always)]
523 unsafe fn _set(bits: usize) {
524 unsafe {
525 core :: arch :: asm ! ("csrrs x0, 0x7c2, {0}" , in (reg) bits);
526 }
527 }
528 #[inline(always)]
529 unsafe fn _clear(bits: usize) {
530 unsafe {
531 core :: arch :: asm ! ("csrrc x0, 0x7c2, {0}" , in (reg) bits);
532 }
533 }
534 #[doc = r" Read the CSR value."]
535 #[inline]
536 pub fn read() -> MeccCode {
537 unsafe { MeccCode(_read() as u32) }
538 }
539 #[doc = r" Write the CSR value."]
540 #[inline]
541 pub unsafe fn write(val: MeccCode) {
542 unsafe {
543 _write(val.0 as usize);
544 }
545 }
546 #[doc = r" Read-modify-write the CSR."]
547 #[inline]
548 pub unsafe fn modify<R>(f: impl FnOnce(&mut MeccCode) -> R) -> R {
549 let mut val = read();
550 let res = f(&mut val);
551 unsafe {
552 write(val);
553 }
554 res
555 }
556 #[doc = "ECC Code"]
557 #[inline]
558 pub unsafe fn set_code(val: u8) {
559 let mut bits = unsafe { _read() };
560 bits &= !(127usize << 0usize);
561 bits |= (val as usize & 127usize) << 0usize;
562 unsafe {
563 _write(bits);
564 }
565 }
566 #[doc = "Correctable Error Flag"]
567 #[inline]
568 pub unsafe fn set_c() {
569 unsafe {
570 _set(65536usize);
571 }
572 }
573 #[doc = "Correctable Error Flag"]
574 #[inline]
575 pub unsafe fn clear_c() {
576 unsafe {
577 _clear(65536usize);
578 }
579 }
580 #[doc = "Parity Error Flag"]
581 #[inline]
582 pub unsafe fn set_p() {
583 unsafe {
584 _set(131072usize);
585 }
586 }
587 #[doc = "Parity Error Flag"]
588 #[inline]
589 pub unsafe fn clear_p() {
590 unsafe {
591 _clear(131072usize);
592 }
593 }
594 #[doc = "RAM Identifier"]
595 #[inline]
596 pub unsafe fn set_ramid(val: u8) {
597 let mut bits = unsafe { _read() };
598 bits &= !(15usize << 18usize);
599 bits |= (val as usize & 15usize) << 18usize;
600 unsafe {
601 _write(bits);
602 }
603 }
604 #[doc = "Instruction Error Flag"]
605 #[inline]
606 pub unsafe fn set_insn() {
607 unsafe {
608 _set(4194304usize);
609 }
610 }
611 #[doc = "Instruction Error Flag"]
612 #[inline]
613 pub unsafe fn clear_insn() {
614 unsafe {
615 _clear(4194304usize);
616 }
617 }
618 #[doc = "Syndrome"]
619 #[inline]
620 pub unsafe fn set_syndr() {
621 unsafe {
622 _set(8388608usize);
623 }
624 }
625 #[doc = "Syndrome"]
626 #[inline]
627 pub unsafe fn clear_syndr() {
628 unsafe {
629 _clear(8388608usize);
630 }
631 }
632}
633#[doc = "NMI-handler base address."]
634pub mod mnvec {
635 #[inline(always)]
636 unsafe fn _read() -> usize {
637 let r: usize;
638 unsafe {
639 core :: arch :: asm ! ("csrrs {0}, 0x7c3, x0" , out (reg) r);
640 }
641 r
642 }
643 #[inline(always)]
644 unsafe fn _write(bits: usize) {
645 unsafe {
646 core :: arch :: asm ! ("csrrw x0, 0x7c3, {0}" , in (reg) bits);
647 }
648 }
649 #[inline(always)]
650 unsafe fn _set(bits: usize) {
651 unsafe {
652 core :: arch :: asm ! ("csrrs x0, 0x7c3, {0}" , in (reg) bits);
653 }
654 }
655 #[inline(always)]
656 unsafe fn _clear(bits: usize) {
657 unsafe {
658 core :: arch :: asm ! ("csrrc x0, 0x7c3, {0}" , in (reg) bits);
659 }
660 }
661 #[doc = r" Read the CSR value as raw usize."]
662 #[inline]
663 pub fn read() -> usize {
664 unsafe { _read() }
665 }
666 #[doc = r" Write the CSR value as raw usize."]
667 #[inline]
668 pub unsafe fn write(val: usize) {
669 unsafe {
670 _write(val);
671 }
672 }
673}
674#[doc = "Additional machine mode status"]
675pub mod mxstatus {
676 #[doc = "Machine Extended Status Register"]
677 #[repr(transparent)]
678 #[derive(Copy, Clone, Eq, PartialEq)]
679 pub struct Mxstatus(pub u32);
680 impl Mxstatus {
681 #[must_use]
682 #[inline(always)]
683 pub const fn pft_en(&self) -> bool {
684 let val = (self.0 >> 0usize) & 0x01;
685 val != 0
686 }
687 #[inline(always)]
688 pub const fn set_pft_en(&mut self, val: bool) {
689 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
690 }
691 #[must_use]
692 #[inline(always)]
693 pub const fn ppft_en(&self) -> bool {
694 let val = (self.0 >> 1usize) & 0x01;
695 val != 0
696 }
697 #[inline(always)]
698 pub const fn set_ppft_en(&mut self, val: bool) {
699 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
700 }
701 #[must_use]
702 #[inline(always)]
703 pub const fn ime(&self) -> bool {
704 let val = (self.0 >> 2usize) & 0x01;
705 val != 0
706 }
707 #[inline(always)]
708 pub const fn set_ime(&mut self, val: bool) {
709 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
710 }
711 #[must_use]
712 #[inline(always)]
713 pub const fn pime(&self) -> bool {
714 let val = (self.0 >> 3usize) & 0x01;
715 val != 0
716 }
717 #[inline(always)]
718 pub const fn set_pime(&mut self, val: bool) {
719 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
720 }
721 #[must_use]
722 #[inline(always)]
723 pub const fn dme(&self) -> bool {
724 let val = (self.0 >> 4usize) & 0x01;
725 val != 0
726 }
727 #[inline(always)]
728 pub const fn set_dme(&mut self, val: bool) {
729 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
730 }
731 #[must_use]
732 #[inline(always)]
733 pub const fn pdme(&self) -> bool {
734 let val = (self.0 >> 5usize) & 0x01;
735 val != 0
736 }
737 #[inline(always)]
738 pub const fn set_pdme(&mut self, val: bool) {
739 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
740 }
741 #[must_use]
742 #[inline(always)]
743 pub const fn typ(&self) -> u8 {
744 let val = (self.0 >> 6usize) & 0x03;
745 val as u8
746 }
747 #[inline(always)]
748 pub const fn set_typ(&mut self, val: u8) {
749 self.0 = (self.0 & !(0x03 << 6usize)) | (((val as u32) & 0x03) << 6usize);
750 }
751 #[must_use]
752 #[inline(always)]
753 pub const fn ptyp(&self) -> u8 {
754 let val = (self.0 >> 8usize) & 0x03;
755 val as u8
756 }
757 #[inline(always)]
758 pub const fn set_ptyp(&mut self, val: u8) {
759 self.0 = (self.0 & !(0x03 << 8usize)) | (((val as u32) & 0x03) << 8usize);
760 }
761 }
762 impl Default for Mxstatus {
763 #[inline(always)]
764 fn default() -> Mxstatus {
765 Mxstatus(0)
766 }
767 }
768 impl core::fmt::Debug for Mxstatus {
769 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
770 f.debug_struct("Mxstatus")
771 .field("pft_en", &self.pft_en())
772 .field("ppft_en", &self.ppft_en())
773 .field("ime", &self.ime())
774 .field("pime", &self.pime())
775 .field("dme", &self.dme())
776 .field("pdme", &self.pdme())
777 .field("typ", &self.typ())
778 .field("ptyp", &self.ptyp())
779 .finish()
780 }
781 }
782 #[cfg(feature = "defmt")]
783 impl defmt::Format for Mxstatus {
784 fn format(&self, f: defmt::Formatter) {
785 defmt::write!(
786 f,
787 "Mxstatus {{ pft_en: {=bool:?}, ppft_en: {=bool:?}, ime: {=bool:?}, pime: {=bool:?}, dme: {=bool:?}, pdme: {=bool:?}, typ: {=u8:?}, ptyp: {=u8:?} }}",
788 self.pft_en(),
789 self.ppft_en(),
790 self.ime(),
791 self.pime(),
792 self.dme(),
793 self.pdme(),
794 self.typ(),
795 self.ptyp()
796 )
797 }
798 }
799 #[inline(always)]
800 unsafe fn _read() -> usize {
801 let r: usize;
802 unsafe {
803 core :: arch :: asm ! ("csrrs {0}, 0x7c4, x0" , out (reg) r);
804 }
805 r
806 }
807 #[inline(always)]
808 unsafe fn _write(bits: usize) {
809 unsafe {
810 core :: arch :: asm ! ("csrrw x0, 0x7c4, {0}" , in (reg) bits);
811 }
812 }
813 #[inline(always)]
814 unsafe fn _set(bits: usize) {
815 unsafe {
816 core :: arch :: asm ! ("csrrs x0, 0x7c4, {0}" , in (reg) bits);
817 }
818 }
819 #[inline(always)]
820 unsafe fn _clear(bits: usize) {
821 unsafe {
822 core :: arch :: asm ! ("csrrc x0, 0x7c4, {0}" , in (reg) bits);
823 }
824 }
825 #[doc = r" Read the CSR value."]
826 #[inline]
827 pub fn read() -> Mxstatus {
828 unsafe { Mxstatus(_read() as u32) }
829 }
830 #[doc = r" Write the CSR value."]
831 #[inline]
832 pub unsafe fn write(val: Mxstatus) {
833 unsafe {
834 _write(val.0 as usize);
835 }
836 }
837 #[doc = r" Read-modify-write the CSR."]
838 #[inline]
839 pub unsafe fn modify<R>(f: impl FnOnce(&mut Mxstatus) -> R) -> R {
840 let mut val = read();
841 let res = f(&mut val);
842 unsafe {
843 write(val);
844 }
845 res
846 }
847 #[inline]
848 pub unsafe fn set_pft_en() {
849 unsafe {
850 _set(1usize);
851 }
852 }
853 #[inline]
854 pub unsafe fn clear_pft_en() {
855 unsafe {
856 _clear(1usize);
857 }
858 }
859 #[inline]
860 pub unsafe fn set_ppft_en() {
861 unsafe {
862 _set(2usize);
863 }
864 }
865 #[inline]
866 pub unsafe fn clear_ppft_en() {
867 unsafe {
868 _clear(2usize);
869 }
870 }
871 #[inline]
872 pub unsafe fn set_ime() {
873 unsafe {
874 _set(4usize);
875 }
876 }
877 #[inline]
878 pub unsafe fn clear_ime() {
879 unsafe {
880 _clear(4usize);
881 }
882 }
883 #[inline]
884 pub unsafe fn set_pime() {
885 unsafe {
886 _set(8usize);
887 }
888 }
889 #[inline]
890 pub unsafe fn clear_pime() {
891 unsafe {
892 _clear(8usize);
893 }
894 }
895 #[inline]
896 pub unsafe fn set_dme() {
897 unsafe {
898 _set(16usize);
899 }
900 }
901 #[inline]
902 pub unsafe fn clear_dme() {
903 unsafe {
904 _clear(16usize);
905 }
906 }
907 #[inline]
908 pub unsafe fn set_pdme() {
909 unsafe {
910 _set(32usize);
911 }
912 }
913 #[inline]
914 pub unsafe fn clear_pdme() {
915 unsafe {
916 _clear(32usize);
917 }
918 }
919 #[inline]
920 pub unsafe fn set_typ(val: u8) {
921 let mut bits = unsafe { _read() };
922 bits &= !(3usize << 6usize);
923 bits |= (val as usize & 3usize) << 6usize;
924 unsafe {
925 _write(bits);
926 }
927 }
928 #[inline]
929 pub unsafe fn set_ptyp(val: u8) {
930 let mut bits = unsafe { _read() };
931 bits &= !(3usize << 8usize);
932 bits |= (val as usize & 3usize) << 8usize;
933 unsafe {
934 _write(bits);
935 }
936 }
937}
938#[doc = "Performance throttling control"]
939pub mod mpft_ctl {
940 #[doc = "Performance Throttling Control Register"]
941 #[repr(transparent)]
942 #[derive(Copy, Clone, Eq, PartialEq)]
943 pub struct MpftCtl(pub u32);
944 impl MpftCtl {
945 #[doc = "Throttling Level"]
946 #[must_use]
947 #[inline(always)]
948 pub const fn t_level(&self) -> u8 {
949 let val = (self.0 >> 4usize) & 0x0f;
950 val as u8
951 }
952 #[doc = "Throttling Level"]
953 #[inline(always)]
954 pub const fn set_t_level(&mut self, val: u8) {
955 self.0 = (self.0 & !(0x0f << 4usize)) | (((val as u32) & 0x0f) << 4usize);
956 }
957 #[doc = "Fast Interrupt"]
958 #[must_use]
959 #[inline(always)]
960 pub const fn fast_int(&self) -> bool {
961 let val = (self.0 >> 8usize) & 0x01;
962 val != 0
963 }
964 #[doc = "Fast Interrupt"]
965 #[inline(always)]
966 pub const fn set_fast_int(&mut self, val: bool) {
967 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
968 }
969 }
970 impl Default for MpftCtl {
971 #[inline(always)]
972 fn default() -> MpftCtl {
973 MpftCtl(0)
974 }
975 }
976 impl core::fmt::Debug for MpftCtl {
977 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
978 f.debug_struct("MpftCtl")
979 .field("t_level", &self.t_level())
980 .field("fast_int", &self.fast_int())
981 .finish()
982 }
983 }
984 #[cfg(feature = "defmt")]
985 impl defmt::Format for MpftCtl {
986 fn format(&self, f: defmt::Formatter) {
987 defmt::write!(
988 f,
989 "MpftCtl {{ t_level: {=u8:?}, fast_int: {=bool:?} }}",
990 self.t_level(),
991 self.fast_int()
992 )
993 }
994 }
995 #[inline(always)]
996 unsafe fn _read() -> usize {
997 let r: usize;
998 unsafe {
999 core :: arch :: asm ! ("csrrs {0}, 0x7c5, x0" , out (reg) r);
1000 }
1001 r
1002 }
1003 #[inline(always)]
1004 unsafe fn _write(bits: usize) {
1005 unsafe {
1006 core :: arch :: asm ! ("csrrw x0, 0x7c5, {0}" , in (reg) bits);
1007 }
1008 }
1009 #[inline(always)]
1010 unsafe fn _set(bits: usize) {
1011 unsafe {
1012 core :: arch :: asm ! ("csrrs x0, 0x7c5, {0}" , in (reg) bits);
1013 }
1014 }
1015 #[inline(always)]
1016 unsafe fn _clear(bits: usize) {
1017 unsafe {
1018 core :: arch :: asm ! ("csrrc x0, 0x7c5, {0}" , in (reg) bits);
1019 }
1020 }
1021 #[doc = r" Read the CSR value."]
1022 #[inline]
1023 pub fn read() -> MpftCtl {
1024 unsafe { MpftCtl(_read() as u32) }
1025 }
1026 #[doc = r" Write the CSR value."]
1027 #[inline]
1028 pub unsafe fn write(val: MpftCtl) {
1029 unsafe {
1030 _write(val.0 as usize);
1031 }
1032 }
1033 #[doc = r" Read-modify-write the CSR."]
1034 #[inline]
1035 pub unsafe fn modify<R>(f: impl FnOnce(&mut MpftCtl) -> R) -> R {
1036 let mut val = read();
1037 let res = f(&mut val);
1038 unsafe {
1039 write(val);
1040 }
1041 res
1042 }
1043 #[doc = "Throttling Level"]
1044 #[inline]
1045 pub unsafe fn set_t_level(val: u8) {
1046 let mut bits = unsafe { _read() };
1047 bits &= !(15usize << 4usize);
1048 bits |= (val as usize & 15usize) << 4usize;
1049 unsafe {
1050 _write(bits);
1051 }
1052 }
1053 #[doc = "Fast Interrupt"]
1054 #[inline]
1055 pub unsafe fn set_fast_int() {
1056 unsafe {
1057 _set(256usize);
1058 }
1059 }
1060 #[doc = "Fast Interrupt"]
1061 #[inline]
1062 pub unsafe fn clear_fast_int() {
1063 unsafe {
1064 _clear(256usize);
1065 }
1066 }
1067}
1068#[doc = "Hardware stack protection control"]
1069pub mod mhsp_ctl {
1070 #[doc = "Machine Hardware Stack Protection Control Register"]
1071 #[repr(transparent)]
1072 #[derive(Copy, Clone, Eq, PartialEq)]
1073 pub struct MhspCtl(pub u32);
1074 impl MhspCtl {
1075 #[must_use]
1076 #[inline(always)]
1077 pub const fn ovf_en(&self) -> bool {
1078 let val = (self.0 >> 0usize) & 0x01;
1079 val != 0
1080 }
1081 #[inline(always)]
1082 pub const fn set_ovf_en(&mut self, val: bool) {
1083 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
1084 }
1085 #[must_use]
1086 #[inline(always)]
1087 pub const fn udf_en(&self) -> bool {
1088 let val = (self.0 >> 1usize) & 0x01;
1089 val != 0
1090 }
1091 #[inline(always)]
1092 pub const fn set_udf_en(&mut self, val: bool) {
1093 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
1094 }
1095 #[must_use]
1096 #[inline(always)]
1097 pub const fn schm(&self) -> bool {
1098 let val = (self.0 >> 2usize) & 0x01;
1099 val != 0
1100 }
1101 #[inline(always)]
1102 pub const fn set_schm(&mut self, val: bool) {
1103 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
1104 }
1105 #[must_use]
1106 #[inline(always)]
1107 pub const fn u(&self) -> bool {
1108 let val = (self.0 >> 3usize) & 0x01;
1109 val != 0
1110 }
1111 #[inline(always)]
1112 pub const fn set_u(&mut self, val: bool) {
1113 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
1114 }
1115 #[must_use]
1116 #[inline(always)]
1117 pub const fn s(&self) -> bool {
1118 let val = (self.0 >> 4usize) & 0x01;
1119 val != 0
1120 }
1121 #[inline(always)]
1122 pub const fn set_s(&mut self, val: bool) {
1123 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
1124 }
1125 #[must_use]
1126 #[inline(always)]
1127 pub const fn m(&self) -> bool {
1128 let val = (self.0 >> 5usize) & 0x01;
1129 val != 0
1130 }
1131 #[inline(always)]
1132 pub const fn set_m(&mut self, val: bool) {
1133 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
1134 }
1135 }
1136 impl Default for MhspCtl {
1137 #[inline(always)]
1138 fn default() -> MhspCtl {
1139 MhspCtl(0)
1140 }
1141 }
1142 impl core::fmt::Debug for MhspCtl {
1143 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1144 f.debug_struct("MhspCtl")
1145 .field("ovf_en", &self.ovf_en())
1146 .field("udf_en", &self.udf_en())
1147 .field("schm", &self.schm())
1148 .field("u", &self.u())
1149 .field("s", &self.s())
1150 .field("m", &self.m())
1151 .finish()
1152 }
1153 }
1154 #[cfg(feature = "defmt")]
1155 impl defmt::Format for MhspCtl {
1156 fn format(&self, f: defmt::Formatter) {
1157 defmt::write!(
1158 f,
1159 "MhspCtl {{ ovf_en: {=bool:?}, udf_en: {=bool:?}, schm: {=bool:?}, u: {=bool:?}, s: {=bool:?}, m: {=bool:?} }}",
1160 self.ovf_en(),
1161 self.udf_en(),
1162 self.schm(),
1163 self.u(),
1164 self.s(),
1165 self.m()
1166 )
1167 }
1168 }
1169 #[inline(always)]
1170 unsafe fn _read() -> usize {
1171 let r: usize;
1172 unsafe {
1173 core :: arch :: asm ! ("csrrs {0}, 0x7c6, x0" , out (reg) r);
1174 }
1175 r
1176 }
1177 #[inline(always)]
1178 unsafe fn _write(bits: usize) {
1179 unsafe {
1180 core :: arch :: asm ! ("csrrw x0, 0x7c6, {0}" , in (reg) bits);
1181 }
1182 }
1183 #[inline(always)]
1184 unsafe fn _set(bits: usize) {
1185 unsafe {
1186 core :: arch :: asm ! ("csrrs x0, 0x7c6, {0}" , in (reg) bits);
1187 }
1188 }
1189 #[inline(always)]
1190 unsafe fn _clear(bits: usize) {
1191 unsafe {
1192 core :: arch :: asm ! ("csrrc x0, 0x7c6, {0}" , in (reg) bits);
1193 }
1194 }
1195 #[doc = r" Read the CSR value."]
1196 #[inline]
1197 pub fn read() -> MhspCtl {
1198 unsafe { MhspCtl(_read() as u32) }
1199 }
1200 #[doc = r" Write the CSR value."]
1201 #[inline]
1202 pub unsafe fn write(val: MhspCtl) {
1203 unsafe {
1204 _write(val.0 as usize);
1205 }
1206 }
1207 #[doc = r" Read-modify-write the CSR."]
1208 #[inline]
1209 pub unsafe fn modify<R>(f: impl FnOnce(&mut MhspCtl) -> R) -> R {
1210 let mut val = read();
1211 let res = f(&mut val);
1212 unsafe {
1213 write(val);
1214 }
1215 res
1216 }
1217 #[inline]
1218 pub unsafe fn set_ovf_en() {
1219 unsafe {
1220 _set(1usize);
1221 }
1222 }
1223 #[inline]
1224 pub unsafe fn clear_ovf_en() {
1225 unsafe {
1226 _clear(1usize);
1227 }
1228 }
1229 #[inline]
1230 pub unsafe fn set_udf_en() {
1231 unsafe {
1232 _set(2usize);
1233 }
1234 }
1235 #[inline]
1236 pub unsafe fn clear_udf_en() {
1237 unsafe {
1238 _clear(2usize);
1239 }
1240 }
1241 #[inline]
1242 pub unsafe fn set_schm() {
1243 unsafe {
1244 _set(4usize);
1245 }
1246 }
1247 #[inline]
1248 pub unsafe fn clear_schm() {
1249 unsafe {
1250 _clear(4usize);
1251 }
1252 }
1253 #[inline]
1254 pub unsafe fn set_u() {
1255 unsafe {
1256 _set(8usize);
1257 }
1258 }
1259 #[inline]
1260 pub unsafe fn clear_u() {
1261 unsafe {
1262 _clear(8usize);
1263 }
1264 }
1265 #[inline]
1266 pub unsafe fn set_s() {
1267 unsafe {
1268 _set(16usize);
1269 }
1270 }
1271 #[inline]
1272 pub unsafe fn clear_s() {
1273 unsafe {
1274 _clear(16usize);
1275 }
1276 }
1277 #[inline]
1278 pub unsafe fn set_m() {
1279 unsafe {
1280 _set(32usize);
1281 }
1282 }
1283 #[inline]
1284 pub unsafe fn clear_m() {
1285 unsafe {
1286 _clear(32usize);
1287 }
1288 }
1289}
1290#[doc = "SP bound register"]
1291pub mod msp_bound {
1292 #[inline(always)]
1293 unsafe fn _read() -> usize {
1294 let r: usize;
1295 unsafe {
1296 core :: arch :: asm ! ("csrrs {0}, 0x7c7, x0" , out (reg) r);
1297 }
1298 r
1299 }
1300 #[inline(always)]
1301 unsafe fn _write(bits: usize) {
1302 unsafe {
1303 core :: arch :: asm ! ("csrrw x0, 0x7c7, {0}" , in (reg) bits);
1304 }
1305 }
1306 #[inline(always)]
1307 unsafe fn _set(bits: usize) {
1308 unsafe {
1309 core :: arch :: asm ! ("csrrs x0, 0x7c7, {0}" , in (reg) bits);
1310 }
1311 }
1312 #[inline(always)]
1313 unsafe fn _clear(bits: usize) {
1314 unsafe {
1315 core :: arch :: asm ! ("csrrc x0, 0x7c7, {0}" , in (reg) bits);
1316 }
1317 }
1318 #[doc = r" Read the CSR value as raw usize."]
1319 #[inline]
1320 pub fn read() -> usize {
1321 unsafe { _read() }
1322 }
1323 #[doc = r" Write the CSR value as raw usize."]
1324 #[inline]
1325 pub unsafe fn write(val: usize) {
1326 unsafe {
1327 _write(val);
1328 }
1329 }
1330}
1331#[doc = "SP base register"]
1332pub mod msp_base {
1333 #[inline(always)]
1334 unsafe fn _read() -> usize {
1335 let r: usize;
1336 unsafe {
1337 core :: arch :: asm ! ("csrrs {0}, 0x7c8, x0" , out (reg) r);
1338 }
1339 r
1340 }
1341 #[inline(always)]
1342 unsafe fn _write(bits: usize) {
1343 unsafe {
1344 core :: arch :: asm ! ("csrrw x0, 0x7c8, {0}" , in (reg) bits);
1345 }
1346 }
1347 #[inline(always)]
1348 unsafe fn _set(bits: usize) {
1349 unsafe {
1350 core :: arch :: asm ! ("csrrs x0, 0x7c8, {0}" , in (reg) bits);
1351 }
1352 }
1353 #[inline(always)]
1354 unsafe fn _clear(bits: usize) {
1355 unsafe {
1356 core :: arch :: asm ! ("csrrc x0, 0x7c8, {0}" , in (reg) bits);
1357 }
1358 }
1359 #[doc = r" Read the CSR value as raw usize."]
1360 #[inline]
1361 pub fn read() -> usize {
1362 unsafe { _read() }
1363 }
1364 #[doc = r" Write the CSR value as raw usize."]
1365 #[inline]
1366 pub unsafe fn write(val: usize) {
1367 unsafe {
1368 _write(val);
1369 }
1370 }
1371}
1372#[doc = "Detailed exception cause"]
1373pub mod mdcause {
1374 #[doc = "Machine Detailed Trap Cause Register (for imprecise exception/interrupt)"]
1375 #[repr(transparent)]
1376 #[derive(Copy, Clone, Eq, PartialEq)]
1377 pub struct Mdcause(pub u32);
1378 impl Mdcause {
1379 #[must_use]
1380 #[inline(always)]
1381 pub const fn mdcause(&self) -> u8 {
1382 let val = (self.0 >> 0usize) & 0x1f;
1383 val as u8
1384 }
1385 #[inline(always)]
1386 pub const fn set_mdcause(&mut self, val: u8) {
1387 self.0 = (self.0 & !(0x1f << 0usize)) | (((val as u32) & 0x1f) << 0usize);
1388 }
1389 #[must_use]
1390 #[inline(always)]
1391 pub const fn pm(&self) -> u8 {
1392 let val = (self.0 >> 5usize) & 0x03;
1393 val as u8
1394 }
1395 #[inline(always)]
1396 pub const fn set_pm(&mut self, val: u8) {
1397 self.0 = (self.0 & !(0x03 << 5usize)) | (((val as u32) & 0x03) << 5usize);
1398 }
1399 }
1400 impl Default for Mdcause {
1401 #[inline(always)]
1402 fn default() -> Mdcause {
1403 Mdcause(0)
1404 }
1405 }
1406 impl core::fmt::Debug for Mdcause {
1407 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1408 f.debug_struct("Mdcause")
1409 .field("mdcause", &self.mdcause())
1410 .field("pm", &self.pm())
1411 .finish()
1412 }
1413 }
1414 #[cfg(feature = "defmt")]
1415 impl defmt::Format for Mdcause {
1416 fn format(&self, f: defmt::Formatter) {
1417 defmt::write!(
1418 f,
1419 "Mdcause {{ mdcause: {=u8:?}, pm: {=u8:?} }}",
1420 self.mdcause(),
1421 self.pm()
1422 )
1423 }
1424 }
1425 #[inline(always)]
1426 unsafe fn _read() -> usize {
1427 let r: usize;
1428 unsafe {
1429 core :: arch :: asm ! ("csrrs {0}, 0x7c9, x0" , out (reg) r);
1430 }
1431 r
1432 }
1433 #[inline(always)]
1434 unsafe fn _write(bits: usize) {
1435 unsafe {
1436 core :: arch :: asm ! ("csrrw x0, 0x7c9, {0}" , in (reg) bits);
1437 }
1438 }
1439 #[inline(always)]
1440 unsafe fn _set(bits: usize) {
1441 unsafe {
1442 core :: arch :: asm ! ("csrrs x0, 0x7c9, {0}" , in (reg) bits);
1443 }
1444 }
1445 #[inline(always)]
1446 unsafe fn _clear(bits: usize) {
1447 unsafe {
1448 core :: arch :: asm ! ("csrrc x0, 0x7c9, {0}" , in (reg) bits);
1449 }
1450 }
1451 #[doc = r" Read the CSR value."]
1452 #[inline]
1453 pub fn read() -> Mdcause {
1454 unsafe { Mdcause(_read() as u32) }
1455 }
1456 #[doc = r" Write the CSR value."]
1457 #[inline]
1458 pub unsafe fn write(val: Mdcause) {
1459 unsafe {
1460 _write(val.0 as usize);
1461 }
1462 }
1463 #[doc = r" Read-modify-write the CSR."]
1464 #[inline]
1465 pub unsafe fn modify<R>(f: impl FnOnce(&mut Mdcause) -> R) -> R {
1466 let mut val = read();
1467 let res = f(&mut val);
1468 unsafe {
1469 write(val);
1470 }
1471 res
1472 }
1473 #[inline]
1474 pub unsafe fn set_mdcause(val: u8) {
1475 let mut bits = unsafe { _read() };
1476 bits &= !(31usize << 0usize);
1477 bits |= (val as usize & 31usize) << 0usize;
1478 unsafe {
1479 _write(bits);
1480 }
1481 }
1482 #[inline]
1483 pub unsafe fn set_pm(val: u8) {
1484 let mut bits = unsafe { _read() };
1485 bits &= !(3usize << 5usize);
1486 bits |= (val as usize & 3usize) << 5usize;
1487 unsafe {
1488 _write(bits);
1489 }
1490 }
1491}
1492#[doc = "Cache control"]
1493pub mod mcache_ctl {
1494 #[doc = "Cache Control Register"]
1495 #[repr(transparent)]
1496 #[derive(Copy, Clone, Eq, PartialEq)]
1497 pub struct McacheCtl(pub u32);
1498 impl McacheCtl {
1499 #[doc = "Instruction Cache Enable"]
1500 #[must_use]
1501 #[inline(always)]
1502 pub const fn ic_en(&self) -> bool {
1503 let val = (self.0 >> 0usize) & 0x01;
1504 val != 0
1505 }
1506 #[doc = "Instruction Cache Enable"]
1507 #[inline(always)]
1508 pub const fn set_ic_en(&mut self, val: bool) {
1509 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
1510 }
1511 #[doc = "Data Cache Enable"]
1512 #[must_use]
1513 #[inline(always)]
1514 pub const fn dc_en(&self) -> bool {
1515 let val = (self.0 >> 1usize) & 0x01;
1516 val != 0
1517 }
1518 #[doc = "Data Cache Enable"]
1519 #[inline(always)]
1520 pub const fn set_dc_en(&mut self, val: bool) {
1521 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
1522 }
1523 #[doc = "Instruction Cache ECC Enable"]
1524 #[must_use]
1525 #[inline(always)]
1526 pub const fn ic_eccen(&self) -> u8 {
1527 let val = (self.0 >> 2usize) & 0x03;
1528 val as u8
1529 }
1530 #[doc = "Instruction Cache ECC Enable"]
1531 #[inline(always)]
1532 pub const fn set_ic_eccen(&mut self, val: u8) {
1533 self.0 = (self.0 & !(0x03 << 2usize)) | (((val as u32) & 0x03) << 2usize);
1534 }
1535 #[doc = "Data Cache ECC Enable"]
1536 #[must_use]
1537 #[inline(always)]
1538 pub const fn dc_eccen(&self) -> u8 {
1539 let val = (self.0 >> 4usize) & 0x03;
1540 val as u8
1541 }
1542 #[doc = "Data Cache ECC Enable"]
1543 #[inline(always)]
1544 pub const fn set_dc_eccen(&mut self, val: u8) {
1545 self.0 = (self.0 & !(0x03 << 4usize)) | (((val as u32) & 0x03) << 4usize);
1546 }
1547 #[doc = "Instruction Cache Read/Write ECC"]
1548 #[must_use]
1549 #[inline(always)]
1550 pub const fn ic_rwecc(&self) -> bool {
1551 let val = (self.0 >> 6usize) & 0x01;
1552 val != 0
1553 }
1554 #[doc = "Instruction Cache Read/Write ECC"]
1555 #[inline(always)]
1556 pub const fn set_ic_rwecc(&mut self, val: bool) {
1557 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
1558 }
1559 #[doc = "Data Cache Read/Write ECC"]
1560 #[must_use]
1561 #[inline(always)]
1562 pub const fn dc_rwecc(&self) -> bool {
1563 let val = (self.0 >> 7usize) & 0x01;
1564 val != 0
1565 }
1566 #[doc = "Data Cache Read/Write ECC"]
1567 #[inline(always)]
1568 pub const fn set_dc_rwecc(&mut self, val: bool) {
1569 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
1570 }
1571 #[doc = "Cache Control SU Enable"]
1572 #[must_use]
1573 #[inline(always)]
1574 pub const fn cctl_suen(&self) -> bool {
1575 let val = (self.0 >> 8usize) & 0x01;
1576 val != 0
1577 }
1578 #[doc = "Cache Control SU Enable"]
1579 #[inline(always)]
1580 pub const fn set_cctl_suen(&mut self, val: bool) {
1581 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
1582 }
1583 #[doc = "Instruction Prefetch Enable"]
1584 #[must_use]
1585 #[inline(always)]
1586 pub const fn ipref_en(&self) -> bool {
1587 let val = (self.0 >> 9usize) & 0x01;
1588 val != 0
1589 }
1590 #[doc = "Instruction Prefetch Enable"]
1591 #[inline(always)]
1592 pub const fn set_ipref_en(&mut self, val: bool) {
1593 self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
1594 }
1595 #[doc = "Data Prefetch Enable"]
1596 #[must_use]
1597 #[inline(always)]
1598 pub const fn dpref_en(&self) -> bool {
1599 let val = (self.0 >> 10usize) & 0x01;
1600 val != 0
1601 }
1602 #[doc = "Data Prefetch Enable"]
1603 #[inline(always)]
1604 pub const fn set_dpref_en(&mut self, val: bool) {
1605 self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
1606 }
1607 #[doc = "Instruction Cache 1st Way Disable"]
1608 #[must_use]
1609 #[inline(always)]
1610 pub const fn ic_1st_wd(&self) -> bool {
1611 let val = (self.0 >> 11usize) & 0x01;
1612 val != 0
1613 }
1614 #[doc = "Instruction Cache 1st Way Disable"]
1615 #[inline(always)]
1616 pub const fn set_ic_1st_wd(&mut self, val: bool) {
1617 self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
1618 }
1619 #[doc = "Data Cache 1st Way Disable"]
1620 #[must_use]
1621 #[inline(always)]
1622 pub const fn dc_1st_wd(&self) -> bool {
1623 let val = (self.0 >> 12usize) & 0x01;
1624 val != 0
1625 }
1626 #[doc = "Data Cache 1st Way Disable"]
1627 #[inline(always)]
1628 pub const fn set_dc_1st_wd(&mut self, val: bool) {
1629 self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
1630 }
1631 #[doc = "Data Cache Write-Around"]
1632 #[must_use]
1633 #[inline(always)]
1634 pub const fn dc_warnd(&self) -> u8 {
1635 let val = (self.0 >> 13usize) & 0x03;
1636 val as u8
1637 }
1638 #[doc = "Data Cache Write-Around"]
1639 #[inline(always)]
1640 pub const fn set_dc_warnd(&mut self, val: u8) {
1641 self.0 = (self.0 & !(0x03 << 13usize)) | (((val as u32) & 0x03) << 13usize);
1642 }
1643 #[doc = "L2 Cache Write-Around"]
1644 #[must_use]
1645 #[inline(always)]
1646 pub const fn l2c_warnd(&self) -> u8 {
1647 let val = (self.0 >> 15usize) & 0x03;
1648 val as u8
1649 }
1650 #[doc = "L2 Cache Write-Around"]
1651 #[inline(always)]
1652 pub const fn set_l2c_warnd(&mut self, val: u8) {
1653 self.0 = (self.0 & !(0x03 << 15usize)) | (((val as u32) & 0x03) << 15usize);
1654 }
1655 #[doc = "TLB ECC Enable"]
1656 #[must_use]
1657 #[inline(always)]
1658 pub const fn tlb_eccen(&self) -> u8 {
1659 let val = (self.0 >> 17usize) & 0x03;
1660 val as u8
1661 }
1662 #[doc = "TLB ECC Enable"]
1663 #[inline(always)]
1664 pub const fn set_tlb_eccen(&mut self, val: u8) {
1665 self.0 = (self.0 & !(0x03 << 17usize)) | (((val as u32) & 0x03) << 17usize);
1666 }
1667 #[doc = "Data Cache Coherence Enable"]
1668 #[must_use]
1669 #[inline(always)]
1670 pub const fn dc_cohen(&self) -> bool {
1671 let val = (self.0 >> 19usize) & 0x01;
1672 val != 0
1673 }
1674 #[doc = "Data Cache Coherence Enable"]
1675 #[inline(always)]
1676 pub const fn set_dc_cohen(&mut self, val: bool) {
1677 self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
1678 }
1679 #[doc = "Data Cache Coherence State"]
1680 #[must_use]
1681 #[inline(always)]
1682 pub const fn dc_cohsta(&self) -> bool {
1683 let val = (self.0 >> 20usize) & 0x01;
1684 val != 0
1685 }
1686 #[doc = "Data Cache Coherence State"]
1687 #[inline(always)]
1688 pub const fn set_dc_cohsta(&mut self, val: bool) {
1689 self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
1690 }
1691 #[doc = "Data Prefetch Mode"]
1692 #[must_use]
1693 #[inline(always)]
1694 pub const fn dpref_mode(&self) -> u8 {
1695 let val = (self.0 >> 21usize) & 0x03;
1696 val as u8
1697 }
1698 #[doc = "Data Prefetch Mode"]
1699 #[inline(always)]
1700 pub const fn set_dpref_mode(&mut self, val: u8) {
1701 self.0 = (self.0 & !(0x03 << 21usize)) | (((val as u32) & 0x03) << 21usize);
1702 }
1703 }
1704 impl Default for McacheCtl {
1705 #[inline(always)]
1706 fn default() -> McacheCtl {
1707 McacheCtl(0)
1708 }
1709 }
1710 impl core::fmt::Debug for McacheCtl {
1711 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1712 f.debug_struct("McacheCtl")
1713 .field("ic_en", &self.ic_en())
1714 .field("dc_en", &self.dc_en())
1715 .field("ic_eccen", &self.ic_eccen())
1716 .field("dc_eccen", &self.dc_eccen())
1717 .field("ic_rwecc", &self.ic_rwecc())
1718 .field("dc_rwecc", &self.dc_rwecc())
1719 .field("cctl_suen", &self.cctl_suen())
1720 .field("ipref_en", &self.ipref_en())
1721 .field("dpref_en", &self.dpref_en())
1722 .field("ic_1st_wd", &self.ic_1st_wd())
1723 .field("dc_1st_wd", &self.dc_1st_wd())
1724 .field("dc_warnd", &self.dc_warnd())
1725 .field("l2c_warnd", &self.l2c_warnd())
1726 .field("tlb_eccen", &self.tlb_eccen())
1727 .field("dc_cohen", &self.dc_cohen())
1728 .field("dc_cohsta", &self.dc_cohsta())
1729 .field("dpref_mode", &self.dpref_mode())
1730 .finish()
1731 }
1732 }
1733 #[cfg(feature = "defmt")]
1734 impl defmt::Format for McacheCtl {
1735 fn format(&self, f: defmt::Formatter) {
1736 defmt::write!(
1737 f,
1738 "McacheCtl {{ ic_en: {=bool:?}, dc_en: {=bool:?}, ic_eccen: {=u8:?}, dc_eccen: {=u8:?}, ic_rwecc: {=bool:?}, dc_rwecc: {=bool:?}, cctl_suen: {=bool:?}, ipref_en: {=bool:?}, dpref_en: {=bool:?}, ic_1st_wd: {=bool:?}, dc_1st_wd: {=bool:?}, dc_warnd: {=u8:?}, l2c_warnd: {=u8:?}, tlb_eccen: {=u8:?}, dc_cohen: {=bool:?}, dc_cohsta: {=bool:?}, dpref_mode: {=u8:?} }}",
1739 self.ic_en(),
1740 self.dc_en(),
1741 self.ic_eccen(),
1742 self.dc_eccen(),
1743 self.ic_rwecc(),
1744 self.dc_rwecc(),
1745 self.cctl_suen(),
1746 self.ipref_en(),
1747 self.dpref_en(),
1748 self.ic_1st_wd(),
1749 self.dc_1st_wd(),
1750 self.dc_warnd(),
1751 self.l2c_warnd(),
1752 self.tlb_eccen(),
1753 self.dc_cohen(),
1754 self.dc_cohsta(),
1755 self.dpref_mode()
1756 )
1757 }
1758 }
1759 #[inline(always)]
1760 unsafe fn _read() -> usize {
1761 let r: usize;
1762 unsafe {
1763 core :: arch :: asm ! ("csrrs {0}, 0x7ca, x0" , out (reg) r);
1764 }
1765 r
1766 }
1767 #[inline(always)]
1768 unsafe fn _write(bits: usize) {
1769 unsafe {
1770 core :: arch :: asm ! ("csrrw x0, 0x7ca, {0}" , in (reg) bits);
1771 }
1772 }
1773 #[inline(always)]
1774 unsafe fn _set(bits: usize) {
1775 unsafe {
1776 core :: arch :: asm ! ("csrrs x0, 0x7ca, {0}" , in (reg) bits);
1777 }
1778 }
1779 #[inline(always)]
1780 unsafe fn _clear(bits: usize) {
1781 unsafe {
1782 core :: arch :: asm ! ("csrrc x0, 0x7ca, {0}" , in (reg) bits);
1783 }
1784 }
1785 #[doc = r" Read the CSR value."]
1786 #[inline]
1787 pub fn read() -> McacheCtl {
1788 unsafe { McacheCtl(_read() as u32) }
1789 }
1790 #[doc = r" Write the CSR value."]
1791 #[inline]
1792 pub unsafe fn write(val: McacheCtl) {
1793 unsafe {
1794 _write(val.0 as usize);
1795 }
1796 }
1797 #[doc = r" Read-modify-write the CSR."]
1798 #[inline]
1799 pub unsafe fn modify<R>(f: impl FnOnce(&mut McacheCtl) -> R) -> R {
1800 let mut val = read();
1801 let res = f(&mut val);
1802 unsafe {
1803 write(val);
1804 }
1805 res
1806 }
1807 #[doc = "Instruction Cache Enable"]
1808 #[inline]
1809 pub unsafe fn set_ic_en() {
1810 unsafe {
1811 _set(1usize);
1812 }
1813 }
1814 #[doc = "Instruction Cache Enable"]
1815 #[inline]
1816 pub unsafe fn clear_ic_en() {
1817 unsafe {
1818 _clear(1usize);
1819 }
1820 }
1821 #[doc = "Data Cache Enable"]
1822 #[inline]
1823 pub unsafe fn set_dc_en() {
1824 unsafe {
1825 _set(2usize);
1826 }
1827 }
1828 #[doc = "Data Cache Enable"]
1829 #[inline]
1830 pub unsafe fn clear_dc_en() {
1831 unsafe {
1832 _clear(2usize);
1833 }
1834 }
1835 #[doc = "Instruction Cache ECC Enable"]
1836 #[inline]
1837 pub unsafe fn set_ic_eccen(val: u8) {
1838 let mut bits = unsafe { _read() };
1839 bits &= !(3usize << 2usize);
1840 bits |= (val as usize & 3usize) << 2usize;
1841 unsafe {
1842 _write(bits);
1843 }
1844 }
1845 #[doc = "Data Cache ECC Enable"]
1846 #[inline]
1847 pub unsafe fn set_dc_eccen(val: u8) {
1848 let mut bits = unsafe { _read() };
1849 bits &= !(3usize << 4usize);
1850 bits |= (val as usize & 3usize) << 4usize;
1851 unsafe {
1852 _write(bits);
1853 }
1854 }
1855 #[doc = "Instruction Cache Read/Write ECC"]
1856 #[inline]
1857 pub unsafe fn set_ic_rwecc() {
1858 unsafe {
1859 _set(64usize);
1860 }
1861 }
1862 #[doc = "Instruction Cache Read/Write ECC"]
1863 #[inline]
1864 pub unsafe fn clear_ic_rwecc() {
1865 unsafe {
1866 _clear(64usize);
1867 }
1868 }
1869 #[doc = "Data Cache Read/Write ECC"]
1870 #[inline]
1871 pub unsafe fn set_dc_rwecc() {
1872 unsafe {
1873 _set(128usize);
1874 }
1875 }
1876 #[doc = "Data Cache Read/Write ECC"]
1877 #[inline]
1878 pub unsafe fn clear_dc_rwecc() {
1879 unsafe {
1880 _clear(128usize);
1881 }
1882 }
1883 #[doc = "Cache Control SU Enable"]
1884 #[inline]
1885 pub unsafe fn set_cctl_suen() {
1886 unsafe {
1887 _set(256usize);
1888 }
1889 }
1890 #[doc = "Cache Control SU Enable"]
1891 #[inline]
1892 pub unsafe fn clear_cctl_suen() {
1893 unsafe {
1894 _clear(256usize);
1895 }
1896 }
1897 #[doc = "Instruction Prefetch Enable"]
1898 #[inline]
1899 pub unsafe fn set_ipref_en() {
1900 unsafe {
1901 _set(512usize);
1902 }
1903 }
1904 #[doc = "Instruction Prefetch Enable"]
1905 #[inline]
1906 pub unsafe fn clear_ipref_en() {
1907 unsafe {
1908 _clear(512usize);
1909 }
1910 }
1911 #[doc = "Data Prefetch Enable"]
1912 #[inline]
1913 pub unsafe fn set_dpref_en() {
1914 unsafe {
1915 _set(1024usize);
1916 }
1917 }
1918 #[doc = "Data Prefetch Enable"]
1919 #[inline]
1920 pub unsafe fn clear_dpref_en() {
1921 unsafe {
1922 _clear(1024usize);
1923 }
1924 }
1925 #[doc = "Instruction Cache 1st Way Disable"]
1926 #[inline]
1927 pub unsafe fn set_ic_1st_wd() {
1928 unsafe {
1929 _set(2048usize);
1930 }
1931 }
1932 #[doc = "Instruction Cache 1st Way Disable"]
1933 #[inline]
1934 pub unsafe fn clear_ic_1st_wd() {
1935 unsafe {
1936 _clear(2048usize);
1937 }
1938 }
1939 #[doc = "Data Cache 1st Way Disable"]
1940 #[inline]
1941 pub unsafe fn set_dc_1st_wd() {
1942 unsafe {
1943 _set(4096usize);
1944 }
1945 }
1946 #[doc = "Data Cache 1st Way Disable"]
1947 #[inline]
1948 pub unsafe fn clear_dc_1st_wd() {
1949 unsafe {
1950 _clear(4096usize);
1951 }
1952 }
1953 #[doc = "Data Cache Write-Around"]
1954 #[inline]
1955 pub unsafe fn set_dc_warnd(val: u8) {
1956 let mut bits = unsafe { _read() };
1957 bits &= !(3usize << 13usize);
1958 bits |= (val as usize & 3usize) << 13usize;
1959 unsafe {
1960 _write(bits);
1961 }
1962 }
1963 #[doc = "L2 Cache Write-Around"]
1964 #[inline]
1965 pub unsafe fn set_l2c_warnd(val: u8) {
1966 let mut bits = unsafe { _read() };
1967 bits &= !(3usize << 15usize);
1968 bits |= (val as usize & 3usize) << 15usize;
1969 unsafe {
1970 _write(bits);
1971 }
1972 }
1973 #[doc = "TLB ECC Enable"]
1974 #[inline]
1975 pub unsafe fn set_tlb_eccen(val: u8) {
1976 let mut bits = unsafe { _read() };
1977 bits &= !(3usize << 17usize);
1978 bits |= (val as usize & 3usize) << 17usize;
1979 unsafe {
1980 _write(bits);
1981 }
1982 }
1983 #[doc = "Data Cache Coherence Enable"]
1984 #[inline]
1985 pub unsafe fn set_dc_cohen() {
1986 unsafe {
1987 _set(524288usize);
1988 }
1989 }
1990 #[doc = "Data Cache Coherence Enable"]
1991 #[inline]
1992 pub unsafe fn clear_dc_cohen() {
1993 unsafe {
1994 _clear(524288usize);
1995 }
1996 }
1997 #[doc = "Data Cache Coherence State"]
1998 #[inline]
1999 pub unsafe fn set_dc_cohsta() {
2000 unsafe {
2001 _set(1048576usize);
2002 }
2003 }
2004 #[doc = "Data Cache Coherence State"]
2005 #[inline]
2006 pub unsafe fn clear_dc_cohsta() {
2007 unsafe {
2008 _clear(1048576usize);
2009 }
2010 }
2011 #[doc = "Data Prefetch Mode"]
2012 #[inline]
2013 pub unsafe fn set_dpref_mode(val: u8) {
2014 let mut bits = unsafe { _read() };
2015 bits &= !(3usize << 21usize);
2016 bits |= (val as usize & 3usize) << 21usize;
2017 unsafe {
2018 _write(bits);
2019 }
2020 }
2021}
2022#[doc = "CCTL begin address"]
2023pub mod mcctlbeginaddr {
2024 #[inline(always)]
2025 unsafe fn _read() -> usize {
2026 let r: usize;
2027 unsafe {
2028 core :: arch :: asm ! ("csrrs {0}, 0x7cb, x0" , out (reg) r);
2029 }
2030 r
2031 }
2032 #[inline(always)]
2033 unsafe fn _write(bits: usize) {
2034 unsafe {
2035 core :: arch :: asm ! ("csrrw x0, 0x7cb, {0}" , in (reg) bits);
2036 }
2037 }
2038 #[inline(always)]
2039 unsafe fn _set(bits: usize) {
2040 unsafe {
2041 core :: arch :: asm ! ("csrrs x0, 0x7cb, {0}" , in (reg) bits);
2042 }
2043 }
2044 #[inline(always)]
2045 unsafe fn _clear(bits: usize) {
2046 unsafe {
2047 core :: arch :: asm ! ("csrrc x0, 0x7cb, {0}" , in (reg) bits);
2048 }
2049 }
2050 #[doc = r" Read the CSR value as raw usize."]
2051 #[inline]
2052 pub fn read() -> usize {
2053 unsafe { _read() }
2054 }
2055 #[doc = r" Write the CSR value as raw usize."]
2056 #[inline]
2057 pub unsafe fn write(val: usize) {
2058 unsafe {
2059 _write(val);
2060 }
2061 }
2062}
2063#[doc = "CCTL command"]
2064pub mod mcctlcommand {
2065 #[inline(always)]
2066 unsafe fn _read() -> usize {
2067 let r: usize;
2068 unsafe {
2069 core :: arch :: asm ! ("csrrs {0}, 0x7cc, x0" , out (reg) r);
2070 }
2071 r
2072 }
2073 #[inline(always)]
2074 unsafe fn _write(bits: usize) {
2075 unsafe {
2076 core :: arch :: asm ! ("csrrw x0, 0x7cc, {0}" , in (reg) bits);
2077 }
2078 }
2079 #[inline(always)]
2080 unsafe fn _set(bits: usize) {
2081 unsafe {
2082 core :: arch :: asm ! ("csrrs x0, 0x7cc, {0}" , in (reg) bits);
2083 }
2084 }
2085 #[inline(always)]
2086 unsafe fn _clear(bits: usize) {
2087 unsafe {
2088 core :: arch :: asm ! ("csrrc x0, 0x7cc, {0}" , in (reg) bits);
2089 }
2090 }
2091 #[doc = r" Read the CSR value as raw usize."]
2092 #[inline]
2093 pub fn read() -> usize {
2094 unsafe { _read() }
2095 }
2096 #[doc = r" Write the CSR value as raw usize."]
2097 #[inline]
2098 pub unsafe fn write(val: usize) {
2099 unsafe {
2100 _write(val);
2101 }
2102 }
2103}
2104#[doc = "CCTL data"]
2105pub mod mcctldata {
2106 #[inline(always)]
2107 unsafe fn _read() -> usize {
2108 let r: usize;
2109 unsafe {
2110 core :: arch :: asm ! ("csrrs {0}, 0x7cd, x0" , out (reg) r);
2111 }
2112 r
2113 }
2114 #[inline(always)]
2115 unsafe fn _write(bits: usize) {
2116 unsafe {
2117 core :: arch :: asm ! ("csrrw x0, 0x7cd, {0}" , in (reg) bits);
2118 }
2119 }
2120 #[inline(always)]
2121 unsafe fn _set(bits: usize) {
2122 unsafe {
2123 core :: arch :: asm ! ("csrrs x0, 0x7cd, {0}" , in (reg) bits);
2124 }
2125 }
2126 #[inline(always)]
2127 unsafe fn _clear(bits: usize) {
2128 unsafe {
2129 core :: arch :: asm ! ("csrrc x0, 0x7cd, {0}" , in (reg) bits);
2130 }
2131 }
2132 #[doc = r" Read the CSR value as raw usize."]
2133 #[inline]
2134 pub fn read() -> usize {
2135 unsafe { _read() }
2136 }
2137 #[doc = r" Write the CSR value as raw usize."]
2138 #[inline]
2139 pub unsafe fn write(val: usize) {
2140 unsafe {
2141 _write(val);
2142 }
2143 }
2144}
2145#[doc = "Counter write enable"]
2146pub mod mcounterwen {
2147 #[doc = "Machine Counter Fields"]
2148 #[repr(transparent)]
2149 #[derive(Copy, Clone, Eq, PartialEq)]
2150 pub struct McounterCommon(pub u32);
2151 impl McounterCommon {
2152 #[doc = "Cycle counter"]
2153 #[must_use]
2154 #[inline(always)]
2155 pub const fn cy(&self) -> bool {
2156 let val = (self.0 >> 0usize) & 0x01;
2157 val != 0
2158 }
2159 #[doc = "Cycle counter"]
2160 #[inline(always)]
2161 pub const fn set_cy(&mut self, val: bool) {
2162 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
2163 }
2164 #[doc = "Instruction retired counter"]
2165 #[must_use]
2166 #[inline(always)]
2167 pub const fn ir(&self) -> bool {
2168 let val = (self.0 >> 2usize) & 0x01;
2169 val != 0
2170 }
2171 #[doc = "Instruction retired counter"]
2172 #[inline(always)]
2173 pub const fn set_ir(&mut self, val: bool) {
2174 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
2175 }
2176 #[doc = "Hardware performance monitor 3 to 31"]
2177 #[must_use]
2178 #[inline(always)]
2179 pub const fn hpm(&self, n: usize) -> bool {
2180 assert!(n < 29usize);
2181 let offs = 3usize + n * 1usize;
2182 let val = (self.0 >> offs) & 0x01;
2183 val != 0
2184 }
2185 #[doc = "Hardware performance monitor 3 to 31"]
2186 #[inline(always)]
2187 pub const fn set_hpm(&mut self, n: usize, val: bool) {
2188 assert!(n < 29usize);
2189 let offs = 3usize + n * 1usize;
2190 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
2191 }
2192 }
2193 impl Default for McounterCommon {
2194 #[inline(always)]
2195 fn default() -> McounterCommon {
2196 McounterCommon(0)
2197 }
2198 }
2199 impl core::fmt::Debug for McounterCommon {
2200 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
2201 f.debug_struct("McounterCommon")
2202 .field("cy", &self.cy())
2203 .field("ir", &self.ir())
2204 .field("hpm[0]", &self.hpm(0usize))
2205 .field("hpm[1]", &self.hpm(1usize))
2206 .field("hpm[2]", &self.hpm(2usize))
2207 .field("hpm[3]", &self.hpm(3usize))
2208 .field("hpm[4]", &self.hpm(4usize))
2209 .field("hpm[5]", &self.hpm(5usize))
2210 .field("hpm[6]", &self.hpm(6usize))
2211 .field("hpm[7]", &self.hpm(7usize))
2212 .field("hpm[8]", &self.hpm(8usize))
2213 .field("hpm[9]", &self.hpm(9usize))
2214 .field("hpm[10]", &self.hpm(10usize))
2215 .field("hpm[11]", &self.hpm(11usize))
2216 .field("hpm[12]", &self.hpm(12usize))
2217 .field("hpm[13]", &self.hpm(13usize))
2218 .field("hpm[14]", &self.hpm(14usize))
2219 .field("hpm[15]", &self.hpm(15usize))
2220 .field("hpm[16]", &self.hpm(16usize))
2221 .field("hpm[17]", &self.hpm(17usize))
2222 .field("hpm[18]", &self.hpm(18usize))
2223 .field("hpm[19]", &self.hpm(19usize))
2224 .field("hpm[20]", &self.hpm(20usize))
2225 .field("hpm[21]", &self.hpm(21usize))
2226 .field("hpm[22]", &self.hpm(22usize))
2227 .field("hpm[23]", &self.hpm(23usize))
2228 .field("hpm[24]", &self.hpm(24usize))
2229 .field("hpm[25]", &self.hpm(25usize))
2230 .field("hpm[26]", &self.hpm(26usize))
2231 .field("hpm[27]", &self.hpm(27usize))
2232 .field("hpm[28]", &self.hpm(28usize))
2233 .finish()
2234 }
2235 }
2236 #[cfg(feature = "defmt")]
2237 impl defmt::Format for McounterCommon {
2238 fn format(&self, f: defmt::Formatter) {
2239 defmt::write!(
2240 f,
2241 "McounterCommon {{ cy: {=bool:?}, ir: {=bool:?}, hpm[0]: {=bool:?}, hpm[1]: {=bool:?}, hpm[2]: {=bool:?}, hpm[3]: {=bool:?}, hpm[4]: {=bool:?}, hpm[5]: {=bool:?}, hpm[6]: {=bool:?}, hpm[7]: {=bool:?}, hpm[8]: {=bool:?}, hpm[9]: {=bool:?}, hpm[10]: {=bool:?}, hpm[11]: {=bool:?}, hpm[12]: {=bool:?}, hpm[13]: {=bool:?}, hpm[14]: {=bool:?}, hpm[15]: {=bool:?}, hpm[16]: {=bool:?}, hpm[17]: {=bool:?}, hpm[18]: {=bool:?}, hpm[19]: {=bool:?}, hpm[20]: {=bool:?}, hpm[21]: {=bool:?}, hpm[22]: {=bool:?}, hpm[23]: {=bool:?}, hpm[24]: {=bool:?}, hpm[25]: {=bool:?}, hpm[26]: {=bool:?}, hpm[27]: {=bool:?}, hpm[28]: {=bool:?} }}",
2242 self.cy(),
2243 self.ir(),
2244 self.hpm(0usize),
2245 self.hpm(1usize),
2246 self.hpm(2usize),
2247 self.hpm(3usize),
2248 self.hpm(4usize),
2249 self.hpm(5usize),
2250 self.hpm(6usize),
2251 self.hpm(7usize),
2252 self.hpm(8usize),
2253 self.hpm(9usize),
2254 self.hpm(10usize),
2255 self.hpm(11usize),
2256 self.hpm(12usize),
2257 self.hpm(13usize),
2258 self.hpm(14usize),
2259 self.hpm(15usize),
2260 self.hpm(16usize),
2261 self.hpm(17usize),
2262 self.hpm(18usize),
2263 self.hpm(19usize),
2264 self.hpm(20usize),
2265 self.hpm(21usize),
2266 self.hpm(22usize),
2267 self.hpm(23usize),
2268 self.hpm(24usize),
2269 self.hpm(25usize),
2270 self.hpm(26usize),
2271 self.hpm(27usize),
2272 self.hpm(28usize)
2273 )
2274 }
2275 }
2276 #[inline(always)]
2277 unsafe fn _read() -> usize {
2278 let r: usize;
2279 unsafe {
2280 core :: arch :: asm ! ("csrrs {0}, 0x7ce, x0" , out (reg) r);
2281 }
2282 r
2283 }
2284 #[inline(always)]
2285 unsafe fn _write(bits: usize) {
2286 unsafe {
2287 core :: arch :: asm ! ("csrrw x0, 0x7ce, {0}" , in (reg) bits);
2288 }
2289 }
2290 #[inline(always)]
2291 unsafe fn _set(bits: usize) {
2292 unsafe {
2293 core :: arch :: asm ! ("csrrs x0, 0x7ce, {0}" , in (reg) bits);
2294 }
2295 }
2296 #[inline(always)]
2297 unsafe fn _clear(bits: usize) {
2298 unsafe {
2299 core :: arch :: asm ! ("csrrc x0, 0x7ce, {0}" , in (reg) bits);
2300 }
2301 }
2302 #[doc = r" Read the CSR value."]
2303 #[inline]
2304 pub fn read() -> McounterCommon {
2305 unsafe { McounterCommon(_read() as u32) }
2306 }
2307 #[doc = r" Write the CSR value."]
2308 #[inline]
2309 pub unsafe fn write(val: McounterCommon) {
2310 unsafe {
2311 _write(val.0 as usize);
2312 }
2313 }
2314 #[doc = r" Read-modify-write the CSR."]
2315 #[inline]
2316 pub unsafe fn modify<R>(f: impl FnOnce(&mut McounterCommon) -> R) -> R {
2317 let mut val = read();
2318 let res = f(&mut val);
2319 unsafe {
2320 write(val);
2321 }
2322 res
2323 }
2324 #[doc = "Cycle counter"]
2325 #[inline]
2326 pub unsafe fn set_cy() {
2327 unsafe {
2328 _set(1usize);
2329 }
2330 }
2331 #[doc = "Cycle counter"]
2332 #[inline]
2333 pub unsafe fn clear_cy() {
2334 unsafe {
2335 _clear(1usize);
2336 }
2337 }
2338 #[doc = "Instruction retired counter"]
2339 #[inline]
2340 pub unsafe fn set_ir() {
2341 unsafe {
2342 _set(4usize);
2343 }
2344 }
2345 #[doc = "Instruction retired counter"]
2346 #[inline]
2347 pub unsafe fn clear_ir() {
2348 unsafe {
2349 _clear(4usize);
2350 }
2351 }
2352}
2353#[doc = "Counter overflow interrupt enable"]
2354pub mod mcounterinten {
2355 #[doc = "Machine Counter Fields"]
2356 #[repr(transparent)]
2357 #[derive(Copy, Clone, Eq, PartialEq)]
2358 pub struct McounterCommon(pub u32);
2359 impl McounterCommon {
2360 #[doc = "Cycle counter"]
2361 #[must_use]
2362 #[inline(always)]
2363 pub const fn cy(&self) -> bool {
2364 let val = (self.0 >> 0usize) & 0x01;
2365 val != 0
2366 }
2367 #[doc = "Cycle counter"]
2368 #[inline(always)]
2369 pub const fn set_cy(&mut self, val: bool) {
2370 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
2371 }
2372 #[doc = "Instruction retired counter"]
2373 #[must_use]
2374 #[inline(always)]
2375 pub const fn ir(&self) -> bool {
2376 let val = (self.0 >> 2usize) & 0x01;
2377 val != 0
2378 }
2379 #[doc = "Instruction retired counter"]
2380 #[inline(always)]
2381 pub const fn set_ir(&mut self, val: bool) {
2382 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
2383 }
2384 #[doc = "Hardware performance monitor 3 to 31"]
2385 #[must_use]
2386 #[inline(always)]
2387 pub const fn hpm(&self, n: usize) -> bool {
2388 assert!(n < 29usize);
2389 let offs = 3usize + n * 1usize;
2390 let val = (self.0 >> offs) & 0x01;
2391 val != 0
2392 }
2393 #[doc = "Hardware performance monitor 3 to 31"]
2394 #[inline(always)]
2395 pub const fn set_hpm(&mut self, n: usize, val: bool) {
2396 assert!(n < 29usize);
2397 let offs = 3usize + n * 1usize;
2398 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
2399 }
2400 }
2401 impl Default for McounterCommon {
2402 #[inline(always)]
2403 fn default() -> McounterCommon {
2404 McounterCommon(0)
2405 }
2406 }
2407 impl core::fmt::Debug for McounterCommon {
2408 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
2409 f.debug_struct("McounterCommon")
2410 .field("cy", &self.cy())
2411 .field("ir", &self.ir())
2412 .field("hpm[0]", &self.hpm(0usize))
2413 .field("hpm[1]", &self.hpm(1usize))
2414 .field("hpm[2]", &self.hpm(2usize))
2415 .field("hpm[3]", &self.hpm(3usize))
2416 .field("hpm[4]", &self.hpm(4usize))
2417 .field("hpm[5]", &self.hpm(5usize))
2418 .field("hpm[6]", &self.hpm(6usize))
2419 .field("hpm[7]", &self.hpm(7usize))
2420 .field("hpm[8]", &self.hpm(8usize))
2421 .field("hpm[9]", &self.hpm(9usize))
2422 .field("hpm[10]", &self.hpm(10usize))
2423 .field("hpm[11]", &self.hpm(11usize))
2424 .field("hpm[12]", &self.hpm(12usize))
2425 .field("hpm[13]", &self.hpm(13usize))
2426 .field("hpm[14]", &self.hpm(14usize))
2427 .field("hpm[15]", &self.hpm(15usize))
2428 .field("hpm[16]", &self.hpm(16usize))
2429 .field("hpm[17]", &self.hpm(17usize))
2430 .field("hpm[18]", &self.hpm(18usize))
2431 .field("hpm[19]", &self.hpm(19usize))
2432 .field("hpm[20]", &self.hpm(20usize))
2433 .field("hpm[21]", &self.hpm(21usize))
2434 .field("hpm[22]", &self.hpm(22usize))
2435 .field("hpm[23]", &self.hpm(23usize))
2436 .field("hpm[24]", &self.hpm(24usize))
2437 .field("hpm[25]", &self.hpm(25usize))
2438 .field("hpm[26]", &self.hpm(26usize))
2439 .field("hpm[27]", &self.hpm(27usize))
2440 .field("hpm[28]", &self.hpm(28usize))
2441 .finish()
2442 }
2443 }
2444 #[cfg(feature = "defmt")]
2445 impl defmt::Format for McounterCommon {
2446 fn format(&self, f: defmt::Formatter) {
2447 defmt::write!(
2448 f,
2449 "McounterCommon {{ cy: {=bool:?}, ir: {=bool:?}, hpm[0]: {=bool:?}, hpm[1]: {=bool:?}, hpm[2]: {=bool:?}, hpm[3]: {=bool:?}, hpm[4]: {=bool:?}, hpm[5]: {=bool:?}, hpm[6]: {=bool:?}, hpm[7]: {=bool:?}, hpm[8]: {=bool:?}, hpm[9]: {=bool:?}, hpm[10]: {=bool:?}, hpm[11]: {=bool:?}, hpm[12]: {=bool:?}, hpm[13]: {=bool:?}, hpm[14]: {=bool:?}, hpm[15]: {=bool:?}, hpm[16]: {=bool:?}, hpm[17]: {=bool:?}, hpm[18]: {=bool:?}, hpm[19]: {=bool:?}, hpm[20]: {=bool:?}, hpm[21]: {=bool:?}, hpm[22]: {=bool:?}, hpm[23]: {=bool:?}, hpm[24]: {=bool:?}, hpm[25]: {=bool:?}, hpm[26]: {=bool:?}, hpm[27]: {=bool:?}, hpm[28]: {=bool:?} }}",
2450 self.cy(),
2451 self.ir(),
2452 self.hpm(0usize),
2453 self.hpm(1usize),
2454 self.hpm(2usize),
2455 self.hpm(3usize),
2456 self.hpm(4usize),
2457 self.hpm(5usize),
2458 self.hpm(6usize),
2459 self.hpm(7usize),
2460 self.hpm(8usize),
2461 self.hpm(9usize),
2462 self.hpm(10usize),
2463 self.hpm(11usize),
2464 self.hpm(12usize),
2465 self.hpm(13usize),
2466 self.hpm(14usize),
2467 self.hpm(15usize),
2468 self.hpm(16usize),
2469 self.hpm(17usize),
2470 self.hpm(18usize),
2471 self.hpm(19usize),
2472 self.hpm(20usize),
2473 self.hpm(21usize),
2474 self.hpm(22usize),
2475 self.hpm(23usize),
2476 self.hpm(24usize),
2477 self.hpm(25usize),
2478 self.hpm(26usize),
2479 self.hpm(27usize),
2480 self.hpm(28usize)
2481 )
2482 }
2483 }
2484 #[inline(always)]
2485 unsafe fn _read() -> usize {
2486 let r: usize;
2487 unsafe {
2488 core :: arch :: asm ! ("csrrs {0}, 0x7cf, x0" , out (reg) r);
2489 }
2490 r
2491 }
2492 #[inline(always)]
2493 unsafe fn _write(bits: usize) {
2494 unsafe {
2495 core :: arch :: asm ! ("csrrw x0, 0x7cf, {0}" , in (reg) bits);
2496 }
2497 }
2498 #[inline(always)]
2499 unsafe fn _set(bits: usize) {
2500 unsafe {
2501 core :: arch :: asm ! ("csrrs x0, 0x7cf, {0}" , in (reg) bits);
2502 }
2503 }
2504 #[inline(always)]
2505 unsafe fn _clear(bits: usize) {
2506 unsafe {
2507 core :: arch :: asm ! ("csrrc x0, 0x7cf, {0}" , in (reg) bits);
2508 }
2509 }
2510 #[doc = r" Read the CSR value."]
2511 #[inline]
2512 pub fn read() -> McounterCommon {
2513 unsafe { McounterCommon(_read() as u32) }
2514 }
2515 #[doc = r" Write the CSR value."]
2516 #[inline]
2517 pub unsafe fn write(val: McounterCommon) {
2518 unsafe {
2519 _write(val.0 as usize);
2520 }
2521 }
2522 #[doc = r" Read-modify-write the CSR."]
2523 #[inline]
2524 pub unsafe fn modify<R>(f: impl FnOnce(&mut McounterCommon) -> R) -> R {
2525 let mut val = read();
2526 let res = f(&mut val);
2527 unsafe {
2528 write(val);
2529 }
2530 res
2531 }
2532 #[doc = "Cycle counter"]
2533 #[inline]
2534 pub unsafe fn set_cy() {
2535 unsafe {
2536 _set(1usize);
2537 }
2538 }
2539 #[doc = "Cycle counter"]
2540 #[inline]
2541 pub unsafe fn clear_cy() {
2542 unsafe {
2543 _clear(1usize);
2544 }
2545 }
2546 #[doc = "Instruction retired counter"]
2547 #[inline]
2548 pub unsafe fn set_ir() {
2549 unsafe {
2550 _set(4usize);
2551 }
2552 }
2553 #[doc = "Instruction retired counter"]
2554 #[inline]
2555 pub unsafe fn clear_ir() {
2556 unsafe {
2557 _clear(4usize);
2558 }
2559 }
2560}
2561#[doc = "Miscellaneous control"]
2562pub mod mmisc_ctl {
2563 #[doc = "Machine Miscellaneous Control Register"]
2564 #[repr(transparent)]
2565 #[derive(Copy, Clone, Eq, PartialEq)]
2566 pub struct MmiscCtl(pub u32);
2567 impl MmiscCtl {
2568 #[doc = "Andes Custom Extension (ACE) enable"]
2569 #[must_use]
2570 #[inline(always)]
2571 pub const fn ace(&self) -> bool {
2572 let val = (self.0 >> 0usize) & 0x01;
2573 val != 0
2574 }
2575 #[doc = "Andes Custom Extension (ACE) enable"]
2576 #[inline(always)]
2577 pub const fn set_ace(&mut self, val: bool) {
2578 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
2579 }
2580 #[doc = "Vectored external PLIC interrupt enable"]
2581 #[must_use]
2582 #[inline(always)]
2583 pub const fn vec_plic(&self) -> bool {
2584 let val = (self.0 >> 1usize) & 0x01;
2585 val != 0
2586 }
2587 #[doc = "Vectored external PLIC interrupt enable"]
2588 #[inline(always)]
2589 pub const fn set_vec_plic(&mut self, val: bool) {
2590 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
2591 }
2592 #[doc = "RV compatibility mode enable bit"]
2593 #[must_use]
2594 #[inline(always)]
2595 pub const fn rvcompm(&self) -> bool {
2596 let val = (self.0 >> 2usize) & 0x01;
2597 val != 0
2598 }
2599 #[doc = "RV compatibility mode enable bit"]
2600 #[inline(always)]
2601 pub const fn set_rvcompm(&mut self, val: bool) {
2602 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
2603 }
2604 #[must_use]
2605 #[inline(always)]
2606 pub const fn brpe(&self) -> bool {
2607 let val = (self.0 >> 3usize) & 0x01;
2608 val != 0
2609 }
2610 #[inline(always)]
2611 pub const fn set_brpe(&mut self, val: bool) {
2612 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
2613 }
2614 #[must_use]
2615 #[inline(always)]
2616 pub const fn aces(&self) -> u8 {
2617 let val = (self.0 >> 4usize) & 0x03;
2618 val as u8
2619 }
2620 #[inline(always)]
2621 pub const fn set_aces(&mut self, val: u8) {
2622 self.0 = (self.0 & !(0x03 << 4usize)) | (((val as u32) & 0x03) << 4usize);
2623 }
2624 #[must_use]
2625 #[inline(always)]
2626 pub const fn msa_una(&self) -> bool {
2627 let val = (self.0 >> 6usize) & 0x01;
2628 val != 0
2629 }
2630 #[inline(always)]
2631 pub const fn set_msa_una(&mut self, val: bool) {
2632 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
2633 }
2634 #[must_use]
2635 #[inline(always)]
2636 pub const fn nbld_en(&self) -> bool {
2637 let val = (self.0 >> 8usize) & 0x01;
2638 val != 0
2639 }
2640 #[inline(always)]
2641 pub const fn set_nbld_en(&mut self, val: bool) {
2642 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
2643 }
2644 #[must_use]
2645 #[inline(always)]
2646 pub const fn newnmi(&self) -> bool {
2647 let val = (self.0 >> 9usize) & 0x01;
2648 val != 0
2649 }
2650 #[inline(always)]
2651 pub const fn set_newnmi(&mut self, val: bool) {
2652 self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
2653 }
2654 #[must_use]
2655 #[inline(always)]
2656 pub const fn vcgl1_en(&self) -> bool {
2657 let val = (self.0 >> 10usize) & 0x01;
2658 val != 0
2659 }
2660 #[inline(always)]
2661 pub const fn set_vcgl1_en(&mut self, val: bool) {
2662 self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
2663 }
2664 #[must_use]
2665 #[inline(always)]
2666 pub const fn vcgl2_en(&self) -> bool {
2667 let val = (self.0 >> 11usize) & 0x01;
2668 val != 0
2669 }
2670 #[inline(always)]
2671 pub const fn set_vcgl2_en(&mut self, val: bool) {
2672 self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
2673 }
2674 #[must_use]
2675 #[inline(always)]
2676 pub const fn vcgl3_en(&self) -> bool {
2677 let val = (self.0 >> 12usize) & 0x01;
2678 val != 0
2679 }
2680 #[inline(always)]
2681 pub const fn set_vcgl3_en(&mut self, val: bool) {
2682 self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
2683 }
2684 #[doc = "“Load to x0” exception generation control bit"]
2685 #[must_use]
2686 #[inline(always)]
2687 pub const fn ldx0nxp(&self) -> bool {
2688 let val = (self.0 >> 13usize) & 0x01;
2689 val != 0
2690 }
2691 #[doc = "“Load to x0” exception generation control bit"]
2692 #[inline(always)]
2693 pub const fn set_ldx0nxp(&mut self, val: bool) {
2694 self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
2695 }
2696 }
2697 impl Default for MmiscCtl {
2698 #[inline(always)]
2699 fn default() -> MmiscCtl {
2700 MmiscCtl(0)
2701 }
2702 }
2703 impl core::fmt::Debug for MmiscCtl {
2704 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
2705 f.debug_struct("MmiscCtl")
2706 .field("ace", &self.ace())
2707 .field("vec_plic", &self.vec_plic())
2708 .field("rvcompm", &self.rvcompm())
2709 .field("brpe", &self.brpe())
2710 .field("aces", &self.aces())
2711 .field("msa_una", &self.msa_una())
2712 .field("nbld_en", &self.nbld_en())
2713 .field("newnmi", &self.newnmi())
2714 .field("vcgl1_en", &self.vcgl1_en())
2715 .field("vcgl2_en", &self.vcgl2_en())
2716 .field("vcgl3_en", &self.vcgl3_en())
2717 .field("ldx0nxp", &self.ldx0nxp())
2718 .finish()
2719 }
2720 }
2721 #[cfg(feature = "defmt")]
2722 impl defmt::Format for MmiscCtl {
2723 fn format(&self, f: defmt::Formatter) {
2724 defmt::write!(
2725 f,
2726 "MmiscCtl {{ ace: {=bool:?}, vec_plic: {=bool:?}, rvcompm: {=bool:?}, brpe: {=bool:?}, aces: {=u8:?}, msa_una: {=bool:?}, nbld_en: {=bool:?}, newnmi: {=bool:?}, vcgl1_en: {=bool:?}, vcgl2_en: {=bool:?}, vcgl3_en: {=bool:?}, ldx0nxp: {=bool:?} }}",
2727 self.ace(),
2728 self.vec_plic(),
2729 self.rvcompm(),
2730 self.brpe(),
2731 self.aces(),
2732 self.msa_una(),
2733 self.nbld_en(),
2734 self.newnmi(),
2735 self.vcgl1_en(),
2736 self.vcgl2_en(),
2737 self.vcgl3_en(),
2738 self.ldx0nxp()
2739 )
2740 }
2741 }
2742 #[inline(always)]
2743 unsafe fn _read() -> usize {
2744 let r: usize;
2745 unsafe {
2746 core :: arch :: asm ! ("csrrs {0}, 0x7d0, x0" , out (reg) r);
2747 }
2748 r
2749 }
2750 #[inline(always)]
2751 unsafe fn _write(bits: usize) {
2752 unsafe {
2753 core :: arch :: asm ! ("csrrw x0, 0x7d0, {0}" , in (reg) bits);
2754 }
2755 }
2756 #[inline(always)]
2757 unsafe fn _set(bits: usize) {
2758 unsafe {
2759 core :: arch :: asm ! ("csrrs x0, 0x7d0, {0}" , in (reg) bits);
2760 }
2761 }
2762 #[inline(always)]
2763 unsafe fn _clear(bits: usize) {
2764 unsafe {
2765 core :: arch :: asm ! ("csrrc x0, 0x7d0, {0}" , in (reg) bits);
2766 }
2767 }
2768 #[doc = r" Read the CSR value."]
2769 #[inline]
2770 pub fn read() -> MmiscCtl {
2771 unsafe { MmiscCtl(_read() as u32) }
2772 }
2773 #[doc = r" Write the CSR value."]
2774 #[inline]
2775 pub unsafe fn write(val: MmiscCtl) {
2776 unsafe {
2777 _write(val.0 as usize);
2778 }
2779 }
2780 #[doc = r" Read-modify-write the CSR."]
2781 #[inline]
2782 pub unsafe fn modify<R>(f: impl FnOnce(&mut MmiscCtl) -> R) -> R {
2783 let mut val = read();
2784 let res = f(&mut val);
2785 unsafe {
2786 write(val);
2787 }
2788 res
2789 }
2790 #[doc = "Andes Custom Extension (ACE) enable"]
2791 #[inline]
2792 pub unsafe fn set_ace() {
2793 unsafe {
2794 _set(1usize);
2795 }
2796 }
2797 #[doc = "Andes Custom Extension (ACE) enable"]
2798 #[inline]
2799 pub unsafe fn clear_ace() {
2800 unsafe {
2801 _clear(1usize);
2802 }
2803 }
2804 #[doc = "Vectored external PLIC interrupt enable"]
2805 #[inline]
2806 pub unsafe fn set_vec_plic() {
2807 unsafe {
2808 _set(2usize);
2809 }
2810 }
2811 #[doc = "Vectored external PLIC interrupt enable"]
2812 #[inline]
2813 pub unsafe fn clear_vec_plic() {
2814 unsafe {
2815 _clear(2usize);
2816 }
2817 }
2818 #[doc = "RV compatibility mode enable bit"]
2819 #[inline]
2820 pub unsafe fn set_rvcompm() {
2821 unsafe {
2822 _set(4usize);
2823 }
2824 }
2825 #[doc = "RV compatibility mode enable bit"]
2826 #[inline]
2827 pub unsafe fn clear_rvcompm() {
2828 unsafe {
2829 _clear(4usize);
2830 }
2831 }
2832 #[inline]
2833 pub unsafe fn set_brpe() {
2834 unsafe {
2835 _set(8usize);
2836 }
2837 }
2838 #[inline]
2839 pub unsafe fn clear_brpe() {
2840 unsafe {
2841 _clear(8usize);
2842 }
2843 }
2844 #[inline]
2845 pub unsafe fn set_aces(val: u8) {
2846 let mut bits = unsafe { _read() };
2847 bits &= !(3usize << 4usize);
2848 bits |= (val as usize & 3usize) << 4usize;
2849 unsafe {
2850 _write(bits);
2851 }
2852 }
2853 #[inline]
2854 pub unsafe fn set_msa_una() {
2855 unsafe {
2856 _set(64usize);
2857 }
2858 }
2859 #[inline]
2860 pub unsafe fn clear_msa_una() {
2861 unsafe {
2862 _clear(64usize);
2863 }
2864 }
2865 #[inline]
2866 pub unsafe fn set_nbld_en() {
2867 unsafe {
2868 _set(256usize);
2869 }
2870 }
2871 #[inline]
2872 pub unsafe fn clear_nbld_en() {
2873 unsafe {
2874 _clear(256usize);
2875 }
2876 }
2877 #[inline]
2878 pub unsafe fn set_newnmi() {
2879 unsafe {
2880 _set(512usize);
2881 }
2882 }
2883 #[inline]
2884 pub unsafe fn clear_newnmi() {
2885 unsafe {
2886 _clear(512usize);
2887 }
2888 }
2889 #[inline]
2890 pub unsafe fn set_vcgl1_en() {
2891 unsafe {
2892 _set(1024usize);
2893 }
2894 }
2895 #[inline]
2896 pub unsafe fn clear_vcgl1_en() {
2897 unsafe {
2898 _clear(1024usize);
2899 }
2900 }
2901 #[inline]
2902 pub unsafe fn set_vcgl2_en() {
2903 unsafe {
2904 _set(2048usize);
2905 }
2906 }
2907 #[inline]
2908 pub unsafe fn clear_vcgl2_en() {
2909 unsafe {
2910 _clear(2048usize);
2911 }
2912 }
2913 #[inline]
2914 pub unsafe fn set_vcgl3_en() {
2915 unsafe {
2916 _set(4096usize);
2917 }
2918 }
2919 #[inline]
2920 pub unsafe fn clear_vcgl3_en() {
2921 unsafe {
2922 _clear(4096usize);
2923 }
2924 }
2925 #[doc = "“Load to x0” exception generation control bit"]
2926 #[inline]
2927 pub unsafe fn set_ldx0nxp() {
2928 unsafe {
2929 _set(8192usize);
2930 }
2931 }
2932 #[doc = "“Load to x0” exception generation control bit"]
2933 #[inline]
2934 pub unsafe fn clear_ldx0nxp() {
2935 unsafe {
2936 _clear(8192usize);
2937 }
2938 }
2939}
2940#[doc = "Counter not counting in M-mode"]
2941pub mod mcountermask_m {
2942 #[doc = "Machine Counter Fields"]
2943 #[repr(transparent)]
2944 #[derive(Copy, Clone, Eq, PartialEq)]
2945 pub struct McounterCommon(pub u32);
2946 impl McounterCommon {
2947 #[doc = "Cycle counter"]
2948 #[must_use]
2949 #[inline(always)]
2950 pub const fn cy(&self) -> bool {
2951 let val = (self.0 >> 0usize) & 0x01;
2952 val != 0
2953 }
2954 #[doc = "Cycle counter"]
2955 #[inline(always)]
2956 pub const fn set_cy(&mut self, val: bool) {
2957 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
2958 }
2959 #[doc = "Instruction retired counter"]
2960 #[must_use]
2961 #[inline(always)]
2962 pub const fn ir(&self) -> bool {
2963 let val = (self.0 >> 2usize) & 0x01;
2964 val != 0
2965 }
2966 #[doc = "Instruction retired counter"]
2967 #[inline(always)]
2968 pub const fn set_ir(&mut self, val: bool) {
2969 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
2970 }
2971 #[doc = "Hardware performance monitor 3 to 31"]
2972 #[must_use]
2973 #[inline(always)]
2974 pub const fn hpm(&self, n: usize) -> bool {
2975 assert!(n < 29usize);
2976 let offs = 3usize + n * 1usize;
2977 let val = (self.0 >> offs) & 0x01;
2978 val != 0
2979 }
2980 #[doc = "Hardware performance monitor 3 to 31"]
2981 #[inline(always)]
2982 pub const fn set_hpm(&mut self, n: usize, val: bool) {
2983 assert!(n < 29usize);
2984 let offs = 3usize + n * 1usize;
2985 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
2986 }
2987 }
2988 impl Default for McounterCommon {
2989 #[inline(always)]
2990 fn default() -> McounterCommon {
2991 McounterCommon(0)
2992 }
2993 }
2994 impl core::fmt::Debug for McounterCommon {
2995 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
2996 f.debug_struct("McounterCommon")
2997 .field("cy", &self.cy())
2998 .field("ir", &self.ir())
2999 .field("hpm[0]", &self.hpm(0usize))
3000 .field("hpm[1]", &self.hpm(1usize))
3001 .field("hpm[2]", &self.hpm(2usize))
3002 .field("hpm[3]", &self.hpm(3usize))
3003 .field("hpm[4]", &self.hpm(4usize))
3004 .field("hpm[5]", &self.hpm(5usize))
3005 .field("hpm[6]", &self.hpm(6usize))
3006 .field("hpm[7]", &self.hpm(7usize))
3007 .field("hpm[8]", &self.hpm(8usize))
3008 .field("hpm[9]", &self.hpm(9usize))
3009 .field("hpm[10]", &self.hpm(10usize))
3010 .field("hpm[11]", &self.hpm(11usize))
3011 .field("hpm[12]", &self.hpm(12usize))
3012 .field("hpm[13]", &self.hpm(13usize))
3013 .field("hpm[14]", &self.hpm(14usize))
3014 .field("hpm[15]", &self.hpm(15usize))
3015 .field("hpm[16]", &self.hpm(16usize))
3016 .field("hpm[17]", &self.hpm(17usize))
3017 .field("hpm[18]", &self.hpm(18usize))
3018 .field("hpm[19]", &self.hpm(19usize))
3019 .field("hpm[20]", &self.hpm(20usize))
3020 .field("hpm[21]", &self.hpm(21usize))
3021 .field("hpm[22]", &self.hpm(22usize))
3022 .field("hpm[23]", &self.hpm(23usize))
3023 .field("hpm[24]", &self.hpm(24usize))
3024 .field("hpm[25]", &self.hpm(25usize))
3025 .field("hpm[26]", &self.hpm(26usize))
3026 .field("hpm[27]", &self.hpm(27usize))
3027 .field("hpm[28]", &self.hpm(28usize))
3028 .finish()
3029 }
3030 }
3031 #[cfg(feature = "defmt")]
3032 impl defmt::Format for McounterCommon {
3033 fn format(&self, f: defmt::Formatter) {
3034 defmt::write!(
3035 f,
3036 "McounterCommon {{ cy: {=bool:?}, ir: {=bool:?}, hpm[0]: {=bool:?}, hpm[1]: {=bool:?}, hpm[2]: {=bool:?}, hpm[3]: {=bool:?}, hpm[4]: {=bool:?}, hpm[5]: {=bool:?}, hpm[6]: {=bool:?}, hpm[7]: {=bool:?}, hpm[8]: {=bool:?}, hpm[9]: {=bool:?}, hpm[10]: {=bool:?}, hpm[11]: {=bool:?}, hpm[12]: {=bool:?}, hpm[13]: {=bool:?}, hpm[14]: {=bool:?}, hpm[15]: {=bool:?}, hpm[16]: {=bool:?}, hpm[17]: {=bool:?}, hpm[18]: {=bool:?}, hpm[19]: {=bool:?}, hpm[20]: {=bool:?}, hpm[21]: {=bool:?}, hpm[22]: {=bool:?}, hpm[23]: {=bool:?}, hpm[24]: {=bool:?}, hpm[25]: {=bool:?}, hpm[26]: {=bool:?}, hpm[27]: {=bool:?}, hpm[28]: {=bool:?} }}",
3037 self.cy(),
3038 self.ir(),
3039 self.hpm(0usize),
3040 self.hpm(1usize),
3041 self.hpm(2usize),
3042 self.hpm(3usize),
3043 self.hpm(4usize),
3044 self.hpm(5usize),
3045 self.hpm(6usize),
3046 self.hpm(7usize),
3047 self.hpm(8usize),
3048 self.hpm(9usize),
3049 self.hpm(10usize),
3050 self.hpm(11usize),
3051 self.hpm(12usize),
3052 self.hpm(13usize),
3053 self.hpm(14usize),
3054 self.hpm(15usize),
3055 self.hpm(16usize),
3056 self.hpm(17usize),
3057 self.hpm(18usize),
3058 self.hpm(19usize),
3059 self.hpm(20usize),
3060 self.hpm(21usize),
3061 self.hpm(22usize),
3062 self.hpm(23usize),
3063 self.hpm(24usize),
3064 self.hpm(25usize),
3065 self.hpm(26usize),
3066 self.hpm(27usize),
3067 self.hpm(28usize)
3068 )
3069 }
3070 }
3071 #[inline(always)]
3072 unsafe fn _read() -> usize {
3073 let r: usize;
3074 unsafe {
3075 core :: arch :: asm ! ("csrrs {0}, 0x7d1, x0" , out (reg) r);
3076 }
3077 r
3078 }
3079 #[inline(always)]
3080 unsafe fn _write(bits: usize) {
3081 unsafe {
3082 core :: arch :: asm ! ("csrrw x0, 0x7d1, {0}" , in (reg) bits);
3083 }
3084 }
3085 #[inline(always)]
3086 unsafe fn _set(bits: usize) {
3087 unsafe {
3088 core :: arch :: asm ! ("csrrs x0, 0x7d1, {0}" , in (reg) bits);
3089 }
3090 }
3091 #[inline(always)]
3092 unsafe fn _clear(bits: usize) {
3093 unsafe {
3094 core :: arch :: asm ! ("csrrc x0, 0x7d1, {0}" , in (reg) bits);
3095 }
3096 }
3097 #[doc = r" Read the CSR value."]
3098 #[inline]
3099 pub fn read() -> McounterCommon {
3100 unsafe { McounterCommon(_read() as u32) }
3101 }
3102 #[doc = r" Write the CSR value."]
3103 #[inline]
3104 pub unsafe fn write(val: McounterCommon) {
3105 unsafe {
3106 _write(val.0 as usize);
3107 }
3108 }
3109 #[doc = r" Read-modify-write the CSR."]
3110 #[inline]
3111 pub unsafe fn modify<R>(f: impl FnOnce(&mut McounterCommon) -> R) -> R {
3112 let mut val = read();
3113 let res = f(&mut val);
3114 unsafe {
3115 write(val);
3116 }
3117 res
3118 }
3119 #[doc = "Cycle counter"]
3120 #[inline]
3121 pub unsafe fn set_cy() {
3122 unsafe {
3123 _set(1usize);
3124 }
3125 }
3126 #[doc = "Cycle counter"]
3127 #[inline]
3128 pub unsafe fn clear_cy() {
3129 unsafe {
3130 _clear(1usize);
3131 }
3132 }
3133 #[doc = "Instruction retired counter"]
3134 #[inline]
3135 pub unsafe fn set_ir() {
3136 unsafe {
3137 _set(4usize);
3138 }
3139 }
3140 #[doc = "Instruction retired counter"]
3141 #[inline]
3142 pub unsafe fn clear_ir() {
3143 unsafe {
3144 _clear(4usize);
3145 }
3146 }
3147}
3148#[doc = "Counter not counting in S-mode"]
3149pub mod mcountermask_s {
3150 #[doc = "Machine Counter Fields"]
3151 #[repr(transparent)]
3152 #[derive(Copy, Clone, Eq, PartialEq)]
3153 pub struct McounterCommon(pub u32);
3154 impl McounterCommon {
3155 #[doc = "Cycle counter"]
3156 #[must_use]
3157 #[inline(always)]
3158 pub const fn cy(&self) -> bool {
3159 let val = (self.0 >> 0usize) & 0x01;
3160 val != 0
3161 }
3162 #[doc = "Cycle counter"]
3163 #[inline(always)]
3164 pub const fn set_cy(&mut self, val: bool) {
3165 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
3166 }
3167 #[doc = "Instruction retired counter"]
3168 #[must_use]
3169 #[inline(always)]
3170 pub const fn ir(&self) -> bool {
3171 let val = (self.0 >> 2usize) & 0x01;
3172 val != 0
3173 }
3174 #[doc = "Instruction retired counter"]
3175 #[inline(always)]
3176 pub const fn set_ir(&mut self, val: bool) {
3177 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
3178 }
3179 #[doc = "Hardware performance monitor 3 to 31"]
3180 #[must_use]
3181 #[inline(always)]
3182 pub const fn hpm(&self, n: usize) -> bool {
3183 assert!(n < 29usize);
3184 let offs = 3usize + n * 1usize;
3185 let val = (self.0 >> offs) & 0x01;
3186 val != 0
3187 }
3188 #[doc = "Hardware performance monitor 3 to 31"]
3189 #[inline(always)]
3190 pub const fn set_hpm(&mut self, n: usize, val: bool) {
3191 assert!(n < 29usize);
3192 let offs = 3usize + n * 1usize;
3193 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
3194 }
3195 }
3196 impl Default for McounterCommon {
3197 #[inline(always)]
3198 fn default() -> McounterCommon {
3199 McounterCommon(0)
3200 }
3201 }
3202 impl core::fmt::Debug for McounterCommon {
3203 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
3204 f.debug_struct("McounterCommon")
3205 .field("cy", &self.cy())
3206 .field("ir", &self.ir())
3207 .field("hpm[0]", &self.hpm(0usize))
3208 .field("hpm[1]", &self.hpm(1usize))
3209 .field("hpm[2]", &self.hpm(2usize))
3210 .field("hpm[3]", &self.hpm(3usize))
3211 .field("hpm[4]", &self.hpm(4usize))
3212 .field("hpm[5]", &self.hpm(5usize))
3213 .field("hpm[6]", &self.hpm(6usize))
3214 .field("hpm[7]", &self.hpm(7usize))
3215 .field("hpm[8]", &self.hpm(8usize))
3216 .field("hpm[9]", &self.hpm(9usize))
3217 .field("hpm[10]", &self.hpm(10usize))
3218 .field("hpm[11]", &self.hpm(11usize))
3219 .field("hpm[12]", &self.hpm(12usize))
3220 .field("hpm[13]", &self.hpm(13usize))
3221 .field("hpm[14]", &self.hpm(14usize))
3222 .field("hpm[15]", &self.hpm(15usize))
3223 .field("hpm[16]", &self.hpm(16usize))
3224 .field("hpm[17]", &self.hpm(17usize))
3225 .field("hpm[18]", &self.hpm(18usize))
3226 .field("hpm[19]", &self.hpm(19usize))
3227 .field("hpm[20]", &self.hpm(20usize))
3228 .field("hpm[21]", &self.hpm(21usize))
3229 .field("hpm[22]", &self.hpm(22usize))
3230 .field("hpm[23]", &self.hpm(23usize))
3231 .field("hpm[24]", &self.hpm(24usize))
3232 .field("hpm[25]", &self.hpm(25usize))
3233 .field("hpm[26]", &self.hpm(26usize))
3234 .field("hpm[27]", &self.hpm(27usize))
3235 .field("hpm[28]", &self.hpm(28usize))
3236 .finish()
3237 }
3238 }
3239 #[cfg(feature = "defmt")]
3240 impl defmt::Format for McounterCommon {
3241 fn format(&self, f: defmt::Formatter) {
3242 defmt::write!(
3243 f,
3244 "McounterCommon {{ cy: {=bool:?}, ir: {=bool:?}, hpm[0]: {=bool:?}, hpm[1]: {=bool:?}, hpm[2]: {=bool:?}, hpm[3]: {=bool:?}, hpm[4]: {=bool:?}, hpm[5]: {=bool:?}, hpm[6]: {=bool:?}, hpm[7]: {=bool:?}, hpm[8]: {=bool:?}, hpm[9]: {=bool:?}, hpm[10]: {=bool:?}, hpm[11]: {=bool:?}, hpm[12]: {=bool:?}, hpm[13]: {=bool:?}, hpm[14]: {=bool:?}, hpm[15]: {=bool:?}, hpm[16]: {=bool:?}, hpm[17]: {=bool:?}, hpm[18]: {=bool:?}, hpm[19]: {=bool:?}, hpm[20]: {=bool:?}, hpm[21]: {=bool:?}, hpm[22]: {=bool:?}, hpm[23]: {=bool:?}, hpm[24]: {=bool:?}, hpm[25]: {=bool:?}, hpm[26]: {=bool:?}, hpm[27]: {=bool:?}, hpm[28]: {=bool:?} }}",
3245 self.cy(),
3246 self.ir(),
3247 self.hpm(0usize),
3248 self.hpm(1usize),
3249 self.hpm(2usize),
3250 self.hpm(3usize),
3251 self.hpm(4usize),
3252 self.hpm(5usize),
3253 self.hpm(6usize),
3254 self.hpm(7usize),
3255 self.hpm(8usize),
3256 self.hpm(9usize),
3257 self.hpm(10usize),
3258 self.hpm(11usize),
3259 self.hpm(12usize),
3260 self.hpm(13usize),
3261 self.hpm(14usize),
3262 self.hpm(15usize),
3263 self.hpm(16usize),
3264 self.hpm(17usize),
3265 self.hpm(18usize),
3266 self.hpm(19usize),
3267 self.hpm(20usize),
3268 self.hpm(21usize),
3269 self.hpm(22usize),
3270 self.hpm(23usize),
3271 self.hpm(24usize),
3272 self.hpm(25usize),
3273 self.hpm(26usize),
3274 self.hpm(27usize),
3275 self.hpm(28usize)
3276 )
3277 }
3278 }
3279 #[inline(always)]
3280 unsafe fn _read() -> usize {
3281 let r: usize;
3282 unsafe {
3283 core :: arch :: asm ! ("csrrs {0}, 0x7d2, x0" , out (reg) r);
3284 }
3285 r
3286 }
3287 #[inline(always)]
3288 unsafe fn _write(bits: usize) {
3289 unsafe {
3290 core :: arch :: asm ! ("csrrw x0, 0x7d2, {0}" , in (reg) bits);
3291 }
3292 }
3293 #[inline(always)]
3294 unsafe fn _set(bits: usize) {
3295 unsafe {
3296 core :: arch :: asm ! ("csrrs x0, 0x7d2, {0}" , in (reg) bits);
3297 }
3298 }
3299 #[inline(always)]
3300 unsafe fn _clear(bits: usize) {
3301 unsafe {
3302 core :: arch :: asm ! ("csrrc x0, 0x7d2, {0}" , in (reg) bits);
3303 }
3304 }
3305 #[doc = r" Read the CSR value."]
3306 #[inline]
3307 pub fn read() -> McounterCommon {
3308 unsafe { McounterCommon(_read() as u32) }
3309 }
3310 #[doc = r" Write the CSR value."]
3311 #[inline]
3312 pub unsafe fn write(val: McounterCommon) {
3313 unsafe {
3314 _write(val.0 as usize);
3315 }
3316 }
3317 #[doc = r" Read-modify-write the CSR."]
3318 #[inline]
3319 pub unsafe fn modify<R>(f: impl FnOnce(&mut McounterCommon) -> R) -> R {
3320 let mut val = read();
3321 let res = f(&mut val);
3322 unsafe {
3323 write(val);
3324 }
3325 res
3326 }
3327 #[doc = "Cycle counter"]
3328 #[inline]
3329 pub unsafe fn set_cy() {
3330 unsafe {
3331 _set(1usize);
3332 }
3333 }
3334 #[doc = "Cycle counter"]
3335 #[inline]
3336 pub unsafe fn clear_cy() {
3337 unsafe {
3338 _clear(1usize);
3339 }
3340 }
3341 #[doc = "Instruction retired counter"]
3342 #[inline]
3343 pub unsafe fn set_ir() {
3344 unsafe {
3345 _set(4usize);
3346 }
3347 }
3348 #[doc = "Instruction retired counter"]
3349 #[inline]
3350 pub unsafe fn clear_ir() {
3351 unsafe {
3352 _clear(4usize);
3353 }
3354 }
3355}
3356#[doc = "Counter not counting in U-mode"]
3357pub mod mcountermask_u {
3358 #[doc = "Machine Counter Fields"]
3359 #[repr(transparent)]
3360 #[derive(Copy, Clone, Eq, PartialEq)]
3361 pub struct McounterCommon(pub u32);
3362 impl McounterCommon {
3363 #[doc = "Cycle counter"]
3364 #[must_use]
3365 #[inline(always)]
3366 pub const fn cy(&self) -> bool {
3367 let val = (self.0 >> 0usize) & 0x01;
3368 val != 0
3369 }
3370 #[doc = "Cycle counter"]
3371 #[inline(always)]
3372 pub const fn set_cy(&mut self, val: bool) {
3373 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
3374 }
3375 #[doc = "Instruction retired counter"]
3376 #[must_use]
3377 #[inline(always)]
3378 pub const fn ir(&self) -> bool {
3379 let val = (self.0 >> 2usize) & 0x01;
3380 val != 0
3381 }
3382 #[doc = "Instruction retired counter"]
3383 #[inline(always)]
3384 pub const fn set_ir(&mut self, val: bool) {
3385 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
3386 }
3387 #[doc = "Hardware performance monitor 3 to 31"]
3388 #[must_use]
3389 #[inline(always)]
3390 pub const fn hpm(&self, n: usize) -> bool {
3391 assert!(n < 29usize);
3392 let offs = 3usize + n * 1usize;
3393 let val = (self.0 >> offs) & 0x01;
3394 val != 0
3395 }
3396 #[doc = "Hardware performance monitor 3 to 31"]
3397 #[inline(always)]
3398 pub const fn set_hpm(&mut self, n: usize, val: bool) {
3399 assert!(n < 29usize);
3400 let offs = 3usize + n * 1usize;
3401 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
3402 }
3403 }
3404 impl Default for McounterCommon {
3405 #[inline(always)]
3406 fn default() -> McounterCommon {
3407 McounterCommon(0)
3408 }
3409 }
3410 impl core::fmt::Debug for McounterCommon {
3411 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
3412 f.debug_struct("McounterCommon")
3413 .field("cy", &self.cy())
3414 .field("ir", &self.ir())
3415 .field("hpm[0]", &self.hpm(0usize))
3416 .field("hpm[1]", &self.hpm(1usize))
3417 .field("hpm[2]", &self.hpm(2usize))
3418 .field("hpm[3]", &self.hpm(3usize))
3419 .field("hpm[4]", &self.hpm(4usize))
3420 .field("hpm[5]", &self.hpm(5usize))
3421 .field("hpm[6]", &self.hpm(6usize))
3422 .field("hpm[7]", &self.hpm(7usize))
3423 .field("hpm[8]", &self.hpm(8usize))
3424 .field("hpm[9]", &self.hpm(9usize))
3425 .field("hpm[10]", &self.hpm(10usize))
3426 .field("hpm[11]", &self.hpm(11usize))
3427 .field("hpm[12]", &self.hpm(12usize))
3428 .field("hpm[13]", &self.hpm(13usize))
3429 .field("hpm[14]", &self.hpm(14usize))
3430 .field("hpm[15]", &self.hpm(15usize))
3431 .field("hpm[16]", &self.hpm(16usize))
3432 .field("hpm[17]", &self.hpm(17usize))
3433 .field("hpm[18]", &self.hpm(18usize))
3434 .field("hpm[19]", &self.hpm(19usize))
3435 .field("hpm[20]", &self.hpm(20usize))
3436 .field("hpm[21]", &self.hpm(21usize))
3437 .field("hpm[22]", &self.hpm(22usize))
3438 .field("hpm[23]", &self.hpm(23usize))
3439 .field("hpm[24]", &self.hpm(24usize))
3440 .field("hpm[25]", &self.hpm(25usize))
3441 .field("hpm[26]", &self.hpm(26usize))
3442 .field("hpm[27]", &self.hpm(27usize))
3443 .field("hpm[28]", &self.hpm(28usize))
3444 .finish()
3445 }
3446 }
3447 #[cfg(feature = "defmt")]
3448 impl defmt::Format for McounterCommon {
3449 fn format(&self, f: defmt::Formatter) {
3450 defmt::write!(
3451 f,
3452 "McounterCommon {{ cy: {=bool:?}, ir: {=bool:?}, hpm[0]: {=bool:?}, hpm[1]: {=bool:?}, hpm[2]: {=bool:?}, hpm[3]: {=bool:?}, hpm[4]: {=bool:?}, hpm[5]: {=bool:?}, hpm[6]: {=bool:?}, hpm[7]: {=bool:?}, hpm[8]: {=bool:?}, hpm[9]: {=bool:?}, hpm[10]: {=bool:?}, hpm[11]: {=bool:?}, hpm[12]: {=bool:?}, hpm[13]: {=bool:?}, hpm[14]: {=bool:?}, hpm[15]: {=bool:?}, hpm[16]: {=bool:?}, hpm[17]: {=bool:?}, hpm[18]: {=bool:?}, hpm[19]: {=bool:?}, hpm[20]: {=bool:?}, hpm[21]: {=bool:?}, hpm[22]: {=bool:?}, hpm[23]: {=bool:?}, hpm[24]: {=bool:?}, hpm[25]: {=bool:?}, hpm[26]: {=bool:?}, hpm[27]: {=bool:?}, hpm[28]: {=bool:?} }}",
3453 self.cy(),
3454 self.ir(),
3455 self.hpm(0usize),
3456 self.hpm(1usize),
3457 self.hpm(2usize),
3458 self.hpm(3usize),
3459 self.hpm(4usize),
3460 self.hpm(5usize),
3461 self.hpm(6usize),
3462 self.hpm(7usize),
3463 self.hpm(8usize),
3464 self.hpm(9usize),
3465 self.hpm(10usize),
3466 self.hpm(11usize),
3467 self.hpm(12usize),
3468 self.hpm(13usize),
3469 self.hpm(14usize),
3470 self.hpm(15usize),
3471 self.hpm(16usize),
3472 self.hpm(17usize),
3473 self.hpm(18usize),
3474 self.hpm(19usize),
3475 self.hpm(20usize),
3476 self.hpm(21usize),
3477 self.hpm(22usize),
3478 self.hpm(23usize),
3479 self.hpm(24usize),
3480 self.hpm(25usize),
3481 self.hpm(26usize),
3482 self.hpm(27usize),
3483 self.hpm(28usize)
3484 )
3485 }
3486 }
3487 #[inline(always)]
3488 unsafe fn _read() -> usize {
3489 let r: usize;
3490 unsafe {
3491 core :: arch :: asm ! ("csrrs {0}, 0x7d3, x0" , out (reg) r);
3492 }
3493 r
3494 }
3495 #[inline(always)]
3496 unsafe fn _write(bits: usize) {
3497 unsafe {
3498 core :: arch :: asm ! ("csrrw x0, 0x7d3, {0}" , in (reg) bits);
3499 }
3500 }
3501 #[inline(always)]
3502 unsafe fn _set(bits: usize) {
3503 unsafe {
3504 core :: arch :: asm ! ("csrrs x0, 0x7d3, {0}" , in (reg) bits);
3505 }
3506 }
3507 #[inline(always)]
3508 unsafe fn _clear(bits: usize) {
3509 unsafe {
3510 core :: arch :: asm ! ("csrrc x0, 0x7d3, {0}" , in (reg) bits);
3511 }
3512 }
3513 #[doc = r" Read the CSR value."]
3514 #[inline]
3515 pub fn read() -> McounterCommon {
3516 unsafe { McounterCommon(_read() as u32) }
3517 }
3518 #[doc = r" Write the CSR value."]
3519 #[inline]
3520 pub unsafe fn write(val: McounterCommon) {
3521 unsafe {
3522 _write(val.0 as usize);
3523 }
3524 }
3525 #[doc = r" Read-modify-write the CSR."]
3526 #[inline]
3527 pub unsafe fn modify<R>(f: impl FnOnce(&mut McounterCommon) -> R) -> R {
3528 let mut val = read();
3529 let res = f(&mut val);
3530 unsafe {
3531 write(val);
3532 }
3533 res
3534 }
3535 #[doc = "Cycle counter"]
3536 #[inline]
3537 pub unsafe fn set_cy() {
3538 unsafe {
3539 _set(1usize);
3540 }
3541 }
3542 #[doc = "Cycle counter"]
3543 #[inline]
3544 pub unsafe fn clear_cy() {
3545 unsafe {
3546 _clear(1usize);
3547 }
3548 }
3549 #[doc = "Instruction retired counter"]
3550 #[inline]
3551 pub unsafe fn set_ir() {
3552 unsafe {
3553 _set(4usize);
3554 }
3555 }
3556 #[doc = "Instruction retired counter"]
3557 #[inline]
3558 pub unsafe fn clear_ir() {
3559 unsafe {
3560 _clear(4usize);
3561 }
3562 }
3563}
3564#[doc = "Counter overflow status"]
3565pub mod mcounterovf {
3566 #[doc = "Machine Counter Fields"]
3567 #[repr(transparent)]
3568 #[derive(Copy, Clone, Eq, PartialEq)]
3569 pub struct McounterCommon(pub u32);
3570 impl McounterCommon {
3571 #[doc = "Cycle counter"]
3572 #[must_use]
3573 #[inline(always)]
3574 pub const fn cy(&self) -> bool {
3575 let val = (self.0 >> 0usize) & 0x01;
3576 val != 0
3577 }
3578 #[doc = "Cycle counter"]
3579 #[inline(always)]
3580 pub const fn set_cy(&mut self, val: bool) {
3581 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
3582 }
3583 #[doc = "Instruction retired counter"]
3584 #[must_use]
3585 #[inline(always)]
3586 pub const fn ir(&self) -> bool {
3587 let val = (self.0 >> 2usize) & 0x01;
3588 val != 0
3589 }
3590 #[doc = "Instruction retired counter"]
3591 #[inline(always)]
3592 pub const fn set_ir(&mut self, val: bool) {
3593 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
3594 }
3595 #[doc = "Hardware performance monitor 3 to 31"]
3596 #[must_use]
3597 #[inline(always)]
3598 pub const fn hpm(&self, n: usize) -> bool {
3599 assert!(n < 29usize);
3600 let offs = 3usize + n * 1usize;
3601 let val = (self.0 >> offs) & 0x01;
3602 val != 0
3603 }
3604 #[doc = "Hardware performance monitor 3 to 31"]
3605 #[inline(always)]
3606 pub const fn set_hpm(&mut self, n: usize, val: bool) {
3607 assert!(n < 29usize);
3608 let offs = 3usize + n * 1usize;
3609 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
3610 }
3611 }
3612 impl Default for McounterCommon {
3613 #[inline(always)]
3614 fn default() -> McounterCommon {
3615 McounterCommon(0)
3616 }
3617 }
3618 impl core::fmt::Debug for McounterCommon {
3619 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
3620 f.debug_struct("McounterCommon")
3621 .field("cy", &self.cy())
3622 .field("ir", &self.ir())
3623 .field("hpm[0]", &self.hpm(0usize))
3624 .field("hpm[1]", &self.hpm(1usize))
3625 .field("hpm[2]", &self.hpm(2usize))
3626 .field("hpm[3]", &self.hpm(3usize))
3627 .field("hpm[4]", &self.hpm(4usize))
3628 .field("hpm[5]", &self.hpm(5usize))
3629 .field("hpm[6]", &self.hpm(6usize))
3630 .field("hpm[7]", &self.hpm(7usize))
3631 .field("hpm[8]", &self.hpm(8usize))
3632 .field("hpm[9]", &self.hpm(9usize))
3633 .field("hpm[10]", &self.hpm(10usize))
3634 .field("hpm[11]", &self.hpm(11usize))
3635 .field("hpm[12]", &self.hpm(12usize))
3636 .field("hpm[13]", &self.hpm(13usize))
3637 .field("hpm[14]", &self.hpm(14usize))
3638 .field("hpm[15]", &self.hpm(15usize))
3639 .field("hpm[16]", &self.hpm(16usize))
3640 .field("hpm[17]", &self.hpm(17usize))
3641 .field("hpm[18]", &self.hpm(18usize))
3642 .field("hpm[19]", &self.hpm(19usize))
3643 .field("hpm[20]", &self.hpm(20usize))
3644 .field("hpm[21]", &self.hpm(21usize))
3645 .field("hpm[22]", &self.hpm(22usize))
3646 .field("hpm[23]", &self.hpm(23usize))
3647 .field("hpm[24]", &self.hpm(24usize))
3648 .field("hpm[25]", &self.hpm(25usize))
3649 .field("hpm[26]", &self.hpm(26usize))
3650 .field("hpm[27]", &self.hpm(27usize))
3651 .field("hpm[28]", &self.hpm(28usize))
3652 .finish()
3653 }
3654 }
3655 #[cfg(feature = "defmt")]
3656 impl defmt::Format for McounterCommon {
3657 fn format(&self, f: defmt::Formatter) {
3658 defmt::write!(
3659 f,
3660 "McounterCommon {{ cy: {=bool:?}, ir: {=bool:?}, hpm[0]: {=bool:?}, hpm[1]: {=bool:?}, hpm[2]: {=bool:?}, hpm[3]: {=bool:?}, hpm[4]: {=bool:?}, hpm[5]: {=bool:?}, hpm[6]: {=bool:?}, hpm[7]: {=bool:?}, hpm[8]: {=bool:?}, hpm[9]: {=bool:?}, hpm[10]: {=bool:?}, hpm[11]: {=bool:?}, hpm[12]: {=bool:?}, hpm[13]: {=bool:?}, hpm[14]: {=bool:?}, hpm[15]: {=bool:?}, hpm[16]: {=bool:?}, hpm[17]: {=bool:?}, hpm[18]: {=bool:?}, hpm[19]: {=bool:?}, hpm[20]: {=bool:?}, hpm[21]: {=bool:?}, hpm[22]: {=bool:?}, hpm[23]: {=bool:?}, hpm[24]: {=bool:?}, hpm[25]: {=bool:?}, hpm[26]: {=bool:?}, hpm[27]: {=bool:?}, hpm[28]: {=bool:?} }}",
3661 self.cy(),
3662 self.ir(),
3663 self.hpm(0usize),
3664 self.hpm(1usize),
3665 self.hpm(2usize),
3666 self.hpm(3usize),
3667 self.hpm(4usize),
3668 self.hpm(5usize),
3669 self.hpm(6usize),
3670 self.hpm(7usize),
3671 self.hpm(8usize),
3672 self.hpm(9usize),
3673 self.hpm(10usize),
3674 self.hpm(11usize),
3675 self.hpm(12usize),
3676 self.hpm(13usize),
3677 self.hpm(14usize),
3678 self.hpm(15usize),
3679 self.hpm(16usize),
3680 self.hpm(17usize),
3681 self.hpm(18usize),
3682 self.hpm(19usize),
3683 self.hpm(20usize),
3684 self.hpm(21usize),
3685 self.hpm(22usize),
3686 self.hpm(23usize),
3687 self.hpm(24usize),
3688 self.hpm(25usize),
3689 self.hpm(26usize),
3690 self.hpm(27usize),
3691 self.hpm(28usize)
3692 )
3693 }
3694 }
3695 #[inline(always)]
3696 unsafe fn _read() -> usize {
3697 let r: usize;
3698 unsafe {
3699 core :: arch :: asm ! ("csrrs {0}, 0x7d4, x0" , out (reg) r);
3700 }
3701 r
3702 }
3703 #[inline(always)]
3704 unsafe fn _write(bits: usize) {
3705 unsafe {
3706 core :: arch :: asm ! ("csrrw x0, 0x7d4, {0}" , in (reg) bits);
3707 }
3708 }
3709 #[inline(always)]
3710 unsafe fn _set(bits: usize) {
3711 unsafe {
3712 core :: arch :: asm ! ("csrrs x0, 0x7d4, {0}" , in (reg) bits);
3713 }
3714 }
3715 #[inline(always)]
3716 unsafe fn _clear(bits: usize) {
3717 unsafe {
3718 core :: arch :: asm ! ("csrrc x0, 0x7d4, {0}" , in (reg) bits);
3719 }
3720 }
3721 #[doc = r" Read the CSR value."]
3722 #[inline]
3723 pub fn read() -> McounterCommon {
3724 unsafe { McounterCommon(_read() as u32) }
3725 }
3726 #[doc = r" Write the CSR value."]
3727 #[inline]
3728 pub unsafe fn write(val: McounterCommon) {
3729 unsafe {
3730 _write(val.0 as usize);
3731 }
3732 }
3733 #[doc = r" Read-modify-write the CSR."]
3734 #[inline]
3735 pub unsafe fn modify<R>(f: impl FnOnce(&mut McounterCommon) -> R) -> R {
3736 let mut val = read();
3737 let res = f(&mut val);
3738 unsafe {
3739 write(val);
3740 }
3741 res
3742 }
3743 #[doc = "Cycle counter"]
3744 #[inline]
3745 pub unsafe fn set_cy() {
3746 unsafe {
3747 _set(1usize);
3748 }
3749 }
3750 #[doc = "Cycle counter"]
3751 #[inline]
3752 pub unsafe fn clear_cy() {
3753 unsafe {
3754 _clear(1usize);
3755 }
3756 }
3757 #[doc = "Instruction retired counter"]
3758 #[inline]
3759 pub unsafe fn set_ir() {
3760 unsafe {
3761 _set(4usize);
3762 }
3763 }
3764 #[doc = "Instruction retired counter"]
3765 #[inline]
3766 pub unsafe fn clear_ir() {
3767 unsafe {
3768 _clear(4usize);
3769 }
3770 }
3771}
3772#[doc = "Supervisor local interrupt delegation"]
3773pub mod mslideleg {
3774 #[doc = "Machine Supervisor Local Interrupt Delegation Register"]
3775 #[repr(transparent)]
3776 #[derive(Copy, Clone, Eq, PartialEq)]
3777 pub struct Mslideleg(pub u32);
3778 impl Mslideleg {
3779 #[must_use]
3780 #[inline(always)]
3781 pub const fn imecci(&self) -> bool {
3782 let val = (self.0 >> 16usize) & 0x01;
3783 val != 0
3784 }
3785 #[inline(always)]
3786 pub const fn set_imecci(&mut self, val: bool) {
3787 self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
3788 }
3789 #[must_use]
3790 #[inline(always)]
3791 pub const fn bwei(&self) -> bool {
3792 let val = (self.0 >> 17usize) & 0x01;
3793 val != 0
3794 }
3795 #[inline(always)]
3796 pub const fn set_bwei(&mut self, val: bool) {
3797 self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
3798 }
3799 #[must_use]
3800 #[inline(always)]
3801 pub const fn pmovi(&self) -> bool {
3802 let val = (self.0 >> 18usize) & 0x01;
3803 val != 0
3804 }
3805 #[inline(always)]
3806 pub const fn set_pmovi(&mut self, val: bool) {
3807 self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
3808 }
3809 #[must_use]
3810 #[inline(always)]
3811 pub const fn imeccdmr(&self) -> bool {
3812 let val = (self.0 >> 19usize) & 0x01;
3813 val != 0
3814 }
3815 #[inline(always)]
3816 pub const fn set_imeccdmr(&mut self, val: bool) {
3817 self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
3818 }
3819 #[must_use]
3820 #[inline(always)]
3821 pub const fn aceerr(&self) -> bool {
3822 let val = (self.0 >> 24usize) & 0x01;
3823 val != 0
3824 }
3825 #[inline(always)]
3826 pub const fn set_aceerr(&mut self, val: bool) {
3827 self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
3828 }
3829 }
3830 impl Default for Mslideleg {
3831 #[inline(always)]
3832 fn default() -> Mslideleg {
3833 Mslideleg(0)
3834 }
3835 }
3836 impl core::fmt::Debug for Mslideleg {
3837 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
3838 f.debug_struct("Mslideleg")
3839 .field("imecci", &self.imecci())
3840 .field("bwei", &self.bwei())
3841 .field("pmovi", &self.pmovi())
3842 .field("imeccdmr", &self.imeccdmr())
3843 .field("aceerr", &self.aceerr())
3844 .finish()
3845 }
3846 }
3847 #[cfg(feature = "defmt")]
3848 impl defmt::Format for Mslideleg {
3849 fn format(&self, f: defmt::Formatter) {
3850 defmt::write!(
3851 f,
3852 "Mslideleg {{ imecci: {=bool:?}, bwei: {=bool:?}, pmovi: {=bool:?}, imeccdmr: {=bool:?}, aceerr: {=bool:?} }}",
3853 self.imecci(),
3854 self.bwei(),
3855 self.pmovi(),
3856 self.imeccdmr(),
3857 self.aceerr()
3858 )
3859 }
3860 }
3861 #[inline(always)]
3862 unsafe fn _read() -> usize {
3863 let r: usize;
3864 unsafe {
3865 core :: arch :: asm ! ("csrrs {0}, 0x7d5, x0" , out (reg) r);
3866 }
3867 r
3868 }
3869 #[inline(always)]
3870 unsafe fn _write(bits: usize) {
3871 unsafe {
3872 core :: arch :: asm ! ("csrrw x0, 0x7d5, {0}" , in (reg) bits);
3873 }
3874 }
3875 #[inline(always)]
3876 unsafe fn _set(bits: usize) {
3877 unsafe {
3878 core :: arch :: asm ! ("csrrs x0, 0x7d5, {0}" , in (reg) bits);
3879 }
3880 }
3881 #[inline(always)]
3882 unsafe fn _clear(bits: usize) {
3883 unsafe {
3884 core :: arch :: asm ! ("csrrc x0, 0x7d5, {0}" , in (reg) bits);
3885 }
3886 }
3887 #[doc = r" Read the CSR value."]
3888 #[inline]
3889 pub fn read() -> Mslideleg {
3890 unsafe { Mslideleg(_read() as u32) }
3891 }
3892 #[doc = r" Write the CSR value."]
3893 #[inline]
3894 pub unsafe fn write(val: Mslideleg) {
3895 unsafe {
3896 _write(val.0 as usize);
3897 }
3898 }
3899 #[doc = r" Read-modify-write the CSR."]
3900 #[inline]
3901 pub unsafe fn modify<R>(f: impl FnOnce(&mut Mslideleg) -> R) -> R {
3902 let mut val = read();
3903 let res = f(&mut val);
3904 unsafe {
3905 write(val);
3906 }
3907 res
3908 }
3909 #[inline]
3910 pub unsafe fn set_imecci() {
3911 unsafe {
3912 _set(65536usize);
3913 }
3914 }
3915 #[inline]
3916 pub unsafe fn clear_imecci() {
3917 unsafe {
3918 _clear(65536usize);
3919 }
3920 }
3921 #[inline]
3922 pub unsafe fn set_bwei() {
3923 unsafe {
3924 _set(131072usize);
3925 }
3926 }
3927 #[inline]
3928 pub unsafe fn clear_bwei() {
3929 unsafe {
3930 _clear(131072usize);
3931 }
3932 }
3933 #[inline]
3934 pub unsafe fn set_pmovi() {
3935 unsafe {
3936 _set(262144usize);
3937 }
3938 }
3939 #[inline]
3940 pub unsafe fn clear_pmovi() {
3941 unsafe {
3942 _clear(262144usize);
3943 }
3944 }
3945 #[inline]
3946 pub unsafe fn set_imeccdmr() {
3947 unsafe {
3948 _set(524288usize);
3949 }
3950 }
3951 #[inline]
3952 pub unsafe fn clear_imeccdmr() {
3953 unsafe {
3954 _clear(524288usize);
3955 }
3956 }
3957 #[inline]
3958 pub unsafe fn set_aceerr() {
3959 unsafe {
3960 _set(16777216usize);
3961 }
3962 }
3963 #[inline]
3964 pub unsafe fn clear_aceerr() {
3965 unsafe {
3966 _clear(16777216usize);
3967 }
3968 }
3969}
3970#[doc = "Status save register (level 1 & level 2)"]
3971pub mod msavestatus {
3972 #[doc = "Machine Status Save Register"]
3973 #[repr(transparent)]
3974 #[derive(Copy, Clone, Eq, PartialEq)]
3975 pub struct Msavestatus(pub u32);
3976 impl Msavestatus {
3977 #[must_use]
3978 #[inline(always)]
3979 pub const fn mpie(&self) -> bool {
3980 let val = (self.0 >> 0usize) & 0x01;
3981 val != 0
3982 }
3983 #[inline(always)]
3984 pub const fn set_mpie(&mut self, val: bool) {
3985 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
3986 }
3987 #[must_use]
3988 #[inline(always)]
3989 pub const fn mpp(&self) -> u8 {
3990 let val = (self.0 >> 1usize) & 0x03;
3991 val as u8
3992 }
3993 #[inline(always)]
3994 pub const fn set_mpp(&mut self, val: u8) {
3995 self.0 = (self.0 & !(0x03 << 1usize)) | (((val as u32) & 0x03) << 1usize);
3996 }
3997 #[must_use]
3998 #[inline(always)]
3999 pub const fn ppft_en(&self) -> bool {
4000 let val = (self.0 >> 3usize) & 0x01;
4001 val != 0
4002 }
4003 #[inline(always)]
4004 pub const fn set_ppft_en(&mut self, val: bool) {
4005 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
4006 }
4007 #[must_use]
4008 #[inline(always)]
4009 pub const fn pime(&self) -> bool {
4010 let val = (self.0 >> 4usize) & 0x01;
4011 val != 0
4012 }
4013 #[inline(always)]
4014 pub const fn set_pime(&mut self, val: bool) {
4015 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
4016 }
4017 #[must_use]
4018 #[inline(always)]
4019 pub const fn pdme(&self) -> bool {
4020 let val = (self.0 >> 5usize) & 0x01;
4021 val != 0
4022 }
4023 #[inline(always)]
4024 pub const fn set_pdme(&mut self, val: bool) {
4025 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
4026 }
4027 #[must_use]
4028 #[inline(always)]
4029 pub const fn ptyp(&self) -> u8 {
4030 let val = (self.0 >> 6usize) & 0x03;
4031 val as u8
4032 }
4033 #[inline(always)]
4034 pub const fn set_ptyp(&mut self, val: u8) {
4035 self.0 = (self.0 & !(0x03 << 6usize)) | (((val as u32) & 0x03) << 6usize);
4036 }
4037 }
4038 impl Default for Msavestatus {
4039 #[inline(always)]
4040 fn default() -> Msavestatus {
4041 Msavestatus(0)
4042 }
4043 }
4044 impl core::fmt::Debug for Msavestatus {
4045 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
4046 f.debug_struct("Msavestatus")
4047 .field("mpie", &self.mpie())
4048 .field("mpp", &self.mpp())
4049 .field("ppft_en", &self.ppft_en())
4050 .field("pime", &self.pime())
4051 .field("pdme", &self.pdme())
4052 .field("ptyp", &self.ptyp())
4053 .finish()
4054 }
4055 }
4056 #[cfg(feature = "defmt")]
4057 impl defmt::Format for Msavestatus {
4058 fn format(&self, f: defmt::Formatter) {
4059 defmt::write!(
4060 f,
4061 "Msavestatus {{ mpie: {=bool:?}, mpp: {=u8:?}, ppft_en: {=bool:?}, pime: {=bool:?}, pdme: {=bool:?}, ptyp: {=u8:?} }}",
4062 self.mpie(),
4063 self.mpp(),
4064 self.ppft_en(),
4065 self.pime(),
4066 self.pdme(),
4067 self.ptyp()
4068 )
4069 }
4070 }
4071 #[inline(always)]
4072 unsafe fn _read() -> usize {
4073 let r: usize;
4074 unsafe {
4075 core :: arch :: asm ! ("csrrs {0}, 0x7d6, x0" , out (reg) r);
4076 }
4077 r
4078 }
4079 #[inline(always)]
4080 unsafe fn _write(bits: usize) {
4081 unsafe {
4082 core :: arch :: asm ! ("csrrw x0, 0x7d6, {0}" , in (reg) bits);
4083 }
4084 }
4085 #[inline(always)]
4086 unsafe fn _set(bits: usize) {
4087 unsafe {
4088 core :: arch :: asm ! ("csrrs x0, 0x7d6, {0}" , in (reg) bits);
4089 }
4090 }
4091 #[inline(always)]
4092 unsafe fn _clear(bits: usize) {
4093 unsafe {
4094 core :: arch :: asm ! ("csrrc x0, 0x7d6, {0}" , in (reg) bits);
4095 }
4096 }
4097 #[doc = r" Read the CSR value."]
4098 #[inline]
4099 pub fn read() -> Msavestatus {
4100 unsafe { Msavestatus(_read() as u32) }
4101 }
4102 #[doc = r" Write the CSR value."]
4103 #[inline]
4104 pub unsafe fn write(val: Msavestatus) {
4105 unsafe {
4106 _write(val.0 as usize);
4107 }
4108 }
4109 #[doc = r" Read-modify-write the CSR."]
4110 #[inline]
4111 pub unsafe fn modify<R>(f: impl FnOnce(&mut Msavestatus) -> R) -> R {
4112 let mut val = read();
4113 let res = f(&mut val);
4114 unsafe {
4115 write(val);
4116 }
4117 res
4118 }
4119 #[inline]
4120 pub unsafe fn set_mpie() {
4121 unsafe {
4122 _set(1usize);
4123 }
4124 }
4125 #[inline]
4126 pub unsafe fn clear_mpie() {
4127 unsafe {
4128 _clear(1usize);
4129 }
4130 }
4131 #[inline]
4132 pub unsafe fn set_mpp(val: u8) {
4133 let mut bits = unsafe { _read() };
4134 bits &= !(3usize << 1usize);
4135 bits |= (val as usize & 3usize) << 1usize;
4136 unsafe {
4137 _write(bits);
4138 }
4139 }
4140 #[inline]
4141 pub unsafe fn set_ppft_en() {
4142 unsafe {
4143 _set(8usize);
4144 }
4145 }
4146 #[inline]
4147 pub unsafe fn clear_ppft_en() {
4148 unsafe {
4149 _clear(8usize);
4150 }
4151 }
4152 #[inline]
4153 pub unsafe fn set_pime() {
4154 unsafe {
4155 _set(16usize);
4156 }
4157 }
4158 #[inline]
4159 pub unsafe fn clear_pime() {
4160 unsafe {
4161 _clear(16usize);
4162 }
4163 }
4164 #[inline]
4165 pub unsafe fn set_pdme() {
4166 unsafe {
4167 _set(32usize);
4168 }
4169 }
4170 #[inline]
4171 pub unsafe fn clear_pdme() {
4172 unsafe {
4173 _clear(32usize);
4174 }
4175 }
4176 #[inline]
4177 pub unsafe fn set_ptyp(val: u8) {
4178 let mut bits = unsafe { _read() };
4179 bits &= !(3usize << 6usize);
4180 bits |= (val as usize & 3usize) << 6usize;
4181 unsafe {
4182 _write(bits);
4183 }
4184 }
4185}
4186#[doc = "EPC save register (level 1)"]
4187pub mod msaveepc1 {
4188 #[inline(always)]
4189 unsafe fn _read() -> usize {
4190 let r: usize;
4191 unsafe {
4192 core :: arch :: asm ! ("csrrs {0}, 0x7d7, x0" , out (reg) r);
4193 }
4194 r
4195 }
4196 #[inline(always)]
4197 unsafe fn _write(bits: usize) {
4198 unsafe {
4199 core :: arch :: asm ! ("csrrw x0, 0x7d7, {0}" , in (reg) bits);
4200 }
4201 }
4202 #[inline(always)]
4203 unsafe fn _set(bits: usize) {
4204 unsafe {
4205 core :: arch :: asm ! ("csrrs x0, 0x7d7, {0}" , in (reg) bits);
4206 }
4207 }
4208 #[inline(always)]
4209 unsafe fn _clear(bits: usize) {
4210 unsafe {
4211 core :: arch :: asm ! ("csrrc x0, 0x7d7, {0}" , in (reg) bits);
4212 }
4213 }
4214 #[doc = r" Read the CSR value as raw usize."]
4215 #[inline]
4216 pub fn read() -> usize {
4217 unsafe { _read() }
4218 }
4219 #[doc = r" Write the CSR value as raw usize."]
4220 #[inline]
4221 pub unsafe fn write(val: usize) {
4222 unsafe {
4223 _write(val);
4224 }
4225 }
4226}
4227#[doc = "Exception cause save register (level 1)"]
4228pub mod msavecause1 {
4229 #[inline(always)]
4230 unsafe fn _read() -> usize {
4231 let r: usize;
4232 unsafe {
4233 core :: arch :: asm ! ("csrrs {0}, 0x7d8, x0" , out (reg) r);
4234 }
4235 r
4236 }
4237 #[inline(always)]
4238 unsafe fn _write(bits: usize) {
4239 unsafe {
4240 core :: arch :: asm ! ("csrrw x0, 0x7d8, {0}" , in (reg) bits);
4241 }
4242 }
4243 #[inline(always)]
4244 unsafe fn _set(bits: usize) {
4245 unsafe {
4246 core :: arch :: asm ! ("csrrs x0, 0x7d8, {0}" , in (reg) bits);
4247 }
4248 }
4249 #[inline(always)]
4250 unsafe fn _clear(bits: usize) {
4251 unsafe {
4252 core :: arch :: asm ! ("csrrc x0, 0x7d8, {0}" , in (reg) bits);
4253 }
4254 }
4255 #[doc = r" Read the CSR value as raw usize."]
4256 #[inline]
4257 pub fn read() -> usize {
4258 unsafe { _read() }
4259 }
4260 #[doc = r" Write the CSR value as raw usize."]
4261 #[inline]
4262 pub unsafe fn write(val: usize) {
4263 unsafe {
4264 _write(val);
4265 }
4266 }
4267}
4268#[doc = "EPC save register (level 2)"]
4269pub mod msaveepc2 {
4270 #[inline(always)]
4271 unsafe fn _read() -> usize {
4272 let r: usize;
4273 unsafe {
4274 core :: arch :: asm ! ("csrrs {0}, 0x7d9, x0" , out (reg) r);
4275 }
4276 r
4277 }
4278 #[inline(always)]
4279 unsafe fn _write(bits: usize) {
4280 unsafe {
4281 core :: arch :: asm ! ("csrrw x0, 0x7d9, {0}" , in (reg) bits);
4282 }
4283 }
4284 #[inline(always)]
4285 unsafe fn _set(bits: usize) {
4286 unsafe {
4287 core :: arch :: asm ! ("csrrs x0, 0x7d9, {0}" , in (reg) bits);
4288 }
4289 }
4290 #[inline(always)]
4291 unsafe fn _clear(bits: usize) {
4292 unsafe {
4293 core :: arch :: asm ! ("csrrc x0, 0x7d9, {0}" , in (reg) bits);
4294 }
4295 }
4296 #[doc = r" Read the CSR value as raw usize."]
4297 #[inline]
4298 pub fn read() -> usize {
4299 unsafe { _read() }
4300 }
4301 #[doc = r" Write the CSR value as raw usize."]
4302 #[inline]
4303 pub unsafe fn write(val: usize) {
4304 unsafe {
4305 _write(val);
4306 }
4307 }
4308}
4309#[doc = "Exception cause save register (level 2)"]
4310pub mod msavecause2 {
4311 #[inline(always)]
4312 unsafe fn _read() -> usize {
4313 let r: usize;
4314 unsafe {
4315 core :: arch :: asm ! ("csrrs {0}, 0x7da, x0" , out (reg) r);
4316 }
4317 r
4318 }
4319 #[inline(always)]
4320 unsafe fn _write(bits: usize) {
4321 unsafe {
4322 core :: arch :: asm ! ("csrrw x0, 0x7da, {0}" , in (reg) bits);
4323 }
4324 }
4325 #[inline(always)]
4326 unsafe fn _set(bits: usize) {
4327 unsafe {
4328 core :: arch :: asm ! ("csrrs x0, 0x7da, {0}" , in (reg) bits);
4329 }
4330 }
4331 #[inline(always)]
4332 unsafe fn _clear(bits: usize) {
4333 unsafe {
4334 core :: arch :: asm ! ("csrrc x0, 0x7da, {0}" , in (reg) bits);
4335 }
4336 }
4337 #[doc = r" Read the CSR value as raw usize."]
4338 #[inline]
4339 pub fn read() -> usize {
4340 unsafe { _read() }
4341 }
4342 #[doc = r" Write the CSR value as raw usize."]
4343 #[inline]
4344 pub unsafe fn write(val: usize) {
4345 unsafe {
4346 _write(val);
4347 }
4348 }
4349}
4350#[doc = "Detailed exception cause save (level 1)"]
4351pub mod msavedcause1 {
4352 #[inline(always)]
4353 unsafe fn _read() -> usize {
4354 let r: usize;
4355 unsafe {
4356 core :: arch :: asm ! ("csrrs {0}, 0x7db, x0" , out (reg) r);
4357 }
4358 r
4359 }
4360 #[inline(always)]
4361 unsafe fn _write(bits: usize) {
4362 unsafe {
4363 core :: arch :: asm ! ("csrrw x0, 0x7db, {0}" , in (reg) bits);
4364 }
4365 }
4366 #[inline(always)]
4367 unsafe fn _set(bits: usize) {
4368 unsafe {
4369 core :: arch :: asm ! ("csrrs x0, 0x7db, {0}" , in (reg) bits);
4370 }
4371 }
4372 #[inline(always)]
4373 unsafe fn _clear(bits: usize) {
4374 unsafe {
4375 core :: arch :: asm ! ("csrrc x0, 0x7db, {0}" , in (reg) bits);
4376 }
4377 }
4378 #[doc = r" Read the CSR value as raw usize."]
4379 #[inline]
4380 pub fn read() -> usize {
4381 unsafe { _read() }
4382 }
4383 #[doc = r" Write the CSR value as raw usize."]
4384 #[inline]
4385 pub unsafe fn write(val: usize) {
4386 unsafe {
4387 _write(val);
4388 }
4389 }
4390}
4391#[doc = "Detailed exception cause save (level 2)"]
4392pub mod msavedcause2 {
4393 #[inline(always)]
4394 unsafe fn _read() -> usize {
4395 let r: usize;
4396 unsafe {
4397 core :: arch :: asm ! ("csrrs {0}, 0x7dc, x0" , out (reg) r);
4398 }
4399 r
4400 }
4401 #[inline(always)]
4402 unsafe fn _write(bits: usize) {
4403 unsafe {
4404 core :: arch :: asm ! ("csrrw x0, 0x7dc, {0}" , in (reg) bits);
4405 }
4406 }
4407 #[inline(always)]
4408 unsafe fn _set(bits: usize) {
4409 unsafe {
4410 core :: arch :: asm ! ("csrrs x0, 0x7dc, {0}" , in (reg) bits);
4411 }
4412 }
4413 #[inline(always)]
4414 unsafe fn _clear(bits: usize) {
4415 unsafe {
4416 core :: arch :: asm ! ("csrrc x0, 0x7dc, {0}" , in (reg) bits);
4417 }
4418 }
4419 #[doc = r" Read the CSR value as raw usize."]
4420 #[inline]
4421 pub fn read() -> usize {
4422 unsafe { _read() }
4423 }
4424 #[doc = r" Write the CSR value as raw usize."]
4425 #[inline]
4426 pub unsafe fn write(val: usize) {
4427 unsafe {
4428 _write(val);
4429 }
4430 }
4431}
4432#[doc = "Clock control"]
4433pub mod mclk_ctl {
4434 #[inline(always)]
4435 unsafe fn _read() -> usize {
4436 let r: usize;
4437 unsafe {
4438 core :: arch :: asm ! ("csrrs {0}, 0x7df, x0" , out (reg) r);
4439 }
4440 r
4441 }
4442 #[inline(always)]
4443 unsafe fn _write(bits: usize) {
4444 unsafe {
4445 core :: arch :: asm ! ("csrrw x0, 0x7df, {0}" , in (reg) bits);
4446 }
4447 }
4448 #[inline(always)]
4449 unsafe fn _set(bits: usize) {
4450 unsafe {
4451 core :: arch :: asm ! ("csrrs x0, 0x7df, {0}" , in (reg) bits);
4452 }
4453 }
4454 #[inline(always)]
4455 unsafe fn _clear(bits: usize) {
4456 unsafe {
4457 core :: arch :: asm ! ("csrrc x0, 0x7df, {0}" , in (reg) bits);
4458 }
4459 }
4460 #[doc = r" Read the CSR value as raw usize."]
4461 #[inline]
4462 pub fn read() -> usize {
4463 unsafe { _read() }
4464 }
4465 #[doc = r" Write the CSR value as raw usize."]
4466 #[inline]
4467 pub unsafe fn write(val: usize) {
4468 unsafe {
4469 _write(val);
4470 }
4471 }
4472}
4473#[doc = "Enable exception to enter Halt Mode."]
4474pub mod dexc2dbg {
4475 #[doc = "Exception Redirection Register"]
4476 #[repr(transparent)]
4477 #[derive(Copy, Clone, Eq, PartialEq)]
4478 pub struct Dexc2dbg(pub u32);
4479 impl Dexc2dbg {
4480 #[must_use]
4481 #[inline(always)]
4482 pub const fn iam(&self) -> bool {
4483 let val = (self.0 >> 0usize) & 0x01;
4484 val != 0
4485 }
4486 #[inline(always)]
4487 pub const fn set_iam(&mut self, val: bool) {
4488 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
4489 }
4490 #[must_use]
4491 #[inline(always)]
4492 pub const fn iaf(&self) -> bool {
4493 let val = (self.0 >> 1usize) & 0x01;
4494 val != 0
4495 }
4496 #[inline(always)]
4497 pub const fn set_iaf(&mut self, val: bool) {
4498 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
4499 }
4500 #[must_use]
4501 #[inline(always)]
4502 pub const fn ii(&self) -> bool {
4503 let val = (self.0 >> 2usize) & 0x01;
4504 val != 0
4505 }
4506 #[inline(always)]
4507 pub const fn set_ii(&mut self, val: bool) {
4508 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
4509 }
4510 #[must_use]
4511 #[inline(always)]
4512 pub const fn nmi(&self) -> bool {
4513 let val = (self.0 >> 3usize) & 0x01;
4514 val != 0
4515 }
4516 #[inline(always)]
4517 pub const fn set_nmi(&mut self, val: bool) {
4518 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
4519 }
4520 #[must_use]
4521 #[inline(always)]
4522 pub const fn lam(&self) -> bool {
4523 let val = (self.0 >> 4usize) & 0x01;
4524 val != 0
4525 }
4526 #[inline(always)]
4527 pub const fn set_lam(&mut self, val: bool) {
4528 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
4529 }
4530 #[must_use]
4531 #[inline(always)]
4532 pub const fn laf(&self) -> bool {
4533 let val = (self.0 >> 5usize) & 0x01;
4534 val != 0
4535 }
4536 #[inline(always)]
4537 pub const fn set_laf(&mut self, val: bool) {
4538 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
4539 }
4540 #[must_use]
4541 #[inline(always)]
4542 pub const fn sam(&self) -> bool {
4543 let val = (self.0 >> 6usize) & 0x01;
4544 val != 0
4545 }
4546 #[inline(always)]
4547 pub const fn set_sam(&mut self, val: bool) {
4548 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
4549 }
4550 #[must_use]
4551 #[inline(always)]
4552 pub const fn saf(&self) -> bool {
4553 let val = (self.0 >> 7usize) & 0x01;
4554 val != 0
4555 }
4556 #[inline(always)]
4557 pub const fn set_saf(&mut self, val: bool) {
4558 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
4559 }
4560 #[must_use]
4561 #[inline(always)]
4562 pub const fn uec(&self) -> bool {
4563 let val = (self.0 >> 8usize) & 0x01;
4564 val != 0
4565 }
4566 #[inline(always)]
4567 pub const fn set_uec(&mut self, val: bool) {
4568 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
4569 }
4570 #[must_use]
4571 #[inline(always)]
4572 pub const fn sec(&self) -> bool {
4573 let val = (self.0 >> 9usize) & 0x01;
4574 val != 0
4575 }
4576 #[inline(always)]
4577 pub const fn set_sec(&mut self, val: bool) {
4578 self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
4579 }
4580 #[must_use]
4581 #[inline(always)]
4582 pub const fn hec(&self) -> bool {
4583 let val = (self.0 >> 10usize) & 0x01;
4584 val != 0
4585 }
4586 #[inline(always)]
4587 pub const fn set_hec(&mut self, val: bool) {
4588 self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
4589 }
4590 #[must_use]
4591 #[inline(always)]
4592 pub const fn mec(&self) -> bool {
4593 let val = (self.0 >> 11usize) & 0x01;
4594 val != 0
4595 }
4596 #[inline(always)]
4597 pub const fn set_mec(&mut self, val: bool) {
4598 self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
4599 }
4600 #[must_use]
4601 #[inline(always)]
4602 pub const fn hsp(&self) -> bool {
4603 let val = (self.0 >> 12usize) & 0x01;
4604 val != 0
4605 }
4606 #[inline(always)]
4607 pub const fn set_hsp(&mut self, val: bool) {
4608 self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
4609 }
4610 #[must_use]
4611 #[inline(always)]
4612 pub const fn ace(&self) -> bool {
4613 let val = (self.0 >> 13usize) & 0x01;
4614 val != 0
4615 }
4616 #[inline(always)]
4617 pub const fn set_ace(&mut self, val: bool) {
4618 self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
4619 }
4620 #[must_use]
4621 #[inline(always)]
4622 pub const fn slpecc(&self) -> bool {
4623 let val = (self.0 >> 14usize) & 0x01;
4624 val != 0
4625 }
4626 #[inline(always)]
4627 pub const fn set_slpecc(&mut self, val: bool) {
4628 self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
4629 }
4630 #[must_use]
4631 #[inline(always)]
4632 pub const fn bwe(&self) -> bool {
4633 let val = (self.0 >> 15usize) & 0x01;
4634 val != 0
4635 }
4636 #[inline(always)]
4637 pub const fn set_bwe(&mut self, val: bool) {
4638 self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
4639 }
4640 #[must_use]
4641 #[inline(always)]
4642 pub const fn ipf(&self) -> bool {
4643 let val = (self.0 >> 16usize) & 0x01;
4644 val != 0
4645 }
4646 #[inline(always)]
4647 pub const fn set_ipf(&mut self, val: bool) {
4648 self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
4649 }
4650 #[must_use]
4651 #[inline(always)]
4652 pub const fn lpf(&self) -> bool {
4653 let val = (self.0 >> 17usize) & 0x01;
4654 val != 0
4655 }
4656 #[inline(always)]
4657 pub const fn set_lpf(&mut self, val: bool) {
4658 self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
4659 }
4660 #[must_use]
4661 #[inline(always)]
4662 pub const fn spf(&self) -> bool {
4663 let val = (self.0 >> 18usize) & 0x01;
4664 val != 0
4665 }
4666 #[inline(always)]
4667 pub const fn set_spf(&mut self, val: bool) {
4668 self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
4669 }
4670 #[must_use]
4671 #[inline(always)]
4672 pub const fn pmov(&self) -> bool {
4673 let val = (self.0 >> 19usize) & 0x01;
4674 val != 0
4675 }
4676 #[inline(always)]
4677 pub const fn set_pmov(&mut self, val: bool) {
4678 self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
4679 }
4680 }
4681 impl Default for Dexc2dbg {
4682 #[inline(always)]
4683 fn default() -> Dexc2dbg {
4684 Dexc2dbg(0)
4685 }
4686 }
4687 impl core::fmt::Debug for Dexc2dbg {
4688 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
4689 f.debug_struct("Dexc2dbg")
4690 .field("iam", &self.iam())
4691 .field("iaf", &self.iaf())
4692 .field("ii", &self.ii())
4693 .field("nmi", &self.nmi())
4694 .field("lam", &self.lam())
4695 .field("laf", &self.laf())
4696 .field("sam", &self.sam())
4697 .field("saf", &self.saf())
4698 .field("uec", &self.uec())
4699 .field("sec", &self.sec())
4700 .field("hec", &self.hec())
4701 .field("mec", &self.mec())
4702 .field("hsp", &self.hsp())
4703 .field("ace", &self.ace())
4704 .field("slpecc", &self.slpecc())
4705 .field("bwe", &self.bwe())
4706 .field("ipf", &self.ipf())
4707 .field("lpf", &self.lpf())
4708 .field("spf", &self.spf())
4709 .field("pmov", &self.pmov())
4710 .finish()
4711 }
4712 }
4713 #[cfg(feature = "defmt")]
4714 impl defmt::Format for Dexc2dbg {
4715 fn format(&self, f: defmt::Formatter) {
4716 defmt::write!(
4717 f,
4718 "Dexc2dbg {{ iam: {=bool:?}, iaf: {=bool:?}, ii: {=bool:?}, nmi: {=bool:?}, lam: {=bool:?}, laf: {=bool:?}, sam: {=bool:?}, saf: {=bool:?}, uec: {=bool:?}, sec: {=bool:?}, hec: {=bool:?}, mec: {=bool:?}, hsp: {=bool:?}, ace: {=bool:?}, slpecc: {=bool:?}, bwe: {=bool:?}, ipf: {=bool:?}, lpf: {=bool:?}, spf: {=bool:?}, pmov: {=bool:?} }}",
4719 self.iam(),
4720 self.iaf(),
4721 self.ii(),
4722 self.nmi(),
4723 self.lam(),
4724 self.laf(),
4725 self.sam(),
4726 self.saf(),
4727 self.uec(),
4728 self.sec(),
4729 self.hec(),
4730 self.mec(),
4731 self.hsp(),
4732 self.ace(),
4733 self.slpecc(),
4734 self.bwe(),
4735 self.ipf(),
4736 self.lpf(),
4737 self.spf(),
4738 self.pmov()
4739 )
4740 }
4741 }
4742 #[inline(always)]
4743 unsafe fn _read() -> usize {
4744 let r: usize;
4745 unsafe {
4746 core :: arch :: asm ! ("csrrs {0}, 0x7e0, x0" , out (reg) r);
4747 }
4748 r
4749 }
4750 #[inline(always)]
4751 unsafe fn _write(bits: usize) {
4752 unsafe {
4753 core :: arch :: asm ! ("csrrw x0, 0x7e0, {0}" , in (reg) bits);
4754 }
4755 }
4756 #[inline(always)]
4757 unsafe fn _set(bits: usize) {
4758 unsafe {
4759 core :: arch :: asm ! ("csrrs x0, 0x7e0, {0}" , in (reg) bits);
4760 }
4761 }
4762 #[inline(always)]
4763 unsafe fn _clear(bits: usize) {
4764 unsafe {
4765 core :: arch :: asm ! ("csrrc x0, 0x7e0, {0}" , in (reg) bits);
4766 }
4767 }
4768 #[doc = r" Read the CSR value."]
4769 #[inline]
4770 pub fn read() -> Dexc2dbg {
4771 unsafe { Dexc2dbg(_read() as u32) }
4772 }
4773 #[doc = r" Write the CSR value."]
4774 #[inline]
4775 pub unsafe fn write(val: Dexc2dbg) {
4776 unsafe {
4777 _write(val.0 as usize);
4778 }
4779 }
4780 #[doc = r" Read-modify-write the CSR."]
4781 #[inline]
4782 pub unsafe fn modify<R>(f: impl FnOnce(&mut Dexc2dbg) -> R) -> R {
4783 let mut val = read();
4784 let res = f(&mut val);
4785 unsafe {
4786 write(val);
4787 }
4788 res
4789 }
4790 #[inline]
4791 pub unsafe fn set_iam() {
4792 unsafe {
4793 _set(1usize);
4794 }
4795 }
4796 #[inline]
4797 pub unsafe fn clear_iam() {
4798 unsafe {
4799 _clear(1usize);
4800 }
4801 }
4802 #[inline]
4803 pub unsafe fn set_iaf() {
4804 unsafe {
4805 _set(2usize);
4806 }
4807 }
4808 #[inline]
4809 pub unsafe fn clear_iaf() {
4810 unsafe {
4811 _clear(2usize);
4812 }
4813 }
4814 #[inline]
4815 pub unsafe fn set_ii() {
4816 unsafe {
4817 _set(4usize);
4818 }
4819 }
4820 #[inline]
4821 pub unsafe fn clear_ii() {
4822 unsafe {
4823 _clear(4usize);
4824 }
4825 }
4826 #[inline]
4827 pub unsafe fn set_nmi() {
4828 unsafe {
4829 _set(8usize);
4830 }
4831 }
4832 #[inline]
4833 pub unsafe fn clear_nmi() {
4834 unsafe {
4835 _clear(8usize);
4836 }
4837 }
4838 #[inline]
4839 pub unsafe fn set_lam() {
4840 unsafe {
4841 _set(16usize);
4842 }
4843 }
4844 #[inline]
4845 pub unsafe fn clear_lam() {
4846 unsafe {
4847 _clear(16usize);
4848 }
4849 }
4850 #[inline]
4851 pub unsafe fn set_laf() {
4852 unsafe {
4853 _set(32usize);
4854 }
4855 }
4856 #[inline]
4857 pub unsafe fn clear_laf() {
4858 unsafe {
4859 _clear(32usize);
4860 }
4861 }
4862 #[inline]
4863 pub unsafe fn set_sam() {
4864 unsafe {
4865 _set(64usize);
4866 }
4867 }
4868 #[inline]
4869 pub unsafe fn clear_sam() {
4870 unsafe {
4871 _clear(64usize);
4872 }
4873 }
4874 #[inline]
4875 pub unsafe fn set_saf() {
4876 unsafe {
4877 _set(128usize);
4878 }
4879 }
4880 #[inline]
4881 pub unsafe fn clear_saf() {
4882 unsafe {
4883 _clear(128usize);
4884 }
4885 }
4886 #[inline]
4887 pub unsafe fn set_uec() {
4888 unsafe {
4889 _set(256usize);
4890 }
4891 }
4892 #[inline]
4893 pub unsafe fn clear_uec() {
4894 unsafe {
4895 _clear(256usize);
4896 }
4897 }
4898 #[inline]
4899 pub unsafe fn set_sec() {
4900 unsafe {
4901 _set(512usize);
4902 }
4903 }
4904 #[inline]
4905 pub unsafe fn clear_sec() {
4906 unsafe {
4907 _clear(512usize);
4908 }
4909 }
4910 #[inline]
4911 pub unsafe fn set_hec() {
4912 unsafe {
4913 _set(1024usize);
4914 }
4915 }
4916 #[inline]
4917 pub unsafe fn clear_hec() {
4918 unsafe {
4919 _clear(1024usize);
4920 }
4921 }
4922 #[inline]
4923 pub unsafe fn set_mec() {
4924 unsafe {
4925 _set(2048usize);
4926 }
4927 }
4928 #[inline]
4929 pub unsafe fn clear_mec() {
4930 unsafe {
4931 _clear(2048usize);
4932 }
4933 }
4934 #[inline]
4935 pub unsafe fn set_hsp() {
4936 unsafe {
4937 _set(4096usize);
4938 }
4939 }
4940 #[inline]
4941 pub unsafe fn clear_hsp() {
4942 unsafe {
4943 _clear(4096usize);
4944 }
4945 }
4946 #[inline]
4947 pub unsafe fn set_ace() {
4948 unsafe {
4949 _set(8192usize);
4950 }
4951 }
4952 #[inline]
4953 pub unsafe fn clear_ace() {
4954 unsafe {
4955 _clear(8192usize);
4956 }
4957 }
4958 #[inline]
4959 pub unsafe fn set_slpecc() {
4960 unsafe {
4961 _set(16384usize);
4962 }
4963 }
4964 #[inline]
4965 pub unsafe fn clear_slpecc() {
4966 unsafe {
4967 _clear(16384usize);
4968 }
4969 }
4970 #[inline]
4971 pub unsafe fn set_bwe() {
4972 unsafe {
4973 _set(32768usize);
4974 }
4975 }
4976 #[inline]
4977 pub unsafe fn clear_bwe() {
4978 unsafe {
4979 _clear(32768usize);
4980 }
4981 }
4982 #[inline]
4983 pub unsafe fn set_ipf() {
4984 unsafe {
4985 _set(65536usize);
4986 }
4987 }
4988 #[inline]
4989 pub unsafe fn clear_ipf() {
4990 unsafe {
4991 _clear(65536usize);
4992 }
4993 }
4994 #[inline]
4995 pub unsafe fn set_lpf() {
4996 unsafe {
4997 _set(131072usize);
4998 }
4999 }
5000 #[inline]
5001 pub unsafe fn clear_lpf() {
5002 unsafe {
5003 _clear(131072usize);
5004 }
5005 }
5006 #[inline]
5007 pub unsafe fn set_spf() {
5008 unsafe {
5009 _set(262144usize);
5010 }
5011 }
5012 #[inline]
5013 pub unsafe fn clear_spf() {
5014 unsafe {
5015 _clear(262144usize);
5016 }
5017 }
5018 #[inline]
5019 pub unsafe fn set_pmov() {
5020 unsafe {
5021 _set(524288usize);
5022 }
5023 }
5024 #[inline]
5025 pub unsafe fn clear_pmov() {
5026 unsafe {
5027 _clear(524288usize);
5028 }
5029 }
5030}
5031#[doc = "Detailed exception type information when an exception enters Halt Mode."]
5032pub mod ddcause {
5033 #[doc = "Debug Detailed Cause Register"]
5034 #[repr(transparent)]
5035 #[derive(Copy, Clone, Eq, PartialEq)]
5036 pub struct Ddcause(pub u32);
5037 impl Ddcause {
5038 #[doc = "Indicates the main types of a Debug Mode entrance. Its definition is listed below."]
5039 #[must_use]
5040 #[inline(always)]
5041 pub const fn maintype(&self) -> u8 {
5042 let val = (self.0 >> 0usize) & 0xff;
5043 val as u8
5044 }
5045 #[doc = "Indicates the main types of a Debug Mode entrance. Its definition is listed below."]
5046 #[inline(always)]
5047 pub const fn set_maintype(&mut self, val: u8) {
5048 self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
5049 }
5050 #[doc = "Indicates the subtypes of a main type. Its definition is listed below. A main type may not have a subtype definition."]
5051 #[must_use]
5052 #[inline(always)]
5053 pub const fn subtype(&self) -> u8 {
5054 let val = (self.0 >> 8usize) & 0xff;
5055 val as u8
5056 }
5057 #[doc = "Indicates the subtypes of a main type. Its definition is listed below. A main type may not have a subtype definition."]
5058 #[inline(always)]
5059 pub const fn set_subtype(&mut self, val: u8) {
5060 self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
5061 }
5062 }
5063 impl Default for Ddcause {
5064 #[inline(always)]
5065 fn default() -> Ddcause {
5066 Ddcause(0)
5067 }
5068 }
5069 impl core::fmt::Debug for Ddcause {
5070 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
5071 f.debug_struct("Ddcause")
5072 .field("maintype", &self.maintype())
5073 .field("subtype", &self.subtype())
5074 .finish()
5075 }
5076 }
5077 #[cfg(feature = "defmt")]
5078 impl defmt::Format for Ddcause {
5079 fn format(&self, f: defmt::Formatter) {
5080 defmt::write!(
5081 f,
5082 "Ddcause {{ maintype: {=u8:?}, subtype: {=u8:?} }}",
5083 self.maintype(),
5084 self.subtype()
5085 )
5086 }
5087 }
5088 #[inline(always)]
5089 unsafe fn _read() -> usize {
5090 let r: usize;
5091 unsafe {
5092 core :: arch :: asm ! ("csrrs {0}, 0x7e1, x0" , out (reg) r);
5093 }
5094 r
5095 }
5096 #[inline(always)]
5097 unsafe fn _write(bits: usize) {
5098 unsafe {
5099 core :: arch :: asm ! ("csrrw x0, 0x7e1, {0}" , in (reg) bits);
5100 }
5101 }
5102 #[inline(always)]
5103 unsafe fn _set(bits: usize) {
5104 unsafe {
5105 core :: arch :: asm ! ("csrrs x0, 0x7e1, {0}" , in (reg) bits);
5106 }
5107 }
5108 #[inline(always)]
5109 unsafe fn _clear(bits: usize) {
5110 unsafe {
5111 core :: arch :: asm ! ("csrrc x0, 0x7e1, {0}" , in (reg) bits);
5112 }
5113 }
5114 #[doc = r" Read the CSR value."]
5115 #[inline]
5116 pub fn read() -> Ddcause {
5117 unsafe { Ddcause(_read() as u32) }
5118 }
5119 #[doc = r" Write the CSR value."]
5120 #[inline]
5121 pub unsafe fn write(val: Ddcause) {
5122 unsafe {
5123 _write(val.0 as usize);
5124 }
5125 }
5126 #[doc = r" Read-modify-write the CSR."]
5127 #[inline]
5128 pub unsafe fn modify<R>(f: impl FnOnce(&mut Ddcause) -> R) -> R {
5129 let mut val = read();
5130 let res = f(&mut val);
5131 unsafe {
5132 write(val);
5133 }
5134 res
5135 }
5136 #[doc = "Indicates the main types of a Debug Mode entrance. Its definition is listed below."]
5137 #[inline]
5138 pub unsafe fn set_maintype(val: u8) {
5139 let mut bits = unsafe { _read() };
5140 bits &= !(255usize << 0usize);
5141 bits |= (val as usize & 255usize) << 0usize;
5142 unsafe {
5143 _write(bits);
5144 }
5145 }
5146 #[doc = "Indicates the subtypes of a main type. Its definition is listed below. A main type may not have a subtype definition."]
5147 #[inline]
5148 pub unsafe fn set_subtype(val: u8) {
5149 let mut bits = unsafe { _read() };
5150 bits &= !(255usize << 8usize);
5151 bits |= (val as usize & 255usize) << 8usize;
5152 unsafe {
5153 _write(bits);
5154 }
5155 }
5156}
5157#[doc = "Store mxstatus to stack"]
5158pub mod pushmxstatus {
5159 #[inline(always)]
5160 unsafe fn _read() -> usize {
5161 let r: usize;
5162 unsafe {
5163 core :: arch :: asm ! ("csrrs {0}, 0x7eb, x0" , out (reg) r);
5164 }
5165 r
5166 }
5167 #[inline(always)]
5168 unsafe fn _write(bits: usize) {
5169 unsafe {
5170 core :: arch :: asm ! ("csrrw x0, 0x7eb, {0}" , in (reg) bits);
5171 }
5172 }
5173 #[inline(always)]
5174 unsafe fn _set(bits: usize) {
5175 unsafe {
5176 core :: arch :: asm ! ("csrrs x0, 0x7eb, {0}" , in (reg) bits);
5177 }
5178 }
5179 #[inline(always)]
5180 unsafe fn _clear(bits: usize) {
5181 unsafe {
5182 core :: arch :: asm ! ("csrrc x0, 0x7eb, {0}" , in (reg) bits);
5183 }
5184 }
5185 #[doc = r" Read the CSR value as raw usize."]
5186 #[inline]
5187 pub fn read() -> usize {
5188 unsafe { _read() }
5189 }
5190 #[doc = r" Write the CSR value as raw usize."]
5191 #[inline]
5192 pub unsafe fn write(val: usize) {
5193 unsafe {
5194 _write(val);
5195 }
5196 }
5197}
5198#[doc = "Interrupt common entry point"]
5199pub mod mirq_entry {
5200 #[doc = "Machine Interrupt Common Entry Address Register"]
5201 #[repr(transparent)]
5202 #[derive(Copy, Clone, Eq, PartialEq)]
5203 pub struct MirqEntry(pub u32);
5204 impl MirqEntry {
5205 #[doc = "Enable"]
5206 #[must_use]
5207 #[inline(always)]
5208 pub const fn en(&self) -> bool {
5209 let val = (self.0 >> 0usize) & 0x01;
5210 val != 0
5211 }
5212 #[doc = "Enable"]
5213 #[inline(always)]
5214 pub const fn set_en(&mut self, val: bool) {
5215 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
5216 }
5217 #[doc = "Interrupt Common Entry Address"]
5218 #[must_use]
5219 #[inline(always)]
5220 pub const fn icea(&self) -> u32 {
5221 let val = (self.0 >> 1usize) & 0x7fff_ffff;
5222 val as u32
5223 }
5224 #[doc = "Interrupt Common Entry Address"]
5225 #[inline(always)]
5226 pub const fn set_icea(&mut self, val: u32) {
5227 self.0 = (self.0 & !(0x7fff_ffff << 1usize)) | (((val as u32) & 0x7fff_ffff) << 1usize);
5228 }
5229 }
5230 impl Default for MirqEntry {
5231 #[inline(always)]
5232 fn default() -> MirqEntry {
5233 MirqEntry(0)
5234 }
5235 }
5236 impl core::fmt::Debug for MirqEntry {
5237 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
5238 f.debug_struct("MirqEntry")
5239 .field("en", &self.en())
5240 .field("icea", &self.icea())
5241 .finish()
5242 }
5243 }
5244 #[cfg(feature = "defmt")]
5245 impl defmt::Format for MirqEntry {
5246 fn format(&self, f: defmt::Formatter) {
5247 defmt::write!(
5248 f,
5249 "MirqEntry {{ en: {=bool:?}, icea: {=u32:?} }}",
5250 self.en(),
5251 self.icea()
5252 )
5253 }
5254 }
5255 #[inline(always)]
5256 unsafe fn _read() -> usize {
5257 let r: usize;
5258 unsafe {
5259 core :: arch :: asm ! ("csrrs {0}, 0x7ec, x0" , out (reg) r);
5260 }
5261 r
5262 }
5263 #[inline(always)]
5264 unsafe fn _write(bits: usize) {
5265 unsafe {
5266 core :: arch :: asm ! ("csrrw x0, 0x7ec, {0}" , in (reg) bits);
5267 }
5268 }
5269 #[inline(always)]
5270 unsafe fn _set(bits: usize) {
5271 unsafe {
5272 core :: arch :: asm ! ("csrrs x0, 0x7ec, {0}" , in (reg) bits);
5273 }
5274 }
5275 #[inline(always)]
5276 unsafe fn _clear(bits: usize) {
5277 unsafe {
5278 core :: arch :: asm ! ("csrrc x0, 0x7ec, {0}" , in (reg) bits);
5279 }
5280 }
5281 #[doc = r" Read the CSR value."]
5282 #[inline]
5283 pub fn read() -> MirqEntry {
5284 unsafe { MirqEntry(_read() as u32) }
5285 }
5286 #[doc = r" Write the CSR value."]
5287 #[inline]
5288 pub unsafe fn write(val: MirqEntry) {
5289 unsafe {
5290 _write(val.0 as usize);
5291 }
5292 }
5293 #[doc = r" Read-modify-write the CSR."]
5294 #[inline]
5295 pub unsafe fn modify<R>(f: impl FnOnce(&mut MirqEntry) -> R) -> R {
5296 let mut val = read();
5297 let res = f(&mut val);
5298 unsafe {
5299 write(val);
5300 }
5301 res
5302 }
5303 #[doc = "Enable"]
5304 #[inline]
5305 pub unsafe fn set_en() {
5306 unsafe {
5307 _set(1usize);
5308 }
5309 }
5310 #[doc = "Enable"]
5311 #[inline]
5312 pub unsafe fn clear_en() {
5313 unsafe {
5314 _clear(1usize);
5315 }
5316 }
5317 #[doc = "Interrupt Common Entry Address"]
5318 #[inline]
5319 pub unsafe fn set_icea(val: u32) {
5320 let mut bits = unsafe { _read() };
5321 bits &= !(2147483647usize << 1usize);
5322 bits |= (val as usize & 2147483647usize) << 1usize;
5323 unsafe {
5324 _write(bits);
5325 }
5326 }
5327}
5328#[doc = "Select interrupt and call ISR"]
5329pub mod mintsel_jal {
5330 #[inline(always)]
5331 unsafe fn _read() -> usize {
5332 let r: usize;
5333 unsafe {
5334 core :: arch :: asm ! ("csrrs {0}, 0x7ed, x0" , out (reg) r);
5335 }
5336 r
5337 }
5338 #[inline(always)]
5339 unsafe fn _write(bits: usize) {
5340 unsafe {
5341 core :: arch :: asm ! ("csrrw x0, 0x7ed, {0}" , in (reg) bits);
5342 }
5343 }
5344 #[inline(always)]
5345 unsafe fn _set(bits: usize) {
5346 unsafe {
5347 core :: arch :: asm ! ("csrrs x0, 0x7ed, {0}" , in (reg) bits);
5348 }
5349 }
5350 #[inline(always)]
5351 unsafe fn _clear(bits: usize) {
5352 unsafe {
5353 core :: arch :: asm ! ("csrrc x0, 0x7ed, {0}" , in (reg) bits);
5354 }
5355 }
5356 #[doc = r" Read the CSR value as raw usize."]
5357 #[inline]
5358 pub fn read() -> usize {
5359 unsafe { _read() }
5360 }
5361 #[doc = r" Write the CSR value as raw usize."]
5362 #[inline]
5363 pub unsafe fn write(val: usize) {
5364 unsafe {
5365 _write(val);
5366 }
5367 }
5368}
5369#[doc = "Store mcause to stack"]
5370pub mod pushmcause {
5371 #[inline(always)]
5372 unsafe fn _read() -> usize {
5373 let r: usize;
5374 unsafe {
5375 core :: arch :: asm ! ("csrrs {0}, 0x7ee, x0" , out (reg) r);
5376 }
5377 r
5378 }
5379 #[inline(always)]
5380 unsafe fn _write(bits: usize) {
5381 unsafe {
5382 core :: arch :: asm ! ("csrrw x0, 0x7ee, {0}" , in (reg) bits);
5383 }
5384 }
5385 #[inline(always)]
5386 unsafe fn _set(bits: usize) {
5387 unsafe {
5388 core :: arch :: asm ! ("csrrs x0, 0x7ee, {0}" , in (reg) bits);
5389 }
5390 }
5391 #[inline(always)]
5392 unsafe fn _clear(bits: usize) {
5393 unsafe {
5394 core :: arch :: asm ! ("csrrc x0, 0x7ee, {0}" , in (reg) bits);
5395 }
5396 }
5397 #[doc = r" Read the CSR value as raw usize."]
5398 #[inline]
5399 pub fn read() -> usize {
5400 unsafe { _read() }
5401 }
5402 #[doc = r" Write the CSR value as raw usize."]
5403 #[inline]
5404 pub unsafe fn write(val: usize) {
5405 unsafe {
5406 _write(val);
5407 }
5408 }
5409}
5410#[doc = "Store mepc to stack"]
5411pub mod pushmepc {
5412 #[inline(always)]
5413 unsafe fn _read() -> usize {
5414 let r: usize;
5415 unsafe {
5416 core :: arch :: asm ! ("csrrs {0}, 0x7ef, x0" , out (reg) r);
5417 }
5418 r
5419 }
5420 #[inline(always)]
5421 unsafe fn _write(bits: usize) {
5422 unsafe {
5423 core :: arch :: asm ! ("csrrw x0, 0x7ef, {0}" , in (reg) bits);
5424 }
5425 }
5426 #[inline(always)]
5427 unsafe fn _set(bits: usize) {
5428 unsafe {
5429 core :: arch :: asm ! ("csrrs x0, 0x7ef, {0}" , in (reg) bits);
5430 }
5431 }
5432 #[inline(always)]
5433 unsafe fn _clear(bits: usize) {
5434 unsafe {
5435 core :: arch :: asm ! ("csrrc x0, 0x7ef, {0}" , in (reg) bits);
5436 }
5437 }
5438 #[doc = r" Read the CSR value as raw usize."]
5439 #[inline]
5440 pub fn read() -> usize {
5441 unsafe { _read() }
5442 }
5443 #[doc = r" Write the CSR value as raw usize."]
5444 #[inline]
5445 pub unsafe fn write(val: usize) {
5446 unsafe {
5447 _write(val);
5448 }
5449 }
5450}
5451#[doc = "Private peripheral interface base address"]
5452pub mod mppib {
5453 #[doc = "PPI (Private Peripheral Interface) Base Register"]
5454 #[repr(transparent)]
5455 #[derive(Copy, Clone, Eq, PartialEq)]
5456 pub struct Mppib(pub u32);
5457 impl Mppib {
5458 #[doc = "Private Peripheral Interface enable bit"]
5459 #[must_use]
5460 #[inline(always)]
5461 pub const fn en(&self) -> bool {
5462 let val = (self.0 >> 0usize) & 0x01;
5463 val != 0
5464 }
5465 #[doc = "Private Peripheral Interface enable bit"]
5466 #[inline(always)]
5467 pub const fn set_en(&mut self, val: bool) {
5468 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
5469 }
5470 #[doc = "Indicates the power-of-2 size of the PPI region"]
5471 #[must_use]
5472 #[inline(always)]
5473 pub const fn size(&self) -> u8 {
5474 let val = (self.0 >> 1usize) & 0x1f;
5475 val as u8
5476 }
5477 #[doc = "Indicates the power-of-2 size of the PPI region"]
5478 #[inline(always)]
5479 pub const fn set_size(&mut self, val: u8) {
5480 self.0 = (self.0 & !(0x1f << 1usize)) | (((val as u32) & 0x1f) << 1usize);
5481 }
5482 #[doc = "Base Physical Address"]
5483 #[must_use]
5484 #[inline(always)]
5485 pub const fn bpa(&self) -> u32 {
5486 let val = (self.0 >> 10usize) & 0x003f_ffff;
5487 val as u32
5488 }
5489 #[doc = "Base Physical Address"]
5490 #[inline(always)]
5491 pub const fn set_bpa(&mut self, val: u32) {
5492 self.0 =
5493 (self.0 & !(0x003f_ffff << 10usize)) | (((val as u32) & 0x003f_ffff) << 10usize);
5494 }
5495 }
5496 impl Default for Mppib {
5497 #[inline(always)]
5498 fn default() -> Mppib {
5499 Mppib(0)
5500 }
5501 }
5502 impl core::fmt::Debug for Mppib {
5503 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
5504 f.debug_struct("Mppib")
5505 .field("en", &self.en())
5506 .field("size", &self.size())
5507 .field("bpa", &self.bpa())
5508 .finish()
5509 }
5510 }
5511 #[cfg(feature = "defmt")]
5512 impl defmt::Format for Mppib {
5513 fn format(&self, f: defmt::Formatter) {
5514 defmt::write!(
5515 f,
5516 "Mppib {{ en: {=bool:?}, size: {=u8:?}, bpa: {=u32:?} }}",
5517 self.en(),
5518 self.size(),
5519 self.bpa()
5520 )
5521 }
5522 }
5523 #[inline(always)]
5524 unsafe fn _read() -> usize {
5525 let r: usize;
5526 unsafe {
5527 core :: arch :: asm ! ("csrrs {0}, 0x7f0, x0" , out (reg) r);
5528 }
5529 r
5530 }
5531 #[inline(always)]
5532 unsafe fn _write(bits: usize) {
5533 unsafe {
5534 core :: arch :: asm ! ("csrrw x0, 0x7f0, {0}" , in (reg) bits);
5535 }
5536 }
5537 #[inline(always)]
5538 unsafe fn _set(bits: usize) {
5539 unsafe {
5540 core :: arch :: asm ! ("csrrs x0, 0x7f0, {0}" , in (reg) bits);
5541 }
5542 }
5543 #[inline(always)]
5544 unsafe fn _clear(bits: usize) {
5545 unsafe {
5546 core :: arch :: asm ! ("csrrc x0, 0x7f0, {0}" , in (reg) bits);
5547 }
5548 }
5549 #[doc = r" Read the CSR value."]
5550 #[inline]
5551 pub fn read() -> Mppib {
5552 unsafe { Mppib(_read() as u32) }
5553 }
5554 #[doc = r" Write the CSR value."]
5555 #[inline]
5556 pub unsafe fn write(val: Mppib) {
5557 unsafe {
5558 _write(val.0 as usize);
5559 }
5560 }
5561 #[doc = r" Read-modify-write the CSR."]
5562 #[inline]
5563 pub unsafe fn modify<R>(f: impl FnOnce(&mut Mppib) -> R) -> R {
5564 let mut val = read();
5565 let res = f(&mut val);
5566 unsafe {
5567 write(val);
5568 }
5569 res
5570 }
5571 #[doc = "Private Peripheral Interface enable bit"]
5572 #[inline]
5573 pub unsafe fn set_en() {
5574 unsafe {
5575 _set(1usize);
5576 }
5577 }
5578 #[doc = "Private Peripheral Interface enable bit"]
5579 #[inline]
5580 pub unsafe fn clear_en() {
5581 unsafe {
5582 _clear(1usize);
5583 }
5584 }
5585 #[doc = "Indicates the power-of-2 size of the PPI region"]
5586 #[inline]
5587 pub unsafe fn set_size(val: u8) {
5588 let mut bits = unsafe { _read() };
5589 bits &= !(31usize << 1usize);
5590 bits |= (val as usize & 31usize) << 1usize;
5591 unsafe {
5592 _write(bits);
5593 }
5594 }
5595 #[doc = "Base Physical Address"]
5596 #[inline]
5597 pub unsafe fn set_bpa(val: u32) {
5598 let mut bits = unsafe { _read() };
5599 bits &= !(4194303usize << 10usize);
5600 bits |= (val as usize & 4194303usize) << 10usize;
5601 unsafe {
5602 _write(bits);
5603 }
5604 }
5605}
5606#[doc = "Fast IO interface base address"]
5607pub mod mfiob {
5608 #[doc = "FIO (Fast IO Interface) Base Register"]
5609 #[repr(transparent)]
5610 #[derive(Copy, Clone, Eq, PartialEq)]
5611 pub struct Mfiob(pub u32);
5612 impl Mfiob {
5613 #[must_use]
5614 #[inline(always)]
5615 pub const fn en(&self) -> bool {
5616 let val = (self.0 >> 0usize) & 0x01;
5617 val != 0
5618 }
5619 #[inline(always)]
5620 pub const fn set_en(&mut self, val: bool) {
5621 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
5622 }
5623 #[must_use]
5624 #[inline(always)]
5625 pub const fn size(&self) -> u8 {
5626 let val = (self.0 >> 1usize) & 0x1f;
5627 val as u8
5628 }
5629 #[inline(always)]
5630 pub const fn set_size(&mut self, val: u8) {
5631 self.0 = (self.0 & !(0x1f << 1usize)) | (((val as u32) & 0x1f) << 1usize);
5632 }
5633 #[doc = "Base Physical Address"]
5634 #[must_use]
5635 #[inline(always)]
5636 pub const fn bpa(&self) -> u32 {
5637 let val = (self.0 >> 10usize) & 0x003f_ffff;
5638 val as u32
5639 }
5640 #[doc = "Base Physical Address"]
5641 #[inline(always)]
5642 pub const fn set_bpa(&mut self, val: u32) {
5643 self.0 =
5644 (self.0 & !(0x003f_ffff << 10usize)) | (((val as u32) & 0x003f_ffff) << 10usize);
5645 }
5646 }
5647 impl Default for Mfiob {
5648 #[inline(always)]
5649 fn default() -> Mfiob {
5650 Mfiob(0)
5651 }
5652 }
5653 impl core::fmt::Debug for Mfiob {
5654 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
5655 f.debug_struct("Mfiob")
5656 .field("en", &self.en())
5657 .field("size", &self.size())
5658 .field("bpa", &self.bpa())
5659 .finish()
5660 }
5661 }
5662 #[cfg(feature = "defmt")]
5663 impl defmt::Format for Mfiob {
5664 fn format(&self, f: defmt::Formatter) {
5665 defmt::write!(
5666 f,
5667 "Mfiob {{ en: {=bool:?}, size: {=u8:?}, bpa: {=u32:?} }}",
5668 self.en(),
5669 self.size(),
5670 self.bpa()
5671 )
5672 }
5673 }
5674 #[inline(always)]
5675 unsafe fn _read() -> usize {
5676 let r: usize;
5677 unsafe {
5678 core :: arch :: asm ! ("csrrs {0}, 0x7f1, x0" , out (reg) r);
5679 }
5680 r
5681 }
5682 #[inline(always)]
5683 unsafe fn _write(bits: usize) {
5684 unsafe {
5685 core :: arch :: asm ! ("csrrw x0, 0x7f1, {0}" , in (reg) bits);
5686 }
5687 }
5688 #[inline(always)]
5689 unsafe fn _set(bits: usize) {
5690 unsafe {
5691 core :: arch :: asm ! ("csrrs x0, 0x7f1, {0}" , in (reg) bits);
5692 }
5693 }
5694 #[inline(always)]
5695 unsafe fn _clear(bits: usize) {
5696 unsafe {
5697 core :: arch :: asm ! ("csrrc x0, 0x7f1, {0}" , in (reg) bits);
5698 }
5699 }
5700 #[doc = r" Read the CSR value."]
5701 #[inline]
5702 pub fn read() -> Mfiob {
5703 unsafe { Mfiob(_read() as u32) }
5704 }
5705 #[doc = r" Write the CSR value."]
5706 #[inline]
5707 pub unsafe fn write(val: Mfiob) {
5708 unsafe {
5709 _write(val.0 as usize);
5710 }
5711 }
5712 #[doc = r" Read-modify-write the CSR."]
5713 #[inline]
5714 pub unsafe fn modify<R>(f: impl FnOnce(&mut Mfiob) -> R) -> R {
5715 let mut val = read();
5716 let res = f(&mut val);
5717 unsafe {
5718 write(val);
5719 }
5720 res
5721 }
5722 #[inline]
5723 pub unsafe fn set_en() {
5724 unsafe {
5725 _set(1usize);
5726 }
5727 }
5728 #[inline]
5729 pub unsafe fn clear_en() {
5730 unsafe {
5731 _clear(1usize);
5732 }
5733 }
5734 #[inline]
5735 pub unsafe fn set_size(val: u8) {
5736 let mut bits = unsafe { _read() };
5737 bits &= !(31usize << 1usize);
5738 bits |= (val as usize & 31usize) << 1usize;
5739 unsafe {
5740 _write(bits);
5741 }
5742 }
5743 #[doc = "Base Physical Address"]
5744 #[inline]
5745 pub unsafe fn set_bpa(val: u32) {
5746 let mut bits = unsafe { _read() };
5747 bits &= !(4194303usize << 10usize);
5748 bits |= (val as usize & 4194303usize) << 10usize;
5749 unsafe {
5750 _write(bits);
5751 }
5752 }
5753}
5754#[doc = "Instruction table base address for CoDense extension."]
5755pub mod uitb {
5756 #[doc = "Instruction Table Base Address Register"]
5757 #[repr(transparent)]
5758 #[derive(Copy, Clone, Eq, PartialEq)]
5759 pub struct Uitb(pub u32);
5760 impl Uitb {
5761 #[doc = "if the Xcodense instruction table is hardwired"]
5762 #[must_use]
5763 #[inline(always)]
5764 pub const fn hw(&self) -> bool {
5765 let val = (self.0 >> 0usize) & 0x01;
5766 val != 0
5767 }
5768 #[doc = "if the Xcodense instruction table is hardwired"]
5769 #[inline(always)]
5770 pub const fn set_hw(&mut self, val: bool) {
5771 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
5772 }
5773 #[must_use]
5774 #[inline(always)]
5775 pub const fn addr(&self) -> u32 {
5776 let val = (self.0 >> 2usize) & 0x3fff_ffff;
5777 val as u32
5778 }
5779 #[inline(always)]
5780 pub const fn set_addr(&mut self, val: u32) {
5781 self.0 = (self.0 & !(0x3fff_ffff << 2usize)) | (((val as u32) & 0x3fff_ffff) << 2usize);
5782 }
5783 }
5784 impl Default for Uitb {
5785 #[inline(always)]
5786 fn default() -> Uitb {
5787 Uitb(0)
5788 }
5789 }
5790 impl core::fmt::Debug for Uitb {
5791 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
5792 f.debug_struct("Uitb")
5793 .field("hw", &self.hw())
5794 .field("addr", &self.addr())
5795 .finish()
5796 }
5797 }
5798 #[cfg(feature = "defmt")]
5799 impl defmt::Format for Uitb {
5800 fn format(&self, f: defmt::Formatter) {
5801 defmt::write!(
5802 f,
5803 "Uitb {{ hw: {=bool:?}, addr: {=u32:?} }}",
5804 self.hw(),
5805 self.addr()
5806 )
5807 }
5808 }
5809 #[inline(always)]
5810 unsafe fn _read() -> usize {
5811 let r: usize;
5812 unsafe {
5813 core :: arch :: asm ! ("csrrs {0}, 0x800, x0" , out (reg) r);
5814 }
5815 r
5816 }
5817 #[inline(always)]
5818 unsafe fn _write(bits: usize) {
5819 unsafe {
5820 core :: arch :: asm ! ("csrrw x0, 0x800, {0}" , in (reg) bits);
5821 }
5822 }
5823 #[inline(always)]
5824 unsafe fn _set(bits: usize) {
5825 unsafe {
5826 core :: arch :: asm ! ("csrrs x0, 0x800, {0}" , in (reg) bits);
5827 }
5828 }
5829 #[inline(always)]
5830 unsafe fn _clear(bits: usize) {
5831 unsafe {
5832 core :: arch :: asm ! ("csrrc x0, 0x800, {0}" , in (reg) bits);
5833 }
5834 }
5835 #[doc = r" Read the CSR value."]
5836 #[inline]
5837 pub fn read() -> Uitb {
5838 unsafe { Uitb(_read() as u32) }
5839 }
5840 #[doc = r" Write the CSR value."]
5841 #[inline]
5842 pub unsafe fn write(val: Uitb) {
5843 unsafe {
5844 _write(val.0 as usize);
5845 }
5846 }
5847 #[doc = r" Read-modify-write the CSR."]
5848 #[inline]
5849 pub unsafe fn modify<R>(f: impl FnOnce(&mut Uitb) -> R) -> R {
5850 let mut val = read();
5851 let res = f(&mut val);
5852 unsafe {
5853 write(val);
5854 }
5855 res
5856 }
5857 #[doc = "if the Xcodense instruction table is hardwired"]
5858 #[inline]
5859 pub unsafe fn set_hw() {
5860 unsafe {
5861 _set(1usize);
5862 }
5863 }
5864 #[doc = "if the Xcodense instruction table is hardwired"]
5865 #[inline]
5866 pub unsafe fn clear_hw() {
5867 unsafe {
5868 _clear(1usize);
5869 }
5870 }
5871 #[inline]
5872 pub unsafe fn set_addr(val: u32) {
5873 let mut bits = unsafe { _read() };
5874 bits &= !(1073741823usize << 2usize);
5875 bits |= (val as usize & 1073741823usize) << 2usize;
5876 unsafe {
5877 _write(bits);
5878 }
5879 }
5880}
5881#[doc = "Contains overflow flag for DSP extension."]
5882pub mod ucode {
5883 #[doc = "Code Register - Stores the overflow flag of the DSP extension"]
5884 #[repr(transparent)]
5885 #[derive(Copy, Clone, Eq, PartialEq)]
5886 pub struct Ucode(pub u32);
5887 impl Ucode {
5888 #[doc = "Overflow flag"]
5889 #[must_use]
5890 #[inline(always)]
5891 pub const fn ov(&self) -> bool {
5892 let val = (self.0 >> 0usize) & 0x01;
5893 val != 0
5894 }
5895 #[doc = "Overflow flag"]
5896 #[inline(always)]
5897 pub const fn set_ov(&mut self, val: bool) {
5898 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
5899 }
5900 }
5901 impl Default for Ucode {
5902 #[inline(always)]
5903 fn default() -> Ucode {
5904 Ucode(0)
5905 }
5906 }
5907 impl core::fmt::Debug for Ucode {
5908 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
5909 f.debug_struct("Ucode").field("ov", &self.ov()).finish()
5910 }
5911 }
5912 #[cfg(feature = "defmt")]
5913 impl defmt::Format for Ucode {
5914 fn format(&self, f: defmt::Formatter) {
5915 defmt::write!(f, "Ucode {{ ov: {=bool:?} }}", self.ov())
5916 }
5917 }
5918 #[inline(always)]
5919 unsafe fn _read() -> usize {
5920 let r: usize;
5921 unsafe {
5922 core :: arch :: asm ! ("csrrs {0}, 0x801, x0" , out (reg) r);
5923 }
5924 r
5925 }
5926 #[inline(always)]
5927 unsafe fn _write(bits: usize) {
5928 unsafe {
5929 core :: arch :: asm ! ("csrrw x0, 0x801, {0}" , in (reg) bits);
5930 }
5931 }
5932 #[inline(always)]
5933 unsafe fn _set(bits: usize) {
5934 unsafe {
5935 core :: arch :: asm ! ("csrrs x0, 0x801, {0}" , in (reg) bits);
5936 }
5937 }
5938 #[inline(always)]
5939 unsafe fn _clear(bits: usize) {
5940 unsafe {
5941 core :: arch :: asm ! ("csrrc x0, 0x801, {0}" , in (reg) bits);
5942 }
5943 }
5944 #[doc = r" Read the CSR value."]
5945 #[inline]
5946 pub fn read() -> Ucode {
5947 unsafe { Ucode(_read() as u32) }
5948 }
5949 #[doc = r" Write the CSR value."]
5950 #[inline]
5951 pub unsafe fn write(val: Ucode) {
5952 unsafe {
5953 _write(val.0 as usize);
5954 }
5955 }
5956 #[doc = r" Read-modify-write the CSR."]
5957 #[inline]
5958 pub unsafe fn modify<R>(f: impl FnOnce(&mut Ucode) -> R) -> R {
5959 let mut val = read();
5960 let res = f(&mut val);
5961 unsafe {
5962 write(val);
5963 }
5964 res
5965 }
5966 #[doc = "Overflow flag"]
5967 #[inline]
5968 pub unsafe fn set_ov() {
5969 unsafe {
5970 _set(1usize);
5971 }
5972 }
5973 #[doc = "Overflow flag"]
5974 #[inline]
5975 pub unsafe fn clear_ov() {
5976 unsafe {
5977 _clear(1usize);
5978 }
5979 }
5980}
5981#[doc = "User detailed trap cause"]
5982pub mod udcause {
5983 #[inline(always)]
5984 unsafe fn _read() -> usize {
5985 let r: usize;
5986 unsafe {
5987 core :: arch :: asm ! ("csrrs {0}, 0x809, x0" , out (reg) r);
5988 }
5989 r
5990 }
5991 #[inline(always)]
5992 unsafe fn _write(bits: usize) {
5993 unsafe {
5994 core :: arch :: asm ! ("csrrw x0, 0x809, {0}" , in (reg) bits);
5995 }
5996 }
5997 #[inline(always)]
5998 unsafe fn _set(bits: usize) {
5999 unsafe {
6000 core :: arch :: asm ! ("csrrs x0, 0x809, {0}" , in (reg) bits);
6001 }
6002 }
6003 #[inline(always)]
6004 unsafe fn _clear(bits: usize) {
6005 unsafe {
6006 core :: arch :: asm ! ("csrrc x0, 0x809, {0}" , in (reg) bits);
6007 }
6008 }
6009 #[doc = r" Read the CSR value as raw usize."]
6010 #[inline]
6011 pub fn read() -> usize {
6012 unsafe { _read() }
6013 }
6014 #[doc = r" Write the CSR value as raw usize."]
6015 #[inline]
6016 pub unsafe fn write(val: usize) {
6017 unsafe {
6018 _write(val);
6019 }
6020 }
6021}
6022#[doc = "CCTL begin address"]
6023pub mod ucctlbeginaddr {
6024 #[inline(always)]
6025 unsafe fn _read() -> usize {
6026 let r: usize;
6027 unsafe {
6028 core :: arch :: asm ! ("csrrs {0}, 0x80b, x0" , out (reg) r);
6029 }
6030 r
6031 }
6032 #[inline(always)]
6033 unsafe fn _write(bits: usize) {
6034 unsafe {
6035 core :: arch :: asm ! ("csrrw x0, 0x80b, {0}" , in (reg) bits);
6036 }
6037 }
6038 #[inline(always)]
6039 unsafe fn _set(bits: usize) {
6040 unsafe {
6041 core :: arch :: asm ! ("csrrs x0, 0x80b, {0}" , in (reg) bits);
6042 }
6043 }
6044 #[inline(always)]
6045 unsafe fn _clear(bits: usize) {
6046 unsafe {
6047 core :: arch :: asm ! ("csrrc x0, 0x80b, {0}" , in (reg) bits);
6048 }
6049 }
6050 #[doc = r" Read the CSR value as raw usize."]
6051 #[inline]
6052 pub fn read() -> usize {
6053 unsafe { _read() }
6054 }
6055 #[doc = r" Write the CSR value as raw usize."]
6056 #[inline]
6057 pub unsafe fn write(val: usize) {
6058 unsafe {
6059 _write(val);
6060 }
6061 }
6062}
6063#[doc = "CCTL command"]
6064pub mod ucctlcommand {
6065 #[inline(always)]
6066 unsafe fn _read() -> usize {
6067 let r: usize;
6068 unsafe {
6069 core :: arch :: asm ! ("csrrs {0}, 0x80c, x0" , out (reg) r);
6070 }
6071 r
6072 }
6073 #[inline(always)]
6074 unsafe fn _write(bits: usize) {
6075 unsafe {
6076 core :: arch :: asm ! ("csrrw x0, 0x80c, {0}" , in (reg) bits);
6077 }
6078 }
6079 #[inline(always)]
6080 unsafe fn _set(bits: usize) {
6081 unsafe {
6082 core :: arch :: asm ! ("csrrs x0, 0x80c, {0}" , in (reg) bits);
6083 }
6084 }
6085 #[inline(always)]
6086 unsafe fn _clear(bits: usize) {
6087 unsafe {
6088 core :: arch :: asm ! ("csrrc x0, 0x80c, {0}" , in (reg) bits);
6089 }
6090 }
6091 #[doc = r" Read the CSR value as raw usize."]
6092 #[inline]
6093 pub fn read() -> usize {
6094 unsafe { _read() }
6095 }
6096 #[doc = r" Write the CSR value as raw usize."]
6097 #[inline]
6098 pub unsafe fn write(val: usize) {
6099 unsafe {
6100 _write(val);
6101 }
6102 }
6103}
6104#[doc = "Wait for event control"]
6105pub mod wfe {
6106 #[doc = "Wait for Event Control Register"]
6107 #[repr(transparent)]
6108 #[derive(Copy, Clone, Eq, PartialEq)]
6109 pub struct Wfe(pub u32);
6110 impl Wfe {
6111 #[doc = "Wait for event"]
6112 #[must_use]
6113 #[inline(always)]
6114 pub const fn wfe(&self) -> bool {
6115 let val = (self.0 >> 0usize) & 0x01;
6116 val != 0
6117 }
6118 #[doc = "Wait for event"]
6119 #[inline(always)]
6120 pub const fn set_wfe(&mut self, val: bool) {
6121 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
6122 }
6123 }
6124 impl Default for Wfe {
6125 #[inline(always)]
6126 fn default() -> Wfe {
6127 Wfe(0)
6128 }
6129 }
6130 impl core::fmt::Debug for Wfe {
6131 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
6132 f.debug_struct("Wfe").field("wfe", &self.wfe()).finish()
6133 }
6134 }
6135 #[cfg(feature = "defmt")]
6136 impl defmt::Format for Wfe {
6137 fn format(&self, f: defmt::Formatter) {
6138 defmt::write!(f, "Wfe {{ wfe: {=bool:?} }}", self.wfe())
6139 }
6140 }
6141 #[inline(always)]
6142 unsafe fn _read() -> usize {
6143 let r: usize;
6144 unsafe {
6145 core :: arch :: asm ! ("csrrs {0}, 0x810, x0" , out (reg) r);
6146 }
6147 r
6148 }
6149 #[inline(always)]
6150 unsafe fn _write(bits: usize) {
6151 unsafe {
6152 core :: arch :: asm ! ("csrrw x0, 0x810, {0}" , in (reg) bits);
6153 }
6154 }
6155 #[inline(always)]
6156 unsafe fn _set(bits: usize) {
6157 unsafe {
6158 core :: arch :: asm ! ("csrrs x0, 0x810, {0}" , in (reg) bits);
6159 }
6160 }
6161 #[inline(always)]
6162 unsafe fn _clear(bits: usize) {
6163 unsafe {
6164 core :: arch :: asm ! ("csrrc x0, 0x810, {0}" , in (reg) bits);
6165 }
6166 }
6167 #[doc = r" Read the CSR value."]
6168 #[inline]
6169 pub fn read() -> Wfe {
6170 unsafe { Wfe(_read() as u32) }
6171 }
6172 #[doc = r" Write the CSR value."]
6173 #[inline]
6174 pub unsafe fn write(val: Wfe) {
6175 unsafe {
6176 _write(val.0 as usize);
6177 }
6178 }
6179 #[doc = r" Read-modify-write the CSR."]
6180 #[inline]
6181 pub unsafe fn modify<R>(f: impl FnOnce(&mut Wfe) -> R) -> R {
6182 let mut val = read();
6183 let res = f(&mut val);
6184 unsafe {
6185 write(val);
6186 }
6187 res
6188 }
6189 #[doc = "Wait for event"]
6190 #[inline]
6191 pub unsafe fn set_wfe() {
6192 unsafe {
6193 _set(1usize);
6194 }
6195 }
6196 #[doc = "Wait for event"]
6197 #[inline]
6198 pub unsafe fn clear_wfe() {
6199 unsafe {
6200 _clear(1usize);
6201 }
6202 }
6203}
6204#[doc = "Sleep value"]
6205pub mod sleepvalue {
6206 #[doc = "Sleep Value Register"]
6207 #[repr(transparent)]
6208 #[derive(Copy, Clone, Eq, PartialEq)]
6209 pub struct Sleepvalue(pub u32);
6210 impl Sleepvalue {
6211 #[doc = "Sleep value"]
6212 #[must_use]
6213 #[inline(always)]
6214 pub const fn sv(&self) -> bool {
6215 let val = (self.0 >> 0usize) & 0x01;
6216 val != 0
6217 }
6218 #[doc = "Sleep value"]
6219 #[inline(always)]
6220 pub const fn set_sv(&mut self, val: bool) {
6221 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
6222 }
6223 }
6224 impl Default for Sleepvalue {
6225 #[inline(always)]
6226 fn default() -> Sleepvalue {
6227 Sleepvalue(0)
6228 }
6229 }
6230 impl core::fmt::Debug for Sleepvalue {
6231 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
6232 f.debug_struct("Sleepvalue")
6233 .field("sv", &self.sv())
6234 .finish()
6235 }
6236 }
6237 #[cfg(feature = "defmt")]
6238 impl defmt::Format for Sleepvalue {
6239 fn format(&self, f: defmt::Formatter) {
6240 defmt::write!(f, "Sleepvalue {{ sv: {=bool:?} }}", self.sv())
6241 }
6242 }
6243 #[inline(always)]
6244 unsafe fn _read() -> usize {
6245 let r: usize;
6246 unsafe {
6247 core :: arch :: asm ! ("csrrs {0}, 0x811, x0" , out (reg) r);
6248 }
6249 r
6250 }
6251 #[inline(always)]
6252 unsafe fn _write(bits: usize) {
6253 unsafe {
6254 core :: arch :: asm ! ("csrrw x0, 0x811, {0}" , in (reg) bits);
6255 }
6256 }
6257 #[inline(always)]
6258 unsafe fn _set(bits: usize) {
6259 unsafe {
6260 core :: arch :: asm ! ("csrrs x0, 0x811, {0}" , in (reg) bits);
6261 }
6262 }
6263 #[inline(always)]
6264 unsafe fn _clear(bits: usize) {
6265 unsafe {
6266 core :: arch :: asm ! ("csrrc x0, 0x811, {0}" , in (reg) bits);
6267 }
6268 }
6269 #[doc = r" Read the CSR value."]
6270 #[inline]
6271 pub fn read() -> Sleepvalue {
6272 unsafe { Sleepvalue(_read() as u32) }
6273 }
6274 #[doc = r" Write the CSR value."]
6275 #[inline]
6276 pub unsafe fn write(val: Sleepvalue) {
6277 unsafe {
6278 _write(val.0 as usize);
6279 }
6280 }
6281 #[doc = r" Read-modify-write the CSR."]
6282 #[inline]
6283 pub unsafe fn modify<R>(f: impl FnOnce(&mut Sleepvalue) -> R) -> R {
6284 let mut val = read();
6285 let res = f(&mut val);
6286 unsafe {
6287 write(val);
6288 }
6289 res
6290 }
6291 #[doc = "Sleep value"]
6292 #[inline]
6293 pub unsafe fn set_sv() {
6294 unsafe {
6295 _set(1usize);
6296 }
6297 }
6298 #[doc = "Sleep value"]
6299 #[inline]
6300 pub unsafe fn clear_sv() {
6301 unsafe {
6302 _clear(1usize);
6303 }
6304 }
6305}
6306#[doc = "Transmit event"]
6307pub mod txevt {
6308 #[doc = "Transmit Event Register"]
6309 #[repr(transparent)]
6310 #[derive(Copy, Clone, Eq, PartialEq)]
6311 pub struct Txevt(pub u32);
6312 impl Txevt {
6313 #[doc = "Event output"]
6314 #[must_use]
6315 #[inline(always)]
6316 pub const fn evto(&self) -> bool {
6317 let val = (self.0 >> 0usize) & 0x01;
6318 val != 0
6319 }
6320 #[doc = "Event output"]
6321 #[inline(always)]
6322 pub const fn set_evto(&mut self, val: bool) {
6323 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
6324 }
6325 }
6326 impl Default for Txevt {
6327 #[inline(always)]
6328 fn default() -> Txevt {
6329 Txevt(0)
6330 }
6331 }
6332 impl core::fmt::Debug for Txevt {
6333 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
6334 f.debug_struct("Txevt").field("evto", &self.evto()).finish()
6335 }
6336 }
6337 #[cfg(feature = "defmt")]
6338 impl defmt::Format for Txevt {
6339 fn format(&self, f: defmt::Formatter) {
6340 defmt::write!(f, "Txevt {{ evto: {=bool:?} }}", self.evto())
6341 }
6342 }
6343 #[inline(always)]
6344 unsafe fn _read() -> usize {
6345 let r: usize;
6346 unsafe {
6347 core :: arch :: asm ! ("csrrs {0}, 0x812, x0" , out (reg) r);
6348 }
6349 r
6350 }
6351 #[inline(always)]
6352 unsafe fn _write(bits: usize) {
6353 unsafe {
6354 core :: arch :: asm ! ("csrrw x0, 0x812, {0}" , in (reg) bits);
6355 }
6356 }
6357 #[inline(always)]
6358 unsafe fn _set(bits: usize) {
6359 unsafe {
6360 core :: arch :: asm ! ("csrrs x0, 0x812, {0}" , in (reg) bits);
6361 }
6362 }
6363 #[inline(always)]
6364 unsafe fn _clear(bits: usize) {
6365 unsafe {
6366 core :: arch :: asm ! ("csrrc x0, 0x812, {0}" , in (reg) bits);
6367 }
6368 }
6369 #[doc = r" Read the CSR value."]
6370 #[inline]
6371 pub fn read() -> Txevt {
6372 unsafe { Txevt(_read() as u32) }
6373 }
6374 #[doc = r" Write the CSR value."]
6375 #[inline]
6376 pub unsafe fn write(val: Txevt) {
6377 unsafe {
6378 _write(val.0 as usize);
6379 }
6380 }
6381 #[doc = r" Read-modify-write the CSR."]
6382 #[inline]
6383 pub unsafe fn modify<R>(f: impl FnOnce(&mut Txevt) -> R) -> R {
6384 let mut val = read();
6385 let res = f(&mut val);
6386 unsafe {
6387 write(val);
6388 }
6389 res
6390 }
6391 #[doc = "Event output"]
6392 #[inline]
6393 pub unsafe fn set_evto() {
6394 unsafe {
6395 _set(1usize);
6396 }
6397 }
6398 #[doc = "Event output"]
6399 #[inline]
6400 pub unsafe fn clear_evto() {
6401 unsafe {
6402 _clear(1usize);
6403 }
6404 }
6405}
6406#[doc = "Supervisor local interrupt enable"]
6407pub mod slie {
6408 #[doc = "Supervisor Local Interrupt Enable"]
6409 #[repr(transparent)]
6410 #[derive(Copy, Clone, Eq, PartialEq)]
6411 pub struct Slie(pub u32);
6412 impl Slie {
6413 #[doc = "Enable S-mode slave-port ECC error local interrupt"]
6414 #[must_use]
6415 #[inline(always)]
6416 pub const fn imecci(&self) -> bool {
6417 let val = (self.0 >> 16usize) & 0x01;
6418 val != 0
6419 }
6420 #[doc = "Enable S-mode slave-port ECC error local interrupt"]
6421 #[inline(always)]
6422 pub const fn set_imecci(&mut self, val: bool) {
6423 self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
6424 }
6425 #[doc = "Enable S-mode bus read/write transaction error local interrupt"]
6426 #[must_use]
6427 #[inline(always)]
6428 pub const fn bwei(&self) -> bool {
6429 let val = (self.0 >> 17usize) & 0x01;
6430 val != 0
6431 }
6432 #[doc = "Enable S-mode bus read/write transaction error local interrupt"]
6433 #[inline(always)]
6434 pub const fn set_bwei(&mut self, val: bool) {
6435 self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
6436 }
6437 #[doc = "Enable S-mode performance monitor overflow local interrupt"]
6438 #[must_use]
6439 #[inline(always)]
6440 pub const fn pmovi(&self) -> bool {
6441 let val = (self.0 >> 18usize) & 0x01;
6442 val != 0
6443 }
6444 #[doc = "Enable S-mode performance monitor overflow local interrupt"]
6445 #[inline(always)]
6446 pub const fn set_pmovi(&mut self, val: bool) {
6447 self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
6448 }
6449 #[doc = "Enable S-mode ECC DMR error local interrupt"]
6450 #[must_use]
6451 #[inline(always)]
6452 pub const fn imeccdmr(&self) -> bool {
6453 let val = (self.0 >> 19usize) & 0x01;
6454 val != 0
6455 }
6456 #[doc = "Enable S-mode ECC DMR error local interrupt"]
6457 #[inline(always)]
6458 pub const fn set_imeccdmr(&mut self, val: bool) {
6459 self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
6460 }
6461 #[doc = "Enable S-mode ACE error local interrupt"]
6462 #[must_use]
6463 #[inline(always)]
6464 pub const fn aceerr(&self) -> bool {
6465 let val = (self.0 >> 24usize) & 0x01;
6466 val != 0
6467 }
6468 #[doc = "Enable S-mode ACE error local interrupt"]
6469 #[inline(always)]
6470 pub const fn set_aceerr(&mut self, val: bool) {
6471 self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
6472 }
6473 }
6474 impl Default for Slie {
6475 #[inline(always)]
6476 fn default() -> Slie {
6477 Slie(0)
6478 }
6479 }
6480 impl core::fmt::Debug for Slie {
6481 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
6482 f.debug_struct("Slie")
6483 .field("imecci", &self.imecci())
6484 .field("bwei", &self.bwei())
6485 .field("pmovi", &self.pmovi())
6486 .field("imeccdmr", &self.imeccdmr())
6487 .field("aceerr", &self.aceerr())
6488 .finish()
6489 }
6490 }
6491 #[cfg(feature = "defmt")]
6492 impl defmt::Format for Slie {
6493 fn format(&self, f: defmt::Formatter) {
6494 defmt::write!(
6495 f,
6496 "Slie {{ imecci: {=bool:?}, bwei: {=bool:?}, pmovi: {=bool:?}, imeccdmr: {=bool:?}, aceerr: {=bool:?} }}",
6497 self.imecci(),
6498 self.bwei(),
6499 self.pmovi(),
6500 self.imeccdmr(),
6501 self.aceerr()
6502 )
6503 }
6504 }
6505 #[inline(always)]
6506 unsafe fn _read() -> usize {
6507 let r: usize;
6508 unsafe {
6509 core :: arch :: asm ! ("csrrs {0}, 0x9c4, x0" , out (reg) r);
6510 }
6511 r
6512 }
6513 #[inline(always)]
6514 unsafe fn _write(bits: usize) {
6515 unsafe {
6516 core :: arch :: asm ! ("csrrw x0, 0x9c4, {0}" , in (reg) bits);
6517 }
6518 }
6519 #[inline(always)]
6520 unsafe fn _set(bits: usize) {
6521 unsafe {
6522 core :: arch :: asm ! ("csrrs x0, 0x9c4, {0}" , in (reg) bits);
6523 }
6524 }
6525 #[inline(always)]
6526 unsafe fn _clear(bits: usize) {
6527 unsafe {
6528 core :: arch :: asm ! ("csrrc x0, 0x9c4, {0}" , in (reg) bits);
6529 }
6530 }
6531 #[doc = r" Read the CSR value."]
6532 #[inline]
6533 pub fn read() -> Slie {
6534 unsafe { Slie(_read() as u32) }
6535 }
6536 #[doc = r" Write the CSR value."]
6537 #[inline]
6538 pub unsafe fn write(val: Slie) {
6539 unsafe {
6540 _write(val.0 as usize);
6541 }
6542 }
6543 #[doc = r" Read-modify-write the CSR."]
6544 #[inline]
6545 pub unsafe fn modify<R>(f: impl FnOnce(&mut Slie) -> R) -> R {
6546 let mut val = read();
6547 let res = f(&mut val);
6548 unsafe {
6549 write(val);
6550 }
6551 res
6552 }
6553 #[doc = "Enable S-mode slave-port ECC error local interrupt"]
6554 #[inline]
6555 pub unsafe fn set_imecci() {
6556 unsafe {
6557 _set(65536usize);
6558 }
6559 }
6560 #[doc = "Enable S-mode slave-port ECC error local interrupt"]
6561 #[inline]
6562 pub unsafe fn clear_imecci() {
6563 unsafe {
6564 _clear(65536usize);
6565 }
6566 }
6567 #[doc = "Enable S-mode bus read/write transaction error local interrupt"]
6568 #[inline]
6569 pub unsafe fn set_bwei() {
6570 unsafe {
6571 _set(131072usize);
6572 }
6573 }
6574 #[doc = "Enable S-mode bus read/write transaction error local interrupt"]
6575 #[inline]
6576 pub unsafe fn clear_bwei() {
6577 unsafe {
6578 _clear(131072usize);
6579 }
6580 }
6581 #[doc = "Enable S-mode performance monitor overflow local interrupt"]
6582 #[inline]
6583 pub unsafe fn set_pmovi() {
6584 unsafe {
6585 _set(262144usize);
6586 }
6587 }
6588 #[doc = "Enable S-mode performance monitor overflow local interrupt"]
6589 #[inline]
6590 pub unsafe fn clear_pmovi() {
6591 unsafe {
6592 _clear(262144usize);
6593 }
6594 }
6595 #[doc = "Enable S-mode ECC DMR error local interrupt"]
6596 #[inline]
6597 pub unsafe fn set_imeccdmr() {
6598 unsafe {
6599 _set(524288usize);
6600 }
6601 }
6602 #[doc = "Enable S-mode ECC DMR error local interrupt"]
6603 #[inline]
6604 pub unsafe fn clear_imeccdmr() {
6605 unsafe {
6606 _clear(524288usize);
6607 }
6608 }
6609 #[doc = "Enable S-mode ACE error local interrupt"]
6610 #[inline]
6611 pub unsafe fn set_aceerr() {
6612 unsafe {
6613 _set(16777216usize);
6614 }
6615 }
6616 #[doc = "Enable S-mode ACE error local interrupt"]
6617 #[inline]
6618 pub unsafe fn clear_aceerr() {
6619 unsafe {
6620 _clear(16777216usize);
6621 }
6622 }
6623}
6624#[doc = "Supervisor local interrupt pending"]
6625pub mod slip {
6626 #[doc = "Supervisor Local Interrupt Pending"]
6627 #[repr(transparent)]
6628 #[derive(Copy, Clone, Eq, PartialEq)]
6629 pub struct Slip(pub u32);
6630 impl Slip {
6631 #[must_use]
6632 #[inline(always)]
6633 pub const fn imecci(&self) -> bool {
6634 let val = (self.0 >> 16usize) & 0x01;
6635 val != 0
6636 }
6637 #[inline(always)]
6638 pub const fn set_imecci(&mut self, val: bool) {
6639 self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
6640 }
6641 #[must_use]
6642 #[inline(always)]
6643 pub const fn bwei(&self) -> bool {
6644 let val = (self.0 >> 17usize) & 0x01;
6645 val != 0
6646 }
6647 #[inline(always)]
6648 pub const fn set_bwei(&mut self, val: bool) {
6649 self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
6650 }
6651 #[must_use]
6652 #[inline(always)]
6653 pub const fn pmovi(&self) -> bool {
6654 let val = (self.0 >> 18usize) & 0x01;
6655 val != 0
6656 }
6657 #[inline(always)]
6658 pub const fn set_pmovi(&mut self, val: bool) {
6659 self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
6660 }
6661 #[must_use]
6662 #[inline(always)]
6663 pub const fn imeccdmr(&self) -> bool {
6664 let val = (self.0 >> 19usize) & 0x01;
6665 val != 0
6666 }
6667 #[inline(always)]
6668 pub const fn set_imeccdmr(&mut self, val: bool) {
6669 self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
6670 }
6671 #[must_use]
6672 #[inline(always)]
6673 pub const fn aceerr(&self) -> bool {
6674 let val = (self.0 >> 24usize) & 0x01;
6675 val != 0
6676 }
6677 #[inline(always)]
6678 pub const fn set_aceerr(&mut self, val: bool) {
6679 self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
6680 }
6681 }
6682 impl Default for Slip {
6683 #[inline(always)]
6684 fn default() -> Slip {
6685 Slip(0)
6686 }
6687 }
6688 impl core::fmt::Debug for Slip {
6689 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
6690 f.debug_struct("Slip")
6691 .field("imecci", &self.imecci())
6692 .field("bwei", &self.bwei())
6693 .field("pmovi", &self.pmovi())
6694 .field("imeccdmr", &self.imeccdmr())
6695 .field("aceerr", &self.aceerr())
6696 .finish()
6697 }
6698 }
6699 #[cfg(feature = "defmt")]
6700 impl defmt::Format for Slip {
6701 fn format(&self, f: defmt::Formatter) {
6702 defmt::write!(
6703 f,
6704 "Slip {{ imecci: {=bool:?}, bwei: {=bool:?}, pmovi: {=bool:?}, imeccdmr: {=bool:?}, aceerr: {=bool:?} }}",
6705 self.imecci(),
6706 self.bwei(),
6707 self.pmovi(),
6708 self.imeccdmr(),
6709 self.aceerr()
6710 )
6711 }
6712 }
6713 #[inline(always)]
6714 unsafe fn _read() -> usize {
6715 let r: usize;
6716 unsafe {
6717 core :: arch :: asm ! ("csrrs {0}, 0x9c5, x0" , out (reg) r);
6718 }
6719 r
6720 }
6721 #[inline(always)]
6722 unsafe fn _write(bits: usize) {
6723 unsafe {
6724 core :: arch :: asm ! ("csrrw x0, 0x9c5, {0}" , in (reg) bits);
6725 }
6726 }
6727 #[inline(always)]
6728 unsafe fn _set(bits: usize) {
6729 unsafe {
6730 core :: arch :: asm ! ("csrrs x0, 0x9c5, {0}" , in (reg) bits);
6731 }
6732 }
6733 #[inline(always)]
6734 unsafe fn _clear(bits: usize) {
6735 unsafe {
6736 core :: arch :: asm ! ("csrrc x0, 0x9c5, {0}" , in (reg) bits);
6737 }
6738 }
6739 #[doc = r" Read the CSR value."]
6740 #[inline]
6741 pub fn read() -> Slip {
6742 unsafe { Slip(_read() as u32) }
6743 }
6744 #[doc = r" Write the CSR value."]
6745 #[inline]
6746 pub unsafe fn write(val: Slip) {
6747 unsafe {
6748 _write(val.0 as usize);
6749 }
6750 }
6751 #[doc = r" Read-modify-write the CSR."]
6752 #[inline]
6753 pub unsafe fn modify<R>(f: impl FnOnce(&mut Slip) -> R) -> R {
6754 let mut val = read();
6755 let res = f(&mut val);
6756 unsafe {
6757 write(val);
6758 }
6759 res
6760 }
6761 #[inline]
6762 pub unsafe fn set_imecci() {
6763 unsafe {
6764 _set(65536usize);
6765 }
6766 }
6767 #[inline]
6768 pub unsafe fn clear_imecci() {
6769 unsafe {
6770 _clear(65536usize);
6771 }
6772 }
6773 #[inline]
6774 pub unsafe fn set_bwei() {
6775 unsafe {
6776 _set(131072usize);
6777 }
6778 }
6779 #[inline]
6780 pub unsafe fn clear_bwei() {
6781 unsafe {
6782 _clear(131072usize);
6783 }
6784 }
6785 #[inline]
6786 pub unsafe fn set_pmovi() {
6787 unsafe {
6788 _set(262144usize);
6789 }
6790 }
6791 #[inline]
6792 pub unsafe fn clear_pmovi() {
6793 unsafe {
6794 _clear(262144usize);
6795 }
6796 }
6797 #[inline]
6798 pub unsafe fn set_imeccdmr() {
6799 unsafe {
6800 _set(524288usize);
6801 }
6802 }
6803 #[inline]
6804 pub unsafe fn clear_imeccdmr() {
6805 unsafe {
6806 _clear(524288usize);
6807 }
6808 }
6809 #[inline]
6810 pub unsafe fn set_aceerr() {
6811 unsafe {
6812 _set(16777216usize);
6813 }
6814 }
6815 #[inline]
6816 pub unsafe fn clear_aceerr() {
6817 unsafe {
6818 _clear(16777216usize);
6819 }
6820 }
6821}
6822#[doc = "Detailed exception cause"]
6823pub mod sdcause {
6824 #[doc = "Supervisor Detailed Cause (for imprecise exception/interrupt)"]
6825 #[repr(transparent)]
6826 #[derive(Copy, Clone, Eq, PartialEq)]
6827 pub struct Sdcause(pub u32);
6828 impl Sdcause {
6829 #[doc = "Detailed cause for imprecise exception"]
6830 #[must_use]
6831 #[inline(always)]
6832 pub const fn sdcause(&self) -> u8 {
6833 let val = (self.0 >> 0usize) & 0x1f;
6834 val as u8
6835 }
6836 #[doc = "Detailed cause for imprecise exception"]
6837 #[inline(always)]
6838 pub const fn set_sdcause(&mut self, val: u8) {
6839 self.0 = (self.0 & !(0x1f << 0usize)) | (((val as u32) & 0x1f) << 0usize);
6840 }
6841 #[doc = "Privilege Mode"]
6842 #[must_use]
6843 #[inline(always)]
6844 pub const fn pm(&self) -> u8 {
6845 let val = (self.0 >> 5usize) & 0x03;
6846 val as u8
6847 }
6848 #[doc = "Privilege Mode"]
6849 #[inline(always)]
6850 pub const fn set_pm(&mut self, val: u8) {
6851 self.0 = (self.0 & !(0x03 << 5usize)) | (((val as u32) & 0x03) << 5usize);
6852 }
6853 }
6854 impl Default for Sdcause {
6855 #[inline(always)]
6856 fn default() -> Sdcause {
6857 Sdcause(0)
6858 }
6859 }
6860 impl core::fmt::Debug for Sdcause {
6861 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
6862 f.debug_struct("Sdcause")
6863 .field("sdcause", &self.sdcause())
6864 .field("pm", &self.pm())
6865 .finish()
6866 }
6867 }
6868 #[cfg(feature = "defmt")]
6869 impl defmt::Format for Sdcause {
6870 fn format(&self, f: defmt::Formatter) {
6871 defmt::write!(
6872 f,
6873 "Sdcause {{ sdcause: {=u8:?}, pm: {=u8:?} }}",
6874 self.sdcause(),
6875 self.pm()
6876 )
6877 }
6878 }
6879 #[inline(always)]
6880 unsafe fn _read() -> usize {
6881 let r: usize;
6882 unsafe {
6883 core :: arch :: asm ! ("csrrs {0}, 0x9c9, x0" , out (reg) r);
6884 }
6885 r
6886 }
6887 #[inline(always)]
6888 unsafe fn _write(bits: usize) {
6889 unsafe {
6890 core :: arch :: asm ! ("csrrw x0, 0x9c9, {0}" , in (reg) bits);
6891 }
6892 }
6893 #[inline(always)]
6894 unsafe fn _set(bits: usize) {
6895 unsafe {
6896 core :: arch :: asm ! ("csrrs x0, 0x9c9, {0}" , in (reg) bits);
6897 }
6898 }
6899 #[inline(always)]
6900 unsafe fn _clear(bits: usize) {
6901 unsafe {
6902 core :: arch :: asm ! ("csrrc x0, 0x9c9, {0}" , in (reg) bits);
6903 }
6904 }
6905 #[doc = r" Read the CSR value."]
6906 #[inline]
6907 pub fn read() -> Sdcause {
6908 unsafe { Sdcause(_read() as u32) }
6909 }
6910 #[doc = r" Write the CSR value."]
6911 #[inline]
6912 pub unsafe fn write(val: Sdcause) {
6913 unsafe {
6914 _write(val.0 as usize);
6915 }
6916 }
6917 #[doc = r" Read-modify-write the CSR."]
6918 #[inline]
6919 pub unsafe fn modify<R>(f: impl FnOnce(&mut Sdcause) -> R) -> R {
6920 let mut val = read();
6921 let res = f(&mut val);
6922 unsafe {
6923 write(val);
6924 }
6925 res
6926 }
6927 #[doc = "Detailed cause for imprecise exception"]
6928 #[inline]
6929 pub unsafe fn set_sdcause(val: u8) {
6930 let mut bits = unsafe { _read() };
6931 bits &= !(31usize << 0usize);
6932 bits |= (val as usize & 31usize) << 0usize;
6933 unsafe {
6934 _write(bits);
6935 }
6936 }
6937 #[doc = "Privilege Mode"]
6938 #[inline]
6939 pub unsafe fn set_pm(val: u8) {
6940 let mut bits = unsafe { _read() };
6941 bits &= !(3usize << 5usize);
6942 bits |= (val as usize & 3usize) << 5usize;
6943 unsafe {
6944 _write(bits);
6945 }
6946 }
6947}
6948#[doc = "CCTL data"]
6949pub mod scctldata {
6950 #[inline(always)]
6951 unsafe fn _read() -> usize {
6952 let r: usize;
6953 unsafe {
6954 core :: arch :: asm ! ("csrrs {0}, 0x9cd, x0" , out (reg) r);
6955 }
6956 r
6957 }
6958 #[inline(always)]
6959 unsafe fn _write(bits: usize) {
6960 unsafe {
6961 core :: arch :: asm ! ("csrrw x0, 0x9cd, {0}" , in (reg) bits);
6962 }
6963 }
6964 #[inline(always)]
6965 unsafe fn _set(bits: usize) {
6966 unsafe {
6967 core :: arch :: asm ! ("csrrs x0, 0x9cd, {0}" , in (reg) bits);
6968 }
6969 }
6970 #[inline(always)]
6971 unsafe fn _clear(bits: usize) {
6972 unsafe {
6973 core :: arch :: asm ! ("csrrc x0, 0x9cd, {0}" , in (reg) bits);
6974 }
6975 }
6976 #[doc = r" Read the CSR value as raw usize."]
6977 #[inline]
6978 pub fn read() -> usize {
6979 unsafe { _read() }
6980 }
6981 #[doc = r" Write the CSR value as raw usize."]
6982 #[inline]
6983 pub unsafe fn write(val: usize) {
6984 unsafe {
6985 _write(val);
6986 }
6987 }
6988}
6989#[doc = "Counter overflow interrupt enable"]
6990pub mod scounterinten {
6991 #[doc = "Machine Counter Fields"]
6992 #[repr(transparent)]
6993 #[derive(Copy, Clone, Eq, PartialEq)]
6994 pub struct ScounterCommon(pub u32);
6995 impl ScounterCommon {
6996 #[doc = "Cycle counter"]
6997 #[must_use]
6998 #[inline(always)]
6999 pub const fn cy(&self) -> bool {
7000 let val = (self.0 >> 0usize) & 0x01;
7001 val != 0
7002 }
7003 #[doc = "Cycle counter"]
7004 #[inline(always)]
7005 pub const fn set_cy(&mut self, val: bool) {
7006 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
7007 }
7008 #[doc = "Instruction retired counter"]
7009 #[must_use]
7010 #[inline(always)]
7011 pub const fn ir(&self) -> bool {
7012 let val = (self.0 >> 2usize) & 0x01;
7013 val != 0
7014 }
7015 #[doc = "Instruction retired counter"]
7016 #[inline(always)]
7017 pub const fn set_ir(&mut self, val: bool) {
7018 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
7019 }
7020 #[doc = "Hardware performance monitor 3 to 31"]
7021 #[must_use]
7022 #[inline(always)]
7023 pub const fn hpm(&self, n: usize) -> bool {
7024 assert!(n < 29usize);
7025 let offs = 3usize + n * 1usize;
7026 let val = (self.0 >> offs) & 0x01;
7027 val != 0
7028 }
7029 #[doc = "Hardware performance monitor 3 to 31"]
7030 #[inline(always)]
7031 pub const fn set_hpm(&mut self, n: usize, val: bool) {
7032 assert!(n < 29usize);
7033 let offs = 3usize + n * 1usize;
7034 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
7035 }
7036 }
7037 impl Default for ScounterCommon {
7038 #[inline(always)]
7039 fn default() -> ScounterCommon {
7040 ScounterCommon(0)
7041 }
7042 }
7043 impl core::fmt::Debug for ScounterCommon {
7044 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
7045 f.debug_struct("ScounterCommon")
7046 .field("cy", &self.cy())
7047 .field("ir", &self.ir())
7048 .field("hpm[0]", &self.hpm(0usize))
7049 .field("hpm[1]", &self.hpm(1usize))
7050 .field("hpm[2]", &self.hpm(2usize))
7051 .field("hpm[3]", &self.hpm(3usize))
7052 .field("hpm[4]", &self.hpm(4usize))
7053 .field("hpm[5]", &self.hpm(5usize))
7054 .field("hpm[6]", &self.hpm(6usize))
7055 .field("hpm[7]", &self.hpm(7usize))
7056 .field("hpm[8]", &self.hpm(8usize))
7057 .field("hpm[9]", &self.hpm(9usize))
7058 .field("hpm[10]", &self.hpm(10usize))
7059 .field("hpm[11]", &self.hpm(11usize))
7060 .field("hpm[12]", &self.hpm(12usize))
7061 .field("hpm[13]", &self.hpm(13usize))
7062 .field("hpm[14]", &self.hpm(14usize))
7063 .field("hpm[15]", &self.hpm(15usize))
7064 .field("hpm[16]", &self.hpm(16usize))
7065 .field("hpm[17]", &self.hpm(17usize))
7066 .field("hpm[18]", &self.hpm(18usize))
7067 .field("hpm[19]", &self.hpm(19usize))
7068 .field("hpm[20]", &self.hpm(20usize))
7069 .field("hpm[21]", &self.hpm(21usize))
7070 .field("hpm[22]", &self.hpm(22usize))
7071 .field("hpm[23]", &self.hpm(23usize))
7072 .field("hpm[24]", &self.hpm(24usize))
7073 .field("hpm[25]", &self.hpm(25usize))
7074 .field("hpm[26]", &self.hpm(26usize))
7075 .field("hpm[27]", &self.hpm(27usize))
7076 .field("hpm[28]", &self.hpm(28usize))
7077 .finish()
7078 }
7079 }
7080 #[cfg(feature = "defmt")]
7081 impl defmt::Format for ScounterCommon {
7082 fn format(&self, f: defmt::Formatter) {
7083 defmt::write!(
7084 f,
7085 "ScounterCommon {{ cy: {=bool:?}, ir: {=bool:?}, hpm[0]: {=bool:?}, hpm[1]: {=bool:?}, hpm[2]: {=bool:?}, hpm[3]: {=bool:?}, hpm[4]: {=bool:?}, hpm[5]: {=bool:?}, hpm[6]: {=bool:?}, hpm[7]: {=bool:?}, hpm[8]: {=bool:?}, hpm[9]: {=bool:?}, hpm[10]: {=bool:?}, hpm[11]: {=bool:?}, hpm[12]: {=bool:?}, hpm[13]: {=bool:?}, hpm[14]: {=bool:?}, hpm[15]: {=bool:?}, hpm[16]: {=bool:?}, hpm[17]: {=bool:?}, hpm[18]: {=bool:?}, hpm[19]: {=bool:?}, hpm[20]: {=bool:?}, hpm[21]: {=bool:?}, hpm[22]: {=bool:?}, hpm[23]: {=bool:?}, hpm[24]: {=bool:?}, hpm[25]: {=bool:?}, hpm[26]: {=bool:?}, hpm[27]: {=bool:?}, hpm[28]: {=bool:?} }}",
7086 self.cy(),
7087 self.ir(),
7088 self.hpm(0usize),
7089 self.hpm(1usize),
7090 self.hpm(2usize),
7091 self.hpm(3usize),
7092 self.hpm(4usize),
7093 self.hpm(5usize),
7094 self.hpm(6usize),
7095 self.hpm(7usize),
7096 self.hpm(8usize),
7097 self.hpm(9usize),
7098 self.hpm(10usize),
7099 self.hpm(11usize),
7100 self.hpm(12usize),
7101 self.hpm(13usize),
7102 self.hpm(14usize),
7103 self.hpm(15usize),
7104 self.hpm(16usize),
7105 self.hpm(17usize),
7106 self.hpm(18usize),
7107 self.hpm(19usize),
7108 self.hpm(20usize),
7109 self.hpm(21usize),
7110 self.hpm(22usize),
7111 self.hpm(23usize),
7112 self.hpm(24usize),
7113 self.hpm(25usize),
7114 self.hpm(26usize),
7115 self.hpm(27usize),
7116 self.hpm(28usize)
7117 )
7118 }
7119 }
7120 #[inline(always)]
7121 unsafe fn _read() -> usize {
7122 let r: usize;
7123 unsafe {
7124 core :: arch :: asm ! ("csrrs {0}, 0x9cf, x0" , out (reg) r);
7125 }
7126 r
7127 }
7128 #[inline(always)]
7129 unsafe fn _write(bits: usize) {
7130 unsafe {
7131 core :: arch :: asm ! ("csrrw x0, 0x9cf, {0}" , in (reg) bits);
7132 }
7133 }
7134 #[inline(always)]
7135 unsafe fn _set(bits: usize) {
7136 unsafe {
7137 core :: arch :: asm ! ("csrrs x0, 0x9cf, {0}" , in (reg) bits);
7138 }
7139 }
7140 #[inline(always)]
7141 unsafe fn _clear(bits: usize) {
7142 unsafe {
7143 core :: arch :: asm ! ("csrrc x0, 0x9cf, {0}" , in (reg) bits);
7144 }
7145 }
7146 #[doc = r" Read the CSR value."]
7147 #[inline]
7148 pub fn read() -> ScounterCommon {
7149 unsafe { ScounterCommon(_read() as u32) }
7150 }
7151 #[doc = r" Write the CSR value."]
7152 #[inline]
7153 pub unsafe fn write(val: ScounterCommon) {
7154 unsafe {
7155 _write(val.0 as usize);
7156 }
7157 }
7158 #[doc = r" Read-modify-write the CSR."]
7159 #[inline]
7160 pub unsafe fn modify<R>(f: impl FnOnce(&mut ScounterCommon) -> R) -> R {
7161 let mut val = read();
7162 let res = f(&mut val);
7163 unsafe {
7164 write(val);
7165 }
7166 res
7167 }
7168 #[doc = "Cycle counter"]
7169 #[inline]
7170 pub unsafe fn set_cy() {
7171 unsafe {
7172 _set(1usize);
7173 }
7174 }
7175 #[doc = "Cycle counter"]
7176 #[inline]
7177 pub unsafe fn clear_cy() {
7178 unsafe {
7179 _clear(1usize);
7180 }
7181 }
7182 #[doc = "Instruction retired counter"]
7183 #[inline]
7184 pub unsafe fn set_ir() {
7185 unsafe {
7186 _set(4usize);
7187 }
7188 }
7189 #[doc = "Instruction retired counter"]
7190 #[inline]
7191 pub unsafe fn clear_ir() {
7192 unsafe {
7193 _clear(4usize);
7194 }
7195 }
7196}
7197#[doc = "Miscellaneous control"]
7198pub mod smisc_ctl {
7199 #[doc = "Supervisor Miscellaneous Control Register"]
7200 #[repr(transparent)]
7201 #[derive(Copy, Clone, Eq, PartialEq)]
7202 pub struct SmiscCtl(pub u32);
7203 impl SmiscCtl {
7204 #[doc = "ACE (Access Control Extension) Status"]
7205 #[must_use]
7206 #[inline(always)]
7207 pub const fn aces(&self) -> super::vals::Aces {
7208 let val = (self.0 >> 4usize) & 0x03;
7209 super::vals::Aces::from_bits(val as u8)
7210 }
7211 #[doc = "ACE (Access Control Extension) Status"]
7212 #[inline(always)]
7213 pub const fn set_aces(&mut self, val: super::vals::Aces) {
7214 self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize);
7215 }
7216 }
7217 impl Default for SmiscCtl {
7218 #[inline(always)]
7219 fn default() -> SmiscCtl {
7220 SmiscCtl(0)
7221 }
7222 }
7223 impl core::fmt::Debug for SmiscCtl {
7224 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
7225 f.debug_struct("SmiscCtl")
7226 .field("aces", &self.aces())
7227 .finish()
7228 }
7229 }
7230 #[cfg(feature = "defmt")]
7231 impl defmt::Format for SmiscCtl {
7232 fn format(&self, f: defmt::Formatter) {
7233 defmt::write!(f, "SmiscCtl {{ aces: {:?} }}", self.aces())
7234 }
7235 }
7236 #[inline(always)]
7237 unsafe fn _read() -> usize {
7238 let r: usize;
7239 unsafe {
7240 core :: arch :: asm ! ("csrrs {0}, 0x9d0, x0" , out (reg) r);
7241 }
7242 r
7243 }
7244 #[inline(always)]
7245 unsafe fn _write(bits: usize) {
7246 unsafe {
7247 core :: arch :: asm ! ("csrrw x0, 0x9d0, {0}" , in (reg) bits);
7248 }
7249 }
7250 #[inline(always)]
7251 unsafe fn _set(bits: usize) {
7252 unsafe {
7253 core :: arch :: asm ! ("csrrs x0, 0x9d0, {0}" , in (reg) bits);
7254 }
7255 }
7256 #[inline(always)]
7257 unsafe fn _clear(bits: usize) {
7258 unsafe {
7259 core :: arch :: asm ! ("csrrc x0, 0x9d0, {0}" , in (reg) bits);
7260 }
7261 }
7262 #[doc = r" Read the CSR value."]
7263 #[inline]
7264 pub fn read() -> SmiscCtl {
7265 unsafe { SmiscCtl(_read() as u32) }
7266 }
7267 #[doc = r" Write the CSR value."]
7268 #[inline]
7269 pub unsafe fn write(val: SmiscCtl) {
7270 unsafe {
7271 _write(val.0 as usize);
7272 }
7273 }
7274 #[doc = r" Read-modify-write the CSR."]
7275 #[inline]
7276 pub unsafe fn modify<R>(f: impl FnOnce(&mut SmiscCtl) -> R) -> R {
7277 let mut val = read();
7278 let res = f(&mut val);
7279 unsafe {
7280 write(val);
7281 }
7282 res
7283 }
7284 #[doc = "ACE (Access Control Extension) Status"]
7285 #[inline]
7286 pub unsafe fn set_aces(val: super::vals::Aces) {
7287 let mut bits = unsafe { _read() };
7288 bits &= !(3usize << 4usize);
7289 bits |= (val.to_bits() as usize & 3usize) << 4usize;
7290 unsafe {
7291 _write(bits);
7292 }
7293 }
7294}
7295#[doc = "Counter mask for M-mode"]
7296pub mod scountermask_m {
7297 #[doc = "Machine Counter Fields"]
7298 #[repr(transparent)]
7299 #[derive(Copy, Clone, Eq, PartialEq)]
7300 pub struct ScounterCommon(pub u32);
7301 impl ScounterCommon {
7302 #[doc = "Cycle counter"]
7303 #[must_use]
7304 #[inline(always)]
7305 pub const fn cy(&self) -> bool {
7306 let val = (self.0 >> 0usize) & 0x01;
7307 val != 0
7308 }
7309 #[doc = "Cycle counter"]
7310 #[inline(always)]
7311 pub const fn set_cy(&mut self, val: bool) {
7312 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
7313 }
7314 #[doc = "Instruction retired counter"]
7315 #[must_use]
7316 #[inline(always)]
7317 pub const fn ir(&self) -> bool {
7318 let val = (self.0 >> 2usize) & 0x01;
7319 val != 0
7320 }
7321 #[doc = "Instruction retired counter"]
7322 #[inline(always)]
7323 pub const fn set_ir(&mut self, val: bool) {
7324 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
7325 }
7326 #[doc = "Hardware performance monitor 3 to 31"]
7327 #[must_use]
7328 #[inline(always)]
7329 pub const fn hpm(&self, n: usize) -> bool {
7330 assert!(n < 29usize);
7331 let offs = 3usize + n * 1usize;
7332 let val = (self.0 >> offs) & 0x01;
7333 val != 0
7334 }
7335 #[doc = "Hardware performance monitor 3 to 31"]
7336 #[inline(always)]
7337 pub const fn set_hpm(&mut self, n: usize, val: bool) {
7338 assert!(n < 29usize);
7339 let offs = 3usize + n * 1usize;
7340 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
7341 }
7342 }
7343 impl Default for ScounterCommon {
7344 #[inline(always)]
7345 fn default() -> ScounterCommon {
7346 ScounterCommon(0)
7347 }
7348 }
7349 impl core::fmt::Debug for ScounterCommon {
7350 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
7351 f.debug_struct("ScounterCommon")
7352 .field("cy", &self.cy())
7353 .field("ir", &self.ir())
7354 .field("hpm[0]", &self.hpm(0usize))
7355 .field("hpm[1]", &self.hpm(1usize))
7356 .field("hpm[2]", &self.hpm(2usize))
7357 .field("hpm[3]", &self.hpm(3usize))
7358 .field("hpm[4]", &self.hpm(4usize))
7359 .field("hpm[5]", &self.hpm(5usize))
7360 .field("hpm[6]", &self.hpm(6usize))
7361 .field("hpm[7]", &self.hpm(7usize))
7362 .field("hpm[8]", &self.hpm(8usize))
7363 .field("hpm[9]", &self.hpm(9usize))
7364 .field("hpm[10]", &self.hpm(10usize))
7365 .field("hpm[11]", &self.hpm(11usize))
7366 .field("hpm[12]", &self.hpm(12usize))
7367 .field("hpm[13]", &self.hpm(13usize))
7368 .field("hpm[14]", &self.hpm(14usize))
7369 .field("hpm[15]", &self.hpm(15usize))
7370 .field("hpm[16]", &self.hpm(16usize))
7371 .field("hpm[17]", &self.hpm(17usize))
7372 .field("hpm[18]", &self.hpm(18usize))
7373 .field("hpm[19]", &self.hpm(19usize))
7374 .field("hpm[20]", &self.hpm(20usize))
7375 .field("hpm[21]", &self.hpm(21usize))
7376 .field("hpm[22]", &self.hpm(22usize))
7377 .field("hpm[23]", &self.hpm(23usize))
7378 .field("hpm[24]", &self.hpm(24usize))
7379 .field("hpm[25]", &self.hpm(25usize))
7380 .field("hpm[26]", &self.hpm(26usize))
7381 .field("hpm[27]", &self.hpm(27usize))
7382 .field("hpm[28]", &self.hpm(28usize))
7383 .finish()
7384 }
7385 }
7386 #[cfg(feature = "defmt")]
7387 impl defmt::Format for ScounterCommon {
7388 fn format(&self, f: defmt::Formatter) {
7389 defmt::write!(
7390 f,
7391 "ScounterCommon {{ cy: {=bool:?}, ir: {=bool:?}, hpm[0]: {=bool:?}, hpm[1]: {=bool:?}, hpm[2]: {=bool:?}, hpm[3]: {=bool:?}, hpm[4]: {=bool:?}, hpm[5]: {=bool:?}, hpm[6]: {=bool:?}, hpm[7]: {=bool:?}, hpm[8]: {=bool:?}, hpm[9]: {=bool:?}, hpm[10]: {=bool:?}, hpm[11]: {=bool:?}, hpm[12]: {=bool:?}, hpm[13]: {=bool:?}, hpm[14]: {=bool:?}, hpm[15]: {=bool:?}, hpm[16]: {=bool:?}, hpm[17]: {=bool:?}, hpm[18]: {=bool:?}, hpm[19]: {=bool:?}, hpm[20]: {=bool:?}, hpm[21]: {=bool:?}, hpm[22]: {=bool:?}, hpm[23]: {=bool:?}, hpm[24]: {=bool:?}, hpm[25]: {=bool:?}, hpm[26]: {=bool:?}, hpm[27]: {=bool:?}, hpm[28]: {=bool:?} }}",
7392 self.cy(),
7393 self.ir(),
7394 self.hpm(0usize),
7395 self.hpm(1usize),
7396 self.hpm(2usize),
7397 self.hpm(3usize),
7398 self.hpm(4usize),
7399 self.hpm(5usize),
7400 self.hpm(6usize),
7401 self.hpm(7usize),
7402 self.hpm(8usize),
7403 self.hpm(9usize),
7404 self.hpm(10usize),
7405 self.hpm(11usize),
7406 self.hpm(12usize),
7407 self.hpm(13usize),
7408 self.hpm(14usize),
7409 self.hpm(15usize),
7410 self.hpm(16usize),
7411 self.hpm(17usize),
7412 self.hpm(18usize),
7413 self.hpm(19usize),
7414 self.hpm(20usize),
7415 self.hpm(21usize),
7416 self.hpm(22usize),
7417 self.hpm(23usize),
7418 self.hpm(24usize),
7419 self.hpm(25usize),
7420 self.hpm(26usize),
7421 self.hpm(27usize),
7422 self.hpm(28usize)
7423 )
7424 }
7425 }
7426 #[inline(always)]
7427 unsafe fn _read() -> usize {
7428 let r: usize;
7429 unsafe {
7430 core :: arch :: asm ! ("csrrs {0}, 0x9d1, x0" , out (reg) r);
7431 }
7432 r
7433 }
7434 #[inline(always)]
7435 unsafe fn _write(bits: usize) {
7436 unsafe {
7437 core :: arch :: asm ! ("csrrw x0, 0x9d1, {0}" , in (reg) bits);
7438 }
7439 }
7440 #[inline(always)]
7441 unsafe fn _set(bits: usize) {
7442 unsafe {
7443 core :: arch :: asm ! ("csrrs x0, 0x9d1, {0}" , in (reg) bits);
7444 }
7445 }
7446 #[inline(always)]
7447 unsafe fn _clear(bits: usize) {
7448 unsafe {
7449 core :: arch :: asm ! ("csrrc x0, 0x9d1, {0}" , in (reg) bits);
7450 }
7451 }
7452 #[doc = r" Read the CSR value."]
7453 #[inline]
7454 pub fn read() -> ScounterCommon {
7455 unsafe { ScounterCommon(_read() as u32) }
7456 }
7457 #[doc = r" Write the CSR value."]
7458 #[inline]
7459 pub unsafe fn write(val: ScounterCommon) {
7460 unsafe {
7461 _write(val.0 as usize);
7462 }
7463 }
7464 #[doc = r" Read-modify-write the CSR."]
7465 #[inline]
7466 pub unsafe fn modify<R>(f: impl FnOnce(&mut ScounterCommon) -> R) -> R {
7467 let mut val = read();
7468 let res = f(&mut val);
7469 unsafe {
7470 write(val);
7471 }
7472 res
7473 }
7474 #[doc = "Cycle counter"]
7475 #[inline]
7476 pub unsafe fn set_cy() {
7477 unsafe {
7478 _set(1usize);
7479 }
7480 }
7481 #[doc = "Cycle counter"]
7482 #[inline]
7483 pub unsafe fn clear_cy() {
7484 unsafe {
7485 _clear(1usize);
7486 }
7487 }
7488 #[doc = "Instruction retired counter"]
7489 #[inline]
7490 pub unsafe fn set_ir() {
7491 unsafe {
7492 _set(4usize);
7493 }
7494 }
7495 #[doc = "Instruction retired counter"]
7496 #[inline]
7497 pub unsafe fn clear_ir() {
7498 unsafe {
7499 _clear(4usize);
7500 }
7501 }
7502}
7503#[doc = "Counter mask for S-mode"]
7504pub mod scountermask_s {
7505 #[doc = "Machine Counter Fields"]
7506 #[repr(transparent)]
7507 #[derive(Copy, Clone, Eq, PartialEq)]
7508 pub struct ScounterCommon(pub u32);
7509 impl ScounterCommon {
7510 #[doc = "Cycle counter"]
7511 #[must_use]
7512 #[inline(always)]
7513 pub const fn cy(&self) -> bool {
7514 let val = (self.0 >> 0usize) & 0x01;
7515 val != 0
7516 }
7517 #[doc = "Cycle counter"]
7518 #[inline(always)]
7519 pub const fn set_cy(&mut self, val: bool) {
7520 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
7521 }
7522 #[doc = "Instruction retired counter"]
7523 #[must_use]
7524 #[inline(always)]
7525 pub const fn ir(&self) -> bool {
7526 let val = (self.0 >> 2usize) & 0x01;
7527 val != 0
7528 }
7529 #[doc = "Instruction retired counter"]
7530 #[inline(always)]
7531 pub const fn set_ir(&mut self, val: bool) {
7532 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
7533 }
7534 #[doc = "Hardware performance monitor 3 to 31"]
7535 #[must_use]
7536 #[inline(always)]
7537 pub const fn hpm(&self, n: usize) -> bool {
7538 assert!(n < 29usize);
7539 let offs = 3usize + n * 1usize;
7540 let val = (self.0 >> offs) & 0x01;
7541 val != 0
7542 }
7543 #[doc = "Hardware performance monitor 3 to 31"]
7544 #[inline(always)]
7545 pub const fn set_hpm(&mut self, n: usize, val: bool) {
7546 assert!(n < 29usize);
7547 let offs = 3usize + n * 1usize;
7548 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
7549 }
7550 }
7551 impl Default for ScounterCommon {
7552 #[inline(always)]
7553 fn default() -> ScounterCommon {
7554 ScounterCommon(0)
7555 }
7556 }
7557 impl core::fmt::Debug for ScounterCommon {
7558 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
7559 f.debug_struct("ScounterCommon")
7560 .field("cy", &self.cy())
7561 .field("ir", &self.ir())
7562 .field("hpm[0]", &self.hpm(0usize))
7563 .field("hpm[1]", &self.hpm(1usize))
7564 .field("hpm[2]", &self.hpm(2usize))
7565 .field("hpm[3]", &self.hpm(3usize))
7566 .field("hpm[4]", &self.hpm(4usize))
7567 .field("hpm[5]", &self.hpm(5usize))
7568 .field("hpm[6]", &self.hpm(6usize))
7569 .field("hpm[7]", &self.hpm(7usize))
7570 .field("hpm[8]", &self.hpm(8usize))
7571 .field("hpm[9]", &self.hpm(9usize))
7572 .field("hpm[10]", &self.hpm(10usize))
7573 .field("hpm[11]", &self.hpm(11usize))
7574 .field("hpm[12]", &self.hpm(12usize))
7575 .field("hpm[13]", &self.hpm(13usize))
7576 .field("hpm[14]", &self.hpm(14usize))
7577 .field("hpm[15]", &self.hpm(15usize))
7578 .field("hpm[16]", &self.hpm(16usize))
7579 .field("hpm[17]", &self.hpm(17usize))
7580 .field("hpm[18]", &self.hpm(18usize))
7581 .field("hpm[19]", &self.hpm(19usize))
7582 .field("hpm[20]", &self.hpm(20usize))
7583 .field("hpm[21]", &self.hpm(21usize))
7584 .field("hpm[22]", &self.hpm(22usize))
7585 .field("hpm[23]", &self.hpm(23usize))
7586 .field("hpm[24]", &self.hpm(24usize))
7587 .field("hpm[25]", &self.hpm(25usize))
7588 .field("hpm[26]", &self.hpm(26usize))
7589 .field("hpm[27]", &self.hpm(27usize))
7590 .field("hpm[28]", &self.hpm(28usize))
7591 .finish()
7592 }
7593 }
7594 #[cfg(feature = "defmt")]
7595 impl defmt::Format for ScounterCommon {
7596 fn format(&self, f: defmt::Formatter) {
7597 defmt::write!(
7598 f,
7599 "ScounterCommon {{ cy: {=bool:?}, ir: {=bool:?}, hpm[0]: {=bool:?}, hpm[1]: {=bool:?}, hpm[2]: {=bool:?}, hpm[3]: {=bool:?}, hpm[4]: {=bool:?}, hpm[5]: {=bool:?}, hpm[6]: {=bool:?}, hpm[7]: {=bool:?}, hpm[8]: {=bool:?}, hpm[9]: {=bool:?}, hpm[10]: {=bool:?}, hpm[11]: {=bool:?}, hpm[12]: {=bool:?}, hpm[13]: {=bool:?}, hpm[14]: {=bool:?}, hpm[15]: {=bool:?}, hpm[16]: {=bool:?}, hpm[17]: {=bool:?}, hpm[18]: {=bool:?}, hpm[19]: {=bool:?}, hpm[20]: {=bool:?}, hpm[21]: {=bool:?}, hpm[22]: {=bool:?}, hpm[23]: {=bool:?}, hpm[24]: {=bool:?}, hpm[25]: {=bool:?}, hpm[26]: {=bool:?}, hpm[27]: {=bool:?}, hpm[28]: {=bool:?} }}",
7600 self.cy(),
7601 self.ir(),
7602 self.hpm(0usize),
7603 self.hpm(1usize),
7604 self.hpm(2usize),
7605 self.hpm(3usize),
7606 self.hpm(4usize),
7607 self.hpm(5usize),
7608 self.hpm(6usize),
7609 self.hpm(7usize),
7610 self.hpm(8usize),
7611 self.hpm(9usize),
7612 self.hpm(10usize),
7613 self.hpm(11usize),
7614 self.hpm(12usize),
7615 self.hpm(13usize),
7616 self.hpm(14usize),
7617 self.hpm(15usize),
7618 self.hpm(16usize),
7619 self.hpm(17usize),
7620 self.hpm(18usize),
7621 self.hpm(19usize),
7622 self.hpm(20usize),
7623 self.hpm(21usize),
7624 self.hpm(22usize),
7625 self.hpm(23usize),
7626 self.hpm(24usize),
7627 self.hpm(25usize),
7628 self.hpm(26usize),
7629 self.hpm(27usize),
7630 self.hpm(28usize)
7631 )
7632 }
7633 }
7634 #[inline(always)]
7635 unsafe fn _read() -> usize {
7636 let r: usize;
7637 unsafe {
7638 core :: arch :: asm ! ("csrrs {0}, 0x9d2, x0" , out (reg) r);
7639 }
7640 r
7641 }
7642 #[inline(always)]
7643 unsafe fn _write(bits: usize) {
7644 unsafe {
7645 core :: arch :: asm ! ("csrrw x0, 0x9d2, {0}" , in (reg) bits);
7646 }
7647 }
7648 #[inline(always)]
7649 unsafe fn _set(bits: usize) {
7650 unsafe {
7651 core :: arch :: asm ! ("csrrs x0, 0x9d2, {0}" , in (reg) bits);
7652 }
7653 }
7654 #[inline(always)]
7655 unsafe fn _clear(bits: usize) {
7656 unsafe {
7657 core :: arch :: asm ! ("csrrc x0, 0x9d2, {0}" , in (reg) bits);
7658 }
7659 }
7660 #[doc = r" Read the CSR value."]
7661 #[inline]
7662 pub fn read() -> ScounterCommon {
7663 unsafe { ScounterCommon(_read() as u32) }
7664 }
7665 #[doc = r" Write the CSR value."]
7666 #[inline]
7667 pub unsafe fn write(val: ScounterCommon) {
7668 unsafe {
7669 _write(val.0 as usize);
7670 }
7671 }
7672 #[doc = r" Read-modify-write the CSR."]
7673 #[inline]
7674 pub unsafe fn modify<R>(f: impl FnOnce(&mut ScounterCommon) -> R) -> R {
7675 let mut val = read();
7676 let res = f(&mut val);
7677 unsafe {
7678 write(val);
7679 }
7680 res
7681 }
7682 #[doc = "Cycle counter"]
7683 #[inline]
7684 pub unsafe fn set_cy() {
7685 unsafe {
7686 _set(1usize);
7687 }
7688 }
7689 #[doc = "Cycle counter"]
7690 #[inline]
7691 pub unsafe fn clear_cy() {
7692 unsafe {
7693 _clear(1usize);
7694 }
7695 }
7696 #[doc = "Instruction retired counter"]
7697 #[inline]
7698 pub unsafe fn set_ir() {
7699 unsafe {
7700 _set(4usize);
7701 }
7702 }
7703 #[doc = "Instruction retired counter"]
7704 #[inline]
7705 pub unsafe fn clear_ir() {
7706 unsafe {
7707 _clear(4usize);
7708 }
7709 }
7710}
7711#[doc = "Counter mask for U-mode"]
7712pub mod scountermask_u {
7713 #[doc = "Machine Counter Fields"]
7714 #[repr(transparent)]
7715 #[derive(Copy, Clone, Eq, PartialEq)]
7716 pub struct ScounterCommon(pub u32);
7717 impl ScounterCommon {
7718 #[doc = "Cycle counter"]
7719 #[must_use]
7720 #[inline(always)]
7721 pub const fn cy(&self) -> bool {
7722 let val = (self.0 >> 0usize) & 0x01;
7723 val != 0
7724 }
7725 #[doc = "Cycle counter"]
7726 #[inline(always)]
7727 pub const fn set_cy(&mut self, val: bool) {
7728 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
7729 }
7730 #[doc = "Instruction retired counter"]
7731 #[must_use]
7732 #[inline(always)]
7733 pub const fn ir(&self) -> bool {
7734 let val = (self.0 >> 2usize) & 0x01;
7735 val != 0
7736 }
7737 #[doc = "Instruction retired counter"]
7738 #[inline(always)]
7739 pub const fn set_ir(&mut self, val: bool) {
7740 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
7741 }
7742 #[doc = "Hardware performance monitor 3 to 31"]
7743 #[must_use]
7744 #[inline(always)]
7745 pub const fn hpm(&self, n: usize) -> bool {
7746 assert!(n < 29usize);
7747 let offs = 3usize + n * 1usize;
7748 let val = (self.0 >> offs) & 0x01;
7749 val != 0
7750 }
7751 #[doc = "Hardware performance monitor 3 to 31"]
7752 #[inline(always)]
7753 pub const fn set_hpm(&mut self, n: usize, val: bool) {
7754 assert!(n < 29usize);
7755 let offs = 3usize + n * 1usize;
7756 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
7757 }
7758 }
7759 impl Default for ScounterCommon {
7760 #[inline(always)]
7761 fn default() -> ScounterCommon {
7762 ScounterCommon(0)
7763 }
7764 }
7765 impl core::fmt::Debug for ScounterCommon {
7766 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
7767 f.debug_struct("ScounterCommon")
7768 .field("cy", &self.cy())
7769 .field("ir", &self.ir())
7770 .field("hpm[0]", &self.hpm(0usize))
7771 .field("hpm[1]", &self.hpm(1usize))
7772 .field("hpm[2]", &self.hpm(2usize))
7773 .field("hpm[3]", &self.hpm(3usize))
7774 .field("hpm[4]", &self.hpm(4usize))
7775 .field("hpm[5]", &self.hpm(5usize))
7776 .field("hpm[6]", &self.hpm(6usize))
7777 .field("hpm[7]", &self.hpm(7usize))
7778 .field("hpm[8]", &self.hpm(8usize))
7779 .field("hpm[9]", &self.hpm(9usize))
7780 .field("hpm[10]", &self.hpm(10usize))
7781 .field("hpm[11]", &self.hpm(11usize))
7782 .field("hpm[12]", &self.hpm(12usize))
7783 .field("hpm[13]", &self.hpm(13usize))
7784 .field("hpm[14]", &self.hpm(14usize))
7785 .field("hpm[15]", &self.hpm(15usize))
7786 .field("hpm[16]", &self.hpm(16usize))
7787 .field("hpm[17]", &self.hpm(17usize))
7788 .field("hpm[18]", &self.hpm(18usize))
7789 .field("hpm[19]", &self.hpm(19usize))
7790 .field("hpm[20]", &self.hpm(20usize))
7791 .field("hpm[21]", &self.hpm(21usize))
7792 .field("hpm[22]", &self.hpm(22usize))
7793 .field("hpm[23]", &self.hpm(23usize))
7794 .field("hpm[24]", &self.hpm(24usize))
7795 .field("hpm[25]", &self.hpm(25usize))
7796 .field("hpm[26]", &self.hpm(26usize))
7797 .field("hpm[27]", &self.hpm(27usize))
7798 .field("hpm[28]", &self.hpm(28usize))
7799 .finish()
7800 }
7801 }
7802 #[cfg(feature = "defmt")]
7803 impl defmt::Format for ScounterCommon {
7804 fn format(&self, f: defmt::Formatter) {
7805 defmt::write!(
7806 f,
7807 "ScounterCommon {{ cy: {=bool:?}, ir: {=bool:?}, hpm[0]: {=bool:?}, hpm[1]: {=bool:?}, hpm[2]: {=bool:?}, hpm[3]: {=bool:?}, hpm[4]: {=bool:?}, hpm[5]: {=bool:?}, hpm[6]: {=bool:?}, hpm[7]: {=bool:?}, hpm[8]: {=bool:?}, hpm[9]: {=bool:?}, hpm[10]: {=bool:?}, hpm[11]: {=bool:?}, hpm[12]: {=bool:?}, hpm[13]: {=bool:?}, hpm[14]: {=bool:?}, hpm[15]: {=bool:?}, hpm[16]: {=bool:?}, hpm[17]: {=bool:?}, hpm[18]: {=bool:?}, hpm[19]: {=bool:?}, hpm[20]: {=bool:?}, hpm[21]: {=bool:?}, hpm[22]: {=bool:?}, hpm[23]: {=bool:?}, hpm[24]: {=bool:?}, hpm[25]: {=bool:?}, hpm[26]: {=bool:?}, hpm[27]: {=bool:?}, hpm[28]: {=bool:?} }}",
7808 self.cy(),
7809 self.ir(),
7810 self.hpm(0usize),
7811 self.hpm(1usize),
7812 self.hpm(2usize),
7813 self.hpm(3usize),
7814 self.hpm(4usize),
7815 self.hpm(5usize),
7816 self.hpm(6usize),
7817 self.hpm(7usize),
7818 self.hpm(8usize),
7819 self.hpm(9usize),
7820 self.hpm(10usize),
7821 self.hpm(11usize),
7822 self.hpm(12usize),
7823 self.hpm(13usize),
7824 self.hpm(14usize),
7825 self.hpm(15usize),
7826 self.hpm(16usize),
7827 self.hpm(17usize),
7828 self.hpm(18usize),
7829 self.hpm(19usize),
7830 self.hpm(20usize),
7831 self.hpm(21usize),
7832 self.hpm(22usize),
7833 self.hpm(23usize),
7834 self.hpm(24usize),
7835 self.hpm(25usize),
7836 self.hpm(26usize),
7837 self.hpm(27usize),
7838 self.hpm(28usize)
7839 )
7840 }
7841 }
7842 #[inline(always)]
7843 unsafe fn _read() -> usize {
7844 let r: usize;
7845 unsafe {
7846 core :: arch :: asm ! ("csrrs {0}, 0x9d3, x0" , out (reg) r);
7847 }
7848 r
7849 }
7850 #[inline(always)]
7851 unsafe fn _write(bits: usize) {
7852 unsafe {
7853 core :: arch :: asm ! ("csrrw x0, 0x9d3, {0}" , in (reg) bits);
7854 }
7855 }
7856 #[inline(always)]
7857 unsafe fn _set(bits: usize) {
7858 unsafe {
7859 core :: arch :: asm ! ("csrrs x0, 0x9d3, {0}" , in (reg) bits);
7860 }
7861 }
7862 #[inline(always)]
7863 unsafe fn _clear(bits: usize) {
7864 unsafe {
7865 core :: arch :: asm ! ("csrrc x0, 0x9d3, {0}" , in (reg) bits);
7866 }
7867 }
7868 #[doc = r" Read the CSR value."]
7869 #[inline]
7870 pub fn read() -> ScounterCommon {
7871 unsafe { ScounterCommon(_read() as u32) }
7872 }
7873 #[doc = r" Write the CSR value."]
7874 #[inline]
7875 pub unsafe fn write(val: ScounterCommon) {
7876 unsafe {
7877 _write(val.0 as usize);
7878 }
7879 }
7880 #[doc = r" Read-modify-write the CSR."]
7881 #[inline]
7882 pub unsafe fn modify<R>(f: impl FnOnce(&mut ScounterCommon) -> R) -> R {
7883 let mut val = read();
7884 let res = f(&mut val);
7885 unsafe {
7886 write(val);
7887 }
7888 res
7889 }
7890 #[doc = "Cycle counter"]
7891 #[inline]
7892 pub unsafe fn set_cy() {
7893 unsafe {
7894 _set(1usize);
7895 }
7896 }
7897 #[doc = "Cycle counter"]
7898 #[inline]
7899 pub unsafe fn clear_cy() {
7900 unsafe {
7901 _clear(1usize);
7902 }
7903 }
7904 #[doc = "Instruction retired counter"]
7905 #[inline]
7906 pub unsafe fn set_ir() {
7907 unsafe {
7908 _set(4usize);
7909 }
7910 }
7911 #[doc = "Instruction retired counter"]
7912 #[inline]
7913 pub unsafe fn clear_ir() {
7914 unsafe {
7915 _clear(4usize);
7916 }
7917 }
7918}
7919#[doc = "Counter overflow status"]
7920pub mod scounterovf {
7921 #[doc = "Machine Counter Fields"]
7922 #[repr(transparent)]
7923 #[derive(Copy, Clone, Eq, PartialEq)]
7924 pub struct ScounterCommon(pub u32);
7925 impl ScounterCommon {
7926 #[doc = "Cycle counter"]
7927 #[must_use]
7928 #[inline(always)]
7929 pub const fn cy(&self) -> bool {
7930 let val = (self.0 >> 0usize) & 0x01;
7931 val != 0
7932 }
7933 #[doc = "Cycle counter"]
7934 #[inline(always)]
7935 pub const fn set_cy(&mut self, val: bool) {
7936 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
7937 }
7938 #[doc = "Instruction retired counter"]
7939 #[must_use]
7940 #[inline(always)]
7941 pub const fn ir(&self) -> bool {
7942 let val = (self.0 >> 2usize) & 0x01;
7943 val != 0
7944 }
7945 #[doc = "Instruction retired counter"]
7946 #[inline(always)]
7947 pub const fn set_ir(&mut self, val: bool) {
7948 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
7949 }
7950 #[doc = "Hardware performance monitor 3 to 31"]
7951 #[must_use]
7952 #[inline(always)]
7953 pub const fn hpm(&self, n: usize) -> bool {
7954 assert!(n < 29usize);
7955 let offs = 3usize + n * 1usize;
7956 let val = (self.0 >> offs) & 0x01;
7957 val != 0
7958 }
7959 #[doc = "Hardware performance monitor 3 to 31"]
7960 #[inline(always)]
7961 pub const fn set_hpm(&mut self, n: usize, val: bool) {
7962 assert!(n < 29usize);
7963 let offs = 3usize + n * 1usize;
7964 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
7965 }
7966 }
7967 impl Default for ScounterCommon {
7968 #[inline(always)]
7969 fn default() -> ScounterCommon {
7970 ScounterCommon(0)
7971 }
7972 }
7973 impl core::fmt::Debug for ScounterCommon {
7974 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
7975 f.debug_struct("ScounterCommon")
7976 .field("cy", &self.cy())
7977 .field("ir", &self.ir())
7978 .field("hpm[0]", &self.hpm(0usize))
7979 .field("hpm[1]", &self.hpm(1usize))
7980 .field("hpm[2]", &self.hpm(2usize))
7981 .field("hpm[3]", &self.hpm(3usize))
7982 .field("hpm[4]", &self.hpm(4usize))
7983 .field("hpm[5]", &self.hpm(5usize))
7984 .field("hpm[6]", &self.hpm(6usize))
7985 .field("hpm[7]", &self.hpm(7usize))
7986 .field("hpm[8]", &self.hpm(8usize))
7987 .field("hpm[9]", &self.hpm(9usize))
7988 .field("hpm[10]", &self.hpm(10usize))
7989 .field("hpm[11]", &self.hpm(11usize))
7990 .field("hpm[12]", &self.hpm(12usize))
7991 .field("hpm[13]", &self.hpm(13usize))
7992 .field("hpm[14]", &self.hpm(14usize))
7993 .field("hpm[15]", &self.hpm(15usize))
7994 .field("hpm[16]", &self.hpm(16usize))
7995 .field("hpm[17]", &self.hpm(17usize))
7996 .field("hpm[18]", &self.hpm(18usize))
7997 .field("hpm[19]", &self.hpm(19usize))
7998 .field("hpm[20]", &self.hpm(20usize))
7999 .field("hpm[21]", &self.hpm(21usize))
8000 .field("hpm[22]", &self.hpm(22usize))
8001 .field("hpm[23]", &self.hpm(23usize))
8002 .field("hpm[24]", &self.hpm(24usize))
8003 .field("hpm[25]", &self.hpm(25usize))
8004 .field("hpm[26]", &self.hpm(26usize))
8005 .field("hpm[27]", &self.hpm(27usize))
8006 .field("hpm[28]", &self.hpm(28usize))
8007 .finish()
8008 }
8009 }
8010 #[cfg(feature = "defmt")]
8011 impl defmt::Format for ScounterCommon {
8012 fn format(&self, f: defmt::Formatter) {
8013 defmt::write!(
8014 f,
8015 "ScounterCommon {{ cy: {=bool:?}, ir: {=bool:?}, hpm[0]: {=bool:?}, hpm[1]: {=bool:?}, hpm[2]: {=bool:?}, hpm[3]: {=bool:?}, hpm[4]: {=bool:?}, hpm[5]: {=bool:?}, hpm[6]: {=bool:?}, hpm[7]: {=bool:?}, hpm[8]: {=bool:?}, hpm[9]: {=bool:?}, hpm[10]: {=bool:?}, hpm[11]: {=bool:?}, hpm[12]: {=bool:?}, hpm[13]: {=bool:?}, hpm[14]: {=bool:?}, hpm[15]: {=bool:?}, hpm[16]: {=bool:?}, hpm[17]: {=bool:?}, hpm[18]: {=bool:?}, hpm[19]: {=bool:?}, hpm[20]: {=bool:?}, hpm[21]: {=bool:?}, hpm[22]: {=bool:?}, hpm[23]: {=bool:?}, hpm[24]: {=bool:?}, hpm[25]: {=bool:?}, hpm[26]: {=bool:?}, hpm[27]: {=bool:?}, hpm[28]: {=bool:?} }}",
8016 self.cy(),
8017 self.ir(),
8018 self.hpm(0usize),
8019 self.hpm(1usize),
8020 self.hpm(2usize),
8021 self.hpm(3usize),
8022 self.hpm(4usize),
8023 self.hpm(5usize),
8024 self.hpm(6usize),
8025 self.hpm(7usize),
8026 self.hpm(8usize),
8027 self.hpm(9usize),
8028 self.hpm(10usize),
8029 self.hpm(11usize),
8030 self.hpm(12usize),
8031 self.hpm(13usize),
8032 self.hpm(14usize),
8033 self.hpm(15usize),
8034 self.hpm(16usize),
8035 self.hpm(17usize),
8036 self.hpm(18usize),
8037 self.hpm(19usize),
8038 self.hpm(20usize),
8039 self.hpm(21usize),
8040 self.hpm(22usize),
8041 self.hpm(23usize),
8042 self.hpm(24usize),
8043 self.hpm(25usize),
8044 self.hpm(26usize),
8045 self.hpm(27usize),
8046 self.hpm(28usize)
8047 )
8048 }
8049 }
8050 #[inline(always)]
8051 unsafe fn _read() -> usize {
8052 let r: usize;
8053 unsafe {
8054 core :: arch :: asm ! ("csrrs {0}, 0x9d4, x0" , out (reg) r);
8055 }
8056 r
8057 }
8058 #[inline(always)]
8059 unsafe fn _write(bits: usize) {
8060 unsafe {
8061 core :: arch :: asm ! ("csrrw x0, 0x9d4, {0}" , in (reg) bits);
8062 }
8063 }
8064 #[inline(always)]
8065 unsafe fn _set(bits: usize) {
8066 unsafe {
8067 core :: arch :: asm ! ("csrrs x0, 0x9d4, {0}" , in (reg) bits);
8068 }
8069 }
8070 #[inline(always)]
8071 unsafe fn _clear(bits: usize) {
8072 unsafe {
8073 core :: arch :: asm ! ("csrrc x0, 0x9d4, {0}" , in (reg) bits);
8074 }
8075 }
8076 #[doc = r" Read the CSR value."]
8077 #[inline]
8078 pub fn read() -> ScounterCommon {
8079 unsafe { ScounterCommon(_read() as u32) }
8080 }
8081 #[doc = r" Write the CSR value."]
8082 #[inline]
8083 pub unsafe fn write(val: ScounterCommon) {
8084 unsafe {
8085 _write(val.0 as usize);
8086 }
8087 }
8088 #[doc = r" Read-modify-write the CSR."]
8089 #[inline]
8090 pub unsafe fn modify<R>(f: impl FnOnce(&mut ScounterCommon) -> R) -> R {
8091 let mut val = read();
8092 let res = f(&mut val);
8093 unsafe {
8094 write(val);
8095 }
8096 res
8097 }
8098 #[doc = "Cycle counter"]
8099 #[inline]
8100 pub unsafe fn set_cy() {
8101 unsafe {
8102 _set(1usize);
8103 }
8104 }
8105 #[doc = "Cycle counter"]
8106 #[inline]
8107 pub unsafe fn clear_cy() {
8108 unsafe {
8109 _clear(1usize);
8110 }
8111 }
8112 #[doc = "Instruction retired counter"]
8113 #[inline]
8114 pub unsafe fn set_ir() {
8115 unsafe {
8116 _set(4usize);
8117 }
8118 }
8119 #[doc = "Instruction retired counter"]
8120 #[inline]
8121 pub unsafe fn clear_ir() {
8122 unsafe {
8123 _clear(4usize);
8124 }
8125 }
8126}
8127#[doc = "Supervisor counter inhibit"]
8128pub mod scountinhibit {
8129 #[doc = "Machine Counter Fields"]
8130 #[repr(transparent)]
8131 #[derive(Copy, Clone, Eq, PartialEq)]
8132 pub struct ScounterCommon(pub u32);
8133 impl ScounterCommon {
8134 #[doc = "Cycle counter"]
8135 #[must_use]
8136 #[inline(always)]
8137 pub const fn cy(&self) -> bool {
8138 let val = (self.0 >> 0usize) & 0x01;
8139 val != 0
8140 }
8141 #[doc = "Cycle counter"]
8142 #[inline(always)]
8143 pub const fn set_cy(&mut self, val: bool) {
8144 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
8145 }
8146 #[doc = "Instruction retired counter"]
8147 #[must_use]
8148 #[inline(always)]
8149 pub const fn ir(&self) -> bool {
8150 let val = (self.0 >> 2usize) & 0x01;
8151 val != 0
8152 }
8153 #[doc = "Instruction retired counter"]
8154 #[inline(always)]
8155 pub const fn set_ir(&mut self, val: bool) {
8156 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
8157 }
8158 #[doc = "Hardware performance monitor 3 to 31"]
8159 #[must_use]
8160 #[inline(always)]
8161 pub const fn hpm(&self, n: usize) -> bool {
8162 assert!(n < 29usize);
8163 let offs = 3usize + n * 1usize;
8164 let val = (self.0 >> offs) & 0x01;
8165 val != 0
8166 }
8167 #[doc = "Hardware performance monitor 3 to 31"]
8168 #[inline(always)]
8169 pub const fn set_hpm(&mut self, n: usize, val: bool) {
8170 assert!(n < 29usize);
8171 let offs = 3usize + n * 1usize;
8172 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
8173 }
8174 }
8175 impl Default for ScounterCommon {
8176 #[inline(always)]
8177 fn default() -> ScounterCommon {
8178 ScounterCommon(0)
8179 }
8180 }
8181 impl core::fmt::Debug for ScounterCommon {
8182 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
8183 f.debug_struct("ScounterCommon")
8184 .field("cy", &self.cy())
8185 .field("ir", &self.ir())
8186 .field("hpm[0]", &self.hpm(0usize))
8187 .field("hpm[1]", &self.hpm(1usize))
8188 .field("hpm[2]", &self.hpm(2usize))
8189 .field("hpm[3]", &self.hpm(3usize))
8190 .field("hpm[4]", &self.hpm(4usize))
8191 .field("hpm[5]", &self.hpm(5usize))
8192 .field("hpm[6]", &self.hpm(6usize))
8193 .field("hpm[7]", &self.hpm(7usize))
8194 .field("hpm[8]", &self.hpm(8usize))
8195 .field("hpm[9]", &self.hpm(9usize))
8196 .field("hpm[10]", &self.hpm(10usize))
8197 .field("hpm[11]", &self.hpm(11usize))
8198 .field("hpm[12]", &self.hpm(12usize))
8199 .field("hpm[13]", &self.hpm(13usize))
8200 .field("hpm[14]", &self.hpm(14usize))
8201 .field("hpm[15]", &self.hpm(15usize))
8202 .field("hpm[16]", &self.hpm(16usize))
8203 .field("hpm[17]", &self.hpm(17usize))
8204 .field("hpm[18]", &self.hpm(18usize))
8205 .field("hpm[19]", &self.hpm(19usize))
8206 .field("hpm[20]", &self.hpm(20usize))
8207 .field("hpm[21]", &self.hpm(21usize))
8208 .field("hpm[22]", &self.hpm(22usize))
8209 .field("hpm[23]", &self.hpm(23usize))
8210 .field("hpm[24]", &self.hpm(24usize))
8211 .field("hpm[25]", &self.hpm(25usize))
8212 .field("hpm[26]", &self.hpm(26usize))
8213 .field("hpm[27]", &self.hpm(27usize))
8214 .field("hpm[28]", &self.hpm(28usize))
8215 .finish()
8216 }
8217 }
8218 #[cfg(feature = "defmt")]
8219 impl defmt::Format for ScounterCommon {
8220 fn format(&self, f: defmt::Formatter) {
8221 defmt::write!(
8222 f,
8223 "ScounterCommon {{ cy: {=bool:?}, ir: {=bool:?}, hpm[0]: {=bool:?}, hpm[1]: {=bool:?}, hpm[2]: {=bool:?}, hpm[3]: {=bool:?}, hpm[4]: {=bool:?}, hpm[5]: {=bool:?}, hpm[6]: {=bool:?}, hpm[7]: {=bool:?}, hpm[8]: {=bool:?}, hpm[9]: {=bool:?}, hpm[10]: {=bool:?}, hpm[11]: {=bool:?}, hpm[12]: {=bool:?}, hpm[13]: {=bool:?}, hpm[14]: {=bool:?}, hpm[15]: {=bool:?}, hpm[16]: {=bool:?}, hpm[17]: {=bool:?}, hpm[18]: {=bool:?}, hpm[19]: {=bool:?}, hpm[20]: {=bool:?}, hpm[21]: {=bool:?}, hpm[22]: {=bool:?}, hpm[23]: {=bool:?}, hpm[24]: {=bool:?}, hpm[25]: {=bool:?}, hpm[26]: {=bool:?}, hpm[27]: {=bool:?}, hpm[28]: {=bool:?} }}",
8224 self.cy(),
8225 self.ir(),
8226 self.hpm(0usize),
8227 self.hpm(1usize),
8228 self.hpm(2usize),
8229 self.hpm(3usize),
8230 self.hpm(4usize),
8231 self.hpm(5usize),
8232 self.hpm(6usize),
8233 self.hpm(7usize),
8234 self.hpm(8usize),
8235 self.hpm(9usize),
8236 self.hpm(10usize),
8237 self.hpm(11usize),
8238 self.hpm(12usize),
8239 self.hpm(13usize),
8240 self.hpm(14usize),
8241 self.hpm(15usize),
8242 self.hpm(16usize),
8243 self.hpm(17usize),
8244 self.hpm(18usize),
8245 self.hpm(19usize),
8246 self.hpm(20usize),
8247 self.hpm(21usize),
8248 self.hpm(22usize),
8249 self.hpm(23usize),
8250 self.hpm(24usize),
8251 self.hpm(25usize),
8252 self.hpm(26usize),
8253 self.hpm(27usize),
8254 self.hpm(28usize)
8255 )
8256 }
8257 }
8258 #[inline(always)]
8259 unsafe fn _read() -> usize {
8260 let r: usize;
8261 unsafe {
8262 core :: arch :: asm ! ("csrrs {0}, 0x9e0, x0" , out (reg) r);
8263 }
8264 r
8265 }
8266 #[inline(always)]
8267 unsafe fn _write(bits: usize) {
8268 unsafe {
8269 core :: arch :: asm ! ("csrrw x0, 0x9e0, {0}" , in (reg) bits);
8270 }
8271 }
8272 #[inline(always)]
8273 unsafe fn _set(bits: usize) {
8274 unsafe {
8275 core :: arch :: asm ! ("csrrs x0, 0x9e0, {0}" , in (reg) bits);
8276 }
8277 }
8278 #[inline(always)]
8279 unsafe fn _clear(bits: usize) {
8280 unsafe {
8281 core :: arch :: asm ! ("csrrc x0, 0x9e0, {0}" , in (reg) bits);
8282 }
8283 }
8284 #[doc = r" Read the CSR value."]
8285 #[inline]
8286 pub fn read() -> ScounterCommon {
8287 unsafe { ScounterCommon(_read() as u32) }
8288 }
8289 #[doc = r" Write the CSR value."]
8290 #[inline]
8291 pub unsafe fn write(val: ScounterCommon) {
8292 unsafe {
8293 _write(val.0 as usize);
8294 }
8295 }
8296 #[doc = r" Read-modify-write the CSR."]
8297 #[inline]
8298 pub unsafe fn modify<R>(f: impl FnOnce(&mut ScounterCommon) -> R) -> R {
8299 let mut val = read();
8300 let res = f(&mut val);
8301 unsafe {
8302 write(val);
8303 }
8304 res
8305 }
8306 #[doc = "Cycle counter"]
8307 #[inline]
8308 pub unsafe fn set_cy() {
8309 unsafe {
8310 _set(1usize);
8311 }
8312 }
8313 #[doc = "Cycle counter"]
8314 #[inline]
8315 pub unsafe fn clear_cy() {
8316 unsafe {
8317 _clear(1usize);
8318 }
8319 }
8320 #[doc = "Instruction retired counter"]
8321 #[inline]
8322 pub unsafe fn set_ir() {
8323 unsafe {
8324 _set(4usize);
8325 }
8326 }
8327 #[doc = "Instruction retired counter"]
8328 #[inline]
8329 pub unsafe fn clear_ir() {
8330 unsafe {
8331 _clear(4usize);
8332 }
8333 }
8334}
8335#[doc = "Performance monitoring event selection"]
8336pub mod shpmevent3 {
8337 #[inline(always)]
8338 unsafe fn _read() -> usize {
8339 let r: usize;
8340 unsafe {
8341 core :: arch :: asm ! ("csrrs {0}, 0x9e3, x0" , out (reg) r);
8342 }
8343 r
8344 }
8345 #[inline(always)]
8346 unsafe fn _write(bits: usize) {
8347 unsafe {
8348 core :: arch :: asm ! ("csrrw x0, 0x9e3, {0}" , in (reg) bits);
8349 }
8350 }
8351 #[inline(always)]
8352 unsafe fn _set(bits: usize) {
8353 unsafe {
8354 core :: arch :: asm ! ("csrrs x0, 0x9e3, {0}" , in (reg) bits);
8355 }
8356 }
8357 #[inline(always)]
8358 unsafe fn _clear(bits: usize) {
8359 unsafe {
8360 core :: arch :: asm ! ("csrrc x0, 0x9e3, {0}" , in (reg) bits);
8361 }
8362 }
8363 #[doc = r" Read the CSR value as raw usize."]
8364 #[inline]
8365 pub fn read() -> usize {
8366 unsafe { _read() }
8367 }
8368 #[doc = r" Write the CSR value as raw usize."]
8369 #[inline]
8370 pub unsafe fn write(val: usize) {
8371 unsafe {
8372 _write(val);
8373 }
8374 }
8375}
8376#[doc = "Performance monitoring event selection"]
8377pub mod shpmevent4 {
8378 #[inline(always)]
8379 unsafe fn _read() -> usize {
8380 let r: usize;
8381 unsafe {
8382 core :: arch :: asm ! ("csrrs {0}, 0x9e4, x0" , out (reg) r);
8383 }
8384 r
8385 }
8386 #[inline(always)]
8387 unsafe fn _write(bits: usize) {
8388 unsafe {
8389 core :: arch :: asm ! ("csrrw x0, 0x9e4, {0}" , in (reg) bits);
8390 }
8391 }
8392 #[inline(always)]
8393 unsafe fn _set(bits: usize) {
8394 unsafe {
8395 core :: arch :: asm ! ("csrrs x0, 0x9e4, {0}" , in (reg) bits);
8396 }
8397 }
8398 #[inline(always)]
8399 unsafe fn _clear(bits: usize) {
8400 unsafe {
8401 core :: arch :: asm ! ("csrrc x0, 0x9e4, {0}" , in (reg) bits);
8402 }
8403 }
8404 #[doc = r" Read the CSR value as raw usize."]
8405 #[inline]
8406 pub fn read() -> usize {
8407 unsafe { _read() }
8408 }
8409 #[doc = r" Write the CSR value as raw usize."]
8410 #[inline]
8411 pub unsafe fn write(val: usize) {
8412 unsafe {
8413 _write(val);
8414 }
8415 }
8416}
8417#[doc = "Performance monitoring event selection"]
8418pub mod shpmevent5 {
8419 #[inline(always)]
8420 unsafe fn _read() -> usize {
8421 let r: usize;
8422 unsafe {
8423 core :: arch :: asm ! ("csrrs {0}, 0x9e5, x0" , out (reg) r);
8424 }
8425 r
8426 }
8427 #[inline(always)]
8428 unsafe fn _write(bits: usize) {
8429 unsafe {
8430 core :: arch :: asm ! ("csrrw x0, 0x9e5, {0}" , in (reg) bits);
8431 }
8432 }
8433 #[inline(always)]
8434 unsafe fn _set(bits: usize) {
8435 unsafe {
8436 core :: arch :: asm ! ("csrrs x0, 0x9e5, {0}" , in (reg) bits);
8437 }
8438 }
8439 #[inline(always)]
8440 unsafe fn _clear(bits: usize) {
8441 unsafe {
8442 core :: arch :: asm ! ("csrrc x0, 0x9e5, {0}" , in (reg) bits);
8443 }
8444 }
8445 #[doc = r" Read the CSR value as raw usize."]
8446 #[inline]
8447 pub fn read() -> usize {
8448 unsafe { _read() }
8449 }
8450 #[doc = r" Write the CSR value as raw usize."]
8451 #[inline]
8452 pub unsafe fn write(val: usize) {
8453 unsafe {
8454 _write(val);
8455 }
8456 }
8457}
8458#[doc = "Performance monitoring event selection"]
8459pub mod shpmevent6 {
8460 #[inline(always)]
8461 unsafe fn _read() -> usize {
8462 let r: usize;
8463 unsafe {
8464 core :: arch :: asm ! ("csrrs {0}, 0x9e6, x0" , out (reg) r);
8465 }
8466 r
8467 }
8468 #[inline(always)]
8469 unsafe fn _write(bits: usize) {
8470 unsafe {
8471 core :: arch :: asm ! ("csrrw x0, 0x9e6, {0}" , in (reg) bits);
8472 }
8473 }
8474 #[inline(always)]
8475 unsafe fn _set(bits: usize) {
8476 unsafe {
8477 core :: arch :: asm ! ("csrrs x0, 0x9e6, {0}" , in (reg) bits);
8478 }
8479 }
8480 #[inline(always)]
8481 unsafe fn _clear(bits: usize) {
8482 unsafe {
8483 core :: arch :: asm ! ("csrrc x0, 0x9e6, {0}" , in (reg) bits);
8484 }
8485 }
8486 #[doc = r" Read the CSR value as raw usize."]
8487 #[inline]
8488 pub fn read() -> usize {
8489 unsafe { _read() }
8490 }
8491 #[doc = r" Write the CSR value as raw usize."]
8492 #[inline]
8493 pub unsafe fn write(val: usize) {
8494 unsafe {
8495 _write(val);
8496 }
8497 }
8498}
8499#[doc = "PMA configuration"]
8500pub mod pmacfg0 {
8501 #[doc = "PMA Configuration Register"]
8502 #[repr(transparent)]
8503 #[derive(Copy, Clone, Eq, PartialEq)]
8504 pub struct Pmacfg(pub u32);
8505 impl Pmacfg {
8506 #[doc = "Entry address matching mode"]
8507 #[must_use]
8508 #[inline(always)]
8509 pub const fn etyp(&self, n: usize) -> super::vals::EntryType {
8510 assert!(n < 4usize);
8511 let offs = 0usize + n * 8usize;
8512 let val = (self.0 >> offs) & 0x03;
8513 super::vals::EntryType::from_bits(val as u8)
8514 }
8515 #[doc = "Entry address matching mode"]
8516 #[inline(always)]
8517 pub const fn set_etyp(&mut self, n: usize, val: super::vals::EntryType) {
8518 assert!(n < 4usize);
8519 let offs = 0usize + n * 8usize;
8520 self.0 = (self.0 & !(0x03 << offs)) | (((val.to_bits() as u32) & 0x03) << offs);
8521 }
8522 #[doc = "Memory type attribute"]
8523 #[must_use]
8524 #[inline(always)]
8525 pub const fn mtyp(&self, n: usize) -> super::vals::MemoryType {
8526 assert!(n < 4usize);
8527 let offs = 2usize + n * 8usize;
8528 let val = (self.0 >> offs) & 0x0f;
8529 super::vals::MemoryType::from_bits(val as u8)
8530 }
8531 #[doc = "Memory type attribute"]
8532 #[inline(always)]
8533 pub const fn set_mtyp(&mut self, n: usize, val: super::vals::MemoryType) {
8534 assert!(n < 4usize);
8535 let offs = 2usize + n * 8usize;
8536 self.0 = (self.0 & !(0x0f << offs)) | (((val.to_bits() as u32) & 0x0f) << offs);
8537 }
8538 #[doc = "Indicate whether Atomic Memory Operation instructions (including LR/SC) are not supported in this region"]
8539 #[must_use]
8540 #[inline(always)]
8541 pub const fn namo(&self, n: usize) -> bool {
8542 assert!(n < 4usize);
8543 let offs = 6usize + n * 8usize;
8544 let val = (self.0 >> offs) & 0x01;
8545 val != 0
8546 }
8547 #[doc = "Indicate whether Atomic Memory Operation instructions (including LR/SC) are not supported in this region"]
8548 #[inline(always)]
8549 pub const fn set_namo(&mut self, n: usize, val: bool) {
8550 assert!(n < 4usize);
8551 let offs = 6usize + n * 8usize;
8552 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
8553 }
8554 }
8555 impl Default for Pmacfg {
8556 #[inline(always)]
8557 fn default() -> Pmacfg {
8558 Pmacfg(0)
8559 }
8560 }
8561 impl core::fmt::Debug for Pmacfg {
8562 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
8563 f.debug_struct("Pmacfg")
8564 .field("etyp[0]", &self.etyp(0usize))
8565 .field("etyp[1]", &self.etyp(1usize))
8566 .field("etyp[2]", &self.etyp(2usize))
8567 .field("etyp[3]", &self.etyp(3usize))
8568 .field("mtyp[0]", &self.mtyp(0usize))
8569 .field("mtyp[1]", &self.mtyp(1usize))
8570 .field("mtyp[2]", &self.mtyp(2usize))
8571 .field("mtyp[3]", &self.mtyp(3usize))
8572 .field("namo[0]", &self.namo(0usize))
8573 .field("namo[1]", &self.namo(1usize))
8574 .field("namo[2]", &self.namo(2usize))
8575 .field("namo[3]", &self.namo(3usize))
8576 .finish()
8577 }
8578 }
8579 #[cfg(feature = "defmt")]
8580 impl defmt::Format for Pmacfg {
8581 fn format(&self, f: defmt::Formatter) {
8582 defmt::write!(
8583 f,
8584 "Pmacfg {{ etyp[0]: {:?}, etyp[1]: {:?}, etyp[2]: {:?}, etyp[3]: {:?}, mtyp[0]: {:?}, mtyp[1]: {:?}, mtyp[2]: {:?}, mtyp[3]: {:?}, namo[0]: {=bool:?}, namo[1]: {=bool:?}, namo[2]: {=bool:?}, namo[3]: {=bool:?} }}",
8585 self.etyp(0usize),
8586 self.etyp(1usize),
8587 self.etyp(2usize),
8588 self.etyp(3usize),
8589 self.mtyp(0usize),
8590 self.mtyp(1usize),
8591 self.mtyp(2usize),
8592 self.mtyp(3usize),
8593 self.namo(0usize),
8594 self.namo(1usize),
8595 self.namo(2usize),
8596 self.namo(3usize)
8597 )
8598 }
8599 }
8600 #[inline(always)]
8601 unsafe fn _read() -> usize {
8602 let r: usize;
8603 unsafe {
8604 core :: arch :: asm ! ("csrrs {0}, 0xbc0, x0" , out (reg) r);
8605 }
8606 r
8607 }
8608 #[inline(always)]
8609 unsafe fn _write(bits: usize) {
8610 unsafe {
8611 core :: arch :: asm ! ("csrrw x0, 0xbc0, {0}" , in (reg) bits);
8612 }
8613 }
8614 #[inline(always)]
8615 unsafe fn _set(bits: usize) {
8616 unsafe {
8617 core :: arch :: asm ! ("csrrs x0, 0xbc0, {0}" , in (reg) bits);
8618 }
8619 }
8620 #[inline(always)]
8621 unsafe fn _clear(bits: usize) {
8622 unsafe {
8623 core :: arch :: asm ! ("csrrc x0, 0xbc0, {0}" , in (reg) bits);
8624 }
8625 }
8626 #[doc = r" Read the CSR value."]
8627 #[inline]
8628 pub fn read() -> Pmacfg {
8629 unsafe { Pmacfg(_read() as u32) }
8630 }
8631 #[doc = r" Write the CSR value."]
8632 #[inline]
8633 pub unsafe fn write(val: Pmacfg) {
8634 unsafe {
8635 _write(val.0 as usize);
8636 }
8637 }
8638 #[doc = r" Read-modify-write the CSR."]
8639 #[inline]
8640 pub unsafe fn modify<R>(f: impl FnOnce(&mut Pmacfg) -> R) -> R {
8641 let mut val = read();
8642 let res = f(&mut val);
8643 unsafe {
8644 write(val);
8645 }
8646 res
8647 }
8648}
8649#[doc = "PMA configuration"]
8650pub mod pmacfg1 {
8651 #[doc = "PMA Configuration Register"]
8652 #[repr(transparent)]
8653 #[derive(Copy, Clone, Eq, PartialEq)]
8654 pub struct Pmacfg(pub u32);
8655 impl Pmacfg {
8656 #[doc = "Entry address matching mode"]
8657 #[must_use]
8658 #[inline(always)]
8659 pub const fn etyp(&self, n: usize) -> super::vals::EntryType {
8660 assert!(n < 4usize);
8661 let offs = 0usize + n * 8usize;
8662 let val = (self.0 >> offs) & 0x03;
8663 super::vals::EntryType::from_bits(val as u8)
8664 }
8665 #[doc = "Entry address matching mode"]
8666 #[inline(always)]
8667 pub const fn set_etyp(&mut self, n: usize, val: super::vals::EntryType) {
8668 assert!(n < 4usize);
8669 let offs = 0usize + n * 8usize;
8670 self.0 = (self.0 & !(0x03 << offs)) | (((val.to_bits() as u32) & 0x03) << offs);
8671 }
8672 #[doc = "Memory type attribute"]
8673 #[must_use]
8674 #[inline(always)]
8675 pub const fn mtyp(&self, n: usize) -> super::vals::MemoryType {
8676 assert!(n < 4usize);
8677 let offs = 2usize + n * 8usize;
8678 let val = (self.0 >> offs) & 0x0f;
8679 super::vals::MemoryType::from_bits(val as u8)
8680 }
8681 #[doc = "Memory type attribute"]
8682 #[inline(always)]
8683 pub const fn set_mtyp(&mut self, n: usize, val: super::vals::MemoryType) {
8684 assert!(n < 4usize);
8685 let offs = 2usize + n * 8usize;
8686 self.0 = (self.0 & !(0x0f << offs)) | (((val.to_bits() as u32) & 0x0f) << offs);
8687 }
8688 #[doc = "Indicate whether Atomic Memory Operation instructions (including LR/SC) are not supported in this region"]
8689 #[must_use]
8690 #[inline(always)]
8691 pub const fn namo(&self, n: usize) -> bool {
8692 assert!(n < 4usize);
8693 let offs = 6usize + n * 8usize;
8694 let val = (self.0 >> offs) & 0x01;
8695 val != 0
8696 }
8697 #[doc = "Indicate whether Atomic Memory Operation instructions (including LR/SC) are not supported in this region"]
8698 #[inline(always)]
8699 pub const fn set_namo(&mut self, n: usize, val: bool) {
8700 assert!(n < 4usize);
8701 let offs = 6usize + n * 8usize;
8702 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
8703 }
8704 }
8705 impl Default for Pmacfg {
8706 #[inline(always)]
8707 fn default() -> Pmacfg {
8708 Pmacfg(0)
8709 }
8710 }
8711 impl core::fmt::Debug for Pmacfg {
8712 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
8713 f.debug_struct("Pmacfg")
8714 .field("etyp[0]", &self.etyp(0usize))
8715 .field("etyp[1]", &self.etyp(1usize))
8716 .field("etyp[2]", &self.etyp(2usize))
8717 .field("etyp[3]", &self.etyp(3usize))
8718 .field("mtyp[0]", &self.mtyp(0usize))
8719 .field("mtyp[1]", &self.mtyp(1usize))
8720 .field("mtyp[2]", &self.mtyp(2usize))
8721 .field("mtyp[3]", &self.mtyp(3usize))
8722 .field("namo[0]", &self.namo(0usize))
8723 .field("namo[1]", &self.namo(1usize))
8724 .field("namo[2]", &self.namo(2usize))
8725 .field("namo[3]", &self.namo(3usize))
8726 .finish()
8727 }
8728 }
8729 #[cfg(feature = "defmt")]
8730 impl defmt::Format for Pmacfg {
8731 fn format(&self, f: defmt::Formatter) {
8732 defmt::write!(
8733 f,
8734 "Pmacfg {{ etyp[0]: {:?}, etyp[1]: {:?}, etyp[2]: {:?}, etyp[3]: {:?}, mtyp[0]: {:?}, mtyp[1]: {:?}, mtyp[2]: {:?}, mtyp[3]: {:?}, namo[0]: {=bool:?}, namo[1]: {=bool:?}, namo[2]: {=bool:?}, namo[3]: {=bool:?} }}",
8735 self.etyp(0usize),
8736 self.etyp(1usize),
8737 self.etyp(2usize),
8738 self.etyp(3usize),
8739 self.mtyp(0usize),
8740 self.mtyp(1usize),
8741 self.mtyp(2usize),
8742 self.mtyp(3usize),
8743 self.namo(0usize),
8744 self.namo(1usize),
8745 self.namo(2usize),
8746 self.namo(3usize)
8747 )
8748 }
8749 }
8750 #[inline(always)]
8751 unsafe fn _read() -> usize {
8752 let r: usize;
8753 unsafe {
8754 core :: arch :: asm ! ("csrrs {0}, 0xbc0, x0" , out (reg) r);
8755 }
8756 r
8757 }
8758 #[inline(always)]
8759 unsafe fn _write(bits: usize) {
8760 unsafe {
8761 core :: arch :: asm ! ("csrrw x0, 0xbc0, {0}" , in (reg) bits);
8762 }
8763 }
8764 #[inline(always)]
8765 unsafe fn _set(bits: usize) {
8766 unsafe {
8767 core :: arch :: asm ! ("csrrs x0, 0xbc0, {0}" , in (reg) bits);
8768 }
8769 }
8770 #[inline(always)]
8771 unsafe fn _clear(bits: usize) {
8772 unsafe {
8773 core :: arch :: asm ! ("csrrc x0, 0xbc0, {0}" , in (reg) bits);
8774 }
8775 }
8776 #[doc = r" Read the CSR value."]
8777 #[inline]
8778 pub fn read() -> Pmacfg {
8779 unsafe { Pmacfg(_read() as u32) }
8780 }
8781 #[doc = r" Write the CSR value."]
8782 #[inline]
8783 pub unsafe fn write(val: Pmacfg) {
8784 unsafe {
8785 _write(val.0 as usize);
8786 }
8787 }
8788 #[doc = r" Read-modify-write the CSR."]
8789 #[inline]
8790 pub unsafe fn modify<R>(f: impl FnOnce(&mut Pmacfg) -> R) -> R {
8791 let mut val = read();
8792 let res = f(&mut val);
8793 unsafe {
8794 write(val);
8795 }
8796 res
8797 }
8798}
8799#[doc = "PMA configuration"]
8800pub mod pmacfg2 {
8801 #[doc = "PMA Configuration Register"]
8802 #[repr(transparent)]
8803 #[derive(Copy, Clone, Eq, PartialEq)]
8804 pub struct Pmacfg(pub u32);
8805 impl Pmacfg {
8806 #[doc = "Entry address matching mode"]
8807 #[must_use]
8808 #[inline(always)]
8809 pub const fn etyp(&self, n: usize) -> super::vals::EntryType {
8810 assert!(n < 4usize);
8811 let offs = 0usize + n * 8usize;
8812 let val = (self.0 >> offs) & 0x03;
8813 super::vals::EntryType::from_bits(val as u8)
8814 }
8815 #[doc = "Entry address matching mode"]
8816 #[inline(always)]
8817 pub const fn set_etyp(&mut self, n: usize, val: super::vals::EntryType) {
8818 assert!(n < 4usize);
8819 let offs = 0usize + n * 8usize;
8820 self.0 = (self.0 & !(0x03 << offs)) | (((val.to_bits() as u32) & 0x03) << offs);
8821 }
8822 #[doc = "Memory type attribute"]
8823 #[must_use]
8824 #[inline(always)]
8825 pub const fn mtyp(&self, n: usize) -> super::vals::MemoryType {
8826 assert!(n < 4usize);
8827 let offs = 2usize + n * 8usize;
8828 let val = (self.0 >> offs) & 0x0f;
8829 super::vals::MemoryType::from_bits(val as u8)
8830 }
8831 #[doc = "Memory type attribute"]
8832 #[inline(always)]
8833 pub const fn set_mtyp(&mut self, n: usize, val: super::vals::MemoryType) {
8834 assert!(n < 4usize);
8835 let offs = 2usize + n * 8usize;
8836 self.0 = (self.0 & !(0x0f << offs)) | (((val.to_bits() as u32) & 0x0f) << offs);
8837 }
8838 #[doc = "Indicate whether Atomic Memory Operation instructions (including LR/SC) are not supported in this region"]
8839 #[must_use]
8840 #[inline(always)]
8841 pub const fn namo(&self, n: usize) -> bool {
8842 assert!(n < 4usize);
8843 let offs = 6usize + n * 8usize;
8844 let val = (self.0 >> offs) & 0x01;
8845 val != 0
8846 }
8847 #[doc = "Indicate whether Atomic Memory Operation instructions (including LR/SC) are not supported in this region"]
8848 #[inline(always)]
8849 pub const fn set_namo(&mut self, n: usize, val: bool) {
8850 assert!(n < 4usize);
8851 let offs = 6usize + n * 8usize;
8852 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
8853 }
8854 }
8855 impl Default for Pmacfg {
8856 #[inline(always)]
8857 fn default() -> Pmacfg {
8858 Pmacfg(0)
8859 }
8860 }
8861 impl core::fmt::Debug for Pmacfg {
8862 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
8863 f.debug_struct("Pmacfg")
8864 .field("etyp[0]", &self.etyp(0usize))
8865 .field("etyp[1]", &self.etyp(1usize))
8866 .field("etyp[2]", &self.etyp(2usize))
8867 .field("etyp[3]", &self.etyp(3usize))
8868 .field("mtyp[0]", &self.mtyp(0usize))
8869 .field("mtyp[1]", &self.mtyp(1usize))
8870 .field("mtyp[2]", &self.mtyp(2usize))
8871 .field("mtyp[3]", &self.mtyp(3usize))
8872 .field("namo[0]", &self.namo(0usize))
8873 .field("namo[1]", &self.namo(1usize))
8874 .field("namo[2]", &self.namo(2usize))
8875 .field("namo[3]", &self.namo(3usize))
8876 .finish()
8877 }
8878 }
8879 #[cfg(feature = "defmt")]
8880 impl defmt::Format for Pmacfg {
8881 fn format(&self, f: defmt::Formatter) {
8882 defmt::write!(
8883 f,
8884 "Pmacfg {{ etyp[0]: {:?}, etyp[1]: {:?}, etyp[2]: {:?}, etyp[3]: {:?}, mtyp[0]: {:?}, mtyp[1]: {:?}, mtyp[2]: {:?}, mtyp[3]: {:?}, namo[0]: {=bool:?}, namo[1]: {=bool:?}, namo[2]: {=bool:?}, namo[3]: {=bool:?} }}",
8885 self.etyp(0usize),
8886 self.etyp(1usize),
8887 self.etyp(2usize),
8888 self.etyp(3usize),
8889 self.mtyp(0usize),
8890 self.mtyp(1usize),
8891 self.mtyp(2usize),
8892 self.mtyp(3usize),
8893 self.namo(0usize),
8894 self.namo(1usize),
8895 self.namo(2usize),
8896 self.namo(3usize)
8897 )
8898 }
8899 }
8900 #[inline(always)]
8901 unsafe fn _read() -> usize {
8902 let r: usize;
8903 unsafe {
8904 core :: arch :: asm ! ("csrrs {0}, 0xbc0, x0" , out (reg) r);
8905 }
8906 r
8907 }
8908 #[inline(always)]
8909 unsafe fn _write(bits: usize) {
8910 unsafe {
8911 core :: arch :: asm ! ("csrrw x0, 0xbc0, {0}" , in (reg) bits);
8912 }
8913 }
8914 #[inline(always)]
8915 unsafe fn _set(bits: usize) {
8916 unsafe {
8917 core :: arch :: asm ! ("csrrs x0, 0xbc0, {0}" , in (reg) bits);
8918 }
8919 }
8920 #[inline(always)]
8921 unsafe fn _clear(bits: usize) {
8922 unsafe {
8923 core :: arch :: asm ! ("csrrc x0, 0xbc0, {0}" , in (reg) bits);
8924 }
8925 }
8926 #[doc = r" Read the CSR value."]
8927 #[inline]
8928 pub fn read() -> Pmacfg {
8929 unsafe { Pmacfg(_read() as u32) }
8930 }
8931 #[doc = r" Write the CSR value."]
8932 #[inline]
8933 pub unsafe fn write(val: Pmacfg) {
8934 unsafe {
8935 _write(val.0 as usize);
8936 }
8937 }
8938 #[doc = r" Read-modify-write the CSR."]
8939 #[inline]
8940 pub unsafe fn modify<R>(f: impl FnOnce(&mut Pmacfg) -> R) -> R {
8941 let mut val = read();
8942 let res = f(&mut val);
8943 unsafe {
8944 write(val);
8945 }
8946 res
8947 }
8948}
8949#[doc = "PMA configuration"]
8950pub mod pmacfg3 {
8951 #[doc = "PMA Configuration Register"]
8952 #[repr(transparent)]
8953 #[derive(Copy, Clone, Eq, PartialEq)]
8954 pub struct Pmacfg(pub u32);
8955 impl Pmacfg {
8956 #[doc = "Entry address matching mode"]
8957 #[must_use]
8958 #[inline(always)]
8959 pub const fn etyp(&self, n: usize) -> super::vals::EntryType {
8960 assert!(n < 4usize);
8961 let offs = 0usize + n * 8usize;
8962 let val = (self.0 >> offs) & 0x03;
8963 super::vals::EntryType::from_bits(val as u8)
8964 }
8965 #[doc = "Entry address matching mode"]
8966 #[inline(always)]
8967 pub const fn set_etyp(&mut self, n: usize, val: super::vals::EntryType) {
8968 assert!(n < 4usize);
8969 let offs = 0usize + n * 8usize;
8970 self.0 = (self.0 & !(0x03 << offs)) | (((val.to_bits() as u32) & 0x03) << offs);
8971 }
8972 #[doc = "Memory type attribute"]
8973 #[must_use]
8974 #[inline(always)]
8975 pub const fn mtyp(&self, n: usize) -> super::vals::MemoryType {
8976 assert!(n < 4usize);
8977 let offs = 2usize + n * 8usize;
8978 let val = (self.0 >> offs) & 0x0f;
8979 super::vals::MemoryType::from_bits(val as u8)
8980 }
8981 #[doc = "Memory type attribute"]
8982 #[inline(always)]
8983 pub const fn set_mtyp(&mut self, n: usize, val: super::vals::MemoryType) {
8984 assert!(n < 4usize);
8985 let offs = 2usize + n * 8usize;
8986 self.0 = (self.0 & !(0x0f << offs)) | (((val.to_bits() as u32) & 0x0f) << offs);
8987 }
8988 #[doc = "Indicate whether Atomic Memory Operation instructions (including LR/SC) are not supported in this region"]
8989 #[must_use]
8990 #[inline(always)]
8991 pub const fn namo(&self, n: usize) -> bool {
8992 assert!(n < 4usize);
8993 let offs = 6usize + n * 8usize;
8994 let val = (self.0 >> offs) & 0x01;
8995 val != 0
8996 }
8997 #[doc = "Indicate whether Atomic Memory Operation instructions (including LR/SC) are not supported in this region"]
8998 #[inline(always)]
8999 pub const fn set_namo(&mut self, n: usize, val: bool) {
9000 assert!(n < 4usize);
9001 let offs = 6usize + n * 8usize;
9002 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
9003 }
9004 }
9005 impl Default for Pmacfg {
9006 #[inline(always)]
9007 fn default() -> Pmacfg {
9008 Pmacfg(0)
9009 }
9010 }
9011 impl core::fmt::Debug for Pmacfg {
9012 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
9013 f.debug_struct("Pmacfg")
9014 .field("etyp[0]", &self.etyp(0usize))
9015 .field("etyp[1]", &self.etyp(1usize))
9016 .field("etyp[2]", &self.etyp(2usize))
9017 .field("etyp[3]", &self.etyp(3usize))
9018 .field("mtyp[0]", &self.mtyp(0usize))
9019 .field("mtyp[1]", &self.mtyp(1usize))
9020 .field("mtyp[2]", &self.mtyp(2usize))
9021 .field("mtyp[3]", &self.mtyp(3usize))
9022 .field("namo[0]", &self.namo(0usize))
9023 .field("namo[1]", &self.namo(1usize))
9024 .field("namo[2]", &self.namo(2usize))
9025 .field("namo[3]", &self.namo(3usize))
9026 .finish()
9027 }
9028 }
9029 #[cfg(feature = "defmt")]
9030 impl defmt::Format for Pmacfg {
9031 fn format(&self, f: defmt::Formatter) {
9032 defmt::write!(
9033 f,
9034 "Pmacfg {{ etyp[0]: {:?}, etyp[1]: {:?}, etyp[2]: {:?}, etyp[3]: {:?}, mtyp[0]: {:?}, mtyp[1]: {:?}, mtyp[2]: {:?}, mtyp[3]: {:?}, namo[0]: {=bool:?}, namo[1]: {=bool:?}, namo[2]: {=bool:?}, namo[3]: {=bool:?} }}",
9035 self.etyp(0usize),
9036 self.etyp(1usize),
9037 self.etyp(2usize),
9038 self.etyp(3usize),
9039 self.mtyp(0usize),
9040 self.mtyp(1usize),
9041 self.mtyp(2usize),
9042 self.mtyp(3usize),
9043 self.namo(0usize),
9044 self.namo(1usize),
9045 self.namo(2usize),
9046 self.namo(3usize)
9047 )
9048 }
9049 }
9050 #[inline(always)]
9051 unsafe fn _read() -> usize {
9052 let r: usize;
9053 unsafe {
9054 core :: arch :: asm ! ("csrrs {0}, 0xbc0, x0" , out (reg) r);
9055 }
9056 r
9057 }
9058 #[inline(always)]
9059 unsafe fn _write(bits: usize) {
9060 unsafe {
9061 core :: arch :: asm ! ("csrrw x0, 0xbc0, {0}" , in (reg) bits);
9062 }
9063 }
9064 #[inline(always)]
9065 unsafe fn _set(bits: usize) {
9066 unsafe {
9067 core :: arch :: asm ! ("csrrs x0, 0xbc0, {0}" , in (reg) bits);
9068 }
9069 }
9070 #[inline(always)]
9071 unsafe fn _clear(bits: usize) {
9072 unsafe {
9073 core :: arch :: asm ! ("csrrc x0, 0xbc0, {0}" , in (reg) bits);
9074 }
9075 }
9076 #[doc = r" Read the CSR value."]
9077 #[inline]
9078 pub fn read() -> Pmacfg {
9079 unsafe { Pmacfg(_read() as u32) }
9080 }
9081 #[doc = r" Write the CSR value."]
9082 #[inline]
9083 pub unsafe fn write(val: Pmacfg) {
9084 unsafe {
9085 _write(val.0 as usize);
9086 }
9087 }
9088 #[doc = r" Read-modify-write the CSR."]
9089 #[inline]
9090 pub unsafe fn modify<R>(f: impl FnOnce(&mut Pmacfg) -> R) -> R {
9091 let mut val = read();
9092 let res = f(&mut val);
9093 unsafe {
9094 write(val);
9095 }
9096 res
9097 }
9098}
9099#[doc = "PMA address"]
9100pub mod pmaaddr0 {
9101 #[inline(always)]
9102 unsafe fn _read() -> usize {
9103 let r: usize;
9104 unsafe {
9105 core :: arch :: asm ! ("csrrs {0}, 0xbd0, x0" , out (reg) r);
9106 }
9107 r
9108 }
9109 #[inline(always)]
9110 unsafe fn _write(bits: usize) {
9111 unsafe {
9112 core :: arch :: asm ! ("csrrw x0, 0xbd0, {0}" , in (reg) bits);
9113 }
9114 }
9115 #[inline(always)]
9116 unsafe fn _set(bits: usize) {
9117 unsafe {
9118 core :: arch :: asm ! ("csrrs x0, 0xbd0, {0}" , in (reg) bits);
9119 }
9120 }
9121 #[inline(always)]
9122 unsafe fn _clear(bits: usize) {
9123 unsafe {
9124 core :: arch :: asm ! ("csrrc x0, 0xbd0, {0}" , in (reg) bits);
9125 }
9126 }
9127 #[doc = r" Read the CSR value as raw usize."]
9128 #[inline]
9129 pub fn read() -> usize {
9130 unsafe { _read() }
9131 }
9132 #[doc = r" Write the CSR value as raw usize."]
9133 #[inline]
9134 pub unsafe fn write(val: usize) {
9135 unsafe {
9136 _write(val);
9137 }
9138 }
9139}
9140#[doc = "PMA address"]
9141pub mod pmaaddr1 {
9142 #[inline(always)]
9143 unsafe fn _read() -> usize {
9144 let r: usize;
9145 unsafe {
9146 core :: arch :: asm ! ("csrrs {0}, 0xbd1, x0" , out (reg) r);
9147 }
9148 r
9149 }
9150 #[inline(always)]
9151 unsafe fn _write(bits: usize) {
9152 unsafe {
9153 core :: arch :: asm ! ("csrrw x0, 0xbd1, {0}" , in (reg) bits);
9154 }
9155 }
9156 #[inline(always)]
9157 unsafe fn _set(bits: usize) {
9158 unsafe {
9159 core :: arch :: asm ! ("csrrs x0, 0xbd1, {0}" , in (reg) bits);
9160 }
9161 }
9162 #[inline(always)]
9163 unsafe fn _clear(bits: usize) {
9164 unsafe {
9165 core :: arch :: asm ! ("csrrc x0, 0xbd1, {0}" , in (reg) bits);
9166 }
9167 }
9168 #[doc = r" Read the CSR value as raw usize."]
9169 #[inline]
9170 pub fn read() -> usize {
9171 unsafe { _read() }
9172 }
9173 #[doc = r" Write the CSR value as raw usize."]
9174 #[inline]
9175 pub unsafe fn write(val: usize) {
9176 unsafe {
9177 _write(val);
9178 }
9179 }
9180}
9181#[doc = "PMA address"]
9182pub mod pmaaddr2 {
9183 #[inline(always)]
9184 unsafe fn _read() -> usize {
9185 let r: usize;
9186 unsafe {
9187 core :: arch :: asm ! ("csrrs {0}, 0xbd2, x0" , out (reg) r);
9188 }
9189 r
9190 }
9191 #[inline(always)]
9192 unsafe fn _write(bits: usize) {
9193 unsafe {
9194 core :: arch :: asm ! ("csrrw x0, 0xbd2, {0}" , in (reg) bits);
9195 }
9196 }
9197 #[inline(always)]
9198 unsafe fn _set(bits: usize) {
9199 unsafe {
9200 core :: arch :: asm ! ("csrrs x0, 0xbd2, {0}" , in (reg) bits);
9201 }
9202 }
9203 #[inline(always)]
9204 unsafe fn _clear(bits: usize) {
9205 unsafe {
9206 core :: arch :: asm ! ("csrrc x0, 0xbd2, {0}" , in (reg) bits);
9207 }
9208 }
9209 #[doc = r" Read the CSR value as raw usize."]
9210 #[inline]
9211 pub fn read() -> usize {
9212 unsafe { _read() }
9213 }
9214 #[doc = r" Write the CSR value as raw usize."]
9215 #[inline]
9216 pub unsafe fn write(val: usize) {
9217 unsafe {
9218 _write(val);
9219 }
9220 }
9221}
9222#[doc = "PMA address"]
9223pub mod pmaaddr3 {
9224 #[inline(always)]
9225 unsafe fn _read() -> usize {
9226 let r: usize;
9227 unsafe {
9228 core :: arch :: asm ! ("csrrs {0}, 0xbd3, x0" , out (reg) r);
9229 }
9230 r
9231 }
9232 #[inline(always)]
9233 unsafe fn _write(bits: usize) {
9234 unsafe {
9235 core :: arch :: asm ! ("csrrw x0, 0xbd3, {0}" , in (reg) bits);
9236 }
9237 }
9238 #[inline(always)]
9239 unsafe fn _set(bits: usize) {
9240 unsafe {
9241 core :: arch :: asm ! ("csrrs x0, 0xbd3, {0}" , in (reg) bits);
9242 }
9243 }
9244 #[inline(always)]
9245 unsafe fn _clear(bits: usize) {
9246 unsafe {
9247 core :: arch :: asm ! ("csrrc x0, 0xbd3, {0}" , in (reg) bits);
9248 }
9249 }
9250 #[doc = r" Read the CSR value as raw usize."]
9251 #[inline]
9252 pub fn read() -> usize {
9253 unsafe { _read() }
9254 }
9255 #[doc = r" Write the CSR value as raw usize."]
9256 #[inline]
9257 pub unsafe fn write(val: usize) {
9258 unsafe {
9259 _write(val);
9260 }
9261 }
9262}
9263#[doc = "PMA address"]
9264pub mod pmaaddr4 {
9265 #[inline(always)]
9266 unsafe fn _read() -> usize {
9267 let r: usize;
9268 unsafe {
9269 core :: arch :: asm ! ("csrrs {0}, 0xbd4, x0" , out (reg) r);
9270 }
9271 r
9272 }
9273 #[inline(always)]
9274 unsafe fn _write(bits: usize) {
9275 unsafe {
9276 core :: arch :: asm ! ("csrrw x0, 0xbd4, {0}" , in (reg) bits);
9277 }
9278 }
9279 #[inline(always)]
9280 unsafe fn _set(bits: usize) {
9281 unsafe {
9282 core :: arch :: asm ! ("csrrs x0, 0xbd4, {0}" , in (reg) bits);
9283 }
9284 }
9285 #[inline(always)]
9286 unsafe fn _clear(bits: usize) {
9287 unsafe {
9288 core :: arch :: asm ! ("csrrc x0, 0xbd4, {0}" , in (reg) bits);
9289 }
9290 }
9291 #[doc = r" Read the CSR value as raw usize."]
9292 #[inline]
9293 pub fn read() -> usize {
9294 unsafe { _read() }
9295 }
9296 #[doc = r" Write the CSR value as raw usize."]
9297 #[inline]
9298 pub unsafe fn write(val: usize) {
9299 unsafe {
9300 _write(val);
9301 }
9302 }
9303}
9304#[doc = "PMA address"]
9305pub mod pmaaddr5 {
9306 #[inline(always)]
9307 unsafe fn _read() -> usize {
9308 let r: usize;
9309 unsafe {
9310 core :: arch :: asm ! ("csrrs {0}, 0xbd5, x0" , out (reg) r);
9311 }
9312 r
9313 }
9314 #[inline(always)]
9315 unsafe fn _write(bits: usize) {
9316 unsafe {
9317 core :: arch :: asm ! ("csrrw x0, 0xbd5, {0}" , in (reg) bits);
9318 }
9319 }
9320 #[inline(always)]
9321 unsafe fn _set(bits: usize) {
9322 unsafe {
9323 core :: arch :: asm ! ("csrrs x0, 0xbd5, {0}" , in (reg) bits);
9324 }
9325 }
9326 #[inline(always)]
9327 unsafe fn _clear(bits: usize) {
9328 unsafe {
9329 core :: arch :: asm ! ("csrrc x0, 0xbd5, {0}" , in (reg) bits);
9330 }
9331 }
9332 #[doc = r" Read the CSR value as raw usize."]
9333 #[inline]
9334 pub fn read() -> usize {
9335 unsafe { _read() }
9336 }
9337 #[doc = r" Write the CSR value as raw usize."]
9338 #[inline]
9339 pub unsafe fn write(val: usize) {
9340 unsafe {
9341 _write(val);
9342 }
9343 }
9344}
9345#[doc = "PMA address"]
9346pub mod pmaaddr6 {
9347 #[inline(always)]
9348 unsafe fn _read() -> usize {
9349 let r: usize;
9350 unsafe {
9351 core :: arch :: asm ! ("csrrs {0}, 0xbd6, x0" , out (reg) r);
9352 }
9353 r
9354 }
9355 #[inline(always)]
9356 unsafe fn _write(bits: usize) {
9357 unsafe {
9358 core :: arch :: asm ! ("csrrw x0, 0xbd6, {0}" , in (reg) bits);
9359 }
9360 }
9361 #[inline(always)]
9362 unsafe fn _set(bits: usize) {
9363 unsafe {
9364 core :: arch :: asm ! ("csrrs x0, 0xbd6, {0}" , in (reg) bits);
9365 }
9366 }
9367 #[inline(always)]
9368 unsafe fn _clear(bits: usize) {
9369 unsafe {
9370 core :: arch :: asm ! ("csrrc x0, 0xbd6, {0}" , in (reg) bits);
9371 }
9372 }
9373 #[doc = r" Read the CSR value as raw usize."]
9374 #[inline]
9375 pub fn read() -> usize {
9376 unsafe { _read() }
9377 }
9378 #[doc = r" Write the CSR value as raw usize."]
9379 #[inline]
9380 pub unsafe fn write(val: usize) {
9381 unsafe {
9382 _write(val);
9383 }
9384 }
9385}
9386#[doc = "PMA address"]
9387pub mod pmaaddr7 {
9388 #[inline(always)]
9389 unsafe fn _read() -> usize {
9390 let r: usize;
9391 unsafe {
9392 core :: arch :: asm ! ("csrrs {0}, 0xbd7, x0" , out (reg) r);
9393 }
9394 r
9395 }
9396 #[inline(always)]
9397 unsafe fn _write(bits: usize) {
9398 unsafe {
9399 core :: arch :: asm ! ("csrrw x0, 0xbd7, {0}" , in (reg) bits);
9400 }
9401 }
9402 #[inline(always)]
9403 unsafe fn _set(bits: usize) {
9404 unsafe {
9405 core :: arch :: asm ! ("csrrs x0, 0xbd7, {0}" , in (reg) bits);
9406 }
9407 }
9408 #[inline(always)]
9409 unsafe fn _clear(bits: usize) {
9410 unsafe {
9411 core :: arch :: asm ! ("csrrc x0, 0xbd7, {0}" , in (reg) bits);
9412 }
9413 }
9414 #[doc = r" Read the CSR value as raw usize."]
9415 #[inline]
9416 pub fn read() -> usize {
9417 unsafe { _read() }
9418 }
9419 #[doc = r" Write the CSR value as raw usize."]
9420 #[inline]
9421 pub unsafe fn write(val: usize) {
9422 unsafe {
9423 _write(val);
9424 }
9425 }
9426}
9427#[doc = "PMA address"]
9428pub mod pmaaddr8 {
9429 #[inline(always)]
9430 unsafe fn _read() -> usize {
9431 let r: usize;
9432 unsafe {
9433 core :: arch :: asm ! ("csrrs {0}, 0xbd8, x0" , out (reg) r);
9434 }
9435 r
9436 }
9437 #[inline(always)]
9438 unsafe fn _write(bits: usize) {
9439 unsafe {
9440 core :: arch :: asm ! ("csrrw x0, 0xbd8, {0}" , in (reg) bits);
9441 }
9442 }
9443 #[inline(always)]
9444 unsafe fn _set(bits: usize) {
9445 unsafe {
9446 core :: arch :: asm ! ("csrrs x0, 0xbd8, {0}" , in (reg) bits);
9447 }
9448 }
9449 #[inline(always)]
9450 unsafe fn _clear(bits: usize) {
9451 unsafe {
9452 core :: arch :: asm ! ("csrrc x0, 0xbd8, {0}" , in (reg) bits);
9453 }
9454 }
9455 #[doc = r" Read the CSR value as raw usize."]
9456 #[inline]
9457 pub fn read() -> usize {
9458 unsafe { _read() }
9459 }
9460 #[doc = r" Write the CSR value as raw usize."]
9461 #[inline]
9462 pub unsafe fn write(val: usize) {
9463 unsafe {
9464 _write(val);
9465 }
9466 }
9467}
9468#[doc = "PMA address"]
9469pub mod pmaaddr9 {
9470 #[inline(always)]
9471 unsafe fn _read() -> usize {
9472 let r: usize;
9473 unsafe {
9474 core :: arch :: asm ! ("csrrs {0}, 0xbd9, x0" , out (reg) r);
9475 }
9476 r
9477 }
9478 #[inline(always)]
9479 unsafe fn _write(bits: usize) {
9480 unsafe {
9481 core :: arch :: asm ! ("csrrw x0, 0xbd9, {0}" , in (reg) bits);
9482 }
9483 }
9484 #[inline(always)]
9485 unsafe fn _set(bits: usize) {
9486 unsafe {
9487 core :: arch :: asm ! ("csrrs x0, 0xbd9, {0}" , in (reg) bits);
9488 }
9489 }
9490 #[inline(always)]
9491 unsafe fn _clear(bits: usize) {
9492 unsafe {
9493 core :: arch :: asm ! ("csrrc x0, 0xbd9, {0}" , in (reg) bits);
9494 }
9495 }
9496 #[doc = r" Read the CSR value as raw usize."]
9497 #[inline]
9498 pub fn read() -> usize {
9499 unsafe { _read() }
9500 }
9501 #[doc = r" Write the CSR value as raw usize."]
9502 #[inline]
9503 pub unsafe fn write(val: usize) {
9504 unsafe {
9505 _write(val);
9506 }
9507 }
9508}
9509#[doc = "PMA address"]
9510pub mod pmaaddr10 {
9511 #[inline(always)]
9512 unsafe fn _read() -> usize {
9513 let r: usize;
9514 unsafe {
9515 core :: arch :: asm ! ("csrrs {0}, 0xbda, x0" , out (reg) r);
9516 }
9517 r
9518 }
9519 #[inline(always)]
9520 unsafe fn _write(bits: usize) {
9521 unsafe {
9522 core :: arch :: asm ! ("csrrw x0, 0xbda, {0}" , in (reg) bits);
9523 }
9524 }
9525 #[inline(always)]
9526 unsafe fn _set(bits: usize) {
9527 unsafe {
9528 core :: arch :: asm ! ("csrrs x0, 0xbda, {0}" , in (reg) bits);
9529 }
9530 }
9531 #[inline(always)]
9532 unsafe fn _clear(bits: usize) {
9533 unsafe {
9534 core :: arch :: asm ! ("csrrc x0, 0xbda, {0}" , in (reg) bits);
9535 }
9536 }
9537 #[doc = r" Read the CSR value as raw usize."]
9538 #[inline]
9539 pub fn read() -> usize {
9540 unsafe { _read() }
9541 }
9542 #[doc = r" Write the CSR value as raw usize."]
9543 #[inline]
9544 pub unsafe fn write(val: usize) {
9545 unsafe {
9546 _write(val);
9547 }
9548 }
9549}
9550#[doc = "PMA address"]
9551pub mod pmaaddr11 {
9552 #[inline(always)]
9553 unsafe fn _read() -> usize {
9554 let r: usize;
9555 unsafe {
9556 core :: arch :: asm ! ("csrrs {0}, 0xbdb, x0" , out (reg) r);
9557 }
9558 r
9559 }
9560 #[inline(always)]
9561 unsafe fn _write(bits: usize) {
9562 unsafe {
9563 core :: arch :: asm ! ("csrrw x0, 0xbdb, {0}" , in (reg) bits);
9564 }
9565 }
9566 #[inline(always)]
9567 unsafe fn _set(bits: usize) {
9568 unsafe {
9569 core :: arch :: asm ! ("csrrs x0, 0xbdb, {0}" , in (reg) bits);
9570 }
9571 }
9572 #[inline(always)]
9573 unsafe fn _clear(bits: usize) {
9574 unsafe {
9575 core :: arch :: asm ! ("csrrc x0, 0xbdb, {0}" , in (reg) bits);
9576 }
9577 }
9578 #[doc = r" Read the CSR value as raw usize."]
9579 #[inline]
9580 pub fn read() -> usize {
9581 unsafe { _read() }
9582 }
9583 #[doc = r" Write the CSR value as raw usize."]
9584 #[inline]
9585 pub unsafe fn write(val: usize) {
9586 unsafe {
9587 _write(val);
9588 }
9589 }
9590}
9591#[doc = "PMA address"]
9592pub mod pmaaddr12 {
9593 #[inline(always)]
9594 unsafe fn _read() -> usize {
9595 let r: usize;
9596 unsafe {
9597 core :: arch :: asm ! ("csrrs {0}, 0xbdc, x0" , out (reg) r);
9598 }
9599 r
9600 }
9601 #[inline(always)]
9602 unsafe fn _write(bits: usize) {
9603 unsafe {
9604 core :: arch :: asm ! ("csrrw x0, 0xbdc, {0}" , in (reg) bits);
9605 }
9606 }
9607 #[inline(always)]
9608 unsafe fn _set(bits: usize) {
9609 unsafe {
9610 core :: arch :: asm ! ("csrrs x0, 0xbdc, {0}" , in (reg) bits);
9611 }
9612 }
9613 #[inline(always)]
9614 unsafe fn _clear(bits: usize) {
9615 unsafe {
9616 core :: arch :: asm ! ("csrrc x0, 0xbdc, {0}" , in (reg) bits);
9617 }
9618 }
9619 #[doc = r" Read the CSR value as raw usize."]
9620 #[inline]
9621 pub fn read() -> usize {
9622 unsafe { _read() }
9623 }
9624 #[doc = r" Write the CSR value as raw usize."]
9625 #[inline]
9626 pub unsafe fn write(val: usize) {
9627 unsafe {
9628 _write(val);
9629 }
9630 }
9631}
9632#[doc = "PMA address"]
9633pub mod pmaaddr13 {
9634 #[inline(always)]
9635 unsafe fn _read() -> usize {
9636 let r: usize;
9637 unsafe {
9638 core :: arch :: asm ! ("csrrs {0}, 0xbdd, x0" , out (reg) r);
9639 }
9640 r
9641 }
9642 #[inline(always)]
9643 unsafe fn _write(bits: usize) {
9644 unsafe {
9645 core :: arch :: asm ! ("csrrw x0, 0xbdd, {0}" , in (reg) bits);
9646 }
9647 }
9648 #[inline(always)]
9649 unsafe fn _set(bits: usize) {
9650 unsafe {
9651 core :: arch :: asm ! ("csrrs x0, 0xbdd, {0}" , in (reg) bits);
9652 }
9653 }
9654 #[inline(always)]
9655 unsafe fn _clear(bits: usize) {
9656 unsafe {
9657 core :: arch :: asm ! ("csrrc x0, 0xbdd, {0}" , in (reg) bits);
9658 }
9659 }
9660 #[doc = r" Read the CSR value as raw usize."]
9661 #[inline]
9662 pub fn read() -> usize {
9663 unsafe { _read() }
9664 }
9665 #[doc = r" Write the CSR value as raw usize."]
9666 #[inline]
9667 pub unsafe fn write(val: usize) {
9668 unsafe {
9669 _write(val);
9670 }
9671 }
9672}
9673#[doc = "PMA address"]
9674pub mod pmaaddr14 {
9675 #[inline(always)]
9676 unsafe fn _read() -> usize {
9677 let r: usize;
9678 unsafe {
9679 core :: arch :: asm ! ("csrrs {0}, 0xbde, x0" , out (reg) r);
9680 }
9681 r
9682 }
9683 #[inline(always)]
9684 unsafe fn _write(bits: usize) {
9685 unsafe {
9686 core :: arch :: asm ! ("csrrw x0, 0xbde, {0}" , in (reg) bits);
9687 }
9688 }
9689 #[inline(always)]
9690 unsafe fn _set(bits: usize) {
9691 unsafe {
9692 core :: arch :: asm ! ("csrrs x0, 0xbde, {0}" , in (reg) bits);
9693 }
9694 }
9695 #[inline(always)]
9696 unsafe fn _clear(bits: usize) {
9697 unsafe {
9698 core :: arch :: asm ! ("csrrc x0, 0xbde, {0}" , in (reg) bits);
9699 }
9700 }
9701 #[doc = r" Read the CSR value as raw usize."]
9702 #[inline]
9703 pub fn read() -> usize {
9704 unsafe { _read() }
9705 }
9706 #[doc = r" Write the CSR value as raw usize."]
9707 #[inline]
9708 pub unsafe fn write(val: usize) {
9709 unsafe {
9710 _write(val);
9711 }
9712 }
9713}
9714#[doc = "PMA address"]
9715pub mod pmaaddr15 {
9716 #[inline(always)]
9717 unsafe fn _read() -> usize {
9718 let r: usize;
9719 unsafe {
9720 core :: arch :: asm ! ("csrrs {0}, 0xbdf, x0" , out (reg) r);
9721 }
9722 r
9723 }
9724 #[inline(always)]
9725 unsafe fn _write(bits: usize) {
9726 unsafe {
9727 core :: arch :: asm ! ("csrrw x0, 0xbdf, {0}" , in (reg) bits);
9728 }
9729 }
9730 #[inline(always)]
9731 unsafe fn _set(bits: usize) {
9732 unsafe {
9733 core :: arch :: asm ! ("csrrs x0, 0xbdf, {0}" , in (reg) bits);
9734 }
9735 }
9736 #[inline(always)]
9737 unsafe fn _clear(bits: usize) {
9738 unsafe {
9739 core :: arch :: asm ! ("csrrc x0, 0xbdf, {0}" , in (reg) bits);
9740 }
9741 }
9742 #[doc = r" Read the CSR value as raw usize."]
9743 #[inline]
9744 pub fn read() -> usize {
9745 unsafe { _read() }
9746 }
9747 #[doc = r" Write the CSR value as raw usize."]
9748 #[inline]
9749 pub unsafe fn write(val: usize) {
9750 unsafe {
9751 _write(val);
9752 }
9753 }
9754}
9755#[doc = "Instruction cache/memory configuration"]
9756pub mod micm_cfg {
9757 #[doc = "Instruction Cache/Memory Configuration Register"]
9758 #[repr(transparent)]
9759 #[derive(Copy, Clone, Eq, PartialEq)]
9760 pub struct MicmCfg(pub u32);
9761 impl MicmCfg {
9762 #[must_use]
9763 #[inline(always)]
9764 pub const fn iset(&self) -> u8 {
9765 let val = (self.0 >> 0usize) & 0x07;
9766 val as u8
9767 }
9768 #[inline(always)]
9769 pub const fn set_iset(&mut self, val: u8) {
9770 self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
9771 }
9772 #[must_use]
9773 #[inline(always)]
9774 pub const fn iway(&self) -> u8 {
9775 let val = (self.0 >> 3usize) & 0x07;
9776 val as u8
9777 }
9778 #[inline(always)]
9779 pub const fn set_iway(&mut self, val: u8) {
9780 self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize);
9781 }
9782 #[must_use]
9783 #[inline(always)]
9784 pub const fn isz(&self) -> u8 {
9785 let val = (self.0 >> 6usize) & 0x07;
9786 val as u8
9787 }
9788 #[inline(always)]
9789 pub const fn set_isz(&mut self, val: u8) {
9790 self.0 = (self.0 & !(0x07 << 6usize)) | (((val as u32) & 0x07) << 6usize);
9791 }
9792 #[must_use]
9793 #[inline(always)]
9794 pub const fn ilck(&self) -> bool {
9795 let val = (self.0 >> 9usize) & 0x01;
9796 val != 0
9797 }
9798 #[inline(always)]
9799 pub const fn set_ilck(&mut self, val: bool) {
9800 self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
9801 }
9802 #[must_use]
9803 #[inline(always)]
9804 pub const fn ic_ecc(&self) -> u8 {
9805 let val = (self.0 >> 10usize) & 0x03;
9806 val as u8
9807 }
9808 #[inline(always)]
9809 pub const fn set_ic_ecc(&mut self, val: u8) {
9810 self.0 = (self.0 & !(0x03 << 10usize)) | (((val as u32) & 0x03) << 10usize);
9811 }
9812 #[must_use]
9813 #[inline(always)]
9814 pub const fn ilmb(&self) -> u8 {
9815 let val = (self.0 >> 12usize) & 0x07;
9816 val as u8
9817 }
9818 #[inline(always)]
9819 pub const fn set_ilmb(&mut self, val: u8) {
9820 self.0 = (self.0 & !(0x07 << 12usize)) | (((val as u32) & 0x07) << 12usize);
9821 }
9822 #[must_use]
9823 #[inline(always)]
9824 pub const fn ilmsz(&self) -> u8 {
9825 let val = (self.0 >> 15usize) & 0x1f;
9826 val as u8
9827 }
9828 #[inline(always)]
9829 pub const fn set_ilmsz(&mut self, val: u8) {
9830 self.0 = (self.0 & !(0x1f << 15usize)) | (((val as u32) & 0x1f) << 15usize);
9831 }
9832 #[must_use]
9833 #[inline(always)]
9834 pub const fn ulm_2bank(&self) -> bool {
9835 let val = (self.0 >> 20usize) & 0x01;
9836 val != 0
9837 }
9838 #[inline(always)]
9839 pub const fn set_ulm_2bank(&mut self, val: bool) {
9840 self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
9841 }
9842 #[must_use]
9843 #[inline(always)]
9844 pub const fn ilm_ecc(&self) -> u8 {
9845 let val = (self.0 >> 21usize) & 0x03;
9846 val as u8
9847 }
9848 #[inline(always)]
9849 pub const fn set_ilm_ecc(&mut self, val: u8) {
9850 self.0 = (self.0 & !(0x03 << 21usize)) | (((val as u32) & 0x03) << 21usize);
9851 }
9852 #[must_use]
9853 #[inline(always)]
9854 pub const fn ilm_xonly(&self) -> bool {
9855 let val = (self.0 >> 23usize) & 0x01;
9856 val != 0
9857 }
9858 #[inline(always)]
9859 pub const fn set_ilm_xonly(&mut self, val: bool) {
9860 self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
9861 }
9862 #[must_use]
9863 #[inline(always)]
9864 pub const fn seth(&self) -> bool {
9865 let val = (self.0 >> 24usize) & 0x01;
9866 val != 0
9867 }
9868 #[inline(always)]
9869 pub const fn set_seth(&mut self, val: bool) {
9870 self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
9871 }
9872 #[must_use]
9873 #[inline(always)]
9874 pub const fn ic_repl(&self) -> u8 {
9875 let val = (self.0 >> 25usize) & 0x03;
9876 val as u8
9877 }
9878 #[inline(always)]
9879 pub const fn set_ic_repl(&mut self, val: u8) {
9880 self.0 = (self.0 & !(0x03 << 25usize)) | (((val as u32) & 0x03) << 25usize);
9881 }
9882 }
9883 impl Default for MicmCfg {
9884 #[inline(always)]
9885 fn default() -> MicmCfg {
9886 MicmCfg(0)
9887 }
9888 }
9889 impl core::fmt::Debug for MicmCfg {
9890 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
9891 f.debug_struct("MicmCfg")
9892 .field("iset", &self.iset())
9893 .field("iway", &self.iway())
9894 .field("isz", &self.isz())
9895 .field("ilck", &self.ilck())
9896 .field("ic_ecc", &self.ic_ecc())
9897 .field("ilmb", &self.ilmb())
9898 .field("ilmsz", &self.ilmsz())
9899 .field("ulm_2bank", &self.ulm_2bank())
9900 .field("ilm_ecc", &self.ilm_ecc())
9901 .field("ilm_xonly", &self.ilm_xonly())
9902 .field("seth", &self.seth())
9903 .field("ic_repl", &self.ic_repl())
9904 .finish()
9905 }
9906 }
9907 #[cfg(feature = "defmt")]
9908 impl defmt::Format for MicmCfg {
9909 fn format(&self, f: defmt::Formatter) {
9910 defmt::write!(
9911 f,
9912 "MicmCfg {{ iset: {=u8:?}, iway: {=u8:?}, isz: {=u8:?}, ilck: {=bool:?}, ic_ecc: {=u8:?}, ilmb: {=u8:?}, ilmsz: {=u8:?}, ulm_2bank: {=bool:?}, ilm_ecc: {=u8:?}, ilm_xonly: {=bool:?}, seth: {=bool:?}, ic_repl: {=u8:?} }}",
9913 self.iset(),
9914 self.iway(),
9915 self.isz(),
9916 self.ilck(),
9917 self.ic_ecc(),
9918 self.ilmb(),
9919 self.ilmsz(),
9920 self.ulm_2bank(),
9921 self.ilm_ecc(),
9922 self.ilm_xonly(),
9923 self.seth(),
9924 self.ic_repl()
9925 )
9926 }
9927 }
9928 #[inline(always)]
9929 unsafe fn _read() -> usize {
9930 let r: usize;
9931 unsafe {
9932 core :: arch :: asm ! ("csrrs {0}, 0xfc0, x0" , out (reg) r);
9933 }
9934 r
9935 }
9936 #[doc = r" Read the CSR value."]
9937 #[inline]
9938 pub fn read() -> MicmCfg {
9939 unsafe { MicmCfg(_read() as u32) }
9940 }
9941}
9942#[doc = "Data cache/memory configuration"]
9943pub mod mdcm_cfg {
9944 #[doc = "Data Cache/Memory Configuration Register"]
9945 #[repr(transparent)]
9946 #[derive(Copy, Clone, Eq, PartialEq)]
9947 pub struct MdcmCfg(pub u32);
9948 impl MdcmCfg {
9949 #[must_use]
9950 #[inline(always)]
9951 pub const fn dset(&self) -> u8 {
9952 let val = (self.0 >> 0usize) & 0x07;
9953 val as u8
9954 }
9955 #[inline(always)]
9956 pub const fn set_dset(&mut self, val: u8) {
9957 self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
9958 }
9959 #[must_use]
9960 #[inline(always)]
9961 pub const fn dway(&self) -> u8 {
9962 let val = (self.0 >> 3usize) & 0x07;
9963 val as u8
9964 }
9965 #[inline(always)]
9966 pub const fn set_dway(&mut self, val: u8) {
9967 self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize);
9968 }
9969 #[must_use]
9970 #[inline(always)]
9971 pub const fn dsz(&self) -> u8 {
9972 let val = (self.0 >> 6usize) & 0x07;
9973 val as u8
9974 }
9975 #[inline(always)]
9976 pub const fn set_dsz(&mut self, val: u8) {
9977 self.0 = (self.0 & !(0x07 << 6usize)) | (((val as u32) & 0x07) << 6usize);
9978 }
9979 #[must_use]
9980 #[inline(always)]
9981 pub const fn dlck(&self) -> bool {
9982 let val = (self.0 >> 9usize) & 0x01;
9983 val != 0
9984 }
9985 #[inline(always)]
9986 pub const fn set_dlck(&mut self, val: bool) {
9987 self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
9988 }
9989 #[must_use]
9990 #[inline(always)]
9991 pub const fn dc_ecc(&self) -> u8 {
9992 let val = (self.0 >> 10usize) & 0x03;
9993 val as u8
9994 }
9995 #[inline(always)]
9996 pub const fn set_dc_ecc(&mut self, val: u8) {
9997 self.0 = (self.0 & !(0x03 << 10usize)) | (((val as u32) & 0x03) << 10usize);
9998 }
9999 #[must_use]
10000 #[inline(always)]
10001 pub const fn dlmb(&self) -> u8 {
10002 let val = (self.0 >> 12usize) & 0x07;
10003 val as u8
10004 }
10005 #[inline(always)]
10006 pub const fn set_dlmb(&mut self, val: u8) {
10007 self.0 = (self.0 & !(0x07 << 12usize)) | (((val as u32) & 0x07) << 12usize);
10008 }
10009 #[must_use]
10010 #[inline(always)]
10011 pub const fn dlmsz(&self) -> u8 {
10012 let val = (self.0 >> 15usize) & 0x1f;
10013 val as u8
10014 }
10015 #[inline(always)]
10016 pub const fn set_dlmsz(&mut self, val: u8) {
10017 self.0 = (self.0 & !(0x1f << 15usize)) | (((val as u32) & 0x1f) << 15usize);
10018 }
10019 #[must_use]
10020 #[inline(always)]
10021 pub const fn ulm_2bank(&self) -> bool {
10022 let val = (self.0 >> 20usize) & 0x01;
10023 val != 0
10024 }
10025 #[inline(always)]
10026 pub const fn set_ulm_2bank(&mut self, val: bool) {
10027 self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
10028 }
10029 #[must_use]
10030 #[inline(always)]
10031 pub const fn dlm_ecc(&self) -> u8 {
10032 let val = (self.0 >> 21usize) & 0x03;
10033 val as u8
10034 }
10035 #[inline(always)]
10036 pub const fn set_dlm_ecc(&mut self, val: u8) {
10037 self.0 = (self.0 & !(0x03 << 21usize)) | (((val as u32) & 0x03) << 21usize);
10038 }
10039 #[must_use]
10040 #[inline(always)]
10041 pub const fn seth(&self) -> bool {
10042 let val = (self.0 >> 24usize) & 0x01;
10043 val != 0
10044 }
10045 #[inline(always)]
10046 pub const fn set_seth(&mut self, val: bool) {
10047 self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
10048 }
10049 #[must_use]
10050 #[inline(always)]
10051 pub const fn dc_repl(&self) -> u8 {
10052 let val = (self.0 >> 25usize) & 0x03;
10053 val as u8
10054 }
10055 #[inline(always)]
10056 pub const fn set_dc_repl(&mut self, val: u8) {
10057 self.0 = (self.0 & !(0x03 << 25usize)) | (((val as u32) & 0x03) << 25usize);
10058 }
10059 }
10060 impl Default for MdcmCfg {
10061 #[inline(always)]
10062 fn default() -> MdcmCfg {
10063 MdcmCfg(0)
10064 }
10065 }
10066 impl core::fmt::Debug for MdcmCfg {
10067 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
10068 f.debug_struct("MdcmCfg")
10069 .field("dset", &self.dset())
10070 .field("dway", &self.dway())
10071 .field("dsz", &self.dsz())
10072 .field("dlck", &self.dlck())
10073 .field("dc_ecc", &self.dc_ecc())
10074 .field("dlmb", &self.dlmb())
10075 .field("dlmsz", &self.dlmsz())
10076 .field("ulm_2bank", &self.ulm_2bank())
10077 .field("dlm_ecc", &self.dlm_ecc())
10078 .field("seth", &self.seth())
10079 .field("dc_repl", &self.dc_repl())
10080 .finish()
10081 }
10082 }
10083 #[cfg(feature = "defmt")]
10084 impl defmt::Format for MdcmCfg {
10085 fn format(&self, f: defmt::Formatter) {
10086 defmt::write!(
10087 f,
10088 "MdcmCfg {{ dset: {=u8:?}, dway: {=u8:?}, dsz: {=u8:?}, dlck: {=bool:?}, dc_ecc: {=u8:?}, dlmb: {=u8:?}, dlmsz: {=u8:?}, ulm_2bank: {=bool:?}, dlm_ecc: {=u8:?}, seth: {=bool:?}, dc_repl: {=u8:?} }}",
10089 self.dset(),
10090 self.dway(),
10091 self.dsz(),
10092 self.dlck(),
10093 self.dc_ecc(),
10094 self.dlmb(),
10095 self.dlmsz(),
10096 self.ulm_2bank(),
10097 self.dlm_ecc(),
10098 self.seth(),
10099 self.dc_repl()
10100 )
10101 }
10102 }
10103 #[inline(always)]
10104 unsafe fn _read() -> usize {
10105 let r: usize;
10106 unsafe {
10107 core :: arch :: asm ! ("csrrs {0}, 0xfc1, x0" , out (reg) r);
10108 }
10109 r
10110 }
10111 #[doc = r" Read the CSR value."]
10112 #[inline]
10113 pub fn read() -> MdcmCfg {
10114 unsafe { MdcmCfg(_read() as u32) }
10115 }
10116}
10117#[doc = "Miscellaneous configuration"]
10118pub mod mmsc_cfg {
10119 #[doc = "Misc. Configuration Register"]
10120 #[repr(transparent)]
10121 #[derive(Copy, Clone, Eq, PartialEq)]
10122 pub struct MmscCfg(pub u32);
10123 impl MmscCfg {
10124 #[doc = "Global configuration for parity/ECC support"]
10125 #[must_use]
10126 #[inline(always)]
10127 pub const fn ecc(&self) -> bool {
10128 let val = (self.0 >> 0usize) & 0x01;
10129 val != 0
10130 }
10131 #[doc = "Global configuration for parity/ECC support"]
10132 #[inline(always)]
10133 pub const fn set_ecc(&mut self, val: bool) {
10134 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
10135 }
10136 #[doc = "TLB parity/ECC support configuration"]
10137 #[must_use]
10138 #[inline(always)]
10139 pub const fn tlb_ecc(&self) -> u8 {
10140 let val = (self.0 >> 1usize) & 0x03;
10141 val as u8
10142 }
10143 #[doc = "TLB parity/ECC support configuration"]
10144 #[inline(always)]
10145 pub const fn set_tlb_ecc(&mut self, val: u8) {
10146 self.0 = (self.0 & !(0x03 << 1usize)) | (((val as u32) & 0x03) << 1usize);
10147 }
10148 #[doc = "Indicates whether CodeDense extension is supported or not"]
10149 #[must_use]
10150 #[inline(always)]
10151 pub const fn ecd(&self) -> bool {
10152 let val = (self.0 >> 3usize) & 0x01;
10153 val != 0
10154 }
10155 #[doc = "Indicates whether CodeDense extension is supported or not"]
10156 #[inline(always)]
10157 pub const fn set_ecd(&mut self, val: bool) {
10158 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
10159 }
10160 #[doc = "Indicates if the PowerBrake (Performance Throttling) feature exists or not"]
10161 #[must_use]
10162 #[inline(always)]
10163 pub const fn pft(&self) -> bool {
10164 let val = (self.0 >> 4usize) & 0x01;
10165 val != 0
10166 }
10167 #[doc = "Indicates if the PowerBrake (Performance Throttling) feature exists or not"]
10168 #[inline(always)]
10169 pub const fn set_pft(&mut self, val: bool) {
10170 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
10171 }
10172 #[doc = "Indicates if the HW Stack protection and recording mechanism exists or not"]
10173 #[must_use]
10174 #[inline(always)]
10175 pub const fn hsp(&self) -> bool {
10176 let val = (self.0 >> 5usize) & 0x01;
10177 val != 0
10178 }
10179 #[doc = "Indicates if the HW Stack protection and recording mechanism exists or not"]
10180 #[inline(always)]
10181 pub const fn set_hsp(&mut self, val: bool) {
10182 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
10183 }
10184 #[doc = "Indicates if Andes Custom Extension exists or not"]
10185 #[must_use]
10186 #[inline(always)]
10187 pub const fn ace(&self) -> bool {
10188 let val = (self.0 >> 6usize) & 0x01;
10189 val != 0
10190 }
10191 #[doc = "Indicates if Andes Custom Extension exists or not"]
10192 #[inline(always)]
10193 pub const fn set_ace(&mut self, val: bool) {
10194 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
10195 }
10196 #[doc = "Indicates the number of additional PM counters from counter3 to counter31"]
10197 #[must_use]
10198 #[inline(always)]
10199 pub const fn addpmc(&self) -> u8 {
10200 let val = (self.0 >> 7usize) & 0x1f;
10201 val as u8
10202 }
10203 #[doc = "Indicates the number of additional PM counters from counter3 to counter31"]
10204 #[inline(always)]
10205 pub const fn set_addpmc(&mut self, val: u8) {
10206 self.0 = (self.0 & !(0x1f << 7usize)) | (((val as u32) & 0x1f) << 7usize);
10207 }
10208 #[doc = "Indicates if vectored PLIC mode is supported or not"]
10209 #[must_use]
10210 #[inline(always)]
10211 pub const fn vplic(&self) -> bool {
10212 let val = (self.0 >> 12usize) & 0x01;
10213 val != 0
10214 }
10215 #[doc = "Indicates if vectored PLIC mode is supported or not"]
10216 #[inline(always)]
10217 pub const fn set_vplic(&mut self, val: bool) {
10218 self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
10219 }
10220 #[doc = "Indicates whether Andes V5 performance extension is supported or not"]
10221 #[must_use]
10222 #[inline(always)]
10223 pub const fn ev5pe(&self) -> bool {
10224 let val = (self.0 >> 13usize) & 0x01;
10225 val != 0
10226 }
10227 #[doc = "Indicates whether Andes V5 performance extension is supported or not"]
10228 #[inline(always)]
10229 pub const fn set_ev5pe(&mut self, val: bool) {
10230 self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
10231 }
10232 #[doc = "Indicate if local memory slave port is present or not"]
10233 #[must_use]
10234 #[inline(always)]
10235 pub const fn lmslvp(&self) -> bool {
10236 let val = (self.0 >> 14usize) & 0x01;
10237 val != 0
10238 }
10239 #[doc = "Indicate if local memory slave port is present or not"]
10240 #[inline(always)]
10241 pub const fn set_lmslvp(&mut self, val: bool) {
10242 self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
10243 }
10244 #[doc = "Indicate if Andes-enhanced performance monitoring feature is present or not"]
10245 #[must_use]
10246 #[inline(always)]
10247 pub const fn pmnds(&self) -> bool {
10248 let val = (self.0 >> 15usize) & 0x01;
10249 val != 0
10250 }
10251 #[doc = "Indicate if Andes-enhanced performance monitoring feature is present or not"]
10252 #[inline(always)]
10253 pub const fn set_pmnds(&mut self, val: bool) {
10254 self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
10255 }
10256 #[doc = "Indicate the presence of CSRs for CCTL operations"]
10257 #[must_use]
10258 #[inline(always)]
10259 pub const fn cctlcsr(&self) -> bool {
10260 let val = (self.0 >> 16usize) & 0x01;
10261 val != 0
10262 }
10263 #[doc = "Indicate the presence of CSRs for CCTL operations"]
10264 #[inline(always)]
10265 pub const fn set_cctlcsr(&mut self, val: bool) {
10266 self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
10267 }
10268 #[doc = "Indicate the support of FLHW and FSHW instructions"]
10269 #[must_use]
10270 #[inline(always)]
10271 pub const fn efhw(&self) -> bool {
10272 let val = (self.0 >> 17usize) & 0x01;
10273 val != 0
10274 }
10275 #[doc = "Indicate the support of FLHW and FSHW instructions"]
10276 #[inline(always)]
10277 pub const fn set_efhw(&mut self, val: bool) {
10278 self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
10279 }
10280 #[doc = "Indicates the version number of CCTL command operation scheme supported by an implementation"]
10281 #[must_use]
10282 #[inline(always)]
10283 pub const fn vcctl(&self) -> u8 {
10284 let val = (self.0 >> 18usize) & 0x03;
10285 val as u8
10286 }
10287 #[doc = "Indicates the version number of CCTL command operation scheme supported by an implementation"]
10288 #[inline(always)]
10289 pub const fn set_vcctl(&mut self, val: u8) {
10290 self.0 = (self.0 & !(0x03 << 18usize)) | (((val as u32) & 0x03) << 18usize);
10291 }
10292 #[doc = "Exception additional save levels for recoverable exception/NMI"]
10293 #[must_use]
10294 #[inline(always)]
10295 pub const fn excslvl(&self) -> u8 {
10296 let val = (self.0 >> 20usize) & 0x03;
10297 val as u8
10298 }
10299 #[doc = "Exception additional save levels for recoverable exception/NMI"]
10300 #[inline(always)]
10301 pub const fn set_excslvl(&mut self, val: u8) {
10302 self.0 = (self.0 & !(0x03 << 20usize)) | (((val as u32) & 0x03) << 20usize);
10303 }
10304 #[doc = "Indicates if Performance Monitoring Counters are implemented or not"]
10305 #[must_use]
10306 #[inline(always)]
10307 pub const fn nopmc(&self) -> bool {
10308 let val = (self.0 >> 22usize) & 0x01;
10309 val != 0
10310 }
10311 #[doc = "Indicates if Performance Monitoring Counters are implemented or not"]
10312 #[inline(always)]
10313 pub const fn set_nopmc(&mut self, val: bool) {
10314 self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
10315 }
10316 #[doc = "Indicates if the stack overflow/underflow exception is implemented as a “before” precise exception or an “after” precise exception"]
10317 #[must_use]
10318 #[inline(always)]
10319 pub const fn spe_aft(&self) -> bool {
10320 let val = (self.0 >> 23usize) & 0x01;
10321 val != 0
10322 }
10323 #[doc = "Indicates if the stack overflow/underflow exception is implemented as a “before” precise exception or an “after” precise exception"]
10324 #[inline(always)]
10325 pub const fn set_spe_aft(&mut self, val: bool) {
10326 self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
10327 }
10328 #[doc = "Indicates if wfe, sleepvalue, txevt CSRs are implemented or not"]
10329 #[must_use]
10330 #[inline(always)]
10331 pub const fn esleep(&self) -> bool {
10332 let val = (self.0 >> 24usize) & 0x01;
10333 val != 0
10334 }
10335 #[doc = "Indicates if wfe, sleepvalue, txevt CSRs are implemented or not"]
10336 #[inline(always)]
10337 pub const fn set_esleep(&mut self, val: bool) {
10338 self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
10339 }
10340 #[doc = "Indicates if PPI region is supported or not"]
10341 #[must_use]
10342 #[inline(always)]
10343 pub const fn ppi(&self) -> bool {
10344 let val = (self.0 >> 25usize) & 0x01;
10345 val != 0
10346 }
10347 #[doc = "Indicates if PPI region is supported or not"]
10348 #[inline(always)]
10349 pub const fn set_ppi(&mut self, val: bool) {
10350 self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize);
10351 }
10352 #[doc = "Indicates if FIO region is supported or not"]
10353 #[must_use]
10354 #[inline(always)]
10355 pub const fn fio(&self) -> bool {
10356 let val = (self.0 >> 26usize) & 0x01;
10357 val != 0
10358 }
10359 #[doc = "Indicates if FIO region is supported or not"]
10360 #[inline(always)]
10361 pub const fn set_fio(&mut self, val: bool) {
10362 self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize);
10363 }
10364 #[doc = "Indicates if CLIC (Core Local Interrupt Controller) is supported or not"]
10365 #[must_use]
10366 #[inline(always)]
10367 pub const fn clic(&self) -> bool {
10368 let val = (self.0 >> 27usize) & 0x01;
10369 val != 0
10370 }
10371 #[doc = "Indicates if CLIC (Core Local Interrupt Controller) is supported or not"]
10372 #[inline(always)]
10373 pub const fn set_clic(&mut self, val: bool) {
10374 self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize);
10375 }
10376 #[doc = "Indicates if Enhnaced CLIC (Core Local Interrupt Controller) extension is supported or not"]
10377 #[must_use]
10378 #[inline(always)]
10379 pub const fn eclic(&self) -> bool {
10380 let val = (self.0 >> 28usize) & 0x01;
10381 val != 0
10382 }
10383 #[doc = "Indicates if Enhnaced CLIC (Core Local Interrupt Controller) extension is supported or not"]
10384 #[inline(always)]
10385 pub const fn set_eclic(&mut self, val: bool) {
10386 self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
10387 }
10388 #[doc = "Indicates if DSP extension is supported or not"]
10389 #[must_use]
10390 #[inline(always)]
10391 pub const fn edsp(&self) -> bool {
10392 let val = (self.0 >> 29usize) & 0x01;
10393 val != 0
10394 }
10395 #[doc = "Indicates if DSP extension is supported or not"]
10396 #[inline(always)]
10397 pub const fn set_edsp(&mut self, val: bool) {
10398 self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize);
10399 }
10400 #[doc = "Indicates if programmable PMA mechanism with PMA region CSRs is supported or not"]
10401 #[must_use]
10402 #[inline(always)]
10403 pub const fn ppma(&self) -> bool {
10404 let val = (self.0 >> 30usize) & 0x01;
10405 val != 0
10406 }
10407 #[doc = "Indicates if programmable PMA mechanism with PMA region CSRs is supported or not"]
10408 #[inline(always)]
10409 pub const fn set_ppma(&mut self, val: bool) {
10410 self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize);
10411 }
10412 #[doc = "Indicates if mmsc_cfg2 CSR is present or not"]
10413 #[must_use]
10414 #[inline(always)]
10415 pub const fn msc_ext(&self) -> bool {
10416 let val = (self.0 >> 31usize) & 0x01;
10417 val != 0
10418 }
10419 #[doc = "Indicates if mmsc_cfg2 CSR is present or not"]
10420 #[inline(always)]
10421 pub const fn set_msc_ext(&mut self, val: bool) {
10422 self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
10423 }
10424 }
10425 impl Default for MmscCfg {
10426 #[inline(always)]
10427 fn default() -> MmscCfg {
10428 MmscCfg(0)
10429 }
10430 }
10431 impl core::fmt::Debug for MmscCfg {
10432 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
10433 f.debug_struct("MmscCfg")
10434 .field("ecc", &self.ecc())
10435 .field("tlb_ecc", &self.tlb_ecc())
10436 .field("ecd", &self.ecd())
10437 .field("pft", &self.pft())
10438 .field("hsp", &self.hsp())
10439 .field("ace", &self.ace())
10440 .field("addpmc", &self.addpmc())
10441 .field("vplic", &self.vplic())
10442 .field("ev5pe", &self.ev5pe())
10443 .field("lmslvp", &self.lmslvp())
10444 .field("pmnds", &self.pmnds())
10445 .field("cctlcsr", &self.cctlcsr())
10446 .field("efhw", &self.efhw())
10447 .field("vcctl", &self.vcctl())
10448 .field("excslvl", &self.excslvl())
10449 .field("nopmc", &self.nopmc())
10450 .field("spe_aft", &self.spe_aft())
10451 .field("esleep", &self.esleep())
10452 .field("ppi", &self.ppi())
10453 .field("fio", &self.fio())
10454 .field("clic", &self.clic())
10455 .field("eclic", &self.eclic())
10456 .field("edsp", &self.edsp())
10457 .field("ppma", &self.ppma())
10458 .field("msc_ext", &self.msc_ext())
10459 .finish()
10460 }
10461 }
10462 #[cfg(feature = "defmt")]
10463 impl defmt::Format for MmscCfg {
10464 fn format(&self, f: defmt::Formatter) {
10465 defmt::write!(
10466 f,
10467 "MmscCfg {{ ecc: {=bool:?}, tlb_ecc: {=u8:?}, ecd: {=bool:?}, pft: {=bool:?}, hsp: {=bool:?}, ace: {=bool:?}, addpmc: {=u8:?}, vplic: {=bool:?}, ev5pe: {=bool:?}, lmslvp: {=bool:?}, pmnds: {=bool:?}, cctlcsr: {=bool:?}, efhw: {=bool:?}, vcctl: {=u8:?}, excslvl: {=u8:?}, nopmc: {=bool:?}, spe_aft: {=bool:?}, esleep: {=bool:?}, ppi: {=bool:?}, fio: {=bool:?}, clic: {=bool:?}, eclic: {=bool:?}, edsp: {=bool:?}, ppma: {=bool:?}, msc_ext: {=bool:?} }}",
10468 self.ecc(),
10469 self.tlb_ecc(),
10470 self.ecd(),
10471 self.pft(),
10472 self.hsp(),
10473 self.ace(),
10474 self.addpmc(),
10475 self.vplic(),
10476 self.ev5pe(),
10477 self.lmslvp(),
10478 self.pmnds(),
10479 self.cctlcsr(),
10480 self.efhw(),
10481 self.vcctl(),
10482 self.excslvl(),
10483 self.nopmc(),
10484 self.spe_aft(),
10485 self.esleep(),
10486 self.ppi(),
10487 self.fio(),
10488 self.clic(),
10489 self.eclic(),
10490 self.edsp(),
10491 self.ppma(),
10492 self.msc_ext()
10493 )
10494 }
10495 }
10496 #[inline(always)]
10497 unsafe fn _read() -> usize {
10498 let r: usize;
10499 unsafe {
10500 core :: arch :: asm ! ("csrrs {0}, 0xfc2, x0" , out (reg) r);
10501 }
10502 r
10503 }
10504 #[doc = r" Read the CSR value."]
10505 #[inline]
10506 pub fn read() -> MmscCfg {
10507 unsafe { MmscCfg(_read() as u32) }
10508 }
10509}
10510#[doc = "Miscellaneous configuration (RV32)"]
10511pub mod mmsc_cfg2 {
10512 #[doc = "Misc. Configuration 2 Register"]
10513 #[repr(transparent)]
10514 #[derive(Copy, Clone, Eq, PartialEq)]
10515 pub struct MmscCfg2(pub u32);
10516 impl MmscCfg2 {
10517 #[doc = "Indicates if BFLOAT16 conversion extension is supported or not"]
10518 #[must_use]
10519 #[inline(always)]
10520 pub const fn bf16cvt(&self) -> bool {
10521 let val = (self.0 >> 0usize) & 0x01;
10522 val != 0
10523 }
10524 #[doc = "Indicates if BFLOAT16 conversion extension is supported or not"]
10525 #[inline(always)]
10526 pub const fn set_bf16cvt(&mut self, val: bool) {
10527 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
10528 }
10529 #[doc = "Indicates if FP16 half-precision floating-point extension (Zfh) is supported or not"]
10530 #[must_use]
10531 #[inline(always)]
10532 pub const fn zfh(&self) -> bool {
10533 let val = (self.0 >> 1usize) & 0x01;
10534 val != 0
10535 }
10536 #[doc = "Indicates if FP16 half-precision floating-point extension (Zfh) is supported or not"]
10537 #[inline(always)]
10538 pub const fn set_zfh(&mut self, val: bool) {
10539 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
10540 }
10541 #[doc = "Indicates if vector INT4 load extension is supported or not"]
10542 #[must_use]
10543 #[inline(always)]
10544 pub const fn vl4(&self) -> bool {
10545 let val = (self.0 >> 2usize) & 0x01;
10546 val != 0
10547 }
10548 #[doc = "Indicates if vector INT4 load extension is supported or not"]
10549 #[inline(always)]
10550 pub const fn set_vl4(&mut self, val: bool) {
10551 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
10552 }
10553 #[doc = "Indicates if crash debugging state save feature is supported or not"]
10554 #[must_use]
10555 #[inline(always)]
10556 pub const fn crashsave(&self) -> bool {
10557 let val = (self.0 >> 3usize) & 0x01;
10558 val != 0
10559 }
10560 #[doc = "Indicates if crash debugging state save feature is supported or not"]
10561 #[inline(always)]
10562 pub const fn set_crashsave(&mut self, val: bool) {
10563 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
10564 }
10565 #[doc = "Indicates if mvec_cfg CSR is present or not"]
10566 #[must_use]
10567 #[inline(always)]
10568 pub const fn veccfg(&self) -> bool {
10569 let val = (self.0 >> 4usize) & 0x01;
10570 val != 0
10571 }
10572 #[doc = "Indicates if mvec_cfg CSR is present or not"]
10573 #[inline(always)]
10574 pub const fn set_veccfg(&mut self, val: bool) {
10575 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
10576 }
10577 #[doc = "Indicates if scalar FPU is implemented using VPU-like pipeline"]
10578 #[must_use]
10579 #[inline(always)]
10580 pub const fn finv(&self) -> bool {
10581 let val = (self.0 >> 5usize) & 0x01;
10582 val != 0
10583 }
10584 #[doc = "Indicates if scalar FPU is implemented using VPU-like pipeline"]
10585 #[inline(always)]
10586 pub const fn set_finv(&mut self, val: bool) {
10587 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
10588 }
10589 #[doc = "Indicates if 16-bit push/pop/popret instructions are supported or not"]
10590 #[must_use]
10591 #[inline(always)]
10592 pub const fn pp16(&self) -> bool {
10593 let val = (self.0 >> 6usize) & 0x01;
10594 val != 0
10595 }
10596 #[doc = "Indicates if 16-bit push/pop/popret instructions are supported or not"]
10597 #[inline(always)]
10598 pub const fn set_pp16(&mut self, val: bool) {
10599 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
10600 }
10601 #[doc = "Indicates if vector small INT handling extension is supported or not"]
10602 #[must_use]
10603 #[inline(always)]
10604 pub const fn vsih(&self) -> bool {
10605 let val = (self.0 >> 8usize) & 0x01;
10606 val != 0
10607 }
10608 #[doc = "Indicates if vector small INT handling extension is supported or not"]
10609 #[inline(always)]
10610 pub const fn set_vsih(&mut self, val: bool) {
10611 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
10612 }
10613 #[doc = "Version of Code Dense Extension"]
10614 #[must_use]
10615 #[inline(always)]
10616 pub const fn ecdv(&self) -> u8 {
10617 let val = (self.0 >> 9usize) & 0x03;
10618 val as u8
10619 }
10620 #[doc = "Version of Code Dense Extension"]
10621 #[inline(always)]
10622 pub const fn set_ecdv(&mut self, val: u8) {
10623 self.0 = (self.0 & !(0x03 << 9usize)) | (((val as u32) & 0x03) << 9usize);
10624 }
10625 #[doc = "Indicates if vector dot product extension is supported or not"]
10626 #[must_use]
10627 #[inline(always)]
10628 pub const fn vdot(&self) -> bool {
10629 let val = (self.0 >> 11usize) & 0x01;
10630 val != 0
10631 }
10632 #[doc = "Indicates if vector dot product extension is supported or not"]
10633 #[inline(always)]
10634 pub const fn set_vdot(&mut self, val: bool) {
10635 self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
10636 }
10637 #[doc = "Indicates if vector packed FP16 extension is supported or not. VFPMADT.VF and VFPMADB.VF"]
10638 #[must_use]
10639 #[inline(always)]
10640 pub const fn vpfh(&self) -> bool {
10641 let val = (self.0 >> 12usize) & 0x01;
10642 val != 0
10643 }
10644 #[doc = "Indicates if vector packed FP16 extension is supported or not. VFPMADT.VF and VFPMADB.VF"]
10645 #[inline(always)]
10646 pub const fn set_vpfh(&mut self, val: bool) {
10647 self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
10648 }
10649 #[doc = "Indicates if CCACHE/MP configuration info is implemented or not. It includes the fields of CCACHE, IO_COHP, CORE_PCLUS, and mccache_ctl_base CSR"]
10650 #[must_use]
10651 #[inline(always)]
10652 pub const fn ccachemp_cfg(&self) -> bool {
10653 let val = (self.0 >> 13usize) & 0x01;
10654 val != 0
10655 }
10656 #[doc = "Indicates if CCACHE/MP configuration info is implemented or not. It includes the fields of CCACHE, IO_COHP, CORE_PCLUS, and mccache_ctl_base CSR"]
10657 #[inline(always)]
10658 pub const fn set_ccachemp_cfg(&mut self, val: bool) {
10659 self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
10660 }
10661 #[doc = "Indicates if cluster cache is present or not"]
10662 #[must_use]
10663 #[inline(always)]
10664 pub const fn ccache(&self) -> bool {
10665 let val = (self.0 >> 14usize) & 0x01;
10666 val != 0
10667 }
10668 #[doc = "Indicates if cluster cache is present or not"]
10669 #[inline(always)]
10670 pub const fn set_ccache(&mut self, val: bool) {
10671 self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
10672 }
10673 #[doc = "Indicates if IO coherence port is present or not"]
10674 #[must_use]
10675 #[inline(always)]
10676 pub const fn io_cohp(&self) -> bool {
10677 let val = (self.0 >> 15usize) & 0x01;
10678 val != 0
10679 }
10680 #[doc = "Indicates if IO coherence port is present or not"]
10681 #[inline(always)]
10682 pub const fn set_io_cohp(&mut self, val: bool) {
10683 self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
10684 }
10685 #[doc = "Indicates the number of cores in a MP cluster. The number of cores is equal to “CORE_PCLUS+1”"]
10686 #[must_use]
10687 #[inline(always)]
10688 pub const fn core_pclus(&self) -> u8 {
10689 let val = (self.0 >> 16usize) & 0x0f;
10690 val as u8
10691 }
10692 #[doc = "Indicates the number of cores in a MP cluster. The number of cores is equal to “CORE_PCLUS+1”"]
10693 #[inline(always)]
10694 pub const fn set_core_pclus(&mut self, val: u8) {
10695 self.0 = (self.0 & !(0x0f << 16usize)) | (((val as u32) & 0x0f) << 16usize);
10696 }
10697 #[doc = "Indicates if mrvarch_cfg CSR is present or not"]
10698 #[must_use]
10699 #[inline(always)]
10700 pub const fn rvarch(&self) -> bool {
10701 let val = (self.0 >> 20usize) & 0x01;
10702 val != 0
10703 }
10704 #[doc = "Indicates if mrvarch_cfg CSR is present or not"]
10705 #[inline(always)]
10706 pub const fn set_rvarch(&mut self, val: bool) {
10707 self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
10708 }
10709 }
10710 impl Default for MmscCfg2 {
10711 #[inline(always)]
10712 fn default() -> MmscCfg2 {
10713 MmscCfg2(0)
10714 }
10715 }
10716 impl core::fmt::Debug for MmscCfg2 {
10717 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
10718 f.debug_struct("MmscCfg2")
10719 .field("bf16cvt", &self.bf16cvt())
10720 .field("zfh", &self.zfh())
10721 .field("vl4", &self.vl4())
10722 .field("crashsave", &self.crashsave())
10723 .field("veccfg", &self.veccfg())
10724 .field("finv", &self.finv())
10725 .field("pp16", &self.pp16())
10726 .field("vsih", &self.vsih())
10727 .field("ecdv", &self.ecdv())
10728 .field("vdot", &self.vdot())
10729 .field("vpfh", &self.vpfh())
10730 .field("ccachemp_cfg", &self.ccachemp_cfg())
10731 .field("ccache", &self.ccache())
10732 .field("io_cohp", &self.io_cohp())
10733 .field("core_pclus", &self.core_pclus())
10734 .field("rvarch", &self.rvarch())
10735 .finish()
10736 }
10737 }
10738 #[cfg(feature = "defmt")]
10739 impl defmt::Format for MmscCfg2 {
10740 fn format(&self, f: defmt::Formatter) {
10741 defmt::write!(
10742 f,
10743 "MmscCfg2 {{ bf16cvt: {=bool:?}, zfh: {=bool:?}, vl4: {=bool:?}, crashsave: {=bool:?}, veccfg: {=bool:?}, finv: {=bool:?}, pp16: {=bool:?}, vsih: {=bool:?}, ecdv: {=u8:?}, vdot: {=bool:?}, vpfh: {=bool:?}, ccachemp_cfg: {=bool:?}, ccache: {=bool:?}, io_cohp: {=bool:?}, core_pclus: {=u8:?}, rvarch: {=bool:?} }}",
10744 self.bf16cvt(),
10745 self.zfh(),
10746 self.vl4(),
10747 self.crashsave(),
10748 self.veccfg(),
10749 self.finv(),
10750 self.pp16(),
10751 self.vsih(),
10752 self.ecdv(),
10753 self.vdot(),
10754 self.vpfh(),
10755 self.ccachemp_cfg(),
10756 self.ccache(),
10757 self.io_cohp(),
10758 self.core_pclus(),
10759 self.rvarch()
10760 )
10761 }
10762 }
10763 #[inline(always)]
10764 unsafe fn _read() -> usize {
10765 let r: usize;
10766 unsafe {
10767 core :: arch :: asm ! ("csrrs {0}, 0xfc3, x0" , out (reg) r);
10768 }
10769 r
10770 }
10771 #[doc = r" Read the CSR value."]
10772 #[inline]
10773 pub fn read() -> MmscCfg2 {
10774 unsafe { MmscCfg2(_read() as u32) }
10775 }
10776}
10777#[doc = "Vector processor configuration"]
10778pub mod mvec_cfg {
10779 #[doc = "Vector Configuration Register"]
10780 #[repr(transparent)]
10781 #[derive(Copy, Clone, Eq, PartialEq)]
10782 pub struct MvecCfg(pub u32);
10783 impl MvecCfg {
10784 #[must_use]
10785 #[inline(always)]
10786 pub const fn minor(&self) -> u8 {
10787 let val = (self.0 >> 0usize) & 0x0f;
10788 val as u8
10789 }
10790 #[inline(always)]
10791 pub const fn set_minor(&mut self, val: u8) {
10792 self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize);
10793 }
10794 #[must_use]
10795 #[inline(always)]
10796 pub const fn major(&self) -> u8 {
10797 let val = (self.0 >> 4usize) & 0x0f;
10798 val as u8
10799 }
10800 #[inline(always)]
10801 pub const fn set_major(&mut self, val: u8) {
10802 self.0 = (self.0 & !(0x0f << 4usize)) | (((val as u32) & 0x0f) << 4usize);
10803 }
10804 #[must_use]
10805 #[inline(always)]
10806 pub const fn dw(&self) -> u8 {
10807 let val = (self.0 >> 8usize) & 0x07;
10808 val as u8
10809 }
10810 #[inline(always)]
10811 pub const fn set_dw(&mut self, val: u8) {
10812 self.0 = (self.0 & !(0x07 << 8usize)) | (((val as u32) & 0x07) << 8usize);
10813 }
10814 #[must_use]
10815 #[inline(always)]
10816 pub const fn mw(&self) -> u8 {
10817 let val = (self.0 >> 11usize) & 0x07;
10818 val as u8
10819 }
10820 #[inline(always)]
10821 pub const fn set_mw(&mut self, val: u8) {
10822 self.0 = (self.0 & !(0x07 << 11usize)) | (((val as u32) & 0x07) << 11usize);
10823 }
10824 #[must_use]
10825 #[inline(always)]
10826 pub const fn misew(&self) -> u8 {
10827 let val = (self.0 >> 14usize) & 0x03;
10828 val as u8
10829 }
10830 #[inline(always)]
10831 pub const fn set_misew(&mut self, val: u8) {
10832 self.0 = (self.0 & !(0x03 << 14usize)) | (((val as u32) & 0x03) << 14usize);
10833 }
10834 #[must_use]
10835 #[inline(always)]
10836 pub const fn mfsew(&self) -> u8 {
10837 let val = (self.0 >> 16usize) & 0x03;
10838 val as u8
10839 }
10840 #[inline(always)]
10841 pub const fn set_mfsew(&mut self, val: u8) {
10842 self.0 = (self.0 & !(0x03 << 16usize)) | (((val as u32) & 0x03) << 16usize);
10843 }
10844 }
10845 impl Default for MvecCfg {
10846 #[inline(always)]
10847 fn default() -> MvecCfg {
10848 MvecCfg(0)
10849 }
10850 }
10851 impl core::fmt::Debug for MvecCfg {
10852 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
10853 f.debug_struct("MvecCfg")
10854 .field("minor", &self.minor())
10855 .field("major", &self.major())
10856 .field("dw", &self.dw())
10857 .field("mw", &self.mw())
10858 .field("misew", &self.misew())
10859 .field("mfsew", &self.mfsew())
10860 .finish()
10861 }
10862 }
10863 #[cfg(feature = "defmt")]
10864 impl defmt::Format for MvecCfg {
10865 fn format(&self, f: defmt::Formatter) {
10866 defmt::write!(
10867 f,
10868 "MvecCfg {{ minor: {=u8:?}, major: {=u8:?}, dw: {=u8:?}, mw: {=u8:?}, misew: {=u8:?}, mfsew: {=u8:?} }}",
10869 self.minor(),
10870 self.major(),
10871 self.dw(),
10872 self.mw(),
10873 self.misew(),
10874 self.mfsew()
10875 )
10876 }
10877 }
10878 #[inline(always)]
10879 unsafe fn _read() -> usize {
10880 let r: usize;
10881 unsafe {
10882 core :: arch :: asm ! ("csrrs {0}, 0xfc7, x0" , out (reg) r);
10883 }
10884 r
10885 }
10886 #[doc = r" Read the CSR value."]
10887 #[inline]
10888 pub fn read() -> MvecCfg {
10889 unsafe { MvecCfg(_read() as u32) }
10890 }
10891}
10892#[doc = "Current state save for crash debugging"]
10893pub mod mcrash_statesave {
10894 #[doc = "Machine Crash State Save"]
10895 #[repr(transparent)]
10896 #[derive(Copy, Clone, Eq, PartialEq)]
10897 pub struct McrashStatesave(pub u32);
10898 impl McrashStatesave {
10899 #[must_use]
10900 #[inline(always)]
10901 pub const fn mie(&self) -> bool {
10902 let val = (self.0 >> 0usize) & 0x01;
10903 val != 0
10904 }
10905 #[inline(always)]
10906 pub const fn set_mie(&mut self, val: bool) {
10907 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
10908 }
10909 #[must_use]
10910 #[inline(always)]
10911 pub const fn cp(&self) -> u8 {
10912 let val = (self.0 >> 1usize) & 0x03;
10913 val as u8
10914 }
10915 #[inline(always)]
10916 pub const fn set_cp(&mut self, val: u8) {
10917 self.0 = (self.0 & !(0x03 << 1usize)) | (((val as u32) & 0x03) << 1usize);
10918 }
10919 #[must_use]
10920 #[inline(always)]
10921 pub const fn ppft_en(&self) -> bool {
10922 let val = (self.0 >> 3usize) & 0x01;
10923 val != 0
10924 }
10925 #[inline(always)]
10926 pub const fn set_ppft_en(&mut self, val: bool) {
10927 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
10928 }
10929 #[must_use]
10930 #[inline(always)]
10931 pub const fn pime(&self) -> bool {
10932 let val = (self.0 >> 4usize) & 0x01;
10933 val != 0
10934 }
10935 #[inline(always)]
10936 pub const fn set_pime(&mut self, val: bool) {
10937 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
10938 }
10939 #[must_use]
10940 #[inline(always)]
10941 pub const fn pdme(&self) -> bool {
10942 let val = (self.0 >> 5usize) & 0x01;
10943 val != 0
10944 }
10945 #[inline(always)]
10946 pub const fn set_pdme(&mut self, val: bool) {
10947 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
10948 }
10949 #[must_use]
10950 #[inline(always)]
10951 pub const fn ptyp(&self) -> u8 {
10952 let val = (self.0 >> 6usize) & 0x03;
10953 val as u8
10954 }
10955 #[inline(always)]
10956 pub const fn set_ptyp(&mut self, val: u8) {
10957 self.0 = (self.0 & !(0x03 << 6usize)) | (((val as u32) & 0x03) << 6usize);
10958 }
10959 }
10960 impl Default for McrashStatesave {
10961 #[inline(always)]
10962 fn default() -> McrashStatesave {
10963 McrashStatesave(0)
10964 }
10965 }
10966 impl core::fmt::Debug for McrashStatesave {
10967 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
10968 f.debug_struct("McrashStatesave")
10969 .field("mie", &self.mie())
10970 .field("cp", &self.cp())
10971 .field("ppft_en", &self.ppft_en())
10972 .field("pime", &self.pime())
10973 .field("pdme", &self.pdme())
10974 .field("ptyp", &self.ptyp())
10975 .finish()
10976 }
10977 }
10978 #[cfg(feature = "defmt")]
10979 impl defmt::Format for McrashStatesave {
10980 fn format(&self, f: defmt::Formatter) {
10981 defmt::write!(
10982 f,
10983 "McrashStatesave {{ mie: {=bool:?}, cp: {=u8:?}, ppft_en: {=bool:?}, pime: {=bool:?}, pdme: {=bool:?}, ptyp: {=u8:?} }}",
10984 self.mie(),
10985 self.cp(),
10986 self.ppft_en(),
10987 self.pime(),
10988 self.pdme(),
10989 self.ptyp()
10990 )
10991 }
10992 }
10993 #[inline(always)]
10994 unsafe fn _read() -> usize {
10995 let r: usize;
10996 unsafe {
10997 core :: arch :: asm ! ("csrrs {0}, 0xfc8, x0" , out (reg) r);
10998 }
10999 r
11000 }
11001 #[doc = r" Read the CSR value."]
11002 #[inline]
11003 pub fn read() -> McrashStatesave {
11004 unsafe { McrashStatesave(_read() as u32) }
11005 }
11006}
11007#[doc = "mstatus state save for crash debugging"]
11008pub mod mstatus_crashsave {
11009 #[inline(always)]
11010 unsafe fn _read() -> usize {
11011 let r: usize;
11012 unsafe {
11013 core :: arch :: asm ! ("csrrs {0}, 0xfc9, x0" , out (reg) r);
11014 }
11015 r
11016 }
11017 #[doc = r" Read the CSR value as raw usize."]
11018 #[inline]
11019 pub fn read() -> usize {
11020 unsafe { _read() }
11021 }
11022}
11023#[doc = "RISC-V Architecture"]
11024pub mod mrvarch_cfg {
11025 #[doc = "RISC-V Architecture Configuration Register"]
11026 #[repr(transparent)]
11027 #[derive(Copy, Clone, Eq, PartialEq)]
11028 pub struct MrvarchCfg(pub u32);
11029 impl MrvarchCfg {
11030 #[must_use]
11031 #[inline(always)]
11032 pub const fn zba(&self) -> bool {
11033 let val = (self.0 >> 0usize) & 0x01;
11034 val != 0
11035 }
11036 #[inline(always)]
11037 pub const fn set_zba(&mut self, val: bool) {
11038 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
11039 }
11040 #[must_use]
11041 #[inline(always)]
11042 pub const fn zbb(&self) -> bool {
11043 let val = (self.0 >> 1usize) & 0x01;
11044 val != 0
11045 }
11046 #[inline(always)]
11047 pub const fn set_zbb(&mut self, val: bool) {
11048 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
11049 }
11050 #[must_use]
11051 #[inline(always)]
11052 pub const fn zbc(&self) -> bool {
11053 let val = (self.0 >> 2usize) & 0x01;
11054 val != 0
11055 }
11056 #[inline(always)]
11057 pub const fn set_zbc(&mut self, val: bool) {
11058 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
11059 }
11060 #[must_use]
11061 #[inline(always)]
11062 pub const fn zbs(&self) -> bool {
11063 let val = (self.0 >> 3usize) & 0x01;
11064 val != 0
11065 }
11066 #[inline(always)]
11067 pub const fn set_zbs(&mut self, val: bool) {
11068 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
11069 }
11070 #[must_use]
11071 #[inline(always)]
11072 pub const fn smepmp(&self) -> bool {
11073 let val = (self.0 >> 4usize) & 0x01;
11074 val != 0
11075 }
11076 #[inline(always)]
11077 pub const fn set_smepmp(&mut self, val: bool) {
11078 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
11079 }
11080 #[must_use]
11081 #[inline(always)]
11082 pub const fn svinval(&self) -> bool {
11083 let val = (self.0 >> 5usize) & 0x01;
11084 val != 0
11085 }
11086 #[inline(always)]
11087 pub const fn set_svinval(&mut self, val: bool) {
11088 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
11089 }
11090 #[must_use]
11091 #[inline(always)]
11092 pub const fn smstateen(&self) -> bool {
11093 let val = (self.0 >> 6usize) & 0x01;
11094 val != 0
11095 }
11096 #[inline(always)]
11097 pub const fn set_smstateen(&mut self, val: bool) {
11098 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
11099 }
11100 #[must_use]
11101 #[inline(always)]
11102 pub const fn sscofmpf(&self) -> bool {
11103 let val = (self.0 >> 7usize) & 0x01;
11104 val != 0
11105 }
11106 #[inline(always)]
11107 pub const fn set_sscofmpf(&mut self, val: bool) {
11108 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
11109 }
11110 #[must_use]
11111 #[inline(always)]
11112 pub const fn sstc(&self) -> bool {
11113 let val = (self.0 >> 8usize) & 0x01;
11114 val != 0
11115 }
11116 #[inline(always)]
11117 pub const fn set_sstc(&mut self, val: bool) {
11118 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
11119 }
11120 #[must_use]
11121 #[inline(always)]
11122 pub const fn zicbom(&self) -> bool {
11123 let val = (self.0 >> 9usize) & 0x01;
11124 val != 0
11125 }
11126 #[inline(always)]
11127 pub const fn set_zicbom(&mut self, val: bool) {
11128 self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
11129 }
11130 #[must_use]
11131 #[inline(always)]
11132 pub const fn zicbop(&self) -> bool {
11133 let val = (self.0 >> 10usize) & 0x01;
11134 val != 0
11135 }
11136 #[inline(always)]
11137 pub const fn set_zicbop(&mut self, val: bool) {
11138 self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
11139 }
11140 #[must_use]
11141 #[inline(always)]
11142 pub const fn zicboz(&self) -> bool {
11143 let val = (self.0 >> 11usize) & 0x01;
11144 val != 0
11145 }
11146 #[inline(always)]
11147 pub const fn set_zicboz(&mut self, val: bool) {
11148 self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
11149 }
11150 #[must_use]
11151 #[inline(always)]
11152 pub const fn zbk(&self) -> bool {
11153 let val = (self.0 >> 12usize) & 0x01;
11154 val != 0
11155 }
11156 #[inline(always)]
11157 pub const fn set_zbk(&mut self, val: bool) {
11158 self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
11159 }
11160 #[must_use]
11161 #[inline(always)]
11162 pub const fn zkn(&self) -> bool {
11163 let val = (self.0 >> 13usize) & 0x01;
11164 val != 0
11165 }
11166 #[inline(always)]
11167 pub const fn set_zkn(&mut self, val: bool) {
11168 self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
11169 }
11170 #[must_use]
11171 #[inline(always)]
11172 pub const fn zks(&self) -> bool {
11173 let val = (self.0 >> 14usize) & 0x01;
11174 val != 0
11175 }
11176 #[inline(always)]
11177 pub const fn set_zks(&mut self, val: bool) {
11178 self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
11179 }
11180 #[must_use]
11181 #[inline(always)]
11182 pub const fn zkt(&self) -> bool {
11183 let val = (self.0 >> 15usize) & 0x01;
11184 val != 0
11185 }
11186 #[inline(always)]
11187 pub const fn set_zkt(&mut self, val: bool) {
11188 self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
11189 }
11190 #[must_use]
11191 #[inline(always)]
11192 pub const fn zkr(&self) -> bool {
11193 let val = (self.0 >> 16usize) & 0x01;
11194 val != 0
11195 }
11196 #[inline(always)]
11197 pub const fn set_zkr(&mut self, val: bool) {
11198 self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
11199 }
11200 #[must_use]
11201 #[inline(always)]
11202 pub const fn sm_verion(&self) -> u8 {
11203 let val = (self.0 >> 17usize) & 0x07;
11204 val as u8
11205 }
11206 #[inline(always)]
11207 pub const fn set_sm_verion(&mut self, val: u8) {
11208 self.0 = (self.0 & !(0x07 << 17usize)) | (((val as u32) & 0x07) << 17usize);
11209 }
11210 #[must_use]
11211 #[inline(always)]
11212 pub const fn ss_version(&self) -> u8 {
11213 let val = (self.0 >> 20usize) & 0x07;
11214 val as u8
11215 }
11216 #[inline(always)]
11217 pub const fn set_ss_version(&mut self, val: u8) {
11218 self.0 = (self.0 & !(0x07 << 20usize)) | (((val as u32) & 0x07) << 20usize);
11219 }
11220 #[must_use]
11221 #[inline(always)]
11222 pub const fn svpbmt(&self) -> bool {
11223 let val = (self.0 >> 23usize) & 0x01;
11224 val != 0
11225 }
11226 #[inline(always)]
11227 pub const fn set_svpbmt(&mut self, val: bool) {
11228 self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
11229 }
11230 #[must_use]
11231 #[inline(always)]
11232 pub const fn svnapot(&self) -> bool {
11233 let val = (self.0 >> 24usize) & 0x01;
11234 val != 0
11235 }
11236 #[inline(always)]
11237 pub const fn set_svnapot(&mut self, val: bool) {
11238 self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
11239 }
11240 #[must_use]
11241 #[inline(always)]
11242 pub const fn zihintpause(&self) -> bool {
11243 let val = (self.0 >> 25usize) & 0x01;
11244 val != 0
11245 }
11246 #[inline(always)]
11247 pub const fn set_zihintpause(&mut self, val: bool) {
11248 self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize);
11249 }
11250 }
11251 impl Default for MrvarchCfg {
11252 #[inline(always)]
11253 fn default() -> MrvarchCfg {
11254 MrvarchCfg(0)
11255 }
11256 }
11257 impl core::fmt::Debug for MrvarchCfg {
11258 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
11259 f.debug_struct("MrvarchCfg")
11260 .field("zba", &self.zba())
11261 .field("zbb", &self.zbb())
11262 .field("zbc", &self.zbc())
11263 .field("zbs", &self.zbs())
11264 .field("smepmp", &self.smepmp())
11265 .field("svinval", &self.svinval())
11266 .field("smstateen", &self.smstateen())
11267 .field("sscofmpf", &self.sscofmpf())
11268 .field("sstc", &self.sstc())
11269 .field("zicbom", &self.zicbom())
11270 .field("zicbop", &self.zicbop())
11271 .field("zicboz", &self.zicboz())
11272 .field("zbk", &self.zbk())
11273 .field("zkn", &self.zkn())
11274 .field("zks", &self.zks())
11275 .field("zkt", &self.zkt())
11276 .field("zkr", &self.zkr())
11277 .field("sm_verion", &self.sm_verion())
11278 .field("ss_version", &self.ss_version())
11279 .field("svpbmt", &self.svpbmt())
11280 .field("svnapot", &self.svnapot())
11281 .field("zihintpause", &self.zihintpause())
11282 .finish()
11283 }
11284 }
11285 #[cfg(feature = "defmt")]
11286 impl defmt::Format for MrvarchCfg {
11287 fn format(&self, f: defmt::Formatter) {
11288 defmt::write!(
11289 f,
11290 "MrvarchCfg {{ zba: {=bool:?}, zbb: {=bool:?}, zbc: {=bool:?}, zbs: {=bool:?}, smepmp: {=bool:?}, svinval: {=bool:?}, smstateen: {=bool:?}, sscofmpf: {=bool:?}, sstc: {=bool:?}, zicbom: {=bool:?}, zicbop: {=bool:?}, zicboz: {=bool:?}, zbk: {=bool:?}, zkn: {=bool:?}, zks: {=bool:?}, zkt: {=bool:?}, zkr: {=bool:?}, sm_verion: {=u8:?}, ss_version: {=u8:?}, svpbmt: {=bool:?}, svnapot: {=bool:?}, zihintpause: {=bool:?} }}",
11291 self.zba(),
11292 self.zbb(),
11293 self.zbc(),
11294 self.zbs(),
11295 self.smepmp(),
11296 self.svinval(),
11297 self.smstateen(),
11298 self.sscofmpf(),
11299 self.sstc(),
11300 self.zicbom(),
11301 self.zicbop(),
11302 self.zicboz(),
11303 self.zbk(),
11304 self.zkn(),
11305 self.zks(),
11306 self.zkt(),
11307 self.zkr(),
11308 self.sm_verion(),
11309 self.ss_version(),
11310 self.svpbmt(),
11311 self.svnapot(),
11312 self.zihintpause()
11313 )
11314 }
11315 }
11316 #[inline(always)]
11317 unsafe fn _read() -> usize {
11318 let r: usize;
11319 unsafe {
11320 core :: arch :: asm ! ("csrrs {0}, 0xfca, x0" , out (reg) r);
11321 }
11322 r
11323 }
11324 #[doc = r" Read the CSR value."]
11325 #[inline]
11326 pub fn read() -> MrvarchCfg {
11327 unsafe { MrvarchCfg(_read() as u32) }
11328 }
11329}
11330#[doc = "Cluster cache control base address"]
11331pub mod mccache_ctl_base {
11332 #[inline(always)]
11333 unsafe fn _read() -> usize {
11334 let r: usize;
11335 unsafe {
11336 core :: arch :: asm ! ("csrrs {0}, 0xfcf, x0" , out (reg) r);
11337 }
11338 r
11339 }
11340 #[doc = r" Read the CSR value as raw usize."]
11341 #[inline]
11342 pub fn read() -> usize {
11343 unsafe { _read() }
11344 }
11345}
11346pub mod vals {
11347 #[repr(u8)]
11348 #[allow(non_camel_case_types)]
11349 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
11350 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
11351 pub enum Aces {
11352 Off = 0x0,
11353 Initial = 0x01,
11354 Clean = 0x02,
11355 Dirty = 0x03,
11356 }
11357 impl Aces {
11358 #[inline(always)]
11359 pub const fn from_bits(val: u8) -> Aces {
11360 unsafe { core::mem::transmute(val & 0x03) }
11361 }
11362 #[inline(always)]
11363 pub const fn to_bits(self) -> u8 {
11364 unsafe { core::mem::transmute(self) }
11365 }
11366 }
11367 impl From<u8> for Aces {
11368 #[inline(always)]
11369 fn from(val: u8) -> Aces {
11370 Aces::from_bits(val)
11371 }
11372 }
11373 impl From<Aces> for u8 {
11374 #[inline(always)]
11375 fn from(val: Aces) -> u8 {
11376 Aces::to_bits(val)
11377 }
11378 }
11379 #[repr(u8)]
11380 #[allow(non_camel_case_types)]
11381 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
11382 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
11383 pub enum EntryType {
11384 #[doc = "This PMA entry is disabled"]
11385 Off = 0x0,
11386 _RESERVED_1 = 0x01,
11387 _RESERVED_2 = 0x02,
11388 #[doc = "Naturally aligned power-of-2 region. The granularity is 4K bytes."]
11389 Napot = 0x03,
11390 }
11391 impl EntryType {
11392 #[inline(always)]
11393 pub const fn from_bits(val: u8) -> EntryType {
11394 unsafe { core::mem::transmute(val & 0x03) }
11395 }
11396 #[inline(always)]
11397 pub const fn to_bits(self) -> u8 {
11398 unsafe { core::mem::transmute(self) }
11399 }
11400 }
11401 impl From<u8> for EntryType {
11402 #[inline(always)]
11403 fn from(val: u8) -> EntryType {
11404 EntryType::from_bits(val)
11405 }
11406 }
11407 impl From<EntryType> for u8 {
11408 #[inline(always)]
11409 fn from(val: EntryType) -> u8 {
11410 EntryType::to_bits(val)
11411 }
11412 }
11413 #[repr(u8)]
11414 #[allow(non_camel_case_types)]
11415 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
11416 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
11417 pub enum MemoryType {
11418 #[doc = "Device memory, non-bufferable"]
11419 DevNonBuf = 0x0,
11420 #[doc = "Device memory, bufferable"]
11421 DevBuf = 0x01,
11422 #[doc = "Normal memory, non-cacheable, non-bufferable"]
11423 MemNonCacheNonBuf = 0x02,
11424 #[doc = "Normal memory, non-cacheable, bufferable"]
11425 MemNonCacheBuf = 0x03,
11426 #[doc = "Normal memory, write-through, no allocate"]
11427 MemWtNoAlloc = 0x04,
11428 #[doc = "Normal memory, write-through, read allocate"]
11429 MemWtReadAlloc = 0x05,
11430 _RESERVED_6 = 0x06,
11431 _RESERVED_7 = 0x07,
11432 #[doc = "Normal memory, write-back, no allocate"]
11433 MemWbNoAlloc = 0x08,
11434 #[doc = "Normal memory, write-back, read allocate"]
11435 MemWbReadAlloc = 0x09,
11436 #[doc = "Normal memory, write-back, write allocate"]
11437 MemWbWriteAlloc = 0x0a,
11438 #[doc = "Normal memory, write-back, read and write allocate"]
11439 MemWbReadWriteAlloc = 0x0b,
11440 _RESERVED_c = 0x0c,
11441 _RESERVED_d = 0x0d,
11442 _RESERVED_e = 0x0e,
11443 #[doc = "Empty hole"]
11444 EmptyHole = 0x0f,
11445 }
11446 impl MemoryType {
11447 #[inline(always)]
11448 pub const fn from_bits(val: u8) -> MemoryType {
11449 unsafe { core::mem::transmute(val & 0x0f) }
11450 }
11451 #[inline(always)]
11452 pub const fn to_bits(self) -> u8 {
11453 unsafe { core::mem::transmute(self) }
11454 }
11455 }
11456 impl From<u8> for MemoryType {
11457 #[inline(always)]
11458 fn from(val: u8) -> MemoryType {
11459 MemoryType::from_bits(val)
11460 }
11461 }
11462 impl From<MemoryType> for u8 {
11463 #[inline(always)]
11464 fn from(val: MemoryType) -> u8 {
11465 MemoryType::to_bits(val)
11466 }
11467 }
11468}