andes-riscv 0.2.0

Low level access to Andes' AndeStar V5 RISC-V processors
Documentation 
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//! Low level access to Andes' AndeStar V5 RISC-V processors

#![no_std]

/// The `register` module provides access to the processor's registers
pub mod register;

pub mod l1c;

pub use riscv;

pub mod plic;