use cortex_m::peripheral::syst::SystClkSource;
use cortex_m::peripheral::SYST;
use crate::clock;
use crate::time::Hertz;
use hal::blocking::delay::{DelayMs, DelayUs};
use pac::CLKGEN;
pub struct Delay {
sysclock: Hertz,
syst: SYST,
}
impl Delay {
pub fn new(mut syst: SYST, clkgen: &mut CLKGEN) -> Self {
syst.set_clock_source(SystClkSource::Core);
let sysclock = match clkgen.cctrl.read().coresel().variant() {
pac::clkgen::cctrl::CORESEL_A::HFRC => {
clock::CLKGEN_FREQ_MAX_HZ
}
pac::clkgen::cctrl::CORESEL_A::HFRC_DIV2 => {
Hertz(clock::CLKGEN_FREQ_MAX_HZ.0 / 2)
}
};
Delay {
syst,
sysclock: sysclock.into(),
}
}
pub fn free(self) -> SYST {
self.syst
}
}
impl DelayMs<u32> for Delay {
fn delay_ms(&mut self, ms: u32) {
self.delay_us(ms * 1_000);
}
}
impl DelayMs<u16> for Delay {
fn delay_ms(&mut self, ms: u16) {
self.delay_ms(ms as u32);
}
}
impl DelayMs<u8> for Delay {
fn delay_ms(&mut self, ms: u8) {
self.delay_ms(ms as u32);
}
}
impl DelayUs<u32> for Delay {
fn delay_us(&mut self, us: u32) {
const MAX_RVR: u32 = 0x00FF_FFFF;
let mut total_rvr = us * (self.sysclock.0 / 1_000_000);
while total_rvr != 0 {
let current_rvr = if total_rvr <= MAX_RVR {
total_rvr
} else {
MAX_RVR
};
self.syst.set_reload(current_rvr);
self.syst.clear_current();
self.syst.enable_counter();
total_rvr -= current_rvr;
while !self.syst.has_wrapped() {}
self.syst.disable_counter();
}
}
}
impl DelayUs<u16> for Delay {
fn delay_us(&mut self, us: u16) {
self.delay_us(us as u32)
}
}
impl DelayUs<u8> for Delay {
fn delay_us(&mut self, us: u8) {
self.delay_us(us as u32)
}
}
#[cfg(feature = "ambiq-sdk")]
pub use flash::FlashDelay;
#[cfg(feature = "ambiq-sdk")]
pub mod flash {
use super::*;
#[derive(Clone, Copy)]
pub struct FlashDelay;
impl FlashDelay {
pub fn new() -> FlashDelay {
FlashDelay
}
pub fn delay_us(us: u32) {
let clkgen = unsafe { &*CLKGEN::ptr() };
let sysclock = match clkgen.cctrl.read().coresel().variant() {
pac::clkgen::cctrl::CORESEL_A::HFRC => {
clock::CLKGEN_FREQ_MAX_HZ
}
pac::clkgen::cctrl::CORESEL_A::HFRC_DIV2 => {
Hertz(clock::CLKGEN_FREQ_MAX_HZ.0 / 2)
}
};
let cycles = us * (sysclock.0 / 3_000_000);
unsafe {
halc::am_hal_flash_delay(cycles);
}
}
pub fn delay_cycles(cycles: u32) {
unsafe {
halc::am_hal_flash_delay(cycles);
}
}
}
impl DelayUs<u32> for FlashDelay {
fn delay_us(&mut self, us: u32) {
let clkgen = unsafe { &*CLKGEN::ptr() };
let sysclock = match clkgen.cctrl.read().coresel().variant() {
pac::clkgen::cctrl::CORESEL_A::HFRC => {
clock::CLKGEN_FREQ_MAX_HZ
}
pac::clkgen::cctrl::CORESEL_A::HFRC_DIV2 => {
Hertz(clock::CLKGEN_FREQ_MAX_HZ.0 / 2)
}
};
let cycles = us * (sysclock.0 / 3_000_000);
unsafe {
halc::am_hal_flash_delay(cycles);
}
}
}
impl DelayUs<u16> for FlashDelay {
fn delay_us(&mut self, us: u16) {
self.delay_us(us as u32)
}
}
impl DelayUs<u8> for FlashDelay {
fn delay_us(&mut self, us: u8) {
self.delay_us(us as u32)
}
}
impl<T> DelayMs<T> for FlashDelay where T: Into<u32> {
fn delay_ms(&mut self, us: T) {
let us = us.into();
DelayUs::<u32>::delay_us(self, us * 1000);
}
}
}