1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
//! Serial Peripheral Interface (SPI) bus
use core::ptr;
use crate::pac::{RCC, SPI1, SPI2, SPI3};
use hal::spi::{FullDuplex, Mode, Phase, Polarity};
use nb;
use crate::gpio::{AltFn, PullType, AF5, AF6};
use crate::gpio::{HighSpeed, PinMode, PushPull};
use crate::gpio::{PA5, PA6, PA7};
use crate::gpio::{PB13, PB14, PB15, PB3, PB4, PB5};
use crate::gpio::{PC10, PC11, PC12};
use crate::rcc::Clocks;
use crate::time::Hertz;
/// SPI error
#[derive(Debug)]
pub enum Error {
/// Overrun occurred
Overrun,
/// Mode fault occurred
ModeFault,
/// CRC error
Crc,
#[doc(hidden)]
_Extensible,
}
/// SPI peripheral operating in full duplex master mode
pub struct Spi<SPI, PINS> {
spi: SPI,
pins: PINS,
}
/// SPI extension for SPI
pub trait SpiExt<SPI, ISCK, IMISO, IMOSI, SCK, MISO, MOSI> {
/// Configures the SPI peripheral to operate in full duplex master mode.
/// Consumes SPI peripheral and triple of (SCK, MISO, MOSI) pins.
/// Returns [`Spi`].
///
/// [`Spi`]: ./struct.Spi.html
fn spi<F>(self,
pins: (ISCK, IMISO, IMOSI),
mode: Mode,
freq: F,
clocks: Clocks)
-> Spi<SPI, (SCK, MISO, MOSI)>
where F: Into<Hertz<u32>>;
}
#[cfg_attr(rustfmt, rustfmt_skip)]
macro_rules! spi {
($SPIX:ident,
$apbenr:ident,
$apbrstr:ident,
$spiXen:ident,
$spiXrst:ident,
$pclkX:ident,
$afn:ident,
$speed:ident,
sck: [$($sck: ident, )+],
miso: $miso: tt,
mosi: $mosi: tt
) => {
spi!{
$SPIX,
$apbenr,
$apbrstr,
$spiXen,
$spiXrst,
$pclkX,
$afn,
$speed,
[$(
($sck, $miso, ),
)+],
$mosi
}
};
($SPIX:ident,
$apbenr:ident,
$apbrstr:ident,
$spiXen:ident,
$spiXrst:ident,
$pclkX:ident,
$afn:ident,
$speed:ident,
[$(($sck: ident,
[$($miso: ident, )+], ),
)+],
$mosi: tt
) => {
spi!{
$SPIX,
$apbenr,
$apbrstr,
$spiXen,
$spiXrst,
$pclkX,
$afn,
$speed,
[$(
($sck,
[$(
($miso, $mosi),
)+]),
)+]
}
};
($SPIX:ident,
$apbenr:ident,
$apbrstr:ident,
$spiXen:ident,
$spiXrst:ident,
$pclkX:ident,
$afn:ident,
$speed:ident,
[$(($sck: ident,
[$(($miso: ident, [$($mosi: ident,)+]), )+]
), )+]
) => {
$(
$(
$(
impl<PT: PullType, PM: PinMode>
SpiExt<$SPIX,
$sck<PT, PM>,
$miso<PT, PM>,
$mosi<PT, PM>,
$sck<PT, AltFn<$afn, PushPull, $speed>>,
$miso<PT, AltFn<$afn, PushPull, $speed>>,
$mosi<PT, AltFn<$afn, PushPull, $speed>>> for $SPIX
{
fn spi<F>(
self,
pins: ($sck<PT, PM>, $miso<PT, PM>, $mosi<PT, PM>),
mode: Mode,
freq: F,
clocks: Clocks)
-> Spi<$SPIX,
($sck<PT, AltFn<$afn, PushPull, $speed>>,
$miso<PT, AltFn<$afn, PushPull, $speed>>,
$mosi<PT, AltFn<$afn, PushPull, $speed>>)>
where F: Into<Hertz<u32>>
{
let outpins = (pins.0.alternating($afn).output_speed($speed),
pins.1.alternating($afn).output_speed($speed),
pins.2.alternating($afn).output_speed($speed));
let apbenr = unsafe { &(*RCC::ptr()).$apbenr };
let apbrstr = unsafe { &(*RCC::ptr()).$apbrstr };
// enable or reset $SPIX
apbenr.modify(|_, w| w.$spiXen().enabled());
apbrstr.modify(|_, w| w.$spiXrst().set_bit());
apbrstr.modify(|_, w| w.$spiXrst().clear_bit());
// FRXTH: RXNE event is generated if the FIFO level is greater
// than or equal to 8-bit
// DS: 8-bit data size
// SSOE: Slave Select output disabled
self.cr2.write(|w| unsafe {
w.frxth()
.set_bit()
.ds()
.bits(0b111)
.ssoe()
.clear_bit()
});
let br = match clocks.$pclkX().0 / freq.into().0 {
0 => unreachable!(),
1..=2 => 0b000,
3..=5 => 0b001,
6..=11 => 0b010,
12..=23 => 0b011,
24..=39 => 0b100,
40..=95 => 0b101,
96..=191 => 0b110,
_ => 0b111,
};
// CPHA: phase
// CPOL: polarity
// MSTR: master mode
// BR: 1 MHz
// SPE: SPI disabled
// LSBFIRST: MSB first
// SSM: enable software slave management (NSS pin free for
// other uses) SSI: set nss high = master mode
// CRCEN: hardware CRC calculation disabled
// BIDIMODE: 2 line unidirectional (full duplex)
self.cr1.write(|w|
w.cpha()
.bit(mode.phase
== Phase::CaptureOnSecondTransition)
.cpol()
.bit(mode.polarity == Polarity::IdleHigh)
.mstr()
.set_bit()
.br()
.bits(br)
.spe()
.set_bit()
.lsbfirst()
.clear_bit()
.ssi()
.set_bit()
.ssm()
.set_bit()
.crcen()
.clear_bit()
.bidimode()
.clear_bit()
);
Spi { spi: self,
pins: outpins, }
}
}
)+
)+
)+
impl<SCK, MISO, MOSI> Spi<$SPIX, (SCK, MISO, MOSI)> {
/// Releases the SPI peripheral and associated pins
pub fn free(self) -> ($SPIX, (SCK, MISO, MOSI)) {
(self.spi, self.pins)
}
}
impl<PINS> FullDuplex<u8> for Spi<$SPIX, PINS> {
type Error = Error;
fn read(&mut self) -> nb::Result<u8, Error> {
let sr = self.spi.sr.read();
Err(if sr.ovr().bit_is_set() {
nb::Error::Other(Error::Overrun)
} else if sr.modf().bit_is_set() {
nb::Error::Other(Error::ModeFault)
} else if sr.crcerr().bit_is_set() {
nb::Error::Other(Error::Crc)
} else if sr.rxne().bit_is_set() {
// NOTE(read_volatile) read only 1 byte (the svd2rust API
// only allows reading a half-word)
return Ok(unsafe {
ptr::read_volatile(&self.spi.dr as *const _
as *const u8)
});
} else {
nb::Error::WouldBlock
})
}
fn send(&mut self, byte: u8) -> nb::Result<(), Error> {
let sr = self.spi.sr.read();
Err(if sr.ovr().bit_is_set() {
nb::Error::Other(Error::Overrun)
} else if sr.modf().bit_is_set() {
nb::Error::Other(Error::ModeFault)
} else if sr.crcerr().bit_is_set() {
nb::Error::Other(Error::Crc)
} else if sr.txe().bit_is_set() {
// NOTE(write_volatile) see note above
unsafe {
ptr::write_volatile(&self.spi.dr as *const _ as *mut u8,
byte)
}
return Ok(());
} else {
nb::Error::WouldBlock
})
}
}
impl<PINS> ::hal::blocking::spi::transfer::Default<u8>
for Spi<$SPIX, PINS>
{}
impl<PINS> ::hal::blocking::spi::write::Default<u8>
for Spi<$SPIX, PINS>
{}
};
}
//// DEFINE traits for Spi1Sck, Spi1Miso or, even better Sck<dev = SPI1>
spi!(SPI1,
apb2enr,
apb2rstr,
spi1en,
spi1rst,
pclk2,
AF5,
HighSpeed,
sck: [PA5, PB3,],
miso: [PA6, PB4,],
mosi: [PA7, PB5,]);
spi!(SPI2,
apb1enr,
apb1rstr,
spi2en,
spi2rst,
pclk1,
AF5,
HighSpeed,
sck: [PB13,],
miso: [PB14,],
mosi: [PB15,]);
spi!(SPI3,
apb1enr,
apb1rstr,
spi3en,
spi3rst,
pclk1,
AF6,
HighSpeed,
sck: [PB3, PC10,],
miso: [PB4, PC11,],
mosi: [PB5, PC12,]);