mod config;
pub mod variant;
pub use config::{read_chip_revision, validate_chip_revision};
pub use variant::{
CHIP_ID_H_MASK,
CHIP_ID_H_VALUE,
CHIP_REV_ADDR,
CHIP_REV_HIGH_SHIFT,
CHIP_REV_MASK,
CHIP_REV_U01,
CHIP_REV_U02,
CHIP_REV_U03,
CHIP_REV_U04,
ChipRevision,
ChipVariant,
DEFAULT_CLOCK_FREQ,
DRV_TASK_ID,
FIRMWARE_START_CLOCK_FREQ,
FW_CONFIG_BASE_OFFSET,
FW_UPLOAD_CHUNK_SIZE,
FW_UPLOAD_PROGRESS_INTERVAL,
HOST_START_APP_AUTO,
HOST_START_APP_CUSTOM,
HOST_START_APP_DUMMY,
HOST_START_APP_FNCALL,
LMAC_FIRST_DBG,
LMAC_MSG_ID_SHIFT,
PATCH_ADDR_REG,
PATCH_NUM_REG,
PATCH_TBL,
PATCH_TBL_START_ADDR,
RAM_FMAC_FW_ADDR,
RAM_FMAC_FW_PATCH_ADDR,
RF_TBL_MASKED,
ROM_FMAC_FW_ADDR,
ROM_FMAC_PATCH_ADDR,
SDIO_TYPE_CFG,
SDIO_TYPE_CFG_CMD_RSP,
SDIO_TYPE_CFG_DATA_CFM,
SDIO_TYPE_CFG_PRINT,
SDIO_TYPE_DATA,
SDIOWIFI_BLOCK_CNT_REG,
SDIOWIFI_BYTEMODE_ENABLE_REG,
SDIOWIFI_BYTEMODE_ENABLE_REG_V3,
SDIOWIFI_BYTEMODE_LEN_MSB_REG_V3,
SDIOWIFI_BYTEMODE_LEN_REG,
SDIOWIFI_BYTEMODE_LEN_REG_V3,
SDIOWIFI_CLK_TEST_RESULT_REG_V3,
SDIOWIFI_FLOW_CTRL_Q1_REG_V3,
SDIOWIFI_FLOW_CTRL_Q2_REG_V3,
SDIOWIFI_FLOW_CTRL_REG,
SDIOWIFI_FLOWCTRL_MASK,
SDIOWIFI_FUNC_BLOCKSIZE,
SDIOWIFI_INTR_CONFIG_REG,
SDIOWIFI_INTR_ENABLE_REG_V3,
SDIOWIFI_MISC_CTRL_REG_V3,
SDIOWIFI_MISC_INT_STATUS_REG_V3,
SDIOWIFI_RD_FIFO_ADDR,
SDIOWIFI_RD_FIFO_ADDR_V3,
SDIOWIFI_REGISTER_BLOCK,
SDIOWIFI_SLEEP_REG,
SDIOWIFI_SLEEP_REG_V3,
SDIOWIFI_V3_SLEEP_READY_BIT,
SDIOWIFI_V3_WAKEUP_VALUE,
SDIOWIFI_WAKEUP_REG,
SDIOWIFI_WAKEUP_REG_V3,
SDIOWIFI_WR_FIFO_ADDR,
SDIOWIFI_WR_FIFO_ADDR_V3,
SYSCFG_TBL,
SYSCFG_TBL_MASKED,
TASK_DBG,
};