#[allow(non_snake_case, non_upper_case_globals)]
pub mod reg {
pub const DEVID_AD: u8 = 0x00;
pub const DEVID_MST: u8 = 0x01;
pub const PARTID: u8 = 0x02;
pub const REVID: u8 = 0x03;
pub const STATUS: u8 = 0x04;
pub const FIFO_ENTRIES: u8 = 0x05;
pub const TEMP2: u8 = 0x06;
pub const TEMP1: u8 = 0x07;
pub const XDATA3: u8 = 0x08;
pub const XDATA2: u8 = 0x09;
pub const XDATA1: u8 = 0x0A;
pub const YDATA3: u8 = 0x0B;
pub const YDATA2: u8 = 0x0C;
pub const YDATA1: u8 = 0x0D;
pub const ZDATA3: u8 = 0x0E;
pub const ZDATA2: u8 = 0x0F;
pub const ZDATA1: u8 = 0x10;
pub const FIFO_DATA: u8 = 0x11;
pub const OFFSET_X_H: u8 = 0x1E;
pub const OFFSET_X_L: u8 = 0x1F;
pub const OFFSET_Y_H: u8 = 0x20;
pub const OFFSET_Y_L: u8 = 0x21;
pub const OFFSET_Z_H: u8 = 0x22;
pub const OFFSET_Z_L: u8 = 0x23;
pub const ACT_EN: u8 = 0x24;
pub const ACT_THRESH_H: u8 = 0x25;
pub const ACT_THRESH_L: u8 = 0x26;
pub const ACT_COUNT: u8 = 0x27;
pub const FILTER: u8 = 0x28;
pub const FIFO_SAMPLES: u8 = 0x29;
pub const INT_MAP: u8 = 0x2A;
pub const SYNC: u8 = 0x2B;
pub const RANGE: u8 = 0x2C;
pub const POWER_CTL: u8 = 0x2D;
pub const SELF_TEST: u8 = 0x2E;
pub const RESET: u8 = 0x2F;
}
pub mod id {
pub const DEVID_AD: u8 = 0xAD;
pub const DEVID_MST: u8 = 0x1D;
pub const PARTID: u8 = 0xED;
}
pub const RESET_CODE: u8 = 0x52;
pub mod temperature {
pub const TEMP2_DATA_MASK: u8 = 0x0F;
pub const READ_ATTEMPTS: usize = 3;
pub const INTERCEPT_LSB: f32 = 1885.0;
pub const INTERCEPT_C: f32 = 25.0;
pub const SLOPE_LSB_PER_C: f32 = -9.05;
}
pub const POWER_MODE_BIT: u8 = 0;
pub mod status {
pub const NVM_BUSY: u8 = 4;
pub const ACTIVITY: u8 = 3;
pub const FIFO_OVR: u8 = 2;
pub const FIFO_FULL: u8 = 1;
pub const DATA_RDY: u8 = 0;
}
pub mod filter {
pub const ODR_MASK: u8 = 0x0F;
pub const ODR_SHIFT: u8 = 0;
pub const HPF_MASK: u8 = 0x70;
pub const HPF_SHIFT: u8 = 4;
}
pub mod range_reg {
pub const SEL_MASK: u8 = 0x03;
pub const G2_VAL: u8 = 0x01;
pub const G4_VAL: u8 = 0x02;
pub const G8_VAL: u8 = 0x03;
}
pub mod spi {
pub fn read_cmd(reg: u8) -> u8 {
(reg << 1) | 0x01
}
pub fn write_cmd(reg: u8) -> u8 {
reg << 1
}
}
pub mod i2c {
pub const DEFAULT_ADDR: u8 = 0x1D;
pub const ALTERNATE_ADDR: u8 = 0x53;
}
#[derive(Debug, Clone, Copy, PartialEq)]
pub enum Range {
G2 = 0x01,
G4 = 0x02,
G8 = 0x03,
}
impl Range {
pub fn to_register(self) -> u8 {
self as u8
}
pub fn from_register(val: u8) -> Option<Self> {
match val & range_reg::SEL_MASK {
0x01 => Some(Range::G2),
0x02 => Some(Range::G4),
0x03 => Some(Range::G8),
_ => None,
}
}
pub fn scale_g_per_lsb(self) -> f32 {
match self {
Range::G2 => 0.0000039,
Range::G4 => 0.0000078,
Range::G8 => 0.0000156,
}
}
}
#[derive(Debug, Clone, Copy, PartialEq)]
pub enum PowerMode {
Standby = 1,
Measurement = 0,
}
#[derive(Debug, Clone, Copy, PartialEq)]
pub enum Odr {
Hz4000 = 0,
Hz2000 = 1,
Hz1000 = 2,
Hz500 = 3,
Hz250 = 4,
Hz125 = 5,
Hz62_5 = 6,
Hz31_25 = 7,
Hz15_625 = 8,
Hz7_813 = 9,
Hz3_906 = 10,
}
pub const STANDARD_GRAVITY_M_S2: f32 = 9.80665;