ab-riscv-primitives 0.0.4

Composable RISC-V primitives (instructions, registers) and abstractions around them
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116

use crate::instructions::Instruction;
use crate::instructions::rv64::b::zba::Rv64ZbaInstruction;
use crate::instructions::test_utils::{make_i_type_with_shamt, make_r_type};
use crate::registers::general_purpose::Reg;

#[test]
fn test_sh1add() {
    let inst = make_r_type(0b0110011, 1, 0b010, 2, 3, 0b0010000);
    let decoded = Rv64ZbaInstruction::<Reg<u64>>::try_decode(inst);
    assert_eq!(
        decoded,
        Some(Rv64ZbaInstruction::Sh1add {
            rd: Reg::Ra,
            rs1: Reg::Sp,
            rs2: Reg::Gp
        })
    );
}

#[test]
fn test_sh2add() {
    let inst = make_r_type(0b0110011, 1, 0b100, 2, 3, 0b0010000);
    let decoded = Rv64ZbaInstruction::<Reg<u64>>::try_decode(inst);
    assert_eq!(
        decoded,
        Some(Rv64ZbaInstruction::Sh2add {
            rd: Reg::Ra,
            rs1: Reg::Sp,
            rs2: Reg::Gp
        })
    );
}

#[test]
fn test_sh3add() {
    let inst = make_r_type(0b0110011, 1, 0b110, 2, 3, 0b0010000);
    let decoded = Rv64ZbaInstruction::<Reg<u64>>::try_decode(inst);
    assert_eq!(
        decoded,
        Some(Rv64ZbaInstruction::Sh3add {
            rd: Reg::Ra,
            rs1: Reg::Sp,
            rs2: Reg::Gp
        })
    );
}

#[test]
fn test_add_uw() {
    let inst = make_r_type(0b0111011, 1, 0b000, 2, 3, 0b0000100);
    let decoded = Rv64ZbaInstruction::<Reg<u64>>::try_decode(inst);
    assert_eq!(
        decoded,
        Some(Rv64ZbaInstruction::AddUw {
            rd: Reg::Ra,
            rs1: Reg::Sp,
            rs2: Reg::Gp
        })
    );
}

#[test]
fn test_slli_uw() {
    let inst = make_i_type_with_shamt(0b0011011, 1, 0b001, 2, 40, 0b000010);
    let decoded = Rv64ZbaInstruction::<Reg<u64>>::try_decode(inst);
    assert_eq!(
        decoded,
        Some(Rv64ZbaInstruction::SlliUw {
            rd: Reg::Ra,
            rs1: Reg::Sp,
            shamt: 40
        })
    );
}

#[test]
fn test_sh1add_uw() {
    let inst = make_r_type(0b0111011, 1, 0b010, 2, 3, 0b0010000);
    let decoded = Rv64ZbaInstruction::<Reg<u64>>::try_decode(inst);
    assert_eq!(
        decoded,
        Some(Rv64ZbaInstruction::Sh1addUw {
            rd: Reg::Ra,
            rs1: Reg::Sp,
            rs2: Reg::Gp
        })
    );
}

#[test]
fn test_sh2add_uw() {
    let inst = make_r_type(0b0111011, 1, 0b100, 2, 3, 0b0010000);
    let decoded = Rv64ZbaInstruction::<Reg<u64>>::try_decode(inst);
    assert_eq!(
        decoded,
        Some(Rv64ZbaInstruction::Sh2addUw {
            rd: Reg::Ra,
            rs1: Reg::Sp,
            rs2: Reg::Gp
        })
    );
}

#[test]
fn test_sh3add_uw() {
    let inst = make_r_type(0b0111011, 1, 0b110, 2, 3, 0b0010000);
    let decoded = Rv64ZbaInstruction::<Reg<u64>>::try_decode(inst);
    assert_eq!(
        decoded,
        Some(Rv64ZbaInstruction::Sh3addUw {
            rd: Reg::Ra,
            rs1: Reg::Sp,
            rs2: Reg::Gp
        })
    );
}