ab-riscv-primitives 0.0.4

Composable RISC-V primitives (instructions, registers) and abstractions around them
Documentation 
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use crate::instructions::Instruction;
use crate::instructions::rv32::zk::zbkx::Rv32ZbkxInstruction;
use crate::instructions::test_utils::make_r_type;
use crate::registers::general_purpose::Reg;

#[test]
fn test_xperm4() {
    let inst = make_r_type(0b0110011, 1, 0b010, 2, 3, 0b0010100);
    let decoded = Rv32ZbkxInstruction::<Reg<u32>>::try_decode(inst);
    assert_eq!(
        decoded,
        Some(Rv32ZbkxInstruction::Xperm4 {
            rd: Reg::Ra,
            rs1: Reg::Sp,
            rs2: Reg::Gp
        })
    );
}

#[test]
fn test_xperm8() {
    let inst = make_r_type(0b0110011, 1, 0b100, 2, 3, 0b0010100);
    let decoded = Rv32ZbkxInstruction::<Reg<u32>>::try_decode(inst);
    assert_eq!(
        decoded,
        Some(Rv32ZbkxInstruction::Xperm8 {
            rd: Reg::Ra,
            rs1: Reg::Sp,
            rs2: Reg::Gp
        })
    );
}

#[test]
fn test_wrong_funct7_no_decode() {
    let inst = make_r_type(0b0110011, 1, 0b010, 2, 3, 0b0000000);
    let decoded = Rv32ZbkxInstruction::<Reg<u32>>::try_decode(inst);
    assert_eq!(decoded, None);
}

#[test]
fn test_wrong_opcode_no_decode() {
    // OP-32 opcode is RV64-only and must not decode under RV32
    let inst = make_r_type(0b0111011, 1, 0b000, 2, 3, 0b0010100);
    let decoded = Rv32ZbkxInstruction::<Reg<u32>>::try_decode(inst);
    assert_eq!(decoded, None);
}