ab-riscv-primitives 0.0.2

Composable RISC-V primitives (instructions, registers) and abstractions around them
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75

//! RV32 Zba extension

#[cfg(test)]
mod tests;

use crate::instructions::Instruction;
use crate::registers::general_purpose::Register;
use ab_riscv_macros::instruction;
use core::fmt;

/// RISC-V RV32 Zba instruction (Address generation)
#[instruction]
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum Rv32ZbaInstruction<Reg> {
    Sh1add { rd: Reg, rs1: Reg, rs2: Reg },
    Sh2add { rd: Reg, rs1: Reg, rs2: Reg },
    Sh3add { rd: Reg, rs1: Reg, rs2: Reg },
}

#[instruction]
impl<Reg> const Instruction for Rv32ZbaInstruction<Reg>
where
    Reg: [const] Register<Type = u32>,
{
    type Reg = Reg;

    #[inline(always)]
    fn try_decode(instruction: u32) -> Option<Self> {
        let opcode = (instruction & 0b111_1111) as u8;
        let rd_bits = ((instruction >> 7) & 0x1f) as u8;
        let funct3 = ((instruction >> 12) & 0b111) as u8;
        let rs1_bits = ((instruction >> 15) & 0x1f) as u8;
        let rs2_bits = ((instruction >> 20) & 0x1f) as u8;
        let funct7 = ((instruction >> 25) & 0b111_1111) as u8;

        match opcode {
            // R-type
            0b0110011 => {
                let rd = Reg::from_bits(rd_bits)?;
                let rs1 = Reg::from_bits(rs1_bits)?;
                let rs2 = Reg::from_bits(rs2_bits)?;
                match (funct3, funct7) {
                    (0b010, 0b0010000) => Some(Self::Sh1add { rd, rs1, rs2 }),
                    (0b100, 0b0010000) => Some(Self::Sh2add { rd, rs1, rs2 }),
                    (0b110, 0b0010000) => Some(Self::Sh3add { rd, rs1, rs2 }),
                    _ => None,
                }
            }
            _ => None,
        }
    }

    #[inline(always)]
    fn alignment() -> u8 {
        size_of::<u32>() as u8
    }

    #[inline(always)]
    fn size(&self) -> u8 {
        size_of::<u32>() as u8
    }
}

impl<Reg> fmt::Display for Rv32ZbaInstruction<Reg>
where
    Reg: fmt::Display,
{
    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
        match self {
            Self::Sh1add { rd, rs1, rs2 } => write!(f, "sh1add {}, {}, {}", rd, rs1, rs2),
            Self::Sh2add { rd, rs1, rs2 } => write!(f, "sh2add {}, {}, {}", rd, rs1, rs2),
            Self::Sh3add { rd, rs1, rs2 } => write!(f, "sh3add {}, {}, {}", rd, rs1, rs2),
        }
    }
}