ab-riscv-interpreter 0.0.4

Composable and generic RISC-V interpreter
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154

use crate::RegisterFile;
use crate::rv64::test_utils::{execute, initialize_state};
use ab_riscv_primitives::prelude::*;

#[test]
fn test_add_uw() {
    let mut state = initialize_state([Rv64ZbaInstruction::AddUw {
        rd: Reg::A2,
        rs1: Reg::A0,
        rs2: Reg::A1,
    }]);

    state.regs.write(Reg::A0, 0xFFFF_FFFF_8000_0000u64);
    state.regs.write(Reg::A1, 0x1000);

    execute(&mut state).unwrap();

    // Only the lower 32 bits are zero-extended
    assert_eq!(state.regs.read(Reg::A2), 0x8000_1000);
}

#[test]
fn test_sh1add() {
    let mut state = initialize_state([Rv64ZbaInstruction::Sh1add {
        rd: Reg::A2,
        rs1: Reg::A0,
        rs2: Reg::A1,
    }]);

    state.regs.write(Reg::A0, 10);
    state.regs.write(Reg::A1, 100);

    execute(&mut state).unwrap();

    // (10 << 1) + 100 = 20 + 100 = 120
    assert_eq!(state.regs.read(Reg::A2), 120);
}

#[test]
fn test_sh2add() {
    let mut state = initialize_state([Rv64ZbaInstruction::Sh2add {
        rd: Reg::A2,
        rs1: Reg::A0,
        rs2: Reg::A1,
    }]);

    state.regs.write(Reg::A0, 10);
    state.regs.write(Reg::A1, 100);

    execute(&mut state).unwrap();

    // (10 << 2) + 100 = 40 + 100 = 140
    assert_eq!(state.regs.read(Reg::A2), 140);
}

#[test]
fn test_sh3add() {
    let mut state = initialize_state([Rv64ZbaInstruction::Sh3add {
        rd: Reg::A2,
        rs1: Reg::A0,
        rs2: Reg::A1,
    }]);

    state.regs.write(Reg::A0, 10);
    state.regs.write(Reg::A1, 100);

    execute(&mut state).unwrap();

    // (10 << 3) + 100 = 80 + 100 = 180
    assert_eq!(state.regs.read(Reg::A2), 180);
}

#[test]
fn test_sh1add_uw() {
    let mut state = initialize_state([Rv64ZbaInstruction::Sh1addUw {
        rd: Reg::A2,
        rs1: Reg::A0,
        rs2: Reg::A1,
    }]);

    state.regs.write(Reg::A0, 0xFFFF_FFFF_0000_000Au64);
    state.regs.write(Reg::A1, 100);

    execute(&mut state).unwrap();

    // Zero-extend lower 32 bits (10), shift left 1, add 100
    assert_eq!(state.regs.read(Reg::A2), 120);
}

#[test]
fn test_sh2add_uw() {
    let mut state = initialize_state([Rv64ZbaInstruction::Sh2addUw {
        rd: Reg::A2,
        rs1: Reg::A0,
        rs2: Reg::A1,
    }]);

    state.regs.write(Reg::A0, 0xFFFF_FFFF_0000_000Au64);
    state.regs.write(Reg::A1, 100);

    execute(&mut state).unwrap();

    // Zero-extend lower 32 bits (10), shift left 2, add 100
    assert_eq!(state.regs.read(Reg::A2), 140);
}

#[test]
fn test_sh3add_uw() {
    let mut state = initialize_state([Rv64ZbaInstruction::Sh3addUw {
        rd: Reg::A2,
        rs1: Reg::A0,
        rs2: Reg::A1,
    }]);

    state.regs.write(Reg::A0, 0xFFFF_FFFF_0000_000Au64);
    state.regs.write(Reg::A1, 100);

    execute(&mut state).unwrap();

    // Zero-extend lower 32 bits (10), shift left 3, add 100
    assert_eq!(state.regs.read(Reg::A2), 180);
}

#[test]
fn test_slli_uw() {
    let mut state = initialize_state([Rv64ZbaInstruction::SlliUw {
        rd: Reg::A2,
        rs1: Reg::A0,
        shamt: 4,
    }]);

    state.regs.write(Reg::A0, 0xFFFF_FFFF_0000_0001u64);

    execute(&mut state).unwrap();

    // Zero-extend lower 32 bits (1), then shift left 4
    assert_eq!(state.regs.read(Reg::A2), 0x10);
}

#[test]
fn test_slli_uw_max_shamt() {
    let mut state = initialize_state([Rv64ZbaInstruction::SlliUw {
        rd: Reg::A2,
        rs1: Reg::A0,
        shamt: 63,
    }]);

    state.regs.write(Reg::A0, 0xFFFF_FFFF_0000_0001u64);

    execute(&mut state).unwrap();

    // Zero-extend lower 32 bits (1), then shift left 63
    assert_eq!(state.regs.read(Reg::A2), 1u64 << 63);
}