pub mod SADD16_A1 {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b00001111111100000000111111110000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b00000110000100000000111100010000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "SADD16_A1";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 12u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_cond_OFFSET: u32 = 28u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_cond_WIDTH: u32 = 4u32;
#[inline]
pub const fn SADD16_A1(
cond: ::aarchmrs_types::BitValue<4>,
Rn: ::aarchmrs_types::BitValue<4>,
Rd: ::aarchmrs_types::BitValue<4>,
Rm: ::aarchmrs_types::BitValue<4>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
cond.into_inner() << 28u32
| 0b01100001u32 << 20u32
| Rn.into_inner() << 16u32
| Rd.into_inner() << 12u32
| 0b11110001u32 << 4u32
| Rm.into_inner() << 0u32,
)
}
}
pub mod SASX_A1 {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b00001111111100000000111111110000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b00000110000100000000111100110000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "SASX_A1";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 12u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_cond_OFFSET: u32 = 28u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_cond_WIDTH: u32 = 4u32;
#[inline]
pub const fn SASX_A1(
cond: ::aarchmrs_types::BitValue<4>,
Rn: ::aarchmrs_types::BitValue<4>,
Rd: ::aarchmrs_types::BitValue<4>,
Rm: ::aarchmrs_types::BitValue<4>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
cond.into_inner() << 28u32
| 0b01100001u32 << 20u32
| Rn.into_inner() << 16u32
| Rd.into_inner() << 12u32
| 0b11110011u32 << 4u32
| Rm.into_inner() << 0u32,
)
}
}
pub mod SSAX_A1 {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b00001111111100000000111111110000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b00000110000100000000111101010000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "SSAX_A1";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 12u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_cond_OFFSET: u32 = 28u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_cond_WIDTH: u32 = 4u32;
#[inline]
pub const fn SSAX_A1(
cond: ::aarchmrs_types::BitValue<4>,
Rn: ::aarchmrs_types::BitValue<4>,
Rd: ::aarchmrs_types::BitValue<4>,
Rm: ::aarchmrs_types::BitValue<4>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
cond.into_inner() << 28u32
| 0b01100001u32 << 20u32
| Rn.into_inner() << 16u32
| Rd.into_inner() << 12u32
| 0b11110101u32 << 4u32
| Rm.into_inner() << 0u32,
)
}
}
pub mod SSUB16_A1 {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b00001111111100000000111111110000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b00000110000100000000111101110000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "SSUB16_A1";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 12u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_cond_OFFSET: u32 = 28u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_cond_WIDTH: u32 = 4u32;
#[inline]
pub const fn SSUB16_A1(
cond: ::aarchmrs_types::BitValue<4>,
Rn: ::aarchmrs_types::BitValue<4>,
Rd: ::aarchmrs_types::BitValue<4>,
Rm: ::aarchmrs_types::BitValue<4>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
cond.into_inner() << 28u32
| 0b01100001u32 << 20u32
| Rn.into_inner() << 16u32
| Rd.into_inner() << 12u32
| 0b11110111u32 << 4u32
| Rm.into_inner() << 0u32,
)
}
}
pub mod SADD8_A1 {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b00001111111100000000111111110000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b00000110000100000000111110010000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "SADD8_A1";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 12u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_cond_OFFSET: u32 = 28u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_cond_WIDTH: u32 = 4u32;
#[inline]
pub const fn SADD8_A1(
cond: ::aarchmrs_types::BitValue<4>,
Rn: ::aarchmrs_types::BitValue<4>,
Rd: ::aarchmrs_types::BitValue<4>,
Rm: ::aarchmrs_types::BitValue<4>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
cond.into_inner() << 28u32
| 0b01100001u32 << 20u32
| Rn.into_inner() << 16u32
| Rd.into_inner() << 12u32
| 0b11111001u32 << 4u32
| Rm.into_inner() << 0u32,
)
}
}
pub mod SSUB8_A1 {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b00001111111100000000111111110000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b00000110000100000000111111110000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "SSUB8_A1";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 12u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_cond_OFFSET: u32 = 28u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_cond_WIDTH: u32 = 4u32;
#[inline]
pub const fn SSUB8_A1(
cond: ::aarchmrs_types::BitValue<4>,
Rn: ::aarchmrs_types::BitValue<4>,
Rd: ::aarchmrs_types::BitValue<4>,
Rm: ::aarchmrs_types::BitValue<4>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
cond.into_inner() << 28u32
| 0b01100001u32 << 20u32
| Rn.into_inner() << 16u32
| Rd.into_inner() << 12u32
| 0b11111111u32 << 4u32
| Rm.into_inner() << 0u32,
)
}
}
pub mod QADD16_A1 {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b00001111111100000000111111110000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b00000110001000000000111100010000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "QADD16_A1";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 12u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_cond_OFFSET: u32 = 28u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_cond_WIDTH: u32 = 4u32;
#[inline]
pub const fn QADD16_A1(
cond: ::aarchmrs_types::BitValue<4>,
Rn: ::aarchmrs_types::BitValue<4>,
Rd: ::aarchmrs_types::BitValue<4>,
Rm: ::aarchmrs_types::BitValue<4>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
cond.into_inner() << 28u32
| 0b01100010u32 << 20u32
| Rn.into_inner() << 16u32
| Rd.into_inner() << 12u32
| 0b11110001u32 << 4u32
| Rm.into_inner() << 0u32,
)
}
}
pub mod QASX_A1 {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b00001111111100000000111111110000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b00000110001000000000111100110000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "QASX_A1";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 12u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_cond_OFFSET: u32 = 28u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_cond_WIDTH: u32 = 4u32;
#[inline]
pub const fn QASX_A1(
cond: ::aarchmrs_types::BitValue<4>,
Rn: ::aarchmrs_types::BitValue<4>,
Rd: ::aarchmrs_types::BitValue<4>,
Rm: ::aarchmrs_types::BitValue<4>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
cond.into_inner() << 28u32
| 0b01100010u32 << 20u32
| Rn.into_inner() << 16u32
| Rd.into_inner() << 12u32
| 0b11110011u32 << 4u32
| Rm.into_inner() << 0u32,
)
}
}
pub mod QSAX_A1 {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b00001111111100000000111111110000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b00000110001000000000111101010000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "QSAX_A1";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 12u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_cond_OFFSET: u32 = 28u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_cond_WIDTH: u32 = 4u32;
#[inline]
pub const fn QSAX_A1(
cond: ::aarchmrs_types::BitValue<4>,
Rn: ::aarchmrs_types::BitValue<4>,
Rd: ::aarchmrs_types::BitValue<4>,
Rm: ::aarchmrs_types::BitValue<4>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
cond.into_inner() << 28u32
| 0b01100010u32 << 20u32
| Rn.into_inner() << 16u32
| Rd.into_inner() << 12u32
| 0b11110101u32 << 4u32
| Rm.into_inner() << 0u32,
)
}
}
pub mod QSUB16_A1 {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b00001111111100000000111111110000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b00000110001000000000111101110000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "QSUB16_A1";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 12u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_cond_OFFSET: u32 = 28u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_cond_WIDTH: u32 = 4u32;
#[inline]
pub const fn QSUB16_A1(
cond: ::aarchmrs_types::BitValue<4>,
Rn: ::aarchmrs_types::BitValue<4>,
Rd: ::aarchmrs_types::BitValue<4>,
Rm: ::aarchmrs_types::BitValue<4>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
cond.into_inner() << 28u32
| 0b01100010u32 << 20u32
| Rn.into_inner() << 16u32
| Rd.into_inner() << 12u32
| 0b11110111u32 << 4u32
| Rm.into_inner() << 0u32,
)
}
}
pub mod QADD8_A1 {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b00001111111100000000111111110000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b00000110001000000000111110010000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "QADD8_A1";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 12u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_cond_OFFSET: u32 = 28u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_cond_WIDTH: u32 = 4u32;
#[inline]
pub const fn QADD8_A1(
cond: ::aarchmrs_types::BitValue<4>,
Rn: ::aarchmrs_types::BitValue<4>,
Rd: ::aarchmrs_types::BitValue<4>,
Rm: ::aarchmrs_types::BitValue<4>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
cond.into_inner() << 28u32
| 0b01100010u32 << 20u32
| Rn.into_inner() << 16u32
| Rd.into_inner() << 12u32
| 0b11111001u32 << 4u32
| Rm.into_inner() << 0u32,
)
}
}
pub mod QSUB8_A1 {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b00001111111100000000111111110000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b00000110001000000000111111110000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "QSUB8_A1";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 12u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_cond_OFFSET: u32 = 28u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_cond_WIDTH: u32 = 4u32;
#[inline]
pub const fn QSUB8_A1(
cond: ::aarchmrs_types::BitValue<4>,
Rn: ::aarchmrs_types::BitValue<4>,
Rd: ::aarchmrs_types::BitValue<4>,
Rm: ::aarchmrs_types::BitValue<4>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
cond.into_inner() << 28u32
| 0b01100010u32 << 20u32
| Rn.into_inner() << 16u32
| Rd.into_inner() << 12u32
| 0b11111111u32 << 4u32
| Rm.into_inner() << 0u32,
)
}
}
pub mod SHADD16_A1 {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b00001111111100000000111111110000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b00000110001100000000111100010000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "SHADD16_A1";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 12u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_cond_OFFSET: u32 = 28u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_cond_WIDTH: u32 = 4u32;
#[inline]
pub const fn SHADD16_A1(
cond: ::aarchmrs_types::BitValue<4>,
Rn: ::aarchmrs_types::BitValue<4>,
Rd: ::aarchmrs_types::BitValue<4>,
Rm: ::aarchmrs_types::BitValue<4>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
cond.into_inner() << 28u32
| 0b01100011u32 << 20u32
| Rn.into_inner() << 16u32
| Rd.into_inner() << 12u32
| 0b11110001u32 << 4u32
| Rm.into_inner() << 0u32,
)
}
}
pub mod SHASX_A1 {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b00001111111100000000111111110000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b00000110001100000000111100110000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "SHASX_A1";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 12u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_cond_OFFSET: u32 = 28u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_cond_WIDTH: u32 = 4u32;
#[inline]
pub const fn SHASX_A1(
cond: ::aarchmrs_types::BitValue<4>,
Rn: ::aarchmrs_types::BitValue<4>,
Rd: ::aarchmrs_types::BitValue<4>,
Rm: ::aarchmrs_types::BitValue<4>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
cond.into_inner() << 28u32
| 0b01100011u32 << 20u32
| Rn.into_inner() << 16u32
| Rd.into_inner() << 12u32
| 0b11110011u32 << 4u32
| Rm.into_inner() << 0u32,
)
}
}
pub mod SHSAX_A1 {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b00001111111100000000111111110000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b00000110001100000000111101010000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "SHSAX_A1";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 12u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_cond_OFFSET: u32 = 28u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_cond_WIDTH: u32 = 4u32;
#[inline]
pub const fn SHSAX_A1(
cond: ::aarchmrs_types::BitValue<4>,
Rn: ::aarchmrs_types::BitValue<4>,
Rd: ::aarchmrs_types::BitValue<4>,
Rm: ::aarchmrs_types::BitValue<4>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
cond.into_inner() << 28u32
| 0b01100011u32 << 20u32
| Rn.into_inner() << 16u32
| Rd.into_inner() << 12u32
| 0b11110101u32 << 4u32
| Rm.into_inner() << 0u32,
)
}
}
pub mod SHSUB16_A1 {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b00001111111100000000111111110000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b00000110001100000000111101110000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "SHSUB16_A1";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 12u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_cond_OFFSET: u32 = 28u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_cond_WIDTH: u32 = 4u32;
#[inline]
pub const fn SHSUB16_A1(
cond: ::aarchmrs_types::BitValue<4>,
Rn: ::aarchmrs_types::BitValue<4>,
Rd: ::aarchmrs_types::BitValue<4>,
Rm: ::aarchmrs_types::BitValue<4>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
cond.into_inner() << 28u32
| 0b01100011u32 << 20u32
| Rn.into_inner() << 16u32
| Rd.into_inner() << 12u32
| 0b11110111u32 << 4u32
| Rm.into_inner() << 0u32,
)
}
}
pub mod SHADD8_A1 {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b00001111111100000000111111110000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b00000110001100000000111110010000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "SHADD8_A1";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 12u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_cond_OFFSET: u32 = 28u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_cond_WIDTH: u32 = 4u32;
#[inline]
pub const fn SHADD8_A1(
cond: ::aarchmrs_types::BitValue<4>,
Rn: ::aarchmrs_types::BitValue<4>,
Rd: ::aarchmrs_types::BitValue<4>,
Rm: ::aarchmrs_types::BitValue<4>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
cond.into_inner() << 28u32
| 0b01100011u32 << 20u32
| Rn.into_inner() << 16u32
| Rd.into_inner() << 12u32
| 0b11111001u32 << 4u32
| Rm.into_inner() << 0u32,
)
}
}
pub mod SHSUB8_A1 {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b00001111111100000000111111110000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b00000110001100000000111111110000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "SHSUB8_A1";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 12u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_cond_OFFSET: u32 = 28u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_cond_WIDTH: u32 = 4u32;
#[inline]
pub const fn SHSUB8_A1(
cond: ::aarchmrs_types::BitValue<4>,
Rn: ::aarchmrs_types::BitValue<4>,
Rd: ::aarchmrs_types::BitValue<4>,
Rm: ::aarchmrs_types::BitValue<4>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
cond.into_inner() << 28u32
| 0b01100011u32 << 20u32
| Rn.into_inner() << 16u32
| Rd.into_inner() << 12u32
| 0b11111111u32 << 4u32
| Rm.into_inner() << 0u32,
)
}
}
pub mod UADD16_A1 {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b00001111111100000000111111110000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b00000110010100000000111100010000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "UADD16_A1";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 12u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_cond_OFFSET: u32 = 28u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_cond_WIDTH: u32 = 4u32;
#[inline]
pub const fn UADD16_A1(
cond: ::aarchmrs_types::BitValue<4>,
Rn: ::aarchmrs_types::BitValue<4>,
Rd: ::aarchmrs_types::BitValue<4>,
Rm: ::aarchmrs_types::BitValue<4>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
cond.into_inner() << 28u32
| 0b01100101u32 << 20u32
| Rn.into_inner() << 16u32
| Rd.into_inner() << 12u32
| 0b11110001u32 << 4u32
| Rm.into_inner() << 0u32,
)
}
}
pub mod UASX_A1 {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b00001111111100000000111111110000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b00000110010100000000111100110000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "UASX_A1";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 12u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_cond_OFFSET: u32 = 28u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_cond_WIDTH: u32 = 4u32;
#[inline]
pub const fn UASX_A1(
cond: ::aarchmrs_types::BitValue<4>,
Rn: ::aarchmrs_types::BitValue<4>,
Rd: ::aarchmrs_types::BitValue<4>,
Rm: ::aarchmrs_types::BitValue<4>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
cond.into_inner() << 28u32
| 0b01100101u32 << 20u32
| Rn.into_inner() << 16u32
| Rd.into_inner() << 12u32
| 0b11110011u32 << 4u32
| Rm.into_inner() << 0u32,
)
}
}
pub mod USAX_A1 {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b00001111111100000000111111110000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b00000110010100000000111101010000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "USAX_A1";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 12u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_cond_OFFSET: u32 = 28u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_cond_WIDTH: u32 = 4u32;
#[inline]
pub const fn USAX_A1(
cond: ::aarchmrs_types::BitValue<4>,
Rn: ::aarchmrs_types::BitValue<4>,
Rd: ::aarchmrs_types::BitValue<4>,
Rm: ::aarchmrs_types::BitValue<4>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
cond.into_inner() << 28u32
| 0b01100101u32 << 20u32
| Rn.into_inner() << 16u32
| Rd.into_inner() << 12u32
| 0b11110101u32 << 4u32
| Rm.into_inner() << 0u32,
)
}
}
pub mod USUB16_A1 {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b00001111111100000000111111110000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b00000110010100000000111101110000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "USUB16_A1";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 12u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_cond_OFFSET: u32 = 28u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_cond_WIDTH: u32 = 4u32;
#[inline]
pub const fn USUB16_A1(
cond: ::aarchmrs_types::BitValue<4>,
Rn: ::aarchmrs_types::BitValue<4>,
Rd: ::aarchmrs_types::BitValue<4>,
Rm: ::aarchmrs_types::BitValue<4>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
cond.into_inner() << 28u32
| 0b01100101u32 << 20u32
| Rn.into_inner() << 16u32
| Rd.into_inner() << 12u32
| 0b11110111u32 << 4u32
| Rm.into_inner() << 0u32,
)
}
}
pub mod UADD8_A1 {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b00001111111100000000111111110000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b00000110010100000000111110010000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "UADD8_A1";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 12u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_cond_OFFSET: u32 = 28u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_cond_WIDTH: u32 = 4u32;
#[inline]
pub const fn UADD8_A1(
cond: ::aarchmrs_types::BitValue<4>,
Rn: ::aarchmrs_types::BitValue<4>,
Rd: ::aarchmrs_types::BitValue<4>,
Rm: ::aarchmrs_types::BitValue<4>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
cond.into_inner() << 28u32
| 0b01100101u32 << 20u32
| Rn.into_inner() << 16u32
| Rd.into_inner() << 12u32
| 0b11111001u32 << 4u32
| Rm.into_inner() << 0u32,
)
}
}
pub mod USUB8_A1 {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b00001111111100000000111111110000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b00000110010100000000111111110000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "USUB8_A1";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 12u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_cond_OFFSET: u32 = 28u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_cond_WIDTH: u32 = 4u32;
#[inline]
pub const fn USUB8_A1(
cond: ::aarchmrs_types::BitValue<4>,
Rn: ::aarchmrs_types::BitValue<4>,
Rd: ::aarchmrs_types::BitValue<4>,
Rm: ::aarchmrs_types::BitValue<4>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
cond.into_inner() << 28u32
| 0b01100101u32 << 20u32
| Rn.into_inner() << 16u32
| Rd.into_inner() << 12u32
| 0b11111111u32 << 4u32
| Rm.into_inner() << 0u32,
)
}
}
pub mod UQADD16_A1 {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b00001111111100000000111111110000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b00000110011000000000111100010000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "UQADD16_A1";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 12u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_cond_OFFSET: u32 = 28u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_cond_WIDTH: u32 = 4u32;
#[inline]
pub const fn UQADD16_A1(
cond: ::aarchmrs_types::BitValue<4>,
Rn: ::aarchmrs_types::BitValue<4>,
Rd: ::aarchmrs_types::BitValue<4>,
Rm: ::aarchmrs_types::BitValue<4>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
cond.into_inner() << 28u32
| 0b01100110u32 << 20u32
| Rn.into_inner() << 16u32
| Rd.into_inner() << 12u32
| 0b11110001u32 << 4u32
| Rm.into_inner() << 0u32,
)
}
}
pub mod UQASX_A1 {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b00001111111100000000111111110000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b00000110011000000000111100110000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "UQASX_A1";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 12u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_cond_OFFSET: u32 = 28u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_cond_WIDTH: u32 = 4u32;
#[inline]
pub const fn UQASX_A1(
cond: ::aarchmrs_types::BitValue<4>,
Rn: ::aarchmrs_types::BitValue<4>,
Rd: ::aarchmrs_types::BitValue<4>,
Rm: ::aarchmrs_types::BitValue<4>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
cond.into_inner() << 28u32
| 0b01100110u32 << 20u32
| Rn.into_inner() << 16u32
| Rd.into_inner() << 12u32
| 0b11110011u32 << 4u32
| Rm.into_inner() << 0u32,
)
}
}
pub mod UQSAX_A1 {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b00001111111100000000111111110000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b00000110011000000000111101010000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "UQSAX_A1";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 12u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_cond_OFFSET: u32 = 28u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_cond_WIDTH: u32 = 4u32;
#[inline]
pub const fn UQSAX_A1(
cond: ::aarchmrs_types::BitValue<4>,
Rn: ::aarchmrs_types::BitValue<4>,
Rd: ::aarchmrs_types::BitValue<4>,
Rm: ::aarchmrs_types::BitValue<4>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
cond.into_inner() << 28u32
| 0b01100110u32 << 20u32
| Rn.into_inner() << 16u32
| Rd.into_inner() << 12u32
| 0b11110101u32 << 4u32
| Rm.into_inner() << 0u32,
)
}
}
pub mod UQSUB16_A1 {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b00001111111100000000111111110000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b00000110011000000000111101110000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "UQSUB16_A1";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 12u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_cond_OFFSET: u32 = 28u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_cond_WIDTH: u32 = 4u32;
#[inline]
pub const fn UQSUB16_A1(
cond: ::aarchmrs_types::BitValue<4>,
Rn: ::aarchmrs_types::BitValue<4>,
Rd: ::aarchmrs_types::BitValue<4>,
Rm: ::aarchmrs_types::BitValue<4>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
cond.into_inner() << 28u32
| 0b01100110u32 << 20u32
| Rn.into_inner() << 16u32
| Rd.into_inner() << 12u32
| 0b11110111u32 << 4u32
| Rm.into_inner() << 0u32,
)
}
}
pub mod UQADD8_A1 {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b00001111111100000000111111110000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b00000110011000000000111110010000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "UQADD8_A1";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 12u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_cond_OFFSET: u32 = 28u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_cond_WIDTH: u32 = 4u32;
#[inline]
pub const fn UQADD8_A1(
cond: ::aarchmrs_types::BitValue<4>,
Rn: ::aarchmrs_types::BitValue<4>,
Rd: ::aarchmrs_types::BitValue<4>,
Rm: ::aarchmrs_types::BitValue<4>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
cond.into_inner() << 28u32
| 0b01100110u32 << 20u32
| Rn.into_inner() << 16u32
| Rd.into_inner() << 12u32
| 0b11111001u32 << 4u32
| Rm.into_inner() << 0u32,
)
}
}
pub mod UQSUB8_A1 {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b00001111111100000000111111110000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b00000110011000000000111111110000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "UQSUB8_A1";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 12u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_cond_OFFSET: u32 = 28u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_cond_WIDTH: u32 = 4u32;
#[inline]
pub const fn UQSUB8_A1(
cond: ::aarchmrs_types::BitValue<4>,
Rn: ::aarchmrs_types::BitValue<4>,
Rd: ::aarchmrs_types::BitValue<4>,
Rm: ::aarchmrs_types::BitValue<4>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
cond.into_inner() << 28u32
| 0b01100110u32 << 20u32
| Rn.into_inner() << 16u32
| Rd.into_inner() << 12u32
| 0b11111111u32 << 4u32
| Rm.into_inner() << 0u32,
)
}
}
pub mod UHADD16_A1 {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b00001111111100000000111111110000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b00000110011100000000111100010000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "UHADD16_A1";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 12u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_cond_OFFSET: u32 = 28u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_cond_WIDTH: u32 = 4u32;
#[inline]
pub const fn UHADD16_A1(
cond: ::aarchmrs_types::BitValue<4>,
Rn: ::aarchmrs_types::BitValue<4>,
Rd: ::aarchmrs_types::BitValue<4>,
Rm: ::aarchmrs_types::BitValue<4>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
cond.into_inner() << 28u32
| 0b01100111u32 << 20u32
| Rn.into_inner() << 16u32
| Rd.into_inner() << 12u32
| 0b11110001u32 << 4u32
| Rm.into_inner() << 0u32,
)
}
}
pub mod UHASX_A1 {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b00001111111100000000111111110000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b00000110011100000000111100110000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "UHASX_A1";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 12u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_cond_OFFSET: u32 = 28u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_cond_WIDTH: u32 = 4u32;
#[inline]
pub const fn UHASX_A1(
cond: ::aarchmrs_types::BitValue<4>,
Rn: ::aarchmrs_types::BitValue<4>,
Rd: ::aarchmrs_types::BitValue<4>,
Rm: ::aarchmrs_types::BitValue<4>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
cond.into_inner() << 28u32
| 0b01100111u32 << 20u32
| Rn.into_inner() << 16u32
| Rd.into_inner() << 12u32
| 0b11110011u32 << 4u32
| Rm.into_inner() << 0u32,
)
}
}
pub mod UHSAX_A1 {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b00001111111100000000111111110000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b00000110011100000000111101010000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "UHSAX_A1";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 12u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_cond_OFFSET: u32 = 28u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_cond_WIDTH: u32 = 4u32;
#[inline]
pub const fn UHSAX_A1(
cond: ::aarchmrs_types::BitValue<4>,
Rn: ::aarchmrs_types::BitValue<4>,
Rd: ::aarchmrs_types::BitValue<4>,
Rm: ::aarchmrs_types::BitValue<4>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
cond.into_inner() << 28u32
| 0b01100111u32 << 20u32
| Rn.into_inner() << 16u32
| Rd.into_inner() << 12u32
| 0b11110101u32 << 4u32
| Rm.into_inner() << 0u32,
)
}
}
pub mod UHSUB16_A1 {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b00001111111100000000111111110000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b00000110011100000000111101110000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "UHSUB16_A1";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 12u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_cond_OFFSET: u32 = 28u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_cond_WIDTH: u32 = 4u32;
#[inline]
pub const fn UHSUB16_A1(
cond: ::aarchmrs_types::BitValue<4>,
Rn: ::aarchmrs_types::BitValue<4>,
Rd: ::aarchmrs_types::BitValue<4>,
Rm: ::aarchmrs_types::BitValue<4>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
cond.into_inner() << 28u32
| 0b01100111u32 << 20u32
| Rn.into_inner() << 16u32
| Rd.into_inner() << 12u32
| 0b11110111u32 << 4u32
| Rm.into_inner() << 0u32,
)
}
}
pub mod UHADD8_A1 {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b00001111111100000000111111110000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b00000110011100000000111110010000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "UHADD8_A1";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 12u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_cond_OFFSET: u32 = 28u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_cond_WIDTH: u32 = 4u32;
#[inline]
pub const fn UHADD8_A1(
cond: ::aarchmrs_types::BitValue<4>,
Rn: ::aarchmrs_types::BitValue<4>,
Rd: ::aarchmrs_types::BitValue<4>,
Rm: ::aarchmrs_types::BitValue<4>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
cond.into_inner() << 28u32
| 0b01100111u32 << 20u32
| Rn.into_inner() << 16u32
| Rd.into_inner() << 12u32
| 0b11111001u32 << 4u32
| Rm.into_inner() << 0u32,
)
}
}
pub mod UHSUB8_A1 {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b00001111111100000000111111110000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b00000110011100000000111111110000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000111100000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "UHSUB8_A1";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 12u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 4u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_cond_OFFSET: u32 = 28u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_cond_WIDTH: u32 = 4u32;
#[inline]
pub const fn UHSUB8_A1(
cond: ::aarchmrs_types::BitValue<4>,
Rn: ::aarchmrs_types::BitValue<4>,
Rd: ::aarchmrs_types::BitValue<4>,
Rm: ::aarchmrs_types::BitValue<4>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
cond.into_inner() << 28u32
| 0b01100111u32 << 20u32
| Rn.into_inner() << 16u32
| Rd.into_inner() << 12u32
| 0b11111111u32 << 4u32
| Rm.into_inner() << 0u32,
)
}
}