aarch64_cpu/registers/
scr_el3.rs

1// SPDX-License-Identifier: Apache-2.0 OR MIT
2//
3// Copyright (c) 2019-2023 by the author(s)
4//
5// Author(s):
6//   - Berkus Decker <berkus+github@metta.systems>
7
8//! Secure Configuration Register - EL3, page D12.2.99 of armv8arm.
9//! Defines the configuration of the current Security state. It specifies:
10//! • The Security state of EL0, EL1, and EL2. The Security state is either Secure or Non-secure.
11//! • The Execution state at lower Exception levels.
12//! • Whether IRQ, FIQ, SError interrupts, and External abort exceptions are taken to EL3.
13//! • Whether various operations are trapped to EL3.
14
15use tock_registers::{
16    interfaces::{Readable, Writeable},
17    register_bitfields,
18};
19
20register_bitfields! {u64,
21    pub SCR_EL3 [
22        /// Execution state control for lower Exception levels:
23        ///
24        /// 0 Lower levels are all AArch32.
25        /// 1 The next lower level is AArch64.
26        ///   If EL2 is present:
27        ///     The Execution state for EL2 is AArch64.
28        ///     EL2 controls EL1 and EL0 behaviors.
29        ///   If EL2 is not present:
30        ///     The Execution state for EL1 is AArch64.
31        ///     The Execution state for EL0 is determined by the current value of PSTATE.nRW when
32        ///     executing at EL0.
33        ///
34        /// If all lower Exception levels cannot use AArch32 then this bit is RAO/WI.
35        ///
36        /// When SCR_EL3.{EEL2,NS}=={1,0}, this bit is treated as 1 for all purposes other than
37        /// reading or writing the register.
38        ///
39        /// The RW bit is permitted to be cached in a TLB.
40        RW   OFFSET(10) NUMBITS(1) [
41            AllLowerELsAreAarch32 = 0,
42            NextELIsAarch64 = 1
43        ],
44
45        /// Hypervisor Call Enable
46        ///
47        /// 0 The HVC instruction is undefined at all exception levels.
48        /// 1 The HVC instruction is enabled at EL1, EL2, or EL3.
49        HCE OFFSET(8) NUMBITS(1) [
50            HvcDisabled = 0,
51            HvcEnabled = 1
52        ],
53
54        /// Secure Monitor call Disable
55        ///
56        /// 0 The SMC instruction is enabled at EL1, EL2, and EL3.
57        ///
58        /// 1 The SMC instruction is undefined at all exception levels. At EL1, in the Non-secure
59        ///   state, the HCR_EL2.TSC bit has priority over this control.
60        SMD OFFSET(7) NUMBITS(1) [
61            SmcEnabled = 0,
62            SmcDisabled = 1
63        ],
64
65        /// External Abort and SError interrupt routing.
66        /// 0 When executing at Exception levels below EL3, External aborts and SError interrupts are not taken to EL3.
67        ///     In addition, when executing at EL3:
68        ///       SError interrupts are not taken.
69        ///       External aborts are taken to EL3.
70        ///
71        /// 1 When executing at any Exception level, External aborts and SError interrupts are taken to EL3.
72        EA  OFFSET(3) NUMBITS(1) [
73            NotTaken = 0,
74            Taken = 1
75        ],
76
77        /// Physical FIQ Routing.
78        /// 0 When executing at Exception levels below EL3, physical FIQ interrupts are not taken
79        ///   to EL3. When executing at EL3, physical FIQ interrupts are not taken.
80        ///
81        /// 1 When executing at any Exception level, physical FIQ interrupts are taken to EL3.
82        FIQ OFFSET(2) NUMBITS(1) [
83            NotTaken = 0,
84            Taken = 1
85        ],
86
87        /// Physical IRQ Routing.
88        /// 0 When executing at Exception levels below EL3, physical IRQ interrupts are not taken
89        ///   to EL3. When executing at EL3, physical IRQ interrupts are not taken.
90        ///
91        /// 1 When executing at any Exception level, physical IRQ interrupts are taken to EL3.
92        IRQ OFFSET(1) NUMBITS(1) [
93            NotTaken = 0,
94            Taken = 1
95        ],
96
97        /// Non-secure bit.
98        /// 0 Indicates that EL0 and EL1 are in Secure state.
99        ///
100        /// 1 Indicates that Exception levels lower than EL3 are in Non-secure state, and so memory
101        ///   accesses from those Exception levels cannot access Secure memory.
102        ///
103        /// When SCR_EL3.{EEL2, NS} == {1, 0}, then EL2 is using AArch64 and in Secure state.
104        NS  OFFSET(0) NUMBITS(1) [
105            Secure = 0,
106            NonSecure = 1
107        ]
108    ]
109}
110
111pub struct Reg;
112
113impl Readable for Reg {
114    type T = u64;
115    type R = SCR_EL3::Register;
116
117    sys_coproc_read_raw!(u64, "SCR_EL3", "x");
118}
119
120impl Writeable for Reg {
121    type T = u64;
122    type R = SCR_EL3::Register;
123
124    sys_coproc_write_raw!(u64, "SCR_EL3", "x");
125}
126
127pub const SCR_EL3: Reg = Reg {};
aarch64_cpu/registers/scr_el3.rs

aarch64_cpu/registers/
scr_el3.rs
