aarch32_cpu/register/
ccsidr.rs

1//! Code for managing CCSIDR (*Current Cache Size ID Register*)
2
3use crate::register::{SysReg, SysRegRead};
4use arbitrary_int::{u10, u15, u3};
5
6/// CCSIDR (*Current Cache Size ID Register*)
7#[bitbybit::bitfield(u32, debug, defmt_bitfields(feature = "defmt"))]
8#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
9pub struct Ccsidr {
10    #[bit(31, rw)]
11    write_through: bool,
12    #[bit(30, rw)]
13    write_back: bool,
14    #[bit(29, rw)]
15    read_alloc: bool,
16    #[bit(28, rw)]
17    write_alloc: bool,
18    #[bits(13..=27, rw)]
19    num_sets: u15,
20    #[bits(3..=12, rw)]
21    associativity: u10,
22    #[bits(0..=2, rw)]
23    line_size: u3,
24}
25
26impl SysReg for Ccsidr {
27    const CP: u32 = 15;
28    const CRN: u32 = 0;
29    const OP1: u32 = 1;
30    const CRM: u32 = 0;
31    const OP2: u32 = 0;
32}
33
34impl crate::register::SysRegRead for Ccsidr {}
35
36impl Ccsidr {
37    #[inline]
38    /// Reads CCSIDR (*Current Cache Size ID Register*)
39    pub fn read() -> Ccsidr {
40        unsafe { Self::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
41    }
42}
aarch32_cpu/register/ccsidr.rs

aarch32_cpu/register/
ccsidr.rs
