a7105/registers/
delay.rs

1use super::*;
2use defmt::Format;
3
4#[derive(Format, PartialEq, Debug, Copy, Clone)]
5pub enum WpllToTx {
6    Us20,
7    Us40,
8    Us60,
9    Us80,
10}
11
12#[derive(Format, PartialEq, Debug, Copy, Clone)]
13pub enum PllToWpll {
14    Us50,
15    Us70,
16    Us90,
17    Us110,
18}
19
20#[derive(Format, PartialEq, Debug, Copy, Clone)]
21pub struct Delay1 {
22    pub wpl_to_tx: WpllToTx,
23    pub pll_to_wpll: PllToWpll,
24}
25
26impl Default for Delay1 {
27    fn default() -> Self {
28        Self {
29            wpl_to_tx: WpllToTx::Us60,
30            pll_to_wpll: PllToWpll::Us70,
31        }
32    }
33}
34
35impl Register for Delay1 {
36    fn id() -> u8 {
37        0x16
38    }
39}
40
41impl WritableRegister for Delay1 {}
42
43impl From<Delay1> for u8 {
44    fn from(val: Delay1) -> u8 {
45        (match val.wpl_to_tx {
46            WpllToTx::Us20 => 0b00,
47            WpllToTx::Us40 => 0b01,
48            WpllToTx::Us60 => 0b10,
49            WpllToTx::Us80 => 0b11,
50        } << 3)
51            | match val.pll_to_wpll {
52                PllToWpll::Us50 => 0b001,
53                PllToWpll::Us70 => 0b010,
54                PllToWpll::Us90 => 0b011,
55                PllToWpll::Us110 => 0b100,
56            }
57    }
58}
59
60#[derive(Format, PartialEq, Debug, Copy, Clone)]
61pub enum XtalSettlingDelay {
62    Us200,
63    Us400,
64    Us600,
65    Us800,
66    Us1000,
67    Us1500,
68    Us2000,
69    Us2500,
70}
71
72#[derive(Format, PartialEq, Debug, Copy, Clone)]
73pub enum AgcDelaySettling {
74    Us10,
75    Us20,
76    Us30,
77    Us40,
78}
79
80#[derive(Format, PartialEq, Debug, Copy, Clone)]
81pub enum RssiMeasurementDelay {
82    Us10,
83    Us20,
84    Us30,
85    Us40,
86    Us50,
87    Us60,
88    Us70,
89    Us80,
90}
91
92#[derive(Format, PartialEq, Debug, Copy, Clone)]
93pub struct Delay2 {
94    pub xtal_settling_delay: XtalSettlingDelay,
95    pub agc_delay_settling: AgcDelaySettling,
96    pub rssi_measurement_delay: RssiMeasurementDelay,
97}
98
99impl Default for Delay2 {
100    fn default() -> Self {
101        Self {
102            xtal_settling_delay: XtalSettlingDelay::Us600,
103            agc_delay_settling: AgcDelaySettling::Us10,
104            // default value is 20uS, but datasheet suggets using 10uS
105            rssi_measurement_delay: RssiMeasurementDelay::Us10,
106        }
107    }
108}
109
110impl Register for Delay2 {
111    fn id() -> u8 {
112        0x17
113    }
114}
115
116impl WritableRegister for Delay2 {}
117
118impl From<Delay2> for u8 {
119    fn from(val: Delay2) -> u8 {
120        (match val.xtal_settling_delay {
121            XtalSettlingDelay::Us200 => 0b000,
122            XtalSettlingDelay::Us400 => 0b001,
123            XtalSettlingDelay::Us600 => 0b010,
124            XtalSettlingDelay::Us800 => 0b011,
125            XtalSettlingDelay::Us1000 => 0b100,
126            XtalSettlingDelay::Us1500 => 0b101,
127            XtalSettlingDelay::Us2000 => 0b110,
128            XtalSettlingDelay::Us2500 => 0b111,
129        } << 5)
130            | match val.agc_delay_settling {
131                AgcDelaySettling::Us10 => 0b00,
132                AgcDelaySettling::Us20 => 0b01,
133                AgcDelaySettling::Us30 => 0b10,
134                AgcDelaySettling::Us40 => 0b11,
135            } << 3
136            | match val.rssi_measurement_delay {
137                RssiMeasurementDelay::Us10 => 0b000,
138                RssiMeasurementDelay::Us20 => 0b001,
139                RssiMeasurementDelay::Us30 => 0b010,
140                RssiMeasurementDelay::Us40 => 0b011,
141                RssiMeasurementDelay::Us50 => 0b100,
142                RssiMeasurementDelay::Us60 => 0b101,
143                RssiMeasurementDelay::Us70 => 0b110,
144                RssiMeasurementDelay::Us80 => 0b111,
145            }
146    }
147}
148
149#[cfg(test)]
150mod test {
151    use super::super::Register as _;
152    use super::*;
153
154    #[test]
155    fn test_delay1() {
156        let default: u8 = Delay1::default().into();
157        assert_eq!(default, 0b0001_0010);
158
159        assert_eq!(Delay1::id(), 0x16);
160    }
161
162    #[test]
163    fn test_delay2() {
164        let default: u8 = Delay2::default().into();
165        assert_eq!(default, 0b0100_0000);
166
167        assert_eq!(Delay2::id(), 0x17);
168    }
169}
a7105/registers/delay.rs

a7105/registers/
delay.rs
