PY32f071cxx_pac/exti/
exticr4.rs

1#[doc = "Register `EXTICR4` reader"]
2pub struct R(crate::R<EXTICR4_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<EXTICR4_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<EXTICR4_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<EXTICR4_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `EXTICR4` writer"]
17pub struct W(crate::W<EXTICR4_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<EXTICR4_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<EXTICR4_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<EXTICR4_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `EXTI12` reader - GPIO port selection"]
38pub type EXTI12_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `EXTI12` writer - GPIO port selection"]
40pub type EXTI12_W<'a, const O: u8> = crate::FieldWriter<'a, u32, EXTICR4_SPEC, u8, u8, 2, O>;
41#[doc = "Field `EXTI13` reader - GPIO port selection"]
42pub type EXTI13_R = crate::FieldReader<u8, u8>;
43#[doc = "Field `EXTI13` writer - GPIO port selection"]
44pub type EXTI13_W<'a, const O: u8> = crate::FieldWriter<'a, u32, EXTICR4_SPEC, u8, u8, 2, O>;
45#[doc = "Field `EXTI14` reader - GPIO port selection"]
46pub type EXTI14_R = crate::FieldReader<u8, u8>;
47#[doc = "Field `EXTI14` writer - GPIO port selection"]
48pub type EXTI14_W<'a, const O: u8> = crate::FieldWriter<'a, u32, EXTICR4_SPEC, u8, u8, 2, O>;
49#[doc = "Field `EXTI15` reader - GPIO port selection"]
50pub type EXTI15_R = crate::FieldReader<u8, u8>;
51#[doc = "Field `EXTI15` writer - GPIO port selection"]
52pub type EXTI15_W<'a, const O: u8> = crate::FieldWriter<'a, u32, EXTICR4_SPEC, u8, u8, 2, O>;
53impl R {
54    #[doc = "Bits 0:1 - GPIO port selection"]
55    #[inline(always)]
56    pub fn exti12(&self) -> EXTI12_R {
57        EXTI12_R::new((self.bits & 3) as u8)
58    }
59    #[doc = "Bits 8:9 - GPIO port selection"]
60    #[inline(always)]
61    pub fn exti13(&self) -> EXTI13_R {
62        EXTI13_R::new(((self.bits >> 8) & 3) as u8)
63    }
64    #[doc = "Bits 16:17 - GPIO port selection"]
65    #[inline(always)]
66    pub fn exti14(&self) -> EXTI14_R {
67        EXTI14_R::new(((self.bits >> 16) & 3) as u8)
68    }
69    #[doc = "Bits 24:25 - GPIO port selection"]
70    #[inline(always)]
71    pub fn exti15(&self) -> EXTI15_R {
72        EXTI15_R::new(((self.bits >> 24) & 3) as u8)
73    }
74}
75impl W {
76    #[doc = "Bits 0:1 - GPIO port selection"]
77    #[inline(always)]
78    pub fn exti12(&mut self) -> EXTI12_W<0> {
79        EXTI12_W::new(self)
80    }
81    #[doc = "Bits 8:9 - GPIO port selection"]
82    #[inline(always)]
83    pub fn exti13(&mut self) -> EXTI13_W<8> {
84        EXTI13_W::new(self)
85    }
86    #[doc = "Bits 16:17 - GPIO port selection"]
87    #[inline(always)]
88    pub fn exti14(&mut self) -> EXTI14_W<16> {
89        EXTI14_W::new(self)
90    }
91    #[doc = "Bits 24:25 - GPIO port selection"]
92    #[inline(always)]
93    pub fn exti15(&mut self) -> EXTI15_W<24> {
94        EXTI15_W::new(self)
95    }
96    #[doc = "Writes raw bits to the register."]
97    #[inline(always)]
98    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
99        self.0.bits(bits);
100        self
101    }
102}
103#[doc = "EXTI external interrupt selection register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [exticr4](index.html) module"]
104pub struct EXTICR4_SPEC;
105impl crate::RegisterSpec for EXTICR4_SPEC {
106    type Ux = u32;
107}
108#[doc = "`read()` method returns [exticr4::R](R) reader structure"]
109impl crate::Readable for EXTICR4_SPEC {
110    type Reader = R;
111}
112#[doc = "`write(|w| ..)` method takes [exticr4::W](W) writer structure"]
113impl crate::Writable for EXTICR4_SPEC {
114    type Writer = W;
115}
116#[doc = "`reset()` method sets EXTICR4 to value 0"]
117impl crate::Resettable for EXTICR4_SPEC {
118    #[inline(always)]
119    fn reset_value() -> Self::Ux {
120        0
121    }
122}
PY32f071cxx_pac/exti/exticr4.rs

PY32f071cxx_pac/exti/
exticr4.rs
